Data transmission method, computer readable storage medium and vehicle

Abstract

The application discloses a data transmission method, a computer readable storage medium and a vehicle, and relates to the field of intelligent network connection technology, wherein a plurality of chips share one data transmission channel, and the data transmission method comprises the following steps: in the case that there is at least one target chip with a data transmission request, acquiring data transmission states of other chips; and determining a data transmission state of the target chip according to the data transmission states of the other chips. The method of the application avoids the problem of continuously accumulated packet sending delay and decreased data transmission channel utilization, realizes real-time negotiation of data transmission channel occupation, effectively compresses the time consumption of multi-chip competition for the channel, greatly improves the data transmission real-time performance and utilization of the shared channel, can better adapt to the application scene of the vehicle-mounted system and other multi-chip sharing the same communication frequency band, and guarantees the efficiency and overall stability of the cooperative work of the multi-chip.

Description

Technical Field

[0001] This application relates to the field of intelligent connected vehicle technology, and in particular to a data transmission method, a computer-readable storage medium, and a vehicle. Background Technology

[0002] To meet diverse wireless connectivity needs, two or more WiFi chips are typically configured, with multiple chips operating on a shared 5G frequency band (e.g., 5375-5815MHz). When multiple chips need to transmit data simultaneously or at high frequencies, the allocation of the same wireless channel must be effectively coordinated to avoid data collisions and resource conflicts, thereby ensuring the real-time performance of data transmission and the overall channel utilization of the system.

[0003] In related technologies, the main approach to data transmission between two chips is to select one chip as the master chip and the other as the slave chip. When the master chip sends a message, the data is directly transmitted to the slave chip via the corresponding protocol. However, no solution is provided for data collisions and resource conflicts that may occur when the two chips share the same data transmission channel. Furthermore, other related technologies address data collisions and resource conflicts by using a Clear Channel Assessment (CCA) mechanism, where the two WiFi chips attempt to transmit again after the backoff period. While this passive detection and random waiting mechanism based on the protocol stack can avoid collisions to some extent, the detection and backoff process before each packet transmission introduces a fixed delay at the microsecond level. Moreover, the uncontrollable nature of the random backoff time leads to decreased channel utilization and a significant increase in cumulative latency in high-frequency concurrent scenarios.

[0004] Therefore, in vehicle systems containing multiple WiFi chips sharing the same wireless frequency band, how to reduce packet transmission latency caused by channel contention and improve channel utilization has become an urgent technical problem to be solved. Summary of the Invention

[0005] This application aims to at least partially address one of the technical problems in related technologies. To this end, the first objective of this application is to propose a data transmission method that utilizes the target chip to obtain the data transmission status of other chips when a data transmission request is made, and determines its own transmission availability based on the status of other chips. This avoids the problems of packet delay accumulation and decreased channel utilization caused by traditional reliance on passive CCA detection and random backoff mechanisms. This scheme utilizes direct information interaction between chips to achieve real-time channel occupancy negotiation, effectively shortening the time required for channel contention, improving the real-time performance of data transmission and channel utilization, thereby ensuring the efficiency and stability of multi-chip collaborative operation in shared frequency band scenarios such as automotive systems.

[0006] The second objective of this application is to provide a computer-readable storage medium.

[0007] The third objective of this application is to propose a vehicle.

[0008] To achieve the above objectives, a first aspect of this application proposes a data transmission method, the method comprising: acquiring the data transmission status of other chips when at least one target chip has a data transmission request; and determining the data transmission status of the target chip based on the data transmission status of the other chips.

[0009] According to the data transmission method of this application embodiment, when at least one target chip has a data transmission request, the data transmission status of other chips is obtained, and the data transmission status of the target chip is determined based on the data transmission status of the other chips. Therefore, this method allows the target chip to directly learn the transmission status of other chips through inter-chip information interaction before initiating a data transmission request, without relying on traditional passive channel idle assessment and random backoff mechanisms for channel contention. This fundamentally avoids the problems of continuously accumulating packet transmission delay and decreasing channel utilization, achieves real-time negotiation of channel occupancy, effectively reduces the time consumed by multi-chip channel contention, and significantly improves the real-time performance and utilization of shared channel data transmission. It is better suited to application scenarios such as automotive systems where multiple chips share the same communication frequency band, ensuring the efficiency and overall stability of multi-chip collaborative work.

[0010] According to one embodiment of this application, determining the data transmission state of the target chip based on the data transmission state of the other chips includes: if the target chip is a single chip, and the data transmission state of the other chips is not transmitted, then the data transmission state of the target chip is determined to be transmittable, so that the target chip can transmit data on the data transmission channel; if the data transmission state of the other chips is transmitted, then the data transmission state of the target chip is determined to be not transmitted, so that the other chips can transmit data on the data transmission channel.

[0011] According to one embodiment of this application, determining the data transmission status of the target chip based on the data transmission status of the other chips includes: when there are multiple target chips, if the data transmission status of the other chips is not transmitted, determining the target transmission order of the target chips according to the priority of the data to be transmitted corresponding to the multiple target chips, or determining the target transmission order according to a set transmission order; and performing data transmission based on the target transmission order.

[0012] According to one embodiment of this application, each chip is configured with a general-purpose input / output pin, and the plurality of chips are connected to each other through the general-purpose input / output pin, which is configured in a bidirectional mode for sending and receiving level status signals.

[0013] According to one embodiment of this application, obtaining the data transmission status of other chips includes: obtaining the level status signal of the general-purpose input / output pins of the other chips; determining that the data transmission status of the other chips is in a non-transmission state when the level status signal is a first level; and determining that the data transmission status of the other chips is in a transmission state when the level status signal is a second level.

[0014] According to one embodiment of this application, the plurality of chips includes a target chip and another chip. Determining the data transmission state of the target chip based on the data transmission state of the other chip includes: if the data transmission state of the other chip is determined to be in a transmission state, controlling the target chip to wait for a preset time; after waiting for the preset time, if the level status signal of the general-purpose input / output pin of the other chip switches from the second level to the first level, then determining the data transmission state of the target chip to be in a transmission state, so that the target chip performs data transmission on the data transmission channel.

[0015] According to one embodiment of this application, the method further includes: if, after waiting for the preset duration, the level status signal of the general-purpose input / output pin of the other chip is at the second level and the duration exceeds a preset timeout threshold, then performing an idle channel assessment on the data transmission channel; if it is determined that the data transmission channel is idle, controlling the target chip to perform data transmission on the data transmission channel.

[0016] According to one embodiment of this application, the method further includes: after the target chip completes data transmission on the data transmission channel, controlling the level status signal of the general-purpose input / output pin of the target chip to switch from the second level to the first level.

[0017] To achieve the above objectives, a second aspect of this application provides a computer-readable storage medium having a program stored thereon that, when executed by a processor, implements the above-described vehicle steering wheel control method.

[0018] According to the computer-readable storage medium of the present application embodiment, by implementing the above-described vehicle steering wheel control method during execution, the problems of continuous accumulation of packet sending delay and decreased utilization of data transmission channel can be avoided. Real-time negotiation of data transmission channel occupancy is realized, effectively reducing the time consumption of multi-chip channel contention, and significantly improving the real-time performance and utilization of shared channel data transmission. It can better adapt to application scenarios such as vehicle systems where multiple chips share the same communication frequency band, ensuring the efficiency and overall stability of multi-chip collaborative work.

[0019] To achieve the above objectives, a vehicle is provided in a third aspect of this application, including a memory, a processor, and a program stored in the memory and executable on the processor. When the processor executes the program, it implements the above-described data transmission method.

[0020] According to the vehicle embodiment of this application, by executing the above-described data transmission method, the problems of continuous accumulation of packet delay and decreased utilization of data transmission channel can be avoided. Real-time negotiation of data transmission channel occupancy is realized, effectively reducing the time consumption of multi-chip channel contention, and significantly improving the real-time performance and utilization of shared channel data transmission. It can better adapt to application scenarios such as vehicle systems where multiple chips share the same communication frequency band, ensuring the efficiency and overall stability of multi-chip collaborative work.

[0021] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0022] Figure 1 This is a flowchart of a data transmission method according to an embodiment of this application.

[0023] Figure 2 This is a flowchart illustrating a specific example of a data transmission method according to this application.

[0024] Figure 3 This is a block diagram of a vehicle according to an embodiment of this application. Detailed Implementation

[0025] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0026] In in-vehicle wireless communication systems, especially smart cockpit infotainment systems, to simultaneously support multiple wireless connectivity functions, such as providing in-vehicle Wi-Fi hotspot sharing and mobile device wireless network connections, the common approach is to configure multiple wireless (WiFi) chips on the same in-vehicle platform and have these chips operate on the same wireless frequency band, such as the 5G band (e.g., 5375-5815MHz). These chips all transmit and receive data through this shared wireless channel. This solution is widely adopted primarily to expand the wireless connectivity capabilities of the in-vehicle infotainment system without increasing additional hardware costs, thus meeting users' needs for multi-device, multi-tasking concurrency.

[0027] However, this solution performs poorly when applied to in-vehicle entertainment data transmission scenarios requiring high frequency and low latency. To ensure that multiple chips do not interfere with each other on a shared channel, the channel contention and coordination mechanisms inevitably introduce significant data transmission delays, thus impairing overall channel utilization efficiency and system real-time response performance. For example, in applications where in-vehicle Wi-Fi hotspot sharing and smartphone screen mirroring functions operate simultaneously, when the data packet transmission requests from multiple Wi-Fi chips highly overlap in time, the aforementioned contradiction causes each data packet to undergo a long waiting period before transmission, resulting in frequent playback stuttering, increased screen mirroring latency, or decreased hotspot data transmission rates.

[0028] In-depth analysis revealed that the root cause of the aforementioned contradiction lies in the passive channel detection and backoff mechanism employed by the relevant technology. Specifically, before transmitting any data, each WiFi chip must first perform a Clear Channel Assessment (CCA) to monitor whether the wireless channel is idle. When a channel is detected to be occupied, the chip executes a waiting process based on a random backoff algorithm, typically lasting 10 to 100 microseconds. It only attempts to transmit again after the channel becomes available and the backoff timer expires. While this mechanism can prevent data packet collisions caused by multiple chips transmitting data simultaneously, its inherent waiting time accumulates in high-frequency packet transmission scenarios, resulting in significant end-to-end latency. More importantly, this mechanism is a passive and uncertain form of competition. The chip cannot predict the transmission status of the other chip and can only explore channel availability through repeated detection and waiting. This leads to a large amount of idle waiting time when the chip switches usage rights, making efficient pipelined data transmission impossible.

[0029] To address the aforementioned issues, this invention proposes a data transmission method. By establishing a direct hardware signal line between chips based on General Purpose Input Output (GPIO) pins, the negotiation of channel occupancy status is moved from a passive, protocol stack-based listening layer to direct communication at the physical layer between chips, thereby completely eliminating traditional CCA detection and random backoff processes. This scheme allows any chip to actively and in real-time announce its transmission intention to the other chip via its own GPIO pin when it needs to send data, and can immediately read the other chip's status signal. Channel availability is determined at near-hardware signal transmission speed, thus solving the technical problems of large data packet transmission delays and low channel utilization caused by passive CCA detection and random backoff mechanisms in related technologies. This achieves a reduction in channel request delay from the microsecond level (10-100 microseconds) to the nanosecond level (less than 1 microsecond), significantly improving channel utilization efficiency and system real-time performance.

[0030] In one embodiment of this application, the data transmission method proposed in this application is applicable to a data transmission system, which mainly includes two cooperating WiFi chips: a first WiFi chip and a second WiFi chip. In practical applications, both chips can be integrated on the vehicle's mainboard. For example, the first WiFi chip can act as the master chip, responsible for the main wireless connection tasks, such as establishing and managing in-vehicle hotspots; the second WiFi chip can act as the slave chip, responsible for auxiliary wireless connection tasks, such as establishing point-to-point connections with the user's smartphone. Both chips are configured to operate on the same shared wireless frequency band, such as the 5G frequency band. To achieve hardware-level signal coordination, each chip is configured with a dedicated GPIO pin, which is referred to as a request pin (e.g., REQ pin) in this embodiment. The request pin of the first WiFi chip (e.g., REQ_A) and the request pin (REQ_B) of the second WiFi chip can be directly electrically connected via traces on a printed circuit board (PCB). This direct connection structure forms a simple single-bus hardware signal network, enabling any chip to send signals by changing the level state of its own pins and to know the signal of the other chip by reading the level state at the common connection point.

[0031] The first level and the second level are a pair of relative concepts used to distinguish two different electrical states. Specifically, the first level can refer to a low level (logic 0), which is considered an inactive state in digital circuits; the second level can refer to a high level (logic 1), which is considered an active state. Conversely, it depends on the system logic design. For example, in a preferred implementation of this embodiment, the low level (first level) is defined as an idle or unused state, while the high level (second level) is defined as a busy or occupied state. The transition time of these two level signals on the GPIO pin is typically on the nanosecond level, which is the basis for implementing low-latency hardware handshaking.

[0032] Therefore, this direct hardware handshake method does not require the use of an additional main control chip for coordination, nor does it require the transmission of channel occupancy information through software interaction. It eliminates the additional delay caused by software scheduling and can complete the channel occupancy status notification between the two chips in nanoseconds. This significantly reduces the handshake delay of collaborative transmission and effectively avoids signal conflicts caused by two WiFi chips operating on the same frequency band transmitting data at the same time. Without increasing hardware costs, it improves the transmission stability and efficiency of multi-WiFi chip collaborative operation in the vehicle system.

[0033] The data transmission method and computer-readable storage medium vehicle proposed in this application are described below with reference to the accompanying drawings.

[0034] Figure 1 This is a flowchart of a data transmission method according to an embodiment of this application.

[0035] like Figure 1 As shown, the data transmission method in this application embodiment may include the following steps: S1: If at least one target chip has a data transmission request, obtain the data transmission status of other chips.

[0036] Specifically, this method can be executed by any of the WiFi chips in the aforementioned system. When at least one target chip (i.e., a chip that needs to send data) has a data transmission request, the data transmission status of other chips must first be obtained. These other chips refer to those sharing the same data transmission channel with the target chip and potentially experiencing channel contention. Essentially, before the target chip initiates its data transmission process, it no longer relies on traditional passive CCA detection but actively listens for real-time information about the behavior and status of other chips, indicated by a hardware signal. Subsequently, based on the obtained data transmission status of other chips, it determines whether the target chip itself can transmit data, or what state it should be in. This judgment logic is crucial to the success of the entire coordination mechanism; it ensures that when multiple chips share a channel resource, only one chip is allowed to transmit data at any given time, thus fundamentally avoiding packet collisions.

[0037] As a specific implementation method, acquiring the data transmission status of other chips can be achieved through a direct and efficient hardware read operation. Specifically, each chip can announce or indicate its own data transmission intention through the level state of its GPIO pins. For example, when a chip needs to send data, it can actively switch the level of its own GPIO pins. Simultaneously or immediately after switching its own level, the chip will read the level of the other chip's GPIO pins on the same signal line. If a low level indicating "data transmission channel idle" is read, it means that the other chip currently has no intention to send data, and the channel can be occupied. If a high level indicating "data transmission channel busy" is read, it means that the other chip may have already occupied the channel or is requesting the channel. Using this method, the time required for the chip to acquire the status is determined only by the hardware delay of the GPIO pin read operation, typically within tens of nanoseconds. Compared to related technologies that require waiting for a complete CCA listening cycle (which can last for tens of microseconds), its efficiency is improved by orders of magnitude.

[0038] More generally, the acquisition of data transmission status can be achieved not only through hardware, but also through methods such as polling on the system bus or querying through a dedicated status register independent of the main data path. For example, before initiating data transmission, each chip reads the flag bits in a pre-allocated status register, determines whether the bus is occupied by other chips based on the flag bit values, and if the bus is idle, modifies the corresponding flag bit to the occupied state before initiating transmission. After transmission, the flag bit is changed back to the idle state for other chips to query. This implementation does not require additional GPIO pins; it can reuse the chip's existing bus interface to complete the status acquisition, adapting to compact design scenarios that do not require additional pins. At the same time, the read latency of the status register is much lower than that of traditional CCA monitoring, effectively improving the overall efficiency of data transmission.

[0039] S2, determine the data transmission status of the target chip based on the data transmission status of other chips.

[0040] Specifically, after obtaining the data transmission status of other chips, the data transmission status of the target chip can be determined. The data transmission status refers to the overall situation of whether a chip is currently using a shared data transmission channel for data transmission and reception. Specifically, it can refer to whether the chip is in an active state of sending data packets, or it can encompass whether it is in a preparatory state of requesting a channel but not yet starting to send. In one core implementation, this state is simplified to a binary state: channel idle or channel busy. This simplification is based on the hardware handshake signal design, whereby the chip continuously maintains its pin at a high level during data transmission and immediately pulls it low once transmission is complete, thus physically binding the "transmission state" with the "high level." This binary processing makes status determination exceptionally simple and fast, eliminating the need for complex protocol parsing and enabling nanosecond-level channel switching.

[0041] For example, if the data transmission status of other chips indicates that no other chip is currently occupying the data transmission channel, the transmission status of the target chip can be set to a transmittable state, and the target chip can be controlled to start the corresponding data transmission process. At the same time, the target chip can output a corresponding occupation signal through its own hardware to indicate that the current channel has been occupied by the target chip. If the data transmission status of other chips indicates that another chip is already occupying the data transmission channel, the target chip can be controlled to enter a waiting state. After a preset interval, the status acquisition and transmission judgment process will be restarted until the target chip completes the data transmission and clears its own occupation signal indication for other chips waiting to transmit to use.

[0042] It's important to note that the aforementioned scheme, which determines its own behavior by acquiring the other party's state, fundamentally changes the classic paradigm of channel contention. Under the traditional passive CCA mechanism, channel availability can only be guessed through complex energy detection and signal decoding, and a fixed backoff window must be waited for before retrying. In contrast, this scheme allows chips to obtain the other party's intentions in real-time and accurately through information transmission between hardware signal lines, thus making a deterministic decision.

[0043] Therefore, by actively acquiring the status of other chips before deciding on transmission, this method fundamentally avoids the data packet collision problem when multiple chips share a channel. It does not rely on the fixed-length backoff waiting window in traditional mechanisms, significantly reducing the transmission delay caused by channel contention and improving the overall throughput of multi-chip collaborative transmission. At the same time, it can be achieved with only simple hardware level signal interaction, without adding too much hardware cost. The implementation solution is simple and reliable, and is suitable for application scenarios of multiple chips sharing a wireless channel in vehicles.

[0044] According to one embodiment of this application, determining the data transmission status of a target chip based on the data transmission status of other chips includes: if the target chip is a single chip, and the data transmission status of other chips is in a non-transmission state, then the data transmission status of the target chip is determined to be a transmittable state, so that the target chip can transmit data on the data transmission channel; if the data transmission status of other chips is in a transmission state, then the data transmission status of the target chip is determined to be a non-transmission state, so that the other chips can transmit data on the data transmission channel.

[0045] Specifically, to further optimize the response speed in the single-chip request scenario described in the above embodiments, this application also provides the following preferred solution. After obtaining the data transmission status of other chips, the number of target chips is determined. When there is only one target chip and a data transmission request exists, if the data transmission status of other chips is detected as not transmitting, the data transmission status of the target chip itself is directly determined to be transmittable, thereby immediately authorizing the target chip to transmit data on the data transmission channel. Conversely, if the data transmission status of other chips is transmitting, the data transmission status of the target chip itself is determined to be not transmitting, i.e., it is prohibited from sending, to ensure that other chips that are sending data can complete the transmission without interference.

[0046] For example, after system initialization, the chip's GPIO request pin is configured in bidirectional mode and initialized to a low level. When chip A needs to send data, it first pulls its REQ_A pin high. Immediately afterwards, it reads the level of the REQ_B pin. If REQ_B is low, the channel is considered idle, and chip A begins sending data on the wireless channel. After data transmission is complete, the REQ_A pin is pulled low to release the channel. If REQ_B is high, the channel is considered occupied, chip A enters a waiting state and continuously monitors the REQ_B pin. Once a transition from high to low is detected, data transmission begins immediately. In this process, the transition from high to low is a clear indicator of channel release; its rising / falling edge can itself serve as an interrupt source or trigger signal, directly waking up the waiting chip.

[0047] Those skilled in the art will understand that state determination logic achieving the same purpose can also include parsing the received GPIO level signal through a hardware comparator or state machine, rather than through software polling. For example, a D flip-flop can be used to latch the state of the other pin, and its output can directly enable or disable the chip's MAC (Media Access Control Layer) transmission queue. This pure hardware solution can further reduce the decision latency to zero processor cycles, achieving true hardware-level real-time control.

[0048] Therefore, by adopting the direct authorization mechanism described above in single-chip request scenarios, the fixed latency caused by the need for CCA detection and random backoff when the channel is idle is eliminated. In single-chip request scenarios, channel request latency is theoretically reduced to zero, which further helps to solve the specific problems of excessive accumulated latency and poor user experience in high-frequency interaction scenarios of multi-chip systems.

[0049] According to one embodiment of this application, determining the data transmission status of a target chip based on the data transmission status of other chips includes: when there are multiple target chips, if the data transmission status of other chips is not transmitted, determining the target transmission order of the target chips according to the priority of the data to be transmitted corresponding to the multiple target chips, or determining the target transmission order according to a set transmission order; and performing data transmission based on the target transmission order.

[0050] Specifically, in actual automotive multi-chip systems, situations sometimes arise where two or more chips initiate data transmission requests at almost the exact same time. For example, when the download data packet from the first WiFi chip and the upload data packet from the second WiFi chip are processed and sent out in the kernel's network protocol stack almost simultaneously, they may simultaneously attempt to pull their request pins high. While this can be quickly determined by reading the GPIO level, a more complex situation arises when multiple target chips (i.e., chips initiating requests simultaneously) switch their request pins to the second level almost simultaneously. Their respective read operations will find that the other chip's pin is also at the second level. If only the simple logic of waiting when the other's level is high is used, both sides will believe the channel is occupied by the other, thus resulting in a deadlock and preventing data transmission. To handle this contention caused by almost simultaneous requests, this application also provides the following preferred solution.

[0051] This involves determining the number of target chips. When multiple target chips simultaneously request data transmission, and they have previously detected that other chips are in an inactive state (i.e., the channel has changed from idle to being requested by multiple chips simultaneously), a priority-based sorting mechanism is introduced. Specifically, the target transmission order can be determined according to the priority of the data to be transmitted by each target chip, or according to a system-preset, fixed transmission order. Then, all relevant chips will strictly follow this arbitrated order to transmit data sequentially on the data transmission channel.

[0052] This design aims to solve the problem of determining the order of requests from multiple chips simultaneously. When a simultaneous request occurs, relying solely on the instantaneous state of the signal level is insufficient to distinguish which chip requests data first; additional, higher-level logic must be introduced to make the decision. Software-configurable schemes, such as data priority and preset order, provide system designers with significant flexibility. For example, in an automotive system, safety-related data (such as collision warning information) can be prioritized to the highest level, audio and video streams generated by the entertainment system to the next highest level, and background downloads and updates to the lowest level. This way, when two chips request a channel almost simultaneously, the chip processing safety information will receive the highest priority access. Alternatively, the system can preset a fixed polling order, such as prioritizing access to the master chip, with slave chips only granted authorization when the master chip is idle.

[0053] Those skilled in the art will understand that other methods for determining the order of requests to achieve the same purpose include: based on the size of the chip hardware ID, based on the reverse order of the last access time (time-slice rotation), or based on the voting result of an external arbitrator. For example, a simple hardware state machine can be designed so that when a chip detects a conflict, it no longer performs random backoff, but instead determines whether to retry immediately or wait for a fixed duration based on the last bit of its MAC address. While these solutions can logically solve the problem of the order of simultaneous requests, data priority-based solutions can be more closely integrated with the needs of upper-layer applications, thereby optimizing system-level service quality and user experience.

[0054] For example, when chip A and chip B almost simultaneously pull their REQ (pin request) high, they will both detect a conflict (i.e., the other's REQ is also high). At this point, the conflict handling module begins to operate. This module first reads a preset register used to identify the priority of its own chip or the data to be transmitted. Based on the value in this register, each chip determines whether it has a higher priority through a simple hardware comparator. For example, if the system is set so that the default priority of the first WiFi chip is higher than that of the second WiFi chip, then when a conflict occurs, the register value of the first WiFi chip will be higher than that of the second WiFi chip, the hardware comparator will output a high-level result, and the first WiFi chip will directly maintain its REQ high level and continue to initiate a channel access request; while the second WiFi chip, after detecting that its own priority is lower, will immediately pull its REQ signal low, wait for the first WiFi chip to complete its current transmission, and then re-initiate a channel access request, thereby avoiding transmission conflicts on unidirectional and bidirectional transmission channels and ensuring that the transmission of high-priority data is not blocked.

[0055] For example, when chips A and B almost simultaneously raise their REQ signals, both the first and second WiFi chips can perform a short, random wait, such as 1 to 5 microseconds. After the wait time, the chips re-detect the bus status and initiate a REQ request. Because the two chips have different wait times, only one chip will raise its REQ signal first, thus preventing further conflicts. For instance, if the first WiFi chip waits for 1 microsecond and the second WiFi chip waits for 5 microseconds, the first WiFi chip will end its wait first and lower its raised REQ signal, while the second WiFi chip is still waiting to initiate a request. Therefore, the second WiFi chip can directly detect that the bus is idle and initiate a channel access request. After ending its wait, the first WiFi chip detects that the bus is occupied and automatically cancels its request, waiting for the next transmission window to re-initiate the request. This random backoff method can efficiently resolve transmission conflicts when both chips have the same priority, preventing high-priority transmissions from being continuously blocked, and adapting to different scenarios requiring multi-chip transmission on the same bus. Therefore, this random backoff mechanism can quickly resolve conflicts in scenarios where priorities are not configured or priorities are the same, further improving the stability of channel resource utilization and avoiding repeated chip conflicts that waste transmission bandwidth.

[0056] Therefore, by adopting the aforementioned conflict resolution method based on priority or preset order, it can be ensured that even in extreme scenarios where multiple chips request access simultaneously, the system can still allocate channel usage rights in an orderly manner, without falling into indefinite waiting.

[0057] According to one embodiment of this application, each chip is configured with a general-purpose input / output pin, and multiple chips are connected to each other through the general-purpose input / output pin. The general-purpose input / output pin is configured in bidirectional mode for sending and receiving level status signals.

[0058] Specifically, to achieve the goal described above of chips knowing each other's data transmission status in real time via hardware signal lines, this application provides a preferred scheme for physical connection and signal configuration. That is, each chip participating in channel contention is configured with a dedicated GPIO pin as a request signal pin. Multiple chips are directly electrically connected through these dedicated request pins. Furthermore, these GPIO pins are configured in bidirectional mode. Bidirectional mode means that the pin can be driven by the chip's internal logic to output a high or low level, or it can be driven by external circuitry and its current actual level state can be read through the chip's internal input buffer.

[0059] The core advantage of this design lies in its ability to allow each chip to independently and in real-time broadcast its own request status to a shared signal line, while simultaneously receiving broadcasts from other chips, without requiring any external control signals or additional handshake protocols. For example, when the REQ_A pin of the first WiFi chip is driven high, this high-level signal is directly transmitted to the REQ_B pin of the second WiFi chip via PCB traces. Since REQ_B is configured in bidirectional mode, its internal input buffer can immediately detect this high level, allowing the second WiFi chip to determine the status of the first chip simply by reading a register bit without any software polling.

[0060] Those skilled in the art will understand that, although this embodiment uses GPIO pins as an example, other hardware connection methods to achieve the same function include: using a dedicated bidirectional bus with tri-state gates, or using an analog comparator to detect capacitively coupled signals. For example, in higher-speed applications, low-voltage differential signal pairs can be used to achieve fast signal interconnection between chips. However, GPIO solutions, with their extremely low cost and simplicity of implementation, have unique advantages in automotive applications, where cost and reliability requirements are extremely high.

[0061] For example, the first WiFi chip (Chip A) is configured as the main controller in the vehicle's infotainment system, responsible for managing core functions such as the vehicle hotspot. Chip A's GPIO port PA0 is configured as the request pin REQ_A and set to output mode, initially low. Its GPIO port PA1 is configured as the input pin GNT_B to receive the yield signal from the slave chip. The second WiFi chip (Chip B) is configured as the slave controller. Its GPIO port PB0 is configured as the request pin REQ_B and also set to output mode, initially low. Its GPIO port PB1 is configured as the input pin GNT_A. Chip A's REQ_A pin and Chip B's GNT_A pin are connected to the same signal line called REQ_BUS; similarly, Chip B's REQ_B pin and Chip A's GNT_B pin are connected to the same signal line called GNT_BUS.

[0062] Alternatively, connect chip A's REQ_A and chip B's REQ_B directly, configuring both pins as open-drain outputs with an external pull-up resistor. When either chip needs to send data, it pulls REQ_BUS low (second level) by controlling its internal MOSFET to turn on. The other chip detects this level but doesn't directly drive it. This method avoids the short-circuit risk caused by both chips simultaneously outputting high and low levels. Regardless of the specific configuration, the core objective is to convert the chip's intent into a definite, readable level signal.

[0063] Therefore, by adopting the direct connection and bidirectional mode configuration of the GPIO pins described above, the lowest-level physical foundation for the entire hardware handshake protocol is provided. This connection method reduces signal transmission delay to the nanosecond level, which is only the time it takes for the signal to propagate on the PCB trace.

[0064] According to one embodiment of this application, obtaining the data transmission status of other chips includes: obtaining the level status signal of the general-purpose input / output pins of other chips; determining that the data transmission status of other chips is not transmitted when the level status signal is a first level; and determining that the data transmission status of other chips is transmitted when the level status signal is a second level.

[0065] Specifically, building upon the established GPIO hardware connection, this application further specifies how to accurately identify the data transmission status of the other chip from the hardware signals. As mentioned earlier, the chip obtains the underlying level signals through direct connection to the GPIO pins. However, this step only obtains the raw electrical signals; they still need to be interpreted as semantically meaningful states: transmitting or not transmitting. That is, when obtaining the data transmission status of other chips, the chip first reads the level status signals of the GPIO pins of the other chips connected to the network through its internal input buffer. This is a simple register read operation, typically completed with a single processor instruction.

[0066] Then, a logical judgment is made based on the read level state: if the level state signal is the first level (e.g., low level), it is determined that the data transmission state of other chips is not transmitting, indicating that the other party is not occupying the channel; if the level state signal is the second level (e.g., high level), it is determined that the data transmission state of other chips is transmitting, indicating that the other party is currently or will occupy the channel. This design, which directly maps the transmission state through high and low levels, makes state detection extremely simple and fast. The chip's central processing unit or hardware state machine does not need to perform any complex decoding, demodulation, or timing analysis; it only needs to perform a conditional jump judgment on one bit of register data. Since the change of GPIO pin level is directly driven by the hardware of the other chip, its transition edge can accurately correspond to the moment when the other chip starts and ends transmitting.

[0067] Those skilled in the art will understand that although this embodiment uses the common convention of "high level = transmit, low level = idle" as an example, the state mapping to achieve the same function can also be reversed, for example, using high level for idle and low level for transmit. This reversal is merely a simple logical inversion and does not affect the essence of the inventive concept. More importantly, to ensure the accuracy of state detection, hardware design typically requires jitter elimination processing of the read signal to prevent incorrect level readings due to transient noise on the signal line (such as ground bounce, crosstalk). For example, a simple filter can be introduced, requiring the read level to remain continuously and stably for several clock cycles (e.g., 2-3 cycles) to be considered a valid state. In addition, the chip can also utilize the interrupt function of the GPIO pin to set the transition from "first level to second level" as a trigger signal, thereby passively and in real-time obtaining the change of the other party's state without software polling, which further reduces the power consumption and latency of state detection.

[0068] Specifically, in the internal implementation of the chip, these two voltage levels can be directly connected to the input of a hardware comparator. The output of this comparator is used to control the next state of the chip's MAC layer transmission state machine. For example, if the hardware state machine is in the "request wait" state, it will immediately jump to the "start transmit" state when the input pin is detected to be at the first voltage level; if the second voltage level is detected, it will remain in the "request wait" state or jump to the "wait backoff" state.

[0069] Therefore, by adopting the above-described level-to-state mapping method, a fast and reliable conversion from the physical level (high or low voltage) to the digital level (chip operating state) is achieved. This deterministic mapping provides a reliable input for the entire channel contention algorithm, ensuring that all subsequent decisions based on this state (such as whether to send or wait) are correct and timely.

[0070] According to one embodiment of this application, the plurality of chips includes a target chip and another chip. Determining the data transmission state of the target chip based on the data transmission state of the other chip includes: if the data transmission state of the other chip is determined to be in a transmission state, controlling the target chip to wait for a preset time; after waiting for the preset time, if the level status signal of the general-purpose input / output pin of the other chip switches from a second level to a first level, then the data transmission state of the target chip is determined to be in a transmission state, so that the target chip can perform data transmission on the data transmission channel. The preset time can be determined according to actual conditions.

[0071] Specifically, when a target chip detects that only one other chip is in a transmission state, its data transmission state is determined to be non-transmission, thus entering a waiting state. The target chip can be controlled to wait for a preset duration. After the preset duration, the target chip again checks the GPIO pin levels of other chips. If it finds that the level has switched from the second level representing the transmission state to the first level representing the non-transmission state, it determines that the other party has released the channel, thus determining that its own data transmission state is ready for transmission, and immediately transmits data on the data transmission channel. This design aims to balance system response speed and resource consumption. If the target chip continuously and at full speed polls the other party's GPIO pin level after detecting that the channel is occupied, although it can respond to channel release the fastest, it will consume a large number of processor clock cycles and bus bandwidth, which may affect the execution of other tasks and even interfere with its own WiFi data transmission and reception. Introducing a preset duration is equivalent to setting a sampling interval for the polling operation. During the first waiting cycle, the chip can completely interrupt polling and switch to processing other low-priority tasks, or simply enter a low-power mode to save energy. After the preset duration ends, the timer wakes the chip to perform a status check. If the channel has been released, intervene quickly; if it has not been released, proceed to the next waiting period.

[0072] Those skilled in the art will understand that other waiting methods to achieve the same purpose include: using hardware interrupts, where a level change on a GPIO pin (a falling edge from high to low) directly triggers an interrupt signal, thereby waking the chip from any low-power state or background task. Furthermore, the preset duration can be set to an estimate of the average time it takes for the other chip to send one data packet, such as 100 microseconds. In this way, in most cases, the chip only needs to poll once to obtain channel control, resulting in high efficiency.

[0073] Therefore, by adopting a status detection mechanism that waits for a preset time, it is possible to effectively monitor the channel release time in a more energy-efficient way and with less interference to the processor.

[0074] According to one embodiment of this application, the data transmission method further includes: if, after waiting for a preset time, the level status signal of the general-purpose input / output pin of another chip is at the second level and the duration exceeds a preset timeout threshold, then an idle channel assessment is performed on the data transmission channel; if it is determined that the data transmission channel is idle, the target chip is controlled to transmit data on the data transmission channel.

[0075] Specifically, while GPIO hardware handshake signals provide a low-latency solution for channel contention, this mechanism, which relies on the other chip actively pulling low to release the channel, has a potential problem: if the other chip experiences a software crash, hardware deadlock, or power failure, it may be unable to pull the REQ pin low after data transmission, causing its REQ pin to remain at a high level representing the transmission state. In this case, if the waiting chip continues to wait for the other chip to release the channel as described in the aforementioned embodiment, the system will fall into an indefinite deadlock state. The preferred solution provided in this application aims to solve this robustness problem and ensure that the system can still maintain basic data transmission and reception capabilities under abnormal conditions.

[0076] Building upon the implementation based on a preset waiting time, this preferred solution introduces a timeout and fallback mechanism. Specifically, the method includes a monitoring step: if, during the target chip's waiting period, the GPIO pin level of another chip remains at the second level (busy state), and this state persists for more than a preset timeout threshold, the target chip no longer blindly trusts the hardware handshake signal. Instead, it falls back to a traditional channel availability assessment method that does not rely on the other chip's active cooperation, namely, idle channel assessment (CCA). The target chip performs CCA operations, conducting actual physical layer power detection or carrier sensing on the wireless data transmission channel. If the CCA assessment result shows that the wireless channel is physically idle (no other radio signals), the logic determines that although the other chip's GPIO pin has declared occupancy, the physical channel may already be idle, or the other chip's declaration has expired. In this case, the target chip will be authorized to transmit data on the data transmission channel.

[0077] In other words, GPIO handshake and CCA are effectively integrated. Under normal circumstances, the system prioritizes the low-latency GPIO handshake; if the GPIO handshake signal becomes invalid for an extended period (potentially indicating a failure of the other party), the system can automatically and safely degrade to the traditional CCA mechanism, which, although more latency-intensive, is highly robust. This enables the system to cope with hardware or software failures, greatly enhancing the resilience of the entire vehicle communication system. The timeout threshold can be dynamically adjusted based on the system's real-time requirements and the health status of the other party's chip. For example, in vehicle safety-critical applications, this threshold can be set to a shorter value, such as 500 microseconds, to recover from potential deadlocks as quickly as possible.

[0078] Those skilled in the art will understand that a fallback mechanism achieving the same purpose may also include: starting a watchdog timer, which triggers a system reset signal to force a hardware reset if no valid transition is observed on the other party's REQ pin within a specified timeout period; or, forcibly switching the direction of its own GPIO pin via software instructions to perform a bus scan to confirm the integrity of the hardware link. For example, the timeout threshold can be configured through a hardware register, with an initial default value of 1 millisecond. When the embedded processor on the chip detects that the other party's pin has been continuously high for 1 millisecond, it no longer waits but directly calls a CCA detection subroutine. This subroutine controls the WiFi RF front-end to perform a brief sampling. If the sampling result indicates that the wireless medium is quiet, the subroutine returns that the channel is idle and forces its own REQ to go high to begin transmitting data.

[0079] Therefore, by adopting the aforementioned backup mechanism of timeout rollback to CCA, a crucial security layer is added to the low-latency channel contention method based on hardware trust, ensuring that the system will not lose its data transmission capability under any abnormal circumstances, thereby significantly enhancing the feasibility and reliability of this solution in complex and harsh vehicle environments.

[0080] According to one embodiment of this application, the data transmission method further includes: after the target chip completes data transmission on the data transmission channel, controlling the level status signal of the general-purpose input / output pin of the target chip to switch from a second level to a first level.

[0081] Specifically, in the channel contention method based on hardware signal coordination, in addition to the issues discussed above, such as how to acquire signals before transmission, how to handle conflicts during transmission, and how to back off if transmission fails, there is another crucial but easily overlooked aspect: after transmission is completed, how to correctly and clearly inform the other party's chip that the channel has been released.

[0082] In the embodiments described above, particularly in a scenario where a target chip obtains authorization by waiting for the other party to release the data and successfully completes the data transmission, once the target chip has completed all data transmission on the data transmission channel, it will actively control its own GPIO pins to switch their level from the second level, representing that it is transmitting, back to the first level, representing that it is idle. This action is manifested in hardware as a falling edge interrupt signal from high to low, and from a software or state machine perspective, it is a clear declaration of "releasing channel occupancy".

[0083] In other words, without this release action, the channel would remain in a busy state indefinitely, rendering the entire protocol inoperable. Secondly, this falling edge itself is a highly efficient activation signal. For another chip polling or waiting for an interrupt, this level transition is a faster and more deterministic notification of channel idleness than any software message. This allows for seamless handover of data transmission, virtually eliminating channel idle windows caused by information transmission delays. Finally, this is also fundamental to ensuring fairness; each chip must unconditionally relinquish the channel after completing its task, and cannot continue to occupy it due to software negligence, thus guaranteeing transmission opportunities for other chips.

[0084] Those skilled in the art will understand that signal changes to achieve the same purpose can also include: after transmission is complete, first driving the GPIO pin to a high-impedance state, and then pulling it back to a high level (or low level) by an external pull-up resistor, forming a slower bounce. Alternatively, in more complex systems, the output of the GPIO pin can be directly controlled by the chip's internal automatic transmission state machine, completing the level switch at a precise point in time before the MAC layer completely releases the RF front-end after the CRC check of the last data byte is completed, thereby maximizing channel utilization.

[0085] For example, in the chip's internal implementation, the MAC layer controller sets a transmission completion flag after completing the transmission of a data frame. This flag can be connected to a combinational logic circuit whose output is directly connected to the data bit of the GPIO output register. Therefore, when the transmission completion flag becomes valid, the output level of the GPIO pin immediately goes low in the next clock cycle, without any software intervention. This automated hardware release process is key to ensuring extremely low channel release latency.

[0086] Therefore, by adopting the above-mentioned active release mechanism that switches the GPIO level immediately after data transmission is completed, the lifecycle management of the entire hardware handshake protocol is improved, the throughput drop caused by the failure to update the channel flag in time is avoided, a smooth data path is provided for the next chip, and finally the channel sharing of the entire system with almost no dead zone is realized.

[0087] In summary, as a concrete example, a car equipped with a smart cockpit system has two WiFi chips: Chip A acts as the main chip, providing personal hotspot services for passengers in the car; Chip B acts as the slave chip, wirelessly connecting to the driver's smartphone to play navigation voice prompts from the phone.

[0088] When the driver starts the vehicle and connects their phone, Chip B establishes a connection with the phone and waits to receive data. Simultaneously, Chip A's background program begins establishing a hotspot, waiting for the passenger's device to connect. At this point, the REQ pins of both chips are low, and the channel is idle. In the first instant: the passenger's tablet requests a high-definition video stream through Chip A's WiFi hotspot. Chip A's MAC layer generates a data packet transmission request. First, Chip A's hardware state machine immediately switches the REQ_A pin from low to high. Within the same clock cycle, it reads the REQ_B pin and finds it still low. Therefore, without any backoff, Chip A immediately begins transmitting video data packets via the wireless channel. Meanwhile, because Chip B's REQ_A pin goes high, its internal interrupt is triggered, indicating that Chip A is occupying the channel. Therefore, Chip B's data to be transmitted (such as navigation voice prompts) is temporarily buffered in its transmission queue. After completing a data packet transmission, Chip A automatically pulls the REQ_A pin back low.

[0089] At the second moment: The instant Chip A finishes sending its first data packet and releases the channel, Chip B needs to send the next navigation voice prompt frame. Since Chip B has been monitoring the REQ_A pin via interrupts during Chip A's transmission, once it detects a falling edge on the REQ_A pin (i.e., the channel release signal), it immediately pulls the REQ_B pin high and begins sending its navigation voice data. At this point, the entire channel handover is smooth and almost delay-free. The user's navigation voice prompts sound fluent and without any stuttering.

[0090] In the third moment: Suppose that the network protocol stacks of Chip A and Chip B generate data packets to be sent almost simultaneously for some reason, and their hardware state machines also simultaneously pull up their respective REQ pins within a nanosecond time difference. At this point, both will encounter a conflict. Assuming the system pre-determines that Chip A has a higher priority than Chip B, Chip B's hardware will continuously monitor the REQ_A pin level of Chip A after detecting that its own REQ_B pin is high. When it detects that the REQ_A pin is high, according to the pre-determined priority rules, Chip B will immediately pull the REQ_B pin low, stop transmitting, and store the data to be transmitted in the transmission queue, while continuously monitoring the level change of the REQ_A pin, waiting for the channel to be released before initiating a transmission request. Chip A, upon detecting that the REQ_B pin is high, compares its own priority with the pre-determined priority and finds that it has a higher priority. Therefore, it keeps the REQ_A pin high and continues to complete its own data packet transmission. After transmission, it pulls the REQ_A pin low to release the channel. Chip B then initiates a transmission request according to the above process after detecting the falling edge, thus avoiding bus conflicts, ensuring that the higher-priority device completes data transmission first, and avoiding delays or stuttering of high-priority data.

[0091] This effectively solves the channel conflict problem when multiple WiFi chips coexist, ensures the transmission latency requirements of high-priority services, and improves the stability and user experience of multi-WiFi devices working together in the vehicle.

[0092] The following is combined with Figure 2 The method described in this application is used to describe the method.

[0093] As a specific example, the data transmission method of this application may include the following steps: S101: If at least one target chip has a data transmission request, obtain the data transmission status of other chips.

[0094] S102, determine whether the target chip is a single chip. If yes, proceed to step S103; if no, proceed to step S106.

[0095] S103, determine whether the data transmission status of other chips is in a non-transmission state. If yes, proceed to step S104; if no, proceed to step S105.

[0096] S104, determine that the data transmission state of the target chip is in a transmittable state, so that the target chip can transmit data on the data transmission channel.

[0097] S105, determine that the data transmission status of the target chip is not transmitted, so that other chips can transmit data on the data transmission channel.

[0098] S106, determine whether there are multiple target chips. If yes, proceed to step S107; otherwise, proceed to step S101.

[0099] S107, if the data transmission status of other chips is not transmitted, the target transmission order of the target chips is determined according to the priority of the data to be transmitted corresponding to the multiple target chips, or the target transmission order is determined according to the set transmission order.

[0100] S108, data transmission is performed based on the target transmission order.

[0101] In summary, the data transmission method according to the embodiments of this application, when at least one target chip has a data transmission request, obtains the data transmission status of other chips, and determines the data transmission status of the target chip based on the data transmission status of the other chips. Therefore, this method allows the target chip to directly learn the transmission status of other chips through inter-chip information interaction before initiating a data transmission request, without relying on traditional passive channel idle assessment and random backoff mechanisms for channel contention. This fundamentally avoids the problems of continuously accumulating packet transmission delays and decreasing channel utilization, achieves real-time negotiation of channel occupancy, effectively reduces the time consumed by multi-chip channel contention, and significantly improves the real-time performance and utilization of shared channel data transmission. It is better suited to application scenarios such as automotive systems where multiple chips share the same communication frequency band, ensuring the efficiency and overall stability of multi-chip collaborative work.

[0102] Corresponding to the above embodiments, this application also proposes a computer-readable storage medium.

[0103] The computer-readable storage medium of this application embodiment stores a program that, when executed by a processor, implements the data transmission method described above.

[0104] According to the computer-readable storage medium of the present application embodiment, by executing the above-described data transmission method, the problems of continuous accumulation of packet transmission delay and decreased utilization of data transmission channel can be avoided. Real-time negotiation of data transmission channel occupancy is realized, effectively reducing the time consumption of multi-chip channel contention, and significantly improving the real-time performance and utilization of shared channel data transmission. It can better adapt to application scenarios such as vehicle systems where multiple chips share the same communication frequency band, ensuring the efficiency and overall stability of multi-chip collaborative work.

[0105] Corresponding to the above embodiments, this application also proposes a vehicle.

[0106] like Figure 3As shown, the vehicle 200 in this embodiment may include: a memory 210, a processor 220, and a program stored in the memory 210 and executable on the processor 220. When the processor 220 executes the program, it implements the data transmission method described above.

[0107] According to the vehicle embodiment of this application, by executing the above-described data transmission method, the problems of continuous accumulation of packet delay and decreased utilization of data transmission channel can be avoided. Real-time negotiation of data transmission channel occupancy is realized, effectively reducing the time consumption of multi-chip channel contention, and significantly improving the real-time performance and utilization of shared channel data transmission. It can better adapt to application scenarios such as vehicle systems where multiple chips share the same communication frequency band, ensuring the efficiency and overall stability of multi-chip collaborative work.

[0108] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0109] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0110] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0111] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0112] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0113] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A data transmission method, characterized in that, The method for multiple chips sharing a single data transmission channel includes: If at least one target chip has a data transmission request, obtain the data transmission status of other chips; The data transmission status of the target chip is determined based on the data transmission status of the other chips.

2. The data transmission method according to claim 1, characterized in that, Determining the data transmission status of the target chip based on the data transmission status of the other chips includes: If the target chip is a single chip, and the data transmission status of the other chips is not transmitted, then the data transmission status of the target chip is determined to be transmittable, so that the target chip can transmit data on the data transmission channel. If the data transmission status of the other chips is in the transmission state, then the data transmission status of the target chip is determined to be in the non-transmission state, so that the other chips can transmit data on the data transmission channel.

3. The data transmission method according to claim 1, characterized in that, Determining the data transmission status of the target chip based on the data transmission status of the other chips includes: When there are multiple target chips, if the data transmission status of the other chips is not transmitted, the target transmission order of the target chips is determined according to the priority of the data to be transmitted corresponding to the multiple target chips, or the target transmission order is determined according to the set transmission order. Data transmission is performed based on the target transmission order.

4. The data transmission method according to claim 1, characterized in that, Each chip is equipped with a general-purpose input / output pin, and the multiple chips are connected to each other through the general-purpose input / output pin. The general-purpose input / output pin is configured in bidirectional mode for sending and receiving level status signals.

5. The data transmission method according to claim 4, characterized in that, The step of obtaining the data transmission status of other chips includes: Obtain the level status signals of the general-purpose input / output pins of the other chips; When the level status signal is at the first level, the data transmission status of the other chips is determined to be in a non-transmission state; When the level status signal is at the second level, the data transmission status of the other chips is determined to be a transmission status.

6. The data transmission method according to claim 5, characterized in that, The plurality of chips includes a target chip and other chips. Determining the data transmission status of the target chip based on the data transmission status of the other chips includes: If the data transmission status of the other chips is determined to be in a transmission state, the target chip is controlled to wait for a preset time. After waiting for the preset time, if the level status signal of the general input / output pin of the other chip switches from the second level to the first level, then the data transmission state of the target chip is determined to be the transmission state, so that the target chip can perform data transmission on the data transmission channel.

7. The data transmission method according to claim 6, characterized in that, The method further includes: If, after waiting for the preset duration, the level status signal of the general-purpose input / output pin of the other chip is at the second level and the duration exceeds the preset timeout threshold, then the data transmission channel is evaluated for idle channel status. If the data transmission channel is determined to be idle, the target chip is controlled to transmit data on the data transmission channel.

8. The data transmission method according to claim 6, characterized in that, The method further includes: After the target chip completes the data transmission on the data transmission channel, the level status signal of the general-purpose input / output pin of the target chip is switched from the second level to the first level.

9. A computer-readable storage medium, characterized in that, It stores a program that, when executed by a processor, implements the data transmission method according to any one of claims 1-8.

10. A vehicle, characterized in that, include: A memory, a processor, and a program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the data transmission method according to any one of claims 1-8.

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