A circuit board, a chip packaging structure and an electronic device

Abstract

Embodiments of the present application provide a circuit board, a chip packaging structure and an electronic device, and relate to the technical field of electronics. The circuit board comprises: a dielectric layer; and a first circuit layer disposed on the dielectric layer. The first circuit layer comprises a first transmission line and a second transmission line disposed adjacently, and a winding portion of the first transmission line and a winding portion of the second transmission line are wound in opposite directions. The far-end crosstalk between parallel transmission lines can be reduced in a low-cost and miniaturized solution.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a circuit board, chip packaging structure, and electronic device. Background Technology

[0002] Far-end crosstalk often exists between parallel lines used for single-ended signal transmission, especially in high-speed parallel interface applications such as double data rate (DDR) / low power double data rate (LPDDR) applications. Far-end crosstalk becomes a key bottleneck restricting system performance, and this problem is particularly serious in wire bond (WB) packaging.

[0003] To address remote crosstalk, conventional solutions include increasing the spacing between parallel traces or adding ground vias for isolation. These measures increase the area of ​​the die, packaged chip, and PCB, which in turn increases costs and hinders low-cost and miniaturization efforts. Summary of the Invention

[0004] Embodiments of this application provide a circuit board, chip package structure, and electronic device that can reduce far-end crosstalk between parallel transmission lines in a low-cost and miniaturized manner.

[0005] In a first aspect, a circuit board is provided, comprising: a dielectric layer; and a first circuit layer disposed on the dielectric layer. The first circuit layer includes a first transmission line and a second transmission line disposed adjacent to each other. The first transmission line includes a winding portion wound in a first manner, and the second transmission line includes a winding portion wound in a second manner, wherein the winding directions of the first and second methods are opposite. For example, the first method may be clockwise winding and the second method may be counterclockwise winding; or, the first method may be counterclockwise winding and the second method may be clockwise winding; or, the first method may involve first clockwise winding and then counterclockwise winding, and the second method may involve first counterclockwise winding and then clockwise winding. In the above scheme, by constructing opposite winding (mutually reverse winding) winding sections on two adjacent transmission lines, the reverse mutual inductance between the two signal streams transmitted on the two transmission lines is increased, thereby reducing the forward mutual inductance of the two transmission lines and thus reducing far-end crosstalk. The closer the spacing between the winding sections of the two transmission lines, the better the effect of far-end crosstalk elimination through the opposite winding sections, which allows for the design of transmission line layouts in a smaller size. Furthermore, since the two transmission lines can be deployed on the same line layer, they only occupy one layer of wiring space, which is beneficial for cost savings and miniaturization.

[0006] In one possible implementation, the first circuit layer further includes a first electrode and a second electrode; the first transmission line includes a first end and a second end, and a winding portion of the first transmission line is connected between the first end and the second end; the second transmission line includes a first end and a second end, and a winding portion of the second transmission line is connected between the first end and the second end; the first end of the first transmission line is connected to the first electrode, and the first end of the second transmission line is connected to the second electrode. Placing the first transmission line, the second transmission line, the winding portion of the first transmission line, and the winding portion of the second transmission line on the same layer as the electrodes on the circuit board simplifies the manufacturing process. Typically, the upper electrode of the circuit board can be an electrode for soldering solder balls, a wire bonding (or wire bonding, WB) electrode, or a gold finger.

[0007] In one possible implementation, the winding portion of the first transmission line is wound around the periphery of the first electrode; the winding portion of the second transmission line is wound around the periphery of the second electrode. This arrangement can minimize the area occupied on the circuit board.

[0008] In one possible implementation, a second circuit layer is further included on the dielectric layer; the second circuit layer includes a third transmission line and a fourth transmission line; the second end of the first transmission line is connected to the third transmission line through a first via on the dielectric layer; the second end of the second transmission line is connected to the fourth transmission line through a second via on the dielectric layer. The first circuit layer and the second circuit layer can be respectively disposed on opposite sides of the dielectric layer. Alternatively, when the circuit board is a multilayer board, the first circuit layer and the second circuit layer can be any two circuit layers in the multilayer board. The first and second vias include, but are not limited to, metallized through-holes (e.g., plated through-holes, PTHs) and vias. Typically, one end of the first via can be on the same circuit layer as the first transmission line (e.g., the first circuit layer), and the other end can be on the same circuit layer as the third transmission line (e.g., the second circuit layer). Similarly, one end of the second via can be on the same circuit layer as the second transmission line (e.g., the first circuit layer), and the other end can be on the same circuit layer as the fourth transmission line (e.g., the second circuit layer). Thus, by connecting the first transmission line of the first circuit layer and the third transmission line of the second circuit layer through the first via, and by connecting the second transmission line of the first circuit layer and the fourth transmission line of the second circuit layer through the second via, an example of implementing this scheme on a multilayer board is achieved.

[0009] In one possible implementation, a second circuit layer disposed on the dielectric layer is further included; the second circuit layer includes a first electrode and a second electrode; the first transmission line includes a first end and a second end, and a wound portion of the first transmission line is connected between the first end and the second end of the first transmission line; the second transmission line includes a first end and a second end, and a wound portion of the second transmission line is connected between the first end and the second end of the second transmission line; the first end of the first transmission line is connected to the first electrode through a first via on the dielectric layer; the first end of the second transmission line is connected to the second electrode through a second via on the dielectric layer. In this scheme, the electrode and the first transmission line (and the second transmission line) can be located on different circuit layers.

[0010] In one possible implementation, the winding portion of the first transmission line is wound around the periphery of the first end of the first transmission line; the winding portion of the second transmission line is wound around the periphery of the first end of the second transmission line.

[0011] In one possible implementation, the dielectric layer further includes at least one of the following vias: a third via connecting a first end of the first via to a first end of the first transmission line; a fourth via connecting a second end of the first via to a first electrode; a fifth via connecting a first end of the second via to a first end of the second transmission line; and a sixth via connecting a second end of the second via to a second electrode. This possible implementation can be achieved on multilayer boards with different layers by selectively providing one or more of the third to sixth vias.

[0012] In one possible implementation, the first electrode and the second electrode are used for the solder pads or for the gold fingers.

[0013] In one possible implementation, the winding portion comprises multiple transmission line segments connected in sequence.

[0014] In one possible implementation, the multiple transmission segments include any one or more of the following: rectangular transmission segments and elliptical transmission segments.

[0015] In one possible implementation, the transmission line of the winding portion is a continuous arc-shaped line segment.

[0016] In one possible implementation, the transmission line of the winding portion is provided with comb teeth extending in a direction perpendicular to the transmission line.

[0017] In one possible implementation, the winding portion is wound around a reference point, and the arc occupied by the winding portion with the reference point as the center is greater than or equal to 90°. The winding portion of the transmission line can use an electrode PAD (or pad), Via, PTH, or gold finger as a reference point, and be wound with that reference point as the center. Typically, to ensure effective reverse mutual inductance, when the winding portion is wound around the reference point, the arc occupied by the winding portion with the reference point as the center is greater than or equal to 90°.

[0018] In one possible implementation, the circuit board includes any of the following: a packaging substrate, a carrier board, and a printed circuit board (PCB).

[0019] In one possible implementation, both the first transmission line and the second transmission line are used to transmit single-ended signals.

[0020] In a second aspect, a chip packaging structure is provided, including a chip and a packaging substrate; the packaging substrate is the circuit board described in the first aspect and any possible implementation thereof.

[0021] Thirdly, a chip packaging structure is provided, including a chip, a packaging substrate, and a carrier board; the packaging substrate is the circuit board described in the first aspect and any possible implementation of the first aspect; and / or, the carrier board is the carrier board described in the first aspect and any possible implementation of the first aspect.

[0022] Fourthly, a chip packaging structure is provided, including a chip, an adapter board, and a packaging substrate; the packaging substrate is the circuit board described in the first aspect and any possible implementation thereof.

[0023] Fifthly, an electronic device is provided, including a chip packaging structure and a printed circuit board; the chip packaging structure is any one of the chip packaging structures described in the second to fourth aspects, and / or the printed circuit board is the circuit board described in the first aspect and any possible implementation of the first aspect.

[0024] The technical problems solved and the technical effects achieved by the solutions provided in the second to fifth aspects can be referred to the relevant descriptions in the first aspect and its possible implementation methods, and will not be repeated here. Attached Figure Description

[0025] Figure 1 A schematic diagram of the structure of an electronic device provided for an embodiment of this application;

[0026] Figure 2 A schematic diagram of a chip packaging structure and a PCB structure provided for embodiments of this application. Figure 1 ;

[0027] Figure 3 A schematic diagram of a chip packaging structure and a PCB structure provided for embodiments of this application. Figure 2 ;

[0028] Figure 4 A schematic diagram of a chip packaging structure and a PCB structure provided for embodiments of this application. Figure 3 ;

[0029] Figure 5 A transmission line differential equivalent circuit diagram is provided for embodiments of this application;

[0030] Figure 6 A transmission line differential equivalent circuit diagram is provided for another embodiment of this application;

[0031] Figure 7 A schematic diagram of a circuit board structure provided for an embodiment of this application;

[0032] Figure 8 A top view of a circuit board is provided as another embodiment of this application;

[0033] Figure 9 A schematic diagram of the front view structure of a circuit board is provided for another embodiment of this application;

[0034] Figure 10 A schematic diagram of a circuit board structure provided for another embodiment of this application;

[0035] Figure 11 A schematic diagram of the structure of a winding portion provided for an embodiment of this application;

[0036] Figure 12 A schematic diagram of a transmission line segment provided for an embodiment of this application;

[0037] Figure 13 A partial structural schematic diagram of a circuit board provided for an embodiment of this application;

[0038] Figure 14 The simulation results of a circuit board provided for the embodiments of this application are intended to illustrate the purpose of this application. Figure 1 ;

[0039] Figure 15 The simulation results of a circuit board provided for the embodiments of this application are intended to illustrate the purpose of this application. Figure 2 ;

[0040] Figure 16 The simulation results of a circuit board provided for the embodiments of this application are intended to illustrate the purpose of this application. Figure 3 ;

[0041] Figure 17The simulation results of a circuit board provided for the embodiments of this application are intended to illustrate the purpose of this application. Figure 4 . Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0043] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0044] In the embodiments of this application, directional terms such as "up," "down," "left," and "right" may be defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0045] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. In the embodiments of this application, "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0046] In this application, unless the context otherwise requires, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to," throughout the specification and claims. In the description, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0047] Exemplary embodiments are described in this application with reference to cross-sectional views and / or plan views and / or equivalent circuit diagrams, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0048] This application provides an electronic device. This electronic device can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, a financial terminal product, or a communication electronics product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and rechargeable small household appliances (e.g., soymilk makers, robot vacuum cleaners). In-vehicle electronics products include in-vehicle navigation systems and in-vehicle high-density digital video discs (DVDs). Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics products include servers, storage devices, base stations, and other communication equipment.

[0049] This application does not impose any special limitations on the specific form of the above-described electronic device. For ease of explanation, the following embodiments all use a mobile phone as an example.

[0050] In this case, such as Figure 1 As shown, the electronic device 1 mainly includes a display module 2, a middle frame 3, a housing (or battery cover, back cover) 4, and a cover plate 5.

[0051] The display module 2 has a light-emitting side from which the display image can be seen and a back side opposite to the light-emitting side. The back side of the display module 2 is close to the middle frame 3, and the cover plate 5 is disposed on the light-emitting side of the display module 2.

[0052] The aforementioned display module 2 includes a display panel (DP). In one possible embodiment of this application, the display panel is a liquid crystal display (LCD). Alternatively, in another possible embodiment of this application, the display panel is an organic light-emitting diode (OLED) display.

[0053] The cover plate 5 is located on the side of the display module 2 away from the middle frame 3. The cover plate 5 can be, for example, a cover glass (CG), which can have a certain degree of toughness.

[0054] The middle frame 3 is located between the display module 2 and the housing 4. The surface of the middle frame 3 away from the display module 2 is used to mount internal components such as batteries, printed circuit boards (PCBs), cameras, and antennas. After the housing 4 is closed with the middle frame 3, the aforementioned internal components are located between the housing 4 and the middle frame 3.

[0055] like Figure 2 As shown, the aforementioned electronic device 1 also includes chips disposed on the PCB. The chips may include a processor (CPU) chip, a radio frequency chip, a radio frequency power amplifier (PA) chip, a system on a chip (SOC), a power management integrated circuit (PMIC), a memory chip (e.g., high bandwidth memory (HBM)), an audio processor chip, a touch screen control chip, NAND flash memory, an image sensor chip, a charging protection chip, etc. The PCB is used to carry the aforementioned chips and to complete signal interaction with the aforementioned chips.

[0056] In Example 1, as Figure 2 As shown, the bare die is placed on the packaging substrate, and after being bonded to the packaging substrate to form a chip package structure, the packaging substrate is bonded to the PCB.

[0057] In Example 2, as Figure 3 As shown, the bare chip is mounted on a packaging substrate, which is bonded to a carrier board to form a chip package structure. The carrier board is then bonded to a PCB. This chip package structure can be referred to as a dual-substrate package structure, for example.

[0058] In Example 3, as Figure 4As shown, the bare chip is bonded to the adapter board, and the adapter board is bonded to the packaging substrate to form a chip package structure. Finally, the packaging substrate is bonded to the PCB. This chip package structure can be referred to as a 2.5D package structure, for example.

[0059] Of course, bare chips can also be directly bonded to the PCB, and this application does not limit this. Figures 2 to 4 The examples provided are merely some of the embodiments of this application. The embodiments of this application include, but are not limited to, flip-chip (FC) packaging, WB packaging, and other forms. The solutions provided by the embodiments of this application are not limited to DDR / LPDDR, high bandwidth memory (HBM), die-to-die interconnect, and other parallel port interconnect scenarios for single-ended signals.

[0060] Currently, in products using the aforementioned packaging methods, far-end crosstalk often exists between parallel lines (transmission lines) used for single-ended signal transmission. This is especially problematic in high-speed parallel interface applications, where far-end crosstalk becomes a critical bottleneck restricting system performance. This issue is particularly severe in wire-bonded packages. Conventional solutions to address far-end crosstalk include increasing the spacing between parallel lines or adding ground vias (which improve the signal-to-ground ratio). However, these measures increase the area of ​​the die, packaged chip, and PCB, leading to higher costs and hindering cost reduction and miniaturization.

[0061] The following description uses a model of two transmission lines configured with lossless coupling, typically referring to... Figure 5 As shown, a differential equivalent circuit is provided for two transmission lines (first transmission line 12 and second transmission line 13) configured in a lossless coupling manner. Among them, Figure 5 The first transmission line 12 carries a current i1(z), and the second transmission line carries a current i2(z); the first transmission line 12 carries a ground voltage V1(z), and the second transmission line 13 carries a ground voltage V2(z); after transmission over a unit length dz, the first transmission line 12 outputs a current i1(z+dz), the second transmission line outputs a current i2(z+dz); the first transmission line 12 inputs a ground voltage V1(z+dz), and the second transmission line 13 inputs a ground voltage V2(z+dz). Where L S (L S1 / L S2 L represents the self-inductance per unit length (dz) of a single transmission line. M C represents the mutual inductance of two transmission lines per unit length. M C represents the mutual capacitance between two transmission lines per unit length. g (C g1 / C g2The figure represents the capacitance per unit length of a single transmission line to ground (GND). If the first transmission line 12 is considered the attacking line and the second transmission line 13 is considered the victim line, then the fear-end crosstalk (FEXT) experienced on the second transmission line 13 is:

[0062] Where k is a constant, and C in equation (1) g It is the capacitance to ground of the damaged line, L S It is the self-perception of the victim line.

[0063] Based on the above Figures 2-4 The descriptions of various packaging methods typically involve deploying the aforementioned transmission lines on circuit boards such as packaging substrates, carrier boards, and PCBs. To achieve interconnection between chips and between chips and PCBs, transmission lines are usually connected via structures perpendicular to the circuit board (also known as Z-axis structures, such as vias (Through Silicon Via, TSV, PTH, etc.), solder balls, connectors, wire bonding (WB), etc.). The following relationship exists regarding the far-end crosstalk introduced by these Z-axis structures and parallel transmission lines on the same layer:

[0064]

[0065] Based on equation (2), it can be found that far-end crosstalk can be reduced in the following ways: A. Increase the capacitive coupling coefficient: such as increasing the mutual capacitance of the two interconnect structures C M Or reduce the ground self-containment C of a single structure. g B. Reduce the inductive coupling coefficient: Increase the self-inductance L S Signal path (e.g.) Figure 5 (transmission lines in the middle) and return paths (such as...) Figure 5 The positive mutual inductance L can be increased or decreased on the circuit connected to GND. M Increase reverse mutual inductance L ’ M To cancel out inductance.

[0066] For reducing positive mutual inductance L M , refer to Figure 6 As shown, this is equivalent to adding a reverse mutual inductance L to the first transmission line 12 and the second transmission line 13. ’ M In the examples described below, the main approach involves constructing reciprocal winding sections on two adjacent transmission lines (e.g., forming a clockwise winding section on one transmission line and a counterclockwise winding section on the other transmission line) to increase the reverse mutual inductance L' between the two single-ended signals transmitted on the two transmission lines. MThis reduces forward mutual inductance, thereby lowering far-end crosstalk. Furthermore, since two transmission lines can be deployed on the same line layer, only one layer of wiring space is required, which is beneficial for cost savings and miniaturization. Especially in scenarios with high signal-to-ground ratios (the ratio of signal balls to ground balls in a chip package structure), it eliminates the need for more isolated ground balls (more ground balls require larger package sizes and higher costs), achieving lower far-end crosstalk.

[0067] Specifically, the following examples mainly illustrate the specific structures of the packaging substrate, PCB, and carrier provided in the embodiments of this application. In some examples, a circuit board is provided, which can be any of the packaging substrate, PCB, and carrier in the above examples.

[0068] Reference Figure 7 As shown, the circuit board includes: a dielectric layer 11; a first circuit layer P1 disposed in the dielectric layer 11, the first circuit layer P1 including a first transmission line 12 and a second transmission line 13 disposed adjacently, the first transmission line 12 including a winding portion Cl1 wound in a first manner, and the second transmission line 13 including a winding portion Cl2 wound in a second manner, wherein the winding directions of the first manner and the second manner are opposite.

[0069] In some examples, the first method can be clockwise winding, and the second method can be counterclockwise winding; or, the first method can be counterclockwise winding, and the second method can be clockwise winding; or, the first method can be clockwise winding followed by counterclockwise winding, and the second method can be counterclockwise winding followed by clockwise winding. Figure 7 The diagram also shows the direction of signal flow in the two transmission lines. When the signal flow in the two transmission lines flows in from the same side, the flow direction of the signal flow in the winding section of the two transmission lines is opposite to that of the winding section mentioned above.

[0070] By constructing opposite (reverse) winding sections on two adjacent transmission lines (for example, forming a clockwise winding section on one transmission line and a counterclockwise winding section on the other transmission line), the reverse mutual inductance between the two signal streams transmitted on the two transmission lines is increased, thereby reducing the forward mutual inductance of the two transmission lines and thus reducing far-end crosstalk. The closer the spacing between the winding sections of the two transmission lines, the better the effect of far-end crosstalk cancellation through the opposite winding sections. This allows for the design of transmission line layouts in smaller sizes, and since the two transmission lines can be deployed on the same line layer, they only occupy one layer of wiring space, which is beneficial for cost savings and miniaturization.

[0071] Reference Figure 8and Figure 9 As shown, the first circuit layer P1 further includes a first electrode PAD1 and a second electrode PAD2; the first transmission line 12 includes a first end and a second end, and the winding portion Cl1 of the first transmission line 12 is connected between the first end and the second end of the first transmission line 12; the second transmission line 13 includes a first end and a second end, and the winding portion Cl2 of the second transmission line 13 is connected between the first end and the second end of the second transmission line 13; the first end of the first transmission line 12 is connected to the first electrode PAD1, and the first end of the second transmission line 13 is connected to the second electrode PAD2.

[0072] Among them, in Figure 8 and Figure 9 In this circuit, the first transmission line 12, the second transmission line 13, the winding portion Cl1 of the first transmission line 12, and the winding portion Cl2 of the second transmission line 13 can be disposed on the same layer as the electrodes on the circuit board, thereby simplifying the manufacturing process. Typically, the electrodes on the circuit board can be solder pads for soldering, wire bonding (or wire bonding, WB) electrodes, or gold fingers, etc. Typically, Z-axis structures on the circuit board are located near the electrodes, such as solder balls, connectors, etc.

[0073] In some examples, the winding portion Cl1 of the first transmission line 12 is wound around the periphery of the first electrode PAD1; the winding portion Cl2 of the second transmission line 13 is wound around the periphery of the second electrode PAD2. (Refer to...) Figure 8 As shown, when the first electrode PAD1 and the second electrode PAD2 are used to solder solder balls (B1 / B2), this arrangement can save the area of ​​the circuit board occupied as much as possible.

[0074] Reference Figure 8 and Figure 9 As shown, the circuit board also includes a dielectric layer 11 (wherein, refer to...). Figure 7 As shown, Figure 8 and Figure 9 The second line layer P2 (not shown) is located on the circuit board. The second line layer P2 includes a third transmission line 14 and a fourth transmission line 15 arranged adjacent to each other. In some examples, the first line layer P1 and the second line layer P2 may be respectively disposed on both sides of the dielectric layer 11. In addition, when the circuit board is a multilayer board, the first line layer P1 and the second line layer P2 may be any two line layers in the multilayer board. The signal flow input from the third transmission line 14 flows counterclockwise when it flows through the winding portion Cl1 of the first transmission line 12, and the signal flow input from the fourth transmission line 15 flows clockwise when it flows through the winding portion Cl2 of the second transmission line 13.

[0075] The second end of the first transmission line 12 is connected to the third transmission line 14 through the first via H1 on the dielectric layer 11; the second end of the second transmission line 13 is connected to the fourth transmission line 15 through the second via H2 on the dielectric layer 11. The first via H1 and the second via H2 include, but are not limited to, metallized vias (e.g., PTH and Via). Typically, one end of the first via H1 can be on the same circuit layer as the first transmission line 12 (e.g., first circuit layer P1), and the other end can be on the same circuit layer as the third transmission line 14 (e.g., second circuit layer P2). Similarly, one end of the second via H2 can be on the same circuit layer as the second transmission line 13 (e.g., first circuit layer P1), and the other end can be on the same circuit layer as the fourth transmission line 15 (e.g., second circuit layer P2). Thus, by connecting the first transmission line 12 of the first circuit layer P1 and the third transmission line 14 of the second circuit layer P2 through the first via H1, and by connecting the second transmission line 13 of the first circuit layer P1 and the fourth transmission line 15 of the second circuit layer P2 through the second via H2, an example of implementing this scheme on a multilayer board is achieved. Furthermore, as... Figure 9 As shown, the third transmission line 14 and the fourth transmission line 15 can also be interconnected with other structures (e.g., die pads, electrodes of bare chips) via a WB (wire-by-wire) method, where far-end crosstalk formed on the WB can be canceled out by the oppositely wound portions of the two transmission lines. Furthermore, Figure 9 If the structure in the middle adopts the plating line (PL) process, then in Figure 9 The paper also shows electroplating leads PL1 and PL2 of the electroplating line process, wherein electroplating lead PL1 is connected to the third transmission line 14, and electroplating lead PL2 is connected to the fourth transmission line 15.

[0076] Reference Figure 10 As shown, the circuit board also includes a second circuit layer P2 disposed on the dielectric layer; the second circuit layer P2 includes a first electrode PAD1 and a second electrode PAD2; the first transmission line 12 includes a first end and a second end, and the winding portion Cl1 of the first transmission line 12 is connected between the first end and the second end of the first transmission line 12; the second transmission line 13 includes a first end and a second end, and the winding portion Cl2 of the second transmission line 13 is connected between the first end and the second end of the second transmission line 13; the first end of the first transmission line 12 is connected to the first electrode PAD1 through a first via H1 on the dielectric layer; the first end of the second transmission line 13 is connected to the second electrode PAD2 through a second via H2 on the dielectric layer. In this example, the circuit board can still be a single-layer board, and includes two circuit layers P1 and P2 located on the dielectric layer, which is different from... Figure 8 and Figure 9In this example, the electrodes and the first transmission line (and the second transmission line) are located on different circuit layers. The first via H1 and the second via H2 include, but are not limited to, metallized vias (e.g., PTH) and vias.

[0077] Reference Figure 10 As shown, the winding portion Cl1 of the first transmission line 12 is wound around the periphery of the first via H1; the winding portion of the second transmission line 13 is wound around Cl2 around the periphery of the second via H2.

[0078] Still refer to Figure 10 As shown, the dielectric layer also includes a third via H3 connected between the first end of the first via H1 and the first end of the first transmission line 12, and a fourth via H4 connected between the second end of the first via H1 and the first electrode PAD1; the dielectric layer also includes a fifth via H5 connected between the first end of the second via H2 and the first end of the second transmission line 13, and a sixth via H6 connected between the second end of the second via H2 and the second electrode PAD2.

[0079] In this example, the third via H3, the fourth via H4, the fifth via H5, and the sixth via H6 can all be Via; where, Figure 10 This explanation uses a four-layer circuitry system as an example. Of course, by adjusting the position and number of vias, it can also be applied to circuit boards with other layer counts. Thus, by selectively setting one or more of the third via H3 to the sixth via H6, this solution can be implemented on multilayer boards with different layers.

[0080] In addition, refer to Figure 11 As shown, and in conjunction with the description of the example above, the winding portion Cl of the transmission line can be wound with the electrode PAD (or pad), Via, PTH, or gold finger as the reference point and with the reference point as the center. Usually, in order to ensure the formation of effective reverse mutual inductance, when the winding portion is wound around the reference point, the arc occupied by the winding portion with the reference point as the center is greater than or equal to 90°.

[0081] In some examples, the present invention does not limit the shape of the transmission line in the winding portion; that is, a transmission line of any shape can be designed according to the shape design requirements of the transmission line. (Refer to...) Figure 11 As shown, the winding portion Cl includes multiple transmission segments connected in sequence. These transmission segments can be regular shapes, such as circles, rectangles, or polygons. In some examples, the multiple transmission segments may also include any one or more of the following: rectangular transmission segments (see reference). Figure 12 (1) in the middle) and the elliptical transmission line segment (refer to) Figure 12 (3)). For example, the transmission line of the winding section is a continuous arc segment (see (see...). Figure 12(2) in the middle.

[0082] Additionally, the transmission line segment can be an irregular shape with defects, for example, refer to Figure 12 In (4), the transmission line of the winding section is provided with comb teeth extending in a direction perpendicular to the transmission line, thereby adding a comb-shaped slow wave structure or other defective transmission line structure to the winding section.

[0083] Combination Figure 13 The diagram shows a partial structure of a circuit board, which can be deployed in a similar manner. Figure 9 The specific structure of the circuit board shown can be described in reference to section 9. In the simulation experiment, it is taken as being deployed on a packaging substrate. The benefit is evaluated using the following scenario: the packaging substrate is bonded to a PCB with a thickness of 1.2mm, and the LPDDR4X speed is 3.2Gbps. Combined with... Figure 14 As shown, the embodiments of this application provide solutions for far-end crosstalk at different frequencies, as well as related technologies without a winding transmission line. The solution provided by the embodiments of this application has a far-end crosstalk of -36.5334 dB in the 4.8 GHz frequency domain, while related technologies without a winding transmission line have a far-end crosstalk of -25.7485 dB in the 4.8 GHz frequency domain. Compared with related technologies without a winding transmission line, the solution provided by the embodiments of this application has a far-end crosstalk gain of approximately 11.2 dB in the 4.8 GHz frequency domain.

[0084] Combination Figure 15 As shown, the solutions provided by the embodiments of this application and the far-end crosstalk voltage (V) of related technology 1 without a winding transmission line are presented at different time (s). From the time domain perspective, the solution provided by the embodiments of this application reduces the far-end crosstalk voltage in the time domain from 110mV (millivolts) to 45mV compared to related technology 1; the result is a significant reduction in the far-end crosstalk voltage in the time domain, with a gain of 59%.

[0085] Combination Figure 16 and Figure 17 As shown, where Figure 17 Eye diagrams of solutions provided for embodiments of this application. Figure 16 This is an eye diagram of related technology one, which does not include a winding portion of the transmission line. A larger eye width results in a greater signal timing margin; a larger eye height results in better signal quality and integrity. The solution provided in this application increases the eye width from 112 ps to 132 ps (the larger the eye width, the better) compared to the eye diagram of related technology one, a gain of 17.8%; and increases the eye height from 227 mV to 237 mV (the larger the eye height, the better), a gain of 4.4%.

[0086] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A circuit board, characterized in that, include: Dielectric layer; A first circuit layer disposed on the dielectric layer; The first line layer includes a first transmission line and a second transmission line arranged adjacent to each other. The first transmission line includes a winding portion wound in a first manner, and the second transmission line includes a winding portion wound in a second manner, wherein the winding directions of the first manner and the second manner are opposite.

2. The circuit board according to claim 1, characterized in that, The first circuit layer also includes a first electrode and a second electrode; The first transmission line includes a first end and a second end, and the wound portion of the first transmission line is connected between the first end and the second end; the second transmission line includes a first end and a second end, and the wound portion of the second transmission line is connected between the first end and the second end. The first end of the first transmission line is connected to the first electrode, and the first end of the second transmission line is connected to the second electrode.

3. The circuit board according to claim 2, characterized in that, The winding portion of the first transmission line is wound around the periphery of the first electrode; The winding portion of the second transmission line is wound around the periphery of the second electrode.

4. The circuit board according to claim 2 or 3, characterized in that, It also includes a second circuit layer disposed on the dielectric layer; The second line layer includes a third transmission line and a fourth transmission line arranged adjacent to each other; The second end of the first transmission line is connected to the third transmission line through a first via on the dielectric layer; The second end of the second transmission line is connected to the fourth transmission line through a second via on the dielectric layer.

5. The circuit board according to claim 1, characterized in that, It also includes a second circuit layer disposed on the dielectric layer; the second circuit layer includes a first electrode and a second electrode; The first transmission line includes a first end and a second end, and the wound portion of the first transmission line is connected between the first end and the second end; the second transmission line includes a first end and a second end, and the wound portion of the second transmission line is connected between the first end and the second end. The first end of the first transmission line is connected to the first electrode through a first via on the dielectric layer; The first end of the second transmission line is connected to the second electrode through a second via on the dielectric layer.

6. The circuit board according to claim 5, characterized in that, The winding portion of the first transmission line is wound around the periphery of the first via; The winding portion of the second transmission line is wound around the periphery of the second via.

7. The circuit board according to claim 5 or 6, characterized in that, The dielectric layer further includes at least one of the following vias: A third via connecting the first end of the first via and the first end of the first transmission line; A fourth via connecting the second end of the first via to the first electrode; A fifth via connecting the first end of the second via and the first end of the second transmission line; A sixth via is connected between the second end of the second via and the second electrode.

8. The circuit board according to any one of claims 2-7, characterized in that, The first electrode and the second electrode are used for solder pads or for gold fingers.

9. The circuit board according to any one of claims 1-8, characterized in that, The winding section includes multiple transmission line segments connected in sequence.

10. The circuit board according to claim 9, characterized in that, The plurality of transmission segments include any one or more of the following: rectangular transmission segments and elliptical transmission segments.

11. The circuit board according to any one of claims 1-8, characterized in that, The transmission line of the winding portion is a continuous arc-shaped line segment.

12. The circuit board according to any one of claims 1-8, characterized in that, The winding portion has comb teeth extending along the transmission line in a direction perpendicular to the transmission line.

13. The circuit board according to any one of claims 1-12, characterized in that, The winding portion is wound around the reference point, and the arc occupied by the winding portion with the reference point as the center is greater than or equal to 90°.

14. The circuit board according to any one of claims 1-12, characterized in that, The circuit board includes any of the following: a packaging substrate, a carrier board, and a printed circuit board (PCB).

15. The circuit board according to any one of claims 1-13, characterized in that, Both the first transmission line and the second transmission line are used to transmit single-ended signals.

16. A chip packaging structure, characterized in that, Including chips and packaging substrates; The packaging substrate is the circuit board according to any one of claims 1-15.

17. A chip packaging structure, characterized in that, This includes chips, packaging substrates, and carrier boards; The packaging substrate is a circuit board as described in any one of claims 1-15; and / or, the carrier board is a circuit board as described in any one of claims 1-15.

18. A chip packaging structure, characterized in that, This includes chips, adapter boards, and packaging substrates; The packaging substrate is the circuit board according to any one of claims 1-15.

19. An electronic device, characterized in that, This includes chip packaging structure and printed circuit boards; The chip packaging structure is the chip packaging structure according to any one of claims 16-18, and / or the printed circuit board is the circuit board according to any one of claims 1-15.

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