Circuit board and method of manufacturing the same

Abstract

The application discloses a circuit board and a manufacturing method thereof. The circuit board comprises an inner circuit substrate, a first adhesive layer, a second adhesive layer, a first outer circuit substrate and a second outer circuit substrate. The inner circuit substrate comprises a first dielectric layer and a first inner circuit layer. A coplanar waveguide structure is embedded in the first dielectric layer. The coplanar waveguide structure is exposed on the first dielectric layer and connected with the first inner circuit layer. The coplanar waveguide structure comprises a signal line and ground lines located on opposite sides of the signal line. The signal line and the ground lines are arranged with the first dielectric layer in between. The first adhesive layer covers the surface of the first inner circuit layer. The first adhesive layer is provided with a first cavity penetrating through the first adhesive layer and the first inner circuit layer. The coplanar waveguide structure is exposed from the first cavity. The second adhesive layer covers one side of the first dielectric layer away from the first adhesive layer.

Description

Technical Field

[0001] This application relates to the field of circuit boards, and more particularly to a circuit board and a method for manufacturing the same. Background Technology

[0002] As mid-to-high-end consumer electronics products continue to be updated and iterated, their requirements for high frequency and high speed are becoming increasingly stringent, while also pursuing low material loss. Currently, materials such as polytetrafluoroethylene (PTFE) are commonly used to cover signal lines, resulting in significant dielectric loss and substantial signal attenuation in the transmission lines. Summary of the Invention

[0003] In view of this, this application provides a circuit board that can solve the above-mentioned technical problems and a method for manufacturing the same.

[0004] The first aspect of this application provides a circuit board, comprising:

[0005] An internal circuit board includes a first dielectric layer and a first internal circuit layer. A coplanar waveguide structure is embedded in the first dielectric layer. The coplanar waveguide structure is exposed in the first dielectric layer and connected to the first internal circuit layer. The coplanar waveguide structure includes a signal line and a ground line located on opposite sides of the signal line. The signal line and the ground line are arranged with a gap between the first dielectric layer.

[0006] A first adhesive layer covers the surface of the first inner circuit layer. The first adhesive layer has a first cavity penetrating the first adhesive layer and the first inner circuit layer. The coplanar waveguide structure is exposed from the first cavity.

[0007] A second adhesive layer covers the side of the first dielectric layer that is opposite to the first adhesive layer;

[0008] A first external circuit board covers the surface of the first adhesive layer opposite to the first dielectric layer and is electrically connected to the first internal circuit layer; and...

[0009] The second external circuit board covers the surface of the second adhesive layer that is away from the first dielectric layer.

[0010] A second aspect of this application provides a method for manufacturing a circuit board, comprising:

[0011] A first substrate is provided, the first substrate includes a first dielectric layer, and a plurality of first through slots are formed in the first dielectric layer, the first through slots penetrating the first dielectric layer and being arranged at intervals;

[0012] A first electroplated layer is formed on one side of the first dielectric layer. The first electroplated layer fills the first through-groove to form a coplanar waveguide structure. The coplanar waveguide structure includes a signal line and a ground line. The ground line is located on opposite sides of the signal line to form an internal circuit substrate.

[0013] A second substrate, a first adhesive layer, a third substrate, and a second adhesive layer are provided. A first window is formed on the surface of the first adhesive layer, and the first window penetrates the first adhesive layer.

[0014] The second substrate, the first adhesive layer, the inner circuit substrate, the second adhesive layer, and the third substrate are stacked and pressed in sequence, such that the first adhesive layer covers one side of the inner circuit substrate, the second adhesive layer covers the side of the inner circuit substrate away from the first adhesive layer, the second substrate covers the surface of the first adhesive layer away from the inner circuit substrate, and the third substrate covers the surface of the second adhesive layer away from the inner circuit substrate. The first opening is connected to the first through slot to form a first cavity on the surface of the coplanar waveguide structure.

[0015] The second substrate and the third substrate are fabricated to form a first external circuit substrate and a second external circuit substrate.

[0016] The circuit board provided in this application has a coplanar waveguide structure to improve the frequency and speed of signals. By setting a first cavity on the surface of the coplanar waveguide structure to reduce the dielectric constant between the coplanar waveguide structure and the dielectric layer, signal loss is reduced. Attached Figure Description

[0017] Figure 1 This is a cross-sectional schematic diagram of a first substrate and a first through groove provided in one embodiment of this application.

[0018] Figure 2 In order to be in Figure 1 The diagram shows a cross-sectional view of a coplanar waveguide structure formed by electroplating in the first through slot.

[0019] Figure 3 In order to be in Figure 2 The diagram shows a cross-sectional view of the coplanar waveguide structure with a first groove and a second groove on both sides.

[0020] Figure 4 A cross-sectional schematic diagram of a second substrate, a first adhesive layer, an internal circuit substrate, a second adhesive layer, and a third substrate provided in an embodiment of this application.

[0021] Figure 5 For pressing Figure 4 The diagram shows a cross-sectional view of the structure that forms the first cavity and the second cavity.

[0022] Figure 6 This is a cross-sectional schematic diagram of a circuit board provided in one embodiment of this application.

[0023] Explanation of main component symbols

[0024]

[0025] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0026] To better understand the above-mentioned objectives, features, and advantages of the embodiments of this application, the application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the features in the embodiments of this application can be combined with each other.

[0027] The following description sets forth numerous specific details to provide a thorough understanding of the embodiments of this application. The described implementations are only a portion, not all, of the embodiments described herein. All other implementations obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of the embodiments of this application.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this application belong. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application.

[0029] Please see Figures 1 to 6 This application provides a method for manufacturing a circuit board 100, including the following steps:

[0030] S1: Please refer to Figure 1 A first substrate 11 is provided. The first substrate 11 includes a first dielectric layer 10. A plurality of first through slots 10a are formed in the first dielectric layer 10. The first through slots 10a penetrate the first dielectric layer 10 and are arranged at intervals.

[0031] In this embodiment, please refer to the relevant documentation. Figure 2 The number of first through slots 10a is three, so that subsequent electroplating can form one signal line 31 and two ground lines 32.

[0032] In this embodiment, the first substrate 11 further includes a first metal layer 21 and a second metal layer 22 covering the opposite surfaces of the first dielectric layer 10. Before forming the first through-hole 10a in the first dielectric layer 10, the first metal layer 21 can be pre-etched to facilitate forming the first through-hole 10a through the first metal layer 21 in the first dielectric layer 10. Covering the opposite surfaces of the first dielectric layer 10 with the first metal layer 21 and the second metal layer 22 can enhance the adhesion and reliability between the electroplating material and the first dielectric layer 10. In other embodiments, the adhesion and reliability between the electroplating material and the first dielectric layer 10 can also be enhanced by applying copper or gold plating to the surface of the first dielectric layer 10.

[0033] In this embodiment, the first dielectric layer 10 can be made of epoxy resin board with a flame retardant rating of FR-4. Since epoxy resin board has better absorption of carbon dioxide laser energy, carbon dioxide laser cutting can be used to create the first through-groove 10a. This is just an example; this application does not impose any special restrictions on the material of the first dielectric layer 10 or the method of creating the first through-groove 10a.

[0034] S2: Please refer to Figure 2 A first electroplated layer 33 is formed on one side of the first dielectric layer 10. The first electroplated layer 33 fills the first through groove 10a to form a coplanar waveguide structure 30. The coplanar waveguide structure 30 includes a signal line 31 and a ground line 32. The ground line 32 is located on opposite sides of the signal line 31.

[0035] In this embodiment, the first electroplated layer 33 covers the surface of the first metal layer 21 that faces away from the first dielectric layer 10. The material of the first electroplated layer 33 can be a conductive metal such as copper or gold. The roughness of the contact surface between the electroplated signal line 31 and the dielectric layer is about 0.1 to 0.5 μm, while the roughness of the contact surface between the signal line 31 formed by metal foil and the dielectric layer is about 0.3 to 1.5 μm. It can be seen that forming the signal line 31 by electroplating can reduce the skin effect of the coplanar waveguide structure 30 in high-frequency and high-speed application environments, thereby reducing signal loss.

[0036] In this embodiment, a second electroplated layer 34 is formed on the opposite side of the first dielectric layer 10, and the second electroplated layer 34 is located on the side of the first dielectric layer 10 away from the first electroplated layer 33. Specifically, the second electroplated layer 34 covers the surface of the second metal layer 22 away from the first dielectric layer 10. The material of the second electroplated layer 34 can be a conductive metal material such as copper or gold.

[0037] S3: Please refer to Figure 2 and Figure 3A circuit is fabricated on the first electroplated layer 33 and the first metal layer 21. A first groove 35 is formed on the surface of the first electroplated layer 33 opposite to the first metal layer 21. The first groove 35 penetrates the first electroplated layer 33 and exposes the coplanar waveguide structure 30. The ground wire 32 is connected to the first electroplated layer 33. A circuit is fabricated on the second electroplated layer 34 and the second metal layer 22. A second groove 36 is formed on the surface of the second electroplated layer 34 opposite to the second metal layer 22. The second groove 36 penetrates the second electroplated layer 34 and the second metal layer 22 and exposes the coplanar waveguide structure 30. The second electroplated layer 34 and the second metal layer 22 are separate from and do not contact the ground wire 32. This forms the inner circuit board 39.

[0038] S4: Please refer to Figure 4 A second substrate 53 is provided, the second substrate 53 including a third metal layer 41 and a second dielectric layer 43, the second dielectric layer 43 covering the surface of the third metal layer 41. A third substrate 54 is provided, the third substrate 54 including a fourth metal layer 42 and a third dielectric layer 44, the third dielectric layer 44 covering the surface of the fourth metal layer 42.

[0039] In this embodiment, the third metal layer 41 and the fourth metal layer 42 are made of copper foil. The second dielectric layer 43 and the third dielectric layer 44 are used to improve the voltage withstand performance of the circuit board 100. The second dielectric layer 43 and the third dielectric layer 44 are made of epoxy resin board with a flame retardant rating of FR-4.

[0040] S5: Please refer to Figure 4 A first adhesive layer 45 and a second adhesive layer 46 are provided. A first window 47 is formed on the surface of the first adhesive layer 45, and a second window 48 is formed on the surface of the second adhesive layer 46. The first window 47 penetrates the first adhesive layer 45, and the second window 48 penetrates the second adhesive layer 46. The first window 47 and the second window 48 correspond to the positions of the coplanar waveguide structure 30.

[0041] S6: Please refer to Figure 1 , Figure 4 and Figure 5 The second substrate 53, the first adhesive layer 45, the inner circuit substrate 39, the second adhesive layer 46, and the third substrate 54 are stacked and pressed in sequence, such that the first adhesive layer 45 covers one side of the inner circuit substrate 39, the second adhesive layer 46 covers the side of the inner circuit substrate 39 away from the first adhesive layer 45, the second substrate 53 covers the surface of the first adhesive layer 45 away from the inner circuit substrate 39, and the third substrate 54 covers the surface of the second adhesive layer 46 away from the inner circuit substrate 39. The first window 47 is connected to the first through groove 10a to form a first cavity 51 on the surface of the coplanar waveguide structure 30.

[0042] In this embodiment, a first adhesive layer 45 covers the surface of the first electroplated layer 33 facing away from the first metal layer 21, a second dielectric layer 43 covers the surface of the first adhesive layer 45 facing away from the first electroplated layer 33, and a third metal layer 41 covers the surface of the second dielectric layer 43 facing away from the first adhesive layer 45. A second adhesive layer 46 covers the surface of the second electroplated layer 34 facing away from the second metal layer 22, a third dielectric layer 44 covers the surface of the second adhesive layer 46 facing away from the second electroplated layer 34, and a fourth metal layer 42 covers the surface of the third dielectric layer 44 facing away from the second adhesive layer 46. The first opening 47 of the first adhesive layer 45 communicates with the first groove 35 to form a first cavity 51 on the surface of the coplanar waveguide structure 30. A second opening 48 is formed on the surface of the second adhesive layer 46, penetrating the second adhesive layer 46 and the second electroplated layer 34, and communicating with the second groove 36 to form a second cavity 52 on the opposite surface of the coplanar waveguide structure 30. The coplanar waveguide structure 30 is exposed through the second window 48.

[0043] In this embodiment, the first cavity 51 and the second cavity 52 contain air or are in a vacuum.

[0044] S7: Please refer to Figure 6 A first via 611 and a second via 71 are formed on the third metal layer 41. The first via 611 penetrates the third metal layer 41, the second dielectric layer 43, and the first adhesive layer 45. The second via 71 penetrates the third metal layer 41 to the fourth metal layer 42. A conductive material is electroplated in the first via 611 to form a first conductive structure 612. A conductive material is electroplated on the inner wall of the second via 71 to form a second conductive structure 72. A third electroplated layer 63 is formed on the surface of the third metal layer 41 by electroplating. This allows the first conductive structure 612 to be electrically connected to the first electroplated layer 33 and / or the coplanar waveguide structure 30, the third electroplated layer 63 to cover the surface of the third metal layer 41 facing away from the second dielectric layer 43, and the second conductive structure 72 to be electrically connected to the third metal layer 41, the first electroplated layer 33, the first metal layer 21, the second metal layer 22, the second electroplated layer 34, and the second external circuit layer 62.

[0045] In some embodiments, a third through-hole 621 is also formed on the fourth metal layer 42, the third through-hole 621 penetrating the fourth metal layer 42, the third dielectric layer 44, and the second adhesive layer 46. A conductive material is electroplated on the inner wall of the third through-hole 621 and on the surface of the fourth metal layer 42 to form a third conductive structure 622 and a fourth electroplated layer 64, such that the third conductive structure 622 is electrically connected to the fourth electroplated layer 64, the fourth metal layer 42, the second electroplated layer 34, and the second metal layer 22, and the fourth electroplated layer 64 covers the surface of the fourth metal layer 42 facing away from the third dielectric layer 44.

[0046] S8: Please refer to Figure 6The third electroplated layer 63 and the third metal layer 41 are fabricated to form the first outer circuit layer 61. The fourth electroplated layer 64 and the fourth metal layer 42 are fabricated to form the second outer circuit layer 62. A protective layer 80 is formed on the surfaces of the first outer circuit layer 61 and the second outer circuit layer 62. The protective layer 80 covers the surface of the first outer circuit layer 61 facing away from the second dielectric layer 43, the surface of the second outer circuit layer 62 facing away from the third dielectric layer 44, and the surface of the second conductive structure 72 exposed in the second via 71.

[0047] In some embodiments, if step S7 does not involve the third electroplating layer 63 and the fourth electroplating layer 64, then step S8 may omit the corresponding steps of fabricating circuits for the third electroplating layer 63 and the fourth electroplating layer 64.

[0048] Please see Figure 6 This application also provides a circuit board 100, including an inner circuit substrate 39, a first adhesive layer 45, a second adhesive layer 46, a first outer circuit substrate 91, and a second outer circuit substrate 92. The inner circuit substrate 39 includes a first dielectric layer 10 and a first inner circuit layer 37. A coplanar waveguide structure 30 is embedded within the first dielectric layer 10, exposed above the first dielectric layer 10 and connected to the first inner circuit layer 37. The coplanar waveguide structure 30 includes a signal line 31 and ground lines 32 located on opposite sides of the signal line 31, the signal line 31 and ground lines 32 being arranged with a gap between the first dielectric layer 10 and the ground line 32. The first adhesive layer 45 covers the surface of the first inner circuit layer 37, and the first adhesive layer 45 has a first cavity 51 penetrating the first adhesive layer 45 and the first inner circuit layer 37, through which the coplanar waveguide structure 30 is exposed. The second adhesive layer 46 covers the side of the first dielectric layer 10 opposite to the first adhesive layer 45. The first external circuit board 91 covers the surface of the first adhesive layer 45 away from the surface of the first dielectric layer 10 and is electrically connected to the first internal circuit layer 37. The second external circuit board 92 covers the surface of the second adhesive layer 46 away from the surface of the first dielectric layer 10.

[0049] In this embodiment, the first cavity 51 is filled with air, and the coplanar waveguide structure 30 is in contact with the air. Using air as a medium can better reduce the skin effect of the coplanar waveguide structure 30, resulting in lower damage and a wider bandwidth, which meets the requirements of high-performance microwave integrated circuits for high frequency, high speed and low loss.

[0050] In some embodiments, the second adhesive layer 46 has a second cavity 52 extending through the second adhesive layer 46, and the coplanar waveguide structure 30 is exposed from the second cavity 52.

[0051] In this embodiment, the second cavity 52 is filled with air. The addition of the second cavity 52 ensures that both sides of the coplanar waveguide structure 30 are in contact with air, further reducing signal loss.

[0052] In some embodiments, the first inner circuit layer 37 includes a first metal layer 21 and a first electroplated layer 33. The first metal layer 21 covers the surface of the first dielectric layer 10 facing away from the second adhesive layer 46, and the first electroplated layer 33 covers the surface of the first metal layer 21 facing away from the first dielectric layer 10. The first electroplated layer 33 is electrically connected to the coplanar waveguide structure 30. The electrical connection between the first electroplated layer 33 and the coplanar waveguide structure 30 can achieve electrical connection between the external circuitry and the coplanar waveguide structure 30. The first metal layer 21 is used to enhance the bonding strength between the first electroplated layer 33 and the coplanar waveguide structure 30, resulting in better reliability of the circuit board 100. In this embodiment, the first metal layer 21 and the first electroplated layer 33 may include circuit patterns.

[0053] In some embodiments, the inner circuit board 39 further includes a second inner circuit layer 38, which includes a second metal layer 22 and a second electroplated layer 34. The second metal layer 22 covers the surface of the first dielectric layer 10 facing away from the first adhesive layer 45, and the second electroplated layer 34 covers the surface of the second metal layer 22 facing away from the first dielectric layer 10. The second cavity 52 penetrates the second metal layer 22 and the second electroplated layer 34 and exposes a coplanar waveguide structure 30. The coplanar waveguide structure 30 is separate from the second inner circuit layer 38. The second metal layer 22 and the second electroplated layer 34 are used to achieve circuit conductivity between the interlayer circuitry of the second outer circuit board 92 and the circuit board 100. In this embodiment, the second metal layer 22 and the second electroplated layer 34 may include circuit patterns.

[0054] In some embodiments, the first external circuit board 91 includes a first external circuit layer 61 and a second dielectric layer 43. The second dielectric layer 43 is located between the first external circuit layer 61 and the first adhesive layer 45, and covers the surface of the first adhesive layer 45 facing away from the first dielectric layer 10. A portion of the surface of the second dielectric layer 43 is exposed in the first cavity 51. The second dielectric layer 43 can improve the voltage withstand performance of the circuit board 100.

[0055] In some embodiments, the second external circuit board 92 includes a second external circuit layer 62 and a third dielectric layer 44. The third dielectric layer 44 is located between the second external circuit layer 62 and the second adhesive layer 46, and covers the surface of the second adhesive layer 46 facing away from the first dielectric layer 10. A portion of the surface of the third dielectric layer 44 is exposed in the second cavity 52. ​​The addition of the third dielectric layer 44 further improves the voltage withstand performance of the circuit board 100.

[0056] In some embodiments, the circuit board 100 further includes a first conductive structure 612, which penetrates the first external circuit substrate 91, the second dielectric layer 43, and the first adhesive layer 45 and is electrically connected to the first electroplated layer 33 and the coplanar waveguide structure 30. The first conductive structure 612 is used to achieve circuit conduction between the first external circuit layer 61 and the coplanar waveguide structure 30.

[0057] In some embodiments, the circuit board 100 further includes a second conductive structure 72, which penetrates the circuit board 100 and electrically connects the first external circuit board 91 and the second external circuit board 92. The second conductive structure 72 is used to enable circuit conduction between the first external circuit board 91 and the second external circuit board 92.

[0058] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A circuit board, characterized in that, include: An internal circuit board includes a first dielectric layer and a first internal circuit layer. A coplanar waveguide structure is embedded in the first dielectric layer. The coplanar waveguide structure is exposed in the first dielectric layer and connected to the first internal circuit layer. The coplanar waveguide structure includes a signal line and a ground line located on opposite sides of the signal line. The signal line and the ground line are arranged with a gap between the first dielectric layer. A first adhesive layer covers the surface of the first inner circuit layer. The first adhesive layer has a first cavity penetrating the first adhesive layer and the first inner circuit layer. The coplanar waveguide structure is exposed from the first cavity. A second adhesive layer covers the side of the first dielectric layer that is opposite to the first adhesive layer; The first outer circuit board covers the surface of the first adhesive layer away from the first dielectric layer and is electrically connected to the first inner circuit layer. as well as, The second external circuit board covers the surface of the second adhesive layer that is away from the first dielectric layer.

2. The circuit board as described in claim 1, characterized in that, The second adhesive layer has a second cavity penetrating the second adhesive layer, and the coplanar waveguide structure is exposed from the second cavity.

3. The circuit board as described in claim 1, characterized in that, The first internal circuit layer includes a first metal layer and a first electroplated layer. The first metal layer covers the surface of the first dielectric layer away from the second adhesive layer, and the first electroplated layer covers the surface of the first metal layer away from the first dielectric layer. The first electroplated layer is electrically connected to the coplanar waveguide structure.

4. The circuit board as described in claim 1, characterized in that, The first external circuit board includes a first external circuit layer and a second dielectric layer. The second dielectric layer is located between the first external circuit layer and the first adhesive layer. The second dielectric layer covers the surface of the first adhesive layer away from the first dielectric layer, and a portion of the surface of the second dielectric layer is exposed in the first cavity.

5. The circuit board as described in claim 2, characterized in that, The second external circuit board includes a second external circuit layer and a third dielectric layer. The third dielectric layer is located between the second external circuit layer and the second adhesive layer. The third dielectric layer covers the surface of the second adhesive layer away from the first dielectric layer, and a portion of the surface of the third dielectric layer is exposed in the second cavity.

6. The circuit board as described in claim 1, characterized in that, The circuit board further includes a first conductive structure that penetrates the first outer circuit substrate and the first adhesive layer and is electrically connected to the first inner circuit layer.

7. The circuit board as described in claim 2, characterized in that, The internal circuit substrate further includes a second internal circuit layer, which includes a second metal layer and a second electroplating layer. The second metal layer covers the surface of the first dielectric layer away from the first adhesive layer, and the second electroplating layer covers the surface of the second metal layer away from the first dielectric layer. The second cavity penetrates the second metal layer and the second electroplating layer and exposes the coplanar waveguide structure.

8. A method for manufacturing a circuit board, characterized in that, include: A first substrate is provided, the first substrate includes a first dielectric layer, and a plurality of first through slots are formed in the first dielectric layer, the first through slots penetrating the first dielectric layer and being arranged at intervals; A first electroplated layer is formed on one side of the first dielectric layer. The first electroplated layer fills the first through-groove to form a coplanar waveguide structure. The coplanar waveguide structure includes a signal line and a ground line. The ground line is located on opposite sides of the signal line to form an internal circuit substrate. A second substrate, a first adhesive layer, a third substrate, and a second adhesive layer are provided. A first window is formed on the surface of the first adhesive layer, and the first window penetrates the first adhesive layer. The second substrate, the first adhesive layer, the inner circuit substrate, the second adhesive layer, and the third substrate are stacked and pressed in sequence, such that the first adhesive layer covers one side of the inner circuit substrate, the second adhesive layer covers the side of the inner circuit substrate away from the first adhesive layer, the second substrate covers the surface of the first adhesive layer away from the inner circuit substrate, and the third substrate covers the surface of the second adhesive layer away from the inner circuit substrate. The first opening is connected to the first through slot to form a first cavity on the surface of the coplanar waveguide structure. The second substrate and the third substrate are fabricated to form a first external circuit substrate and a second external circuit substrate.

9. The method for manufacturing a circuit board as described in claim 8, characterized in that, The fabrication method further includes: forming a second electroplating layer on the side of the first dielectric layer away from the first electroplating layer, and opening a second window on the surface of the second adhesive layer, the second window penetrating the second adhesive layer and the second electroplating layer, the coplanar waveguide structure being exposed from the second window.

10. The method for manufacturing a circuit board as described in claim 8, characterized in that, The manufacturing method further includes: forming a first conductive structure within the circuit board, the first conductive structure penetrating the first external circuit substrate and the first adhesive layer and being electrically connected to the coplanar waveguide structure.

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