Electro-hydraulic servo valve control device and electro-hydraulic servo system

Abstract

The present disclosure relates to the technical field of hydraulic control, in particular to an electro-hydraulic servo valve control device and an electro-hydraulic servo system, the device comprising: a main control substrate and a demodulation sub-board, a field programmable gate array (FPGA) and a micro control unit (MCU) being arranged on the main control substrate; the FPGA being connected with the demodulation sub-board and the MCU; the demodulation sub-board being parallel to the main control substrate, and the demodulation sub-board being connected with the main control substrate through a connecting assembly. According to the present disclosure, the demodulation sub-board is parallel to the main control substrate, and the two are in a stacked structure in the vertical direction, thereby being conducive to reducing the circuit area on the plane, and in some scenarios, the demodulation sub-board can act as a shielding layer to shield some interference signals for the main control substrate.

Description

Technical Field

[0001] This disclosure relates to the field of hydraulic control technology, and in particular to electro-hydraulic servo valve control devices and electro-hydraulic servo systems. Background Technology

[0002] The electro-hydraulic servo valve is the core actuator of an electro-hydraulic servo system, and the accuracy and anti-interference capability of its control circuit directly affect the system's performance. Currently, the control circuits of electro-hydraulic servo valves mainly suffer from the following problems:

[0003] 1. Anti-interference capability: The circuit generally uses a microcontroller or discrete components. Digital signals and analog signals coexist, which can easily generate crosstalk. In addition, improper grounding can lead to high-frequency noise, thereby affecting the accuracy of sensor signal acquisition.

[0004] 2. Size and integration: In order to achieve power drive and signal conditioning, the circuit often requires multiple PCBs (Printed Circuit Boards) connected by ribbon cables, which are bulky and introduce electromagnetic interference risks due to the use of long cables.

[0005] 3. Architecture: It has significant limitations. The circuits rely heavily on DSP (Digital Signal Processor) chips and lack specific hardware adaptation structures, making it difficult to simultaneously meet the needs of high-speed logic control and complex algorithm operations. Summary of the Invention

[0006] This disclosure provides an electro-hydraulic servo valve control device and an electro-hydraulic servo system to address the shortcomings in related technologies.

[0007] According to a first aspect of the present disclosure, an electro-hydraulic servo valve control device is provided, comprising: a main control board and a demodulation sub-board, wherein the main control board is provided with a field-programmable gate array (FPGA), a microcontroller unit (MCU), and the demodulation sub-board; the FPGA is connected to the demodulation sub-board and the MCU, the FPGA is used to send generated logic timing signals to the demodulation sub-board, receive feedback information sent by the demodulation sub-board, send the feedback information to the MCU, and receive control commands sent by the MCU for controlling the electro-hydraulic servo valve; the MCU is used to communicate with a host computer, and to run an algorithm based on the feedback information to obtain control commands, and send the control commands to the FPGA; the demodulation sub-board is used to drive elements according to the logic timing signals, and to generate the feedback information from the information collected by the sensors; wherein the demodulation sub-board is parallel to the main control board, and the demodulation sub-board is connected to the main control board through a connecting component.

[0008] Optionally, the connection component includes: a double-row straight pin header and a socket pad; wherein the demodulation sub-board is provided with the socket pad, the main control substrate is provided with the double-row straight pin header, the double-row straight pin header is perpendicular to the main control substrate, and the double-row straight pin header is connected to the demodulation sub-board through the socket pad.

[0009] Optionally, the main control substrate includes at least one conductive layer located within the projection area of ​​the FPGA. A designated conductive layer in the at least one conductive layer is divided into an analog ground plane and a digital ground plane, which are connected by a jumper conductor.

[0010] Optionally, the bridging conductor includes at least one of the following structures: copper foil traces; via arrays.

[0011] Optionally, the device further includes a sinusoidal pulse width modulation (SPWN) circuit connected to the PWN pin of the FPGA, used to convert the logic timing signal output by the FPGA into a sinusoidal excitation signal.

[0012] Optionally, the SPWN circuit includes: a level conversion chip connected to the PWN pin of the FPAG for adjusting the level of the logic timing signal; and a second-order Sallen-Key low-pass filter connected to the level conversion chip and the demodulation sub-board for filtering the adjusted logic timing signal to obtain the sinusoidal excitation signal and sending the sinusoidal excitation signal to the sensor of the demodulation sub-board.

[0013] Optionally, the demodulation board includes: a differential amplifier circuit connected to the sensor for differential amplification of the sensor's acquired information; and an analog-to-digital converter (ADC) connected to the differential amplifier circuit and the FPGA for analog-to-digital conversion of the differentially amplified acquired information to obtain feedback information, and sending the feedback information to the FPGA.

[0014] Optionally, the main control board is further provided with: a digital-to-analog converter (DAC) connected to the FPGA, used to convert the control commands from the FPGA into analog voltage signals; an operational amplifier connected to the DAC, used to amplify the analog voltage signals to obtain analog current signals; and a transistor current amplification circuit connected to the DAC, used to amplify the analog current signals to obtain current signals for controlling the electro-hydraulic servo valve.

[0015] Optionally, the device further includes a gain switching array for controlling the gain of the operational amplifier.

[0016] According to a second aspect of the present disclosure, an electro-hydraulic servo system is provided, including the electro-hydraulic servo valve control device described in the first aspect.

[0017] According to embodiments of this disclosure, the demodulation sub-board is parallel to the main control board, for example... Figure 1 As shown, the demodulation sub-board is located on top of the main control board, and the two are stacked vertically. This helps to reduce the circuit area on the plane, and in some scenarios, the demodulation sub-board can easily act as a shielding layer to shield the main control board from some interference signals. In addition, this disclosure is based on the division of labor and cooperation between the FPGA and MCU on the main control board. The FPGA handles nanosecond-level PWM generation and demodulation, while the MCU handles millisecond-level PID algorithms and communication, giving full play to the advantages of heterogeneous computing.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic structural diagram of an electro-hydraulic servo valve control device according to an embodiment of the present disclosure.

[0021] Figure 2 This is a schematic structural diagram of an electro-hydraulic servo valve according to an embodiment of the present disclosure.

[0022] Figure 3 This is a schematic diagram of component interaction according to an embodiment of the present disclosure. Detailed Implementation

[0023] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0024] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. The singular forms “a” and “the” as used in this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

[0025] It should be understood that although the terms first, second, third, etc., may be used to describe various information in embodiments of this disclosure, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first information may also be referred to as second information without departing from the scope of embodiments of this disclosure, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0026] For the sake of brevity and ease of understanding, this document uses the terms "greater than" or "less than", "higher than" or "lower than" to describe size relationships. However, it will be understood by those skilled in the art that the term "greater than" also includes the meaning of "greater than or equal to", and "less than" also includes the meaning of "less than or equal to"; the term "higher than" also includes the meaning of "higher than or equal to", and "lower than" also includes the meaning of "lower than or equal to".

[0027] Figure 1 This is a schematic diagram of the structure of an electro-hydraulic servo device according to an embodiment of the present disclosure.

[0028] like Figure 1 As shown, the electro-hydraulic servo valve control device includes: a main control board 101 and a demodulation board 102.

[0029] In some embodiments, a heterogeneous processing chipset is provided on the main control board. The heterogeneous processing chipset includes an FPGA (Field Programmable Gate Array) and a microcontroller unit (MCU), for example, an ARM-based MCU.

[0030] In some embodiments, the main control board may also be provided with a V (voltage) / I (current) conversion power drive module and a power interface.

[0031] In some embodiments, the FPGA is connected to the demodulation board and the MCU.

[0032] For example, the FPAG is used to send the generated logic timing signals to the demodulation board, receive feedback information sent by the demodulation board, send the feedback information to the MCU, and receive control commands sent by the MCU to control the electro-hydraulic servo valve.

[0033] In some embodiments, the MCU is used to communicate with a host computer (e.g., to receive instructions from the host computer).

[0034] For example, the MCU can also run an algorithm (such as a proportional-integral-differential (PID) control algorithm) based on feedback information from the FPGA to obtain control commands, and then send the control commands to the FPGA.

[0035] The demodulation board is used to drive components (e.g., LVDT (Linear Variable Displacement Transducer)) based on logic timing signals and to generate feedback information based on information acquired by sensors (e.g., LVDT sensors) (e.g., current signals used to control electro-hydraulic servo valves).

[0036] In some embodiments, the demodulation sub-board is parallel to the main control substrate, and the demodulation sub-board is connected to the main control substrate through a connection component.

[0037] According to this embodiment, the demodulation sub-board is parallel to the main control board, for example... Figure 1 As shown, the demodulation board is located on the main control board, and the two adopt a stacked structure in the vertical direction. This helps to reduce the circuit area on the plane. In some scenarios, the demodulation board can also serve as a shielding layer to shield the main control board from some interference signals.

[0038] In addition, this disclosure is based on the division of labor and cooperation between the FPGA and MCU on the main control board. The FPGA handles nanosecond-level PWM generation and demodulation, while the MCU handles millisecond-level PID algorithms and communication, giving full play to the advantages of heterogeneous computing.

[0039] In some embodiments, the connection component includes:

[0040] Double row straight pin header (e.g.) Figure 1 (1301 shown) and the socket pads;

[0041] The demodulation sub-board is provided with the socket pad, and the main control substrate is provided with the double row of straight pin headers. The double row of straight pin headers is perpendicular to the main control substrate and is connected to the demodulation sub-board through the socket pad.

[0042] In this embodiment, the demodulation board and the main control board are connected by rigid pins such as double-row straight pin headers instead of flexible flat cables, which helps to improve the vibration resistance and impact resistance of the device.

[0043] For example Figure 2 As shown, based on the embodiments of this disclosure, the electro-hydraulic servo valve control device occupies less space on the plane, and the demodulation sub-board can provide a certain anti-interference performance. The overall structure has good vibration resistance and impact resistance. The device can be placed inside the electro-hydraulic servo valve 10 (instead of outside the electro-hydraulic servo valve), which helps to reduce external wiring and improve integration.

[0044] In some embodiments, the main control substrate includes at least one conductive layer located within the projection area of ​​the FPGA (e.g., specifically below a Ball Grid Array (BGA) package), and a designated conductive layer of the at least one conductive layer is divided into an analog ground plane and a digital ground plane, which are connected by a jumper conductor.

[0045] In some embodiments, the bridging conductor includes at least one of the following structures: copper foil traces; via arrays.

[0046] In this embodiment, by setting a single-point bridging between digital ground and analog ground under the FPGA chip, the return path of high-frequency digital signals and sensitive analog signals is greatly shortened, which facilitates the suppression of ground loop noise and helps to improve the acquisition accuracy of LVDT sensor signals.

[0047] In some embodiments, the electro-hydraulic servo valve control device further includes:

[0048] The Sinusoidal Pulse Width Modulation (SPWN) circuit is connected to the PWN pin of the FPGA and is used to convert the logic timing signals output by the FPGA into sinusoidal excitation signals.

[0049] In some embodiments, the SPWN circuit includes:

[0050] A level conversion chip (such as the 74AVC4T245) is connected to the PWN pin of the FPAG and is used to adjust the level of the logic timing signal.

[0051] A second-order Sallen-Key low-pass filter, connected to the level conversion chip and the demodulation board, is used to filter the logic timing signal after level adjustment to obtain the sinusoidal excitation signal, and send the sinusoidal excitation signal to the sensor (e.g., sensor interface) on the demodulation board.

[0052] In some embodiments, the demodulation board is provided with:

[0053] A differential amplifier circuit, connected to a sensor (e.g., a sensor interface), is used to differentially amplify the information acquired by the sensor.

[0054] An analog-to-digital converter (ADC) (e.g., a high-speed ADC chip, such as AD7616 or AD7606) is connected to a differential amplifier circuit and an FPGA (e.g., the ADC digital pins are directly connected to the FPGA's I / O interface). It is used to perform analog-to-digital conversion on the differentially amplified acquisition information to obtain feedback information, and then send the feedback information to the FPGA.

[0055] In some embodiments, the V / I conversion power drive module includes:

[0056] A digital-to-analog converter (DAC) (such as AD5542, AD5353, etc.) is connected to the FPGA to convert the control commands from the FPGA into analog voltage signals.

[0057] An operational amplifier (such as an SGM8567) is connected to a DAC to amplify the analog voltage signal to obtain an analog current signal.

[0058] A transistor current amplification circuit (such as Q0S2L77, SS8050, SS8550, etc.) is connected to the DAC to amplify the analog current signal to obtain a current signal for controlling the electro-hydraulic servo valve.

[0059] In some embodiments, the electro-hydraulic servo valve control device further includes a gain switching array for controlling the gain of the operational amplifier. Accordingly, the gain of the operational amplifier can be adjusted by the gain switching array, for example, by adjusting the resistor ratio in the operational amplifier, to achieve dynamic adjustment of the amplification factor of the operational amplifier. For example, when a small current is needed, the gain can be switched to a small gain setting (fine adjustment), and when a large thrust is needed, the gain can be switched to a large gain setting (coarse adjustment).

[0060] In the above embodiments, the ADC and DAC are directly connected to the FPGA (e.g., the ADC digital pins are directly connected to the FPGA's I / O interface), which facilitates the short-path direct connection of key signals (e.g., excitation, feedback) between the FPGA and the ADC and DAC, reducing transmission loss.

[0061] Figure 3 This is a schematic diagram of component interaction according to an embodiment of the present disclosure.

[0062] like Figure 3 As shown, the signals in the embodiments of this disclosure mainly involve the following aspects: excitation signal flow, feedback signal flow, and power drive.

[0063] In some embodiments, regarding the excitation signal flow:

[0064] The FPGA generates an SPWM signal, which is filtered to generate a sine wave to drive the LVDT coil.

[0065] Source (FPGA): The FPGA module generates SPWM (Sinusoidal Pulse Width Modulation) signals. Functional correspondence: Digital logic generates high-frequency modulated signals as the source of excitation.

[0066] Filtering (LPF): After the SPWM signal flows out of the FPGA, it enters the LPF (Low-Pass Filter). Function: To filter out the carrier wave from the high-frequency SPWM square wave and restore it to a smooth sinusoidal analog signal.

[0067] Driver: The filtered signal enters the driver (driver and / or power amplifier). Function: Enhances the signal's load-carrying capacity and provides sufficient current to the coil.

[0068] Execution (LVDT coil): The signal ultimately flows to the LVDT (e.g., the primary coil of the LVDT). Functional correspondence: Generates an alternating magnetic field to excite the sensor to work.

[0069] In some embodiments, regarding the feedback signal flow:

[0070] The LVDT sensing signal is buffered, demodulated, and filtered before being finally collected back to the FPGA by the ADC.

[0071] Acquisition (LVDT secondary coil): The LVDT secondary coil outputs two differential signals: LVDT input A and LVDT input B.

[0072] Buffer (Buf): The signal first passes through the Buf (buffer and / or voltage follower). Functional correspondence: To perform impedance matching in order to isolate the influence of subsequent circuits on the sensor.

[0073] Path splitting: Digital demodulation (Digital Demodulation). After passing directly through the Buf, the signal enters ADC2 and ADC3 respectively. The digitized signal then enters the Digital Demodulation module inside the FPGA. Function: The FPGA directly performs digital computation and demodulation on the high-frequency sampled data, resulting in higher accuracy.

[0074] In some embodiments, regarding the power drive flow:

[0075] The FPGA outputs PWM, which is converted or filtered by the DAC to drive the valve core (current output).

[0076] Source (PID control): The PID module (located inside or adjacent to the FPGA) calculates the control input.

[0077] PWM modulation: PID output controls the PWM generator.

[0078] Conversion and filtering (DAC and / or LPF): Based on a DAC module on one hand, and the PWM path can pass through an LPF on the other. Functional correspondence: Converting digital control signals into analog voltage signals.

[0079] Power Output (V / I): Analog voltage signals enter the V / I (voltage to current) module. Functional correspondence: Power amplification stage, converting voltage signals into high-precision current signals.

[0080] Final output (valve-controlled output): The output terminal is marked as + / - 10mA valve-controlled output. Functional correspondence: Torque motor that directly drives electro-hydraulic servo valves.

[0081] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0082] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. An electro-hydraulic servo valve control device, characterized in that, include: The main control board and the demodulation sub-board are provided on the main control board, which is equipped with a field-programmable gate array (FPGA), a microcontroller unit (MCU), and the demodulation sub-board. The FPGA is connected to the demodulation sub-board and the MCU. The FPGA is used to send the generated logic timing signals to the demodulation sub-board, receive feedback information sent by the demodulation sub-board, send the feedback information to the MCU, and receive control commands sent by the MCU to control the electro-hydraulic servo valve. The MCU is used to communicate with the host computer, run an algorithm based on the feedback information to obtain control commands, and send the control commands to the FPGA; The demodulation subboard is used to drive the components according to the logic timing signal and to generate the feedback information from the information collected by the sensor; The demodulation sub-board is parallel to the main control substrate, and the demodulation sub-board is connected to the main control substrate through a connecting component.

2. The apparatus according to claim 1, characterized in that, The connection component includes: Double-row straight pin header and socket pads; The demodulation sub-board is provided with the socket pads, and the main control substrate is provided with the double-row straight pin headers. The double-row straight pin headers are perpendicular to the main control substrate and are connected to the demodulation sub-board through the socket pads.

3. The apparatus according to claim 1, characterized in that, The main control substrate includes at least one conductive layer located within the projection area of ​​the FPGA. A designated conductive layer within the at least one conductive layer is divided into an analog ground plane and a digital ground plane, which are connected by a bridging conductor.

4. The apparatus according to claim 3, characterized in that, The bridging conductor includes at least one of the following structures: Copper foil traces; Via array.

5. The apparatus according to claims 1 to 4, characterized in that, Also includes: A sinusoidal pulse width modulation (SPWN) circuit is connected to the PWN pin of the FPGA and is used to convert the logic timing signal output by the FPGA into a sinusoidal excitation signal.

6. The apparatus according to claim 5, characterized in that, The SPWN circuit includes: A level conversion chip, connected to the PWN pin of the FPAG, is used to adjust the level of the logic timing signal; A second-order Sallen-Key low-pass filter is connected to the level conversion chip and the demodulation sub-board. It is used to filter the logic timing signal after level adjustment to obtain the sinusoidal excitation signal, and send the sinusoidal excitation signal to the sensor of the demodulation sub-board.

7. The apparatus according to claim 6, characterized in that, The demodulator board is equipped with: A differential amplifier circuit, connected to the sensor, is used to differentially amplify the information acquired by the sensor; The analog-to-digital converter (ADC) is connected to the differential amplifier circuit and the FPGA. It is used to perform analog-to-digital conversion on the differentially amplified acquired information to obtain feedback information, and then send the feedback information to the FPGA.

8. The apparatus according to any one of claims 1 to 4, characterized in that, The main control board is also provided with: A digital-to-analog converter (DAC), connected to the FPGA, is used to convert the control commands from the FPGA into analog voltage signals; An operational amplifier, connected to the DAC, is used to amplify the analog voltage signal to obtain an analog current signal; A transistor current amplification circuit, connected to the DAC, is used to amplify the analog current signal to obtain a current signal for controlling the electro-hydraulic servo valve.

9. The apparatus according to claim 8, characterized in that, Also includes: A gain switching array is used to control the gain of the operational amplifier.

10. An electro-hydraulic servo system, characterized in that, The electro-hydraulic servo valve control device includes any one of claims 1 to 9.

Images