Circuit board substrate, display module and display device

Abstract

Embodiments of the present application provide a circuit board substrate, a display module and a display device, which are applied to the technical field of display. The substrate comprises: a substrate body having a first binding area; a plurality of connection pads arranged in the first binding area, the plurality of connection pads are arranged in parallel along a first direction and arranged in at least two rows in a second direction; and a plurality of conductive traces, at least two groups of the conductive traces correspond to the at least two rows of the connection pads one by one, and each row of the connection pads and the corresponding group of the conductive traces are electrically connected one by one. At least one group of the plurality of conductive traces comprises at least two connected trace portions, and the at least two trace portions are located in different conductive layers of the substrate body. By using the substrate body, the problem that the lateral size of the circuit board substrate used by the display module of the prior art is difficult to further narrow due to the influence of the minimum spacing size of the binding terminal and cannot meet the requirements of miniaturization and narrow frame of the display module can be solved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to circuit board substrates, display modules, and display devices. Background Technology

[0002] In near-eye display devices such as virtual reality (VR) and augmented reality (AR), narrow bezels and miniaturization of the display module are key indicators for improving immersion and wearing comfort. Existing display modules typically use flexible printed circuit boards (FPCs) and display panels to achieve electrical connections through a bonding process. Limited by current bonding precision, conductive adhesive properties, and manufacturing capabilities, the minimum pitch of the bonding terminals is approaching the limits of mass production. With a fixed number of terminals, the width of the bonding area in the extended direction has already been reduced to a minimum. When attempting to further shrink the module bezel, continuing to compress the terminal pitch will lead to a sharp drop in yield and high costs. Without changing the pitch, the lateral dimension of the bonding area cannot be reduced. This has become a technical bottleneck restricting further miniaturization of display modules. Summary of the Invention

[0003] The purpose of this application is to provide a circuit board substrate, a display module, and a display device to solve the problem that the circuit board substrate used in the prior art display module is limited by the minimum spacing size of the bonding terminals (Pitch), making it difficult to further narrow the lateral dimension of the bonding area, thus failing to meet the miniaturization and narrow bezel requirements of the display module.

[0004] To achieve the above objectives, this application adopts the following technical solution: One embodiment of this application provides a circuit board substrate, including a substrate body, a plurality of connection pads, and at least two sets of conductive traces. The substrate body has a first bonding region; the plurality of connection pads are disposed in the first bonding region, each of the connection pads extending along a first direction and arranged in at least two rows in a second direction perpendicular to the first direction; the at least two sets of conductive traces correspond one-to-one with the at least two rows of connection pads, and each row of connection pads is electrically connected to the corresponding set of conductive traces; wherein, at least one set of conductive traces in the plurality of sets of conductive traces includes at least two interconnected trace portions, and the at least two trace portions are located in different conductive layers of the substrate body.

[0005] In one embodiment, the at least two sets of conductive traces include a first set of traces and a second set of traces; each trace in the first set of traces is electrically connected to a first row of connection pads in the first conductive layer of the substrate body; each trace in the second set of traces is electrically connected to a second row of connection pads in the at least two rows of connection pads; along the first direction, the second set of traces includes a first trace portion located in the first conductive layer of the substrate body, a second trace portion located in the second conductive layer of the substrate body, and a third trace portion located in the first conductive layer, and the first trace portion and the second trace portion are respectively connected by interlayer interconnect structures.

[0006] In one implementation, the first row of connecting pads is positioned away from the edge of the first bonding area, and the second row of connecting pads is positioned close to the edge of the first bonding area.

[0007] In one embodiment, the first conductive layer is located on the upper surface of the substrate body, and the second conductive layer is located on the lower surface of the substrate body.

[0008] In one implementation, the connection pads in at least two rows are arranged along the first direction, or the connection pads in different rows are staggered in the first direction.

[0009] In one embodiment, the substrate body is further provided with a device area, and the ends of the multiple sets of conductive traces away from the connecting pads are led out from the first bonding area and electrically connected to the device area.

[0010] In one embodiment, the interlayer interconnect structure includes vias that penetrate the first conductive layer and the second conductive layer.

[0011] In one embodiment, the substrate body is a flexible circuit board.

[0012] In addition, this application also provides a display module, including a circuit board substrate as described above.

[0013] In one embodiment, the display module further includes a second substrate and a display panel disposed on the second substrate, wherein the second substrate has a second bonding area, and at least two rows of connection terminals are disposed on the second bonding area, and the plurality of connection terminals in the at least two rows are connected one-to-one with the plurality of connection pads in the at least two rows.

[0014] In addition, this application also provides a display device, including a display module as described above.

[0015] At least one of the above-described technical solutions in the embodiments of this application has the following beneficial effects: The circuit board substrate of this application embodiment utilizes an array arrangement of at least two rows of connection pads. While keeping the total number and spacing of the connection pads unchanged, it can significantly reduce the width occupied by the bonding area in the arrangement direction of multiple connection pads. In addition, by placing at least two trace portions of at least one set of conductive traces in different conductive layers of the substrate body, it is possible to ensure the reliability of electrical signal output based on the setting of at least two rows of connection pads. Without breaking the limits of existing processes, the lateral dimension of the bonding area can be further narrowed to meet the miniaturization and narrow bezel requirements of the display module. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the three-dimensional structure of a display module using conventional technology. Figure 2 This is a schematic diagram of the planar structure of the circuit board substrate according to an embodiment of this application; Figure 3 This is a side view of the circuit board substrate according to an embodiment of this application; Figure 4 This is one of the three-dimensional structural schematic diagrams of the display module according to an embodiment of this application; Figure 5 This is a schematic diagram illustrating the connection relationship between the circuit board substrate and the display substrate in the embodiments of this application; Figure 6 This is a schematic diagram of the planar structure of the display module according to an embodiment of this application; Figure 7 This is a second three-dimensional structural schematic diagram of the display module according to an embodiment of this application. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "a" or "one," and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms "connected" or "linked," and similar terms, are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right," etc., are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship also changes accordingly.

[0019] Before describing the embodiments of this application in detail, the structure of the prior art display module and its problems will be explained first with reference to the accompanying drawings.

[0020] like Figure 1 As shown, the existing display module mainly consists of two parts: a flexible printed circuit board (FPC) 1 and a display panel (Panel) 2. The FPC 1 has FPC bumps (i.e., connection pads) 3, conductive traces 4, and electronic components 5, while the display panel 2 has corresponding connection pins (i.e., connection terminals). In the bonding area, the FPC bumps 3 and the connection pins are bonded together using anisotropic conductive adhesive (ACF), thereby establishing an electrical path between the flexible printed circuit board and the display panel.

[0021] In the prior art, the FPC Bump 3 on FPC 1 and the connection terminals on Panel 2 are arranged in a single row linearly. Specifically, all FPC Bump 3 are arranged in a row along a first direction parallel to the edge of Panel 2, and each FPC Bump 3 leads out a signal through a corresponding conductive trace. This single-row layout means that the minimum width of the bonding area in the first direction is equal to the number of FPC Bump 3 multiplied by the minimum pitch between adjacent pads.

[0022] With the rapid development of near-eye display technologies such as virtual reality (VR) and augmented reality (AR), products are placing increasingly stringent requirements on the bezel width and overall size of display modules. However, limited by current mature flexible circuit board manufacturing processes, the characteristics of anisotropic conductive adhesive materials, and the alignment precision of bonding equipment, the minimum pitch of flexible circuit board connection pads in the global VR headset market is approaching the mass production technology limit of 110 micrometers. In this context, increasing the number of signal channels to improve display resolution can only linearly increase the arrangement length of a single row of pads, leading to a continuous increase in the lateral dimension of the bonding area and preventing effective reduction in module bezel size.

[0023] Furthermore, even attempting to reduce the bezel width by further shrinking the pitch distance presents significant challenges, including extremely high manufacturing complexity, high costs, and difficulty in guaranteeing yield. For instance, when the pitch is further reduced from 110 micrometers to even smaller values, the alignment accuracy requirements of the photolithography process increase dramatically, the uniformity of conductive particle distribution in the anisotropic conductive adhesive becomes difficult to ensure, and thermal stress control during the bonding and pressing process becomes more challenging. All of these factors lead to a substantial increase in manufacturing costs and a significant decrease in mass production yield.

[0024] Therefore, how to effectively reduce the lateral size of the bonding area and achieve narrow bezels and miniaturization of the display module without breaking through the limits of existing processes or sacrificing the reliability of electrical connections is a technical problem that urgently needs to be solved in this field.

[0025] To address the issue that existing display modules, limited by the minimum pitch dimension of the bonding terminals, cannot further narrow the lateral dimension of the bonding area, thus failing to meet the miniaturization and narrow bezel requirements of display modules, this application provides a circuit board substrate that, by reconstructing the traditional single-row linear arrangement of the bonding pads into an arrangement of at least two rows, significantly reduces the width occupied by the bonding area in the arrangement direction of multiple bonding pads while keeping the total number and spacing of the bonding pads unchanged. Furthermore, by placing at least two portions of at least one set of conductive traces in different conductive layers of the substrate body, the reliability of electrical signal output is ensured while maintaining at least two rows of bonding pads. Thus, without exceeding the limits of existing processes, the lateral dimension of the bonding area is further narrowed, achieving the goal of meeting the miniaturization and narrow bezel requirements of display modules.

[0026] like Figure 2 As shown, one embodiment of this application provides a circuit board substrate, the circuit board substrate 100 comprising: The substrate body 10 has a first bonding region 11; Multiple connection pads 20 are disposed in the first bonding area 11. The multiple connection pads 20 are arranged parallel to each other in a first direction a, and are arranged in at least two rows in a second direction b perpendicular to the first direction a. At least two sets of conductive traces 30, each set of conductive traces 30 corresponds to at least two rows of connection pads 20, and each row of connection pads 20 is electrically connected to the corresponding set of conductive traces 30. Among them, at least one set of conductive traces 30 includes at least two interconnected trace portions, and the at least two trace portions are located in different conductive layers of the substrate body 10.

[0027] In this embodiment, the substrate body 10 is the supporting base for the entire circuit structure of the circuit board substrate, and can be made of flexible insulating material (such as polyimide PI) or rigid insulating material (such as FR4). This embodiment does not limit this.

[0028] Optionally, the first bonding area 11 is typically located at the edge or end of the substrate body 10, and is a specific functional area for physical bonding and electrical connection with external components (such as a display panel). The interconnecting interfaces for connecting to external components (such as a display panel) are centrally arranged within this first bonding area 11, and its width ultimately affects the bezel width of the display module.

[0029] In this embodiment, multiple rows of connection pads 20 are provided on the first bonding area 11 of the substrate body 10 in the second direction b. For each row of connection pads 20, the multiple connection pads 20 are arranged parallel to each other along the first direction a. Optionally, the first direction a is a direction parallel to the edge of the substrate body 10, or a lateral direction of the edge of the display area of ​​the display panel to which the circuit board substrate 100 is connected. The second direction b is a longitudinal direction perpendicular to the edge of the substrate body 10.

[0030] In this embodiment, optionally, the connecting pad 20 serves as a physical contact for electrical signal input and output, and its shape can be any one of circular, rectangular, and elongated shapes; this application does not limit it.

[0031] In this embodiment of the application, optionally, the width of each connection pad 20 in the first direction a can be about 60 μm, and the spacing between adjacent connection pads 20 in the same row can be about 110 μm.

[0032] Unlike the single-row layout where all pads are linearly arranged in a single direction in traditional technologies, the circuit board substrate of this application embodiment sets the connecting pads 20 into at least two rows arranged in an array, for example, as shown in the example. Figure 2 and Figure 3 As shown in the embodiment of this application, the at least two rows of connection pads 20 include a first row of connection pads 21 and a second row of connection pads 22. It should be noted that this embodiment of the application takes two rows of connection pads 20 as an example, but it is not limited to only two rows. In other embodiments, depending on the number of signal channels required, it can also be set to three, four or more rows, as long as it satisfies the characteristic of being distributed in multiple columns in the second direction.

[0033] In this embodiment of the circuit board substrate, while keeping the total number of connecting pads 20, their individual size, and the minimum safety pitch between adjacent pads unchanged, the projected length in the first direction a can be significantly reduced by arranging the connecting pads in multiple rows in the second direction. For example, if a double-row layout is adopted, the theoretical width of the first bonding area 11 in the first direction a can be reduced to about half that of the traditional single-row layout, thereby providing the most direct structural basis for achieving an ultra-narrow bezel on the display panel.

[0034] In the embodiments of this application, such as Figures 2 to 7 As shown, at least two sets of conductive traces 30 correspond one-to-one with at least two rows of connection pads 20, and each row of connection pads 20 is electrically connected to the corresponding set of conductive traces 30. The conductive traces 30 are used to connect the pads 20 to components disposed on the substrate body 10, transmitting electrical signals from the connection pads 20 to the corresponding components. To ensure signal independence and integrity, each set of conductive traces 30 corresponds to one row of connection pads 20. For example, at least two sets of conductive traces 30 include a first set of traces 31 and a second set of traces 32. The first set of traces 31 is electrically connected to the first row of connection pads 21, and the second set of traces 32 is electrically connected to the second row of connection pads 22. Using this implementation structure, by having each row of connection pads correspond to one set of traces, it is possible to ensure that the multi-row pad array can work collaboratively as a whole, thus avoiding signal crosstalk problems.

[0035] In this embodiment, each of the conductive traces 30 located in the same group has the same arrangement structure and / or routing method on the substrate body 10.

[0036] In some embodiments, optionally, at least one group of conductive traces 30 includes at least two interconnected trace portions located in different conductive layers of the substrate body 10. Specifically, when the connection pads 20 change from a single row to multiple rows, due to the risk of physical interference or short circuits, each group of connection pads 20 cannot be distributed on the same conductive layer plane as the conductive traces of conventional connection pads. To solve this technical problem, in this embodiment, at least one group of conductive traces 30 is divided into multiple trace portions located in different conductive layers, and these trace portions are electrically connected between different layers to construct a signal connection path. By using this method, by setting the conductive traces in multiple layers, the potential for interference between traces is eliminated while retaining the effect of reducing the lateral size through the multi-row connection pad layout.

[0037] In some embodiments of this application, optionally, such as Figure 2 and Figure 3As shown, at least two sets of conductive traces 30 include a first set of traces 31 and a second set of traces 32; wherein the first set of traces 31 and the second set of traces 32 each include a plurality of traces extending along a second direction b. Specifically, each trace in the first set of traces 31 is electrically connected to a first row of connection pads 21 in at least two rows of connection pads 20 in the first conductive layer of the substrate body 10. Each trace in the second set of traces 32 is electrically connected to a second row of connection pads 22 in at least two rows of connection pads 20.

[0038] Optionally, the first row of connecting pads 21 is positioned away from the edge of the first bonding area 11, and the second row of connecting pads 22 is positioned close to the edge of the first bonding area 11.

[0039] Along the second direction b, each trace in the second group of traces 32 includes a first trace portion 321 located in the first conductive layer of the substrate body 10, a second trace portion 322 located in the second conductive layer of the substrate body 10, and a third trace portion 323 located in the first conductive layer. The first trace portion 321 and the second trace portion 322, and the second trace portion 322 and the third trace portion 323, are respectively connected by interlayer interconnect structures 40. With this embodiment, by setting each trace in the second group of traces 32 to include multiple trace portions located in different conductive layers, the second group of traces 32 can avoid the first group of traces 31.

[0040] By adopting this implementation structure, the traces connecting the pads are guided from one conductive layer to another through the interlayer interconnection structure 40, so as to effectively avoid trace conflicts when multiple rows of connecting pads are led out.

[0041] In this embodiment, optionally, the first row of connecting pads 21 is positioned away from the edge of the first bonding area 11, and the second row of connecting pads 22 is positioned close to the edge of the first bonding area 11. It should be noted that in this embodiment, the "edge" typically refers to the edge of the first bonding area 11 facing the display substrate. In this layout, the second row of connecting pads 22 are the "outer row of pads" of the circuit board substrate, and the first row of connecting pads 21 are the "inner row of pads." Using this relative positional relationship, the conductive traces (second group of traces 32) connected to the second row of connecting pads 22 need to avoid the conductive traces (first group of traces 31) connected to the first row of connecting pads 21.

[0042] In this embodiment of the application, optionally, as shown in the example... Figure 3As shown, the first conductive layer 60 is located on the upper surface of the substrate body 10, and the second conductive layer 70 is located on the lower surface of the substrate body 10. In this embodiment, the upper surface generally refers to the side where the connecting pads 20 are provided, which is also the operating surface for bonding with the display panel; the lower surface refers to the side facing away from the bonding surface. By using this embodiment, the upper and lower surfaces in the thickness direction of the substrate body 10 provide two mutually isolated wiring planes for the connection traces of the connecting pads, so that the second trace portion 322 can safely pass through the projection area of ​​the trace on the upper surface on the lower surface without electrical contact.

[0043] It should be noted that the second set of traces 32 can be formed into other multi-layer structures, and the first conductive layer 60 and the second conductive layer 70 can also be any two adjacent or spaced metal layers inside the multi-layer board, as long as the inter-layer transmission of signals and spatial avoidance can be achieved.

[0044] In this embodiment, after the first trace portion 321 is led out from the second row of connecting pads 22, it does not extend directly outward on the surface layer. Instead, it switches to the second conductive layer through the first interlayer interconnect structure 40 to form the second trace portion 322. The second trace portion 322 extends on the second conductive layer, bypassing the first row of connecting pads 21 and the first group of traces 31 from below, and then switches back to the first conductive layer through the second interlayer interconnect structure 40 to form the third trace portion 323. Finally, it is electrically connected to the device area 50 of the circuit or electronic device on the circuit board substrate 100. Optionally, the device area 50 is provided with circuits and / or electronic devices.

[0045] In this embodiment, optionally, the interlayer interconnect structure 40 includes vias that penetrate the first conductive layer 60 and the second conductive layer 70. Optionally, it can be formed on the substrate body 10 by mechanical drilling or laser drilling. Optionally, conductive metal (such as copper) can be further deposited on the via walls to achieve electrical conductivity between the upper and lower surfaces (the first conductive layer 60 and the second conductive layer 70).

[0046] In this embodiment, optionally, as Figure 2 As shown, in at least two rows of connection pads 20, the connection pads 20 located in different rows are arranged along the second direction b, or the connection pads 20 located in different rows are staggered in the second direction b. Specifically, as a preferred embodiment, in this application embodiment, the connection pads 20 located in different rows are aligned along the second direction b, that is, the projection positions of multiple connection pads of the first row of connection pads 21 and multiple connection pads of the second row of connection pads 22 in the second direction are substantially coincident. In addition, the center line connecting the connection pads of each row is perpendicular to the second direction.

[0047] With this implementation structure, the connecting pads 20 located in different rows are aligned along the second direction b. Under the premise of ensuring the minimum size of the circuit board substrate in the lateral direction, the pad manufacturing process can be made simpler and faster, and the yield of substrate products can be guaranteed.

[0048] As another optional implementation, the connecting pads 20 located in different rows can also be staggered in the second direction b, that is, the connecting pads 20 of adjacent rows are staggered by a predetermined distance in the second direction b, so that the inner row pads are located within the gap projection area between two adjacent outer row pads. Using this implementation structure, given that the lateral dimension of the circuit board substrate has sufficient width, more lateral wiring channels can be provided for the conductive traces 30, achieving a further optimization of space utilization. It should be understood that regardless of the arrangement method used, as long as the core concept of multi-row array distribution to achieve width reduction is satisfied, it falls within the protection scope of this application.

[0049] To construct a complete signal transmission loop, the substrate body 10 also includes a device region 50. Multiple sets of conductive traces 30, located away from the connecting pads 20, extend from the first bonding area 11 and are electrically connected to the device region 50. Specifically, the device region 50 is typically located on the substrate body 10 in an area away from the bonding edge, and is used to carry driver chips, passive components, or other functional circuits. After completing the electrical connection with the connecting pads 20, the conductive traces 30 fan outward or converge from the dense first bonding area 11, extending to the device region 50 and electrically interconnecting with the corresponding pins or pads.

[0050] In the embodiments of this application, such as Figure 2 and Figure 3 As shown, the first group of traces 31 connected to the first row of connecting pads 21 are directly connected to the connection pins or pads of the device area 50 in the first conductive layer; the second group of traces 32 connected to the second row of connecting pads 22 are directly connected to the connection pins or pads of the device area 50 through the third trace portion 323 located in the first conductive layer.

[0051] In this embodiment of the application, the substrate body 10 may optionally be a flexible circuit board. Optionally, the flexible circuit board (FPC) uses polyimide or polyester film as a substrate, possessing excellent flexibility and bendability.

[0052] like Figures 4 to 7 As shown in the embodiments of this application, a display module is also provided, which includes a circuit board substrate as described in any of the above.

[0053] In one embodiment, the display module further includes a second substrate 200 and a display panel 210 disposed on the second substrate. The second substrate 200 has a second bonding area 220, and at least two rows of connection terminals 230 are disposed on the second bonding area 220. The plurality of connection terminals 230 in the at least two rows are connected to the plurality of connection pads 20 in the at least two rows.

[0054] Optionally, the second substrate 200 can be a glass substrate on which the display panel 210 is disposed, or another rigid or flexible adapter plate electrically connected to the display panel 210. In this embodiment, the second substrate 200 is described as a glass substrate of the display panel 210. The second bonding region 220 is located at the edge of the non-display area of ​​the display panel 210, and its function corresponds to the first bonding region 11 on the circuit board substrate, forming an interface end for establishing a display driving signal transmission path.

[0055] To accommodate the multi-row layout on the circuit board substrate, the connection terminals 230 (typically ITO conductive pins or metal pins) in the second bonding area 220 are also configured as an array structure arranged along the first direction and in at least two rows in the second direction. For example, if the circuit board substrate has a first row of connection pads 21 and a second row of connection pads 22, the second substrate 200 also has a corresponding first row of connection terminals and a second row of connection terminals. In the assembled state, the first row of connection pads 21 are precisely aligned and electrically connected to the first row of connection terminals, and the second row of connection pads 22 are precisely aligned and electrically connected to the second row of connection terminals.

[0056] When at least two rows of connection terminals 230 are provided in the second bonding area 220 of the second substrate 200, each signal line on the second substrate 200 connected to the connection terminal 230 can be provided in the same conductive layer or in different conductive layers. This application does not limit the layout structure of the signal lines on the second substrate 200.

[0057] The display module using this implementation structure matches the multi-row bonding structure of the circuit board substrate with the corresponding terminal structure on the display panel side, thus forming a complete narrow bezel display module product.

[0058] Furthermore, it should be noted that although this embodiment uses a double-row docking as an example for detailed explanation, in other embodiments, depending on the extreme requirements of the high-resolution display module for the number of signal channels, a three-row, four-row, or even more-row docking structure can also be adopted, as long as the connection pads 20 on the circuit board substrate and the connection terminals 230 on the display panel 210 meet the one-to-one matching relationship in terms of the number of rows and positions.

[0059] The display module in this application can be one of a liquid crystal display module (LCM), an organic light-emitting diode (OLED) display module, or a micro-light-emitting diode (Micro-LED) display module.

[0060] This application also provides a display device, which includes a display module as described in the foregoing embodiments.

[0061] Optionally, the display device can be applied to one or more of smartphones, tablets, in-vehicle displays, smartwatches, virtual reality (VR) headsets, augmented reality (AR) glasses, and other near-eye display terminals.

[0062] Based on the above description of the specific embodiments, those skilled in the art should be able to understand the specific implementation structure of the display device using the circuit board substrate of this embodiment, which will not be described in detail here.

[0063] The circuit board substrate, display module, and display device provided in this application embodiment utilize an array arrangement of at least two rows of connecting pads. While keeping the total number and spacing of the connecting pads unchanged, the width occupied by the bonding area in the arrangement direction of multiple connecting pads can be significantly reduced. In addition, by placing at least two trace portions of at least one set of conductive traces in different conductive layers of the substrate body, the reliability of electrical signal output can be guaranteed based on the setting of at least two rows of connecting pads. Without breaking the limits of existing processes, the lateral dimension of the bonding area can be further narrowed to meet the miniaturization and narrow bezel requirements of the display module.

[0064] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

[0065] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A circuit board substrate, characterized in that, include: The substrate body has a first bonding area; Multiple connection pads are disposed in the first bonding area, and the multiple connection pads are arranged parallel to each other along a first direction and arranged in at least two rows in a second direction perpendicular to the first direction; At least two sets of conductive traces, each set of conductive traces corresponds one-to-one with at least two rows of connection pads, and each row of connection pads is electrically connected to the corresponding set of conductive traces. Among them, at least one of the multiple sets of conductive traces includes at least two interconnected trace portions, and the at least two trace portions are located in different conductive layers of the substrate body.

2. The circuit board substrate according to claim 1, characterized in that, The at least two sets of conductive traces include a first set of traces and a second set of traces. Each trace in the first group of traces is electrically connected to the first row of connection pads in the first conductive layer of the substrate body. Each trace in the second group of traces is electrically connected to the second row of connection pads in at least two rows of connection pads; along the second direction, each trace in the second group of traces includes a first trace portion located in the first conductive layer of the substrate body, a second trace portion located in the second conductive layer of the substrate body, and a third trace portion located in the first conductive layer, and the first trace portion and the second trace portion are respectively connected by interlayer interconnection structures.

3. The circuit board substrate according to claim 2, characterized in that, The first row of connecting pads is positioned away from the edge of the first bonding area, and the second row of connecting pads is positioned close to the edge of the first bonding area.

4. The circuit board substrate according to claim 2, characterized in that, The first conductive layer is located on the upper surface of the substrate body, and the second conductive layer is located on the lower surface of the substrate body.

5. The circuit board substrate according to claim 1, characterized in that, In at least two rows of connection pads, the connection pads located in different rows are arranged along the second direction, or the connection pads located in different rows are staggered in the second direction.

6. The circuit board substrate according to claim 1, characterized in that, The substrate body is also provided with a device area, and the ends of the multiple sets of conductive traces away from the connecting pads are led out from the first bonding area and electrically connected to the device area.

7. The circuit board substrate according to claim 2, characterized in that, The interlayer interconnect structure includes vias that penetrate the first conductive layer and the second conductive layer.

8. The circuit board substrate according to claim 1, characterized in that, The substrate body is a flexible circuit board.

9. A display module, characterized in that, Includes the circuit board substrate as described in any one of claims 1 to 8.

10. The display module according to claim 9, characterized in that, The display module further includes a second substrate and a display panel disposed on the second substrate. The second substrate has a second bonding area, and at least two rows of connection terminals are disposed on the second bonding area. The multiple connection terminals in the at least two rows are connected one-to-one with the multiple connection pads in the at least two rows.

11. A display device, characterized in that, Includes the display module described in claim 9 or 10.

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