Multi-chip parallel high-uniform-flow power module

Abstract

The application discloses a kind of multicore parallel high uniform flow's power module, belong to power semiconductor device technical field;Including bottom plate, substrate, upper bridge chip and lower bridge chip, copper clamp, power terminal and signal pin, the upper bridge chip is circularly distributed in the side of the substrate, the lower bridge chip is circularly distributed in the other side of the substrate;The gate and kelvin source electrode of the SiC MOSFET chip are gathered towards the center of circle in the shape of aggregation;Gate copper-clad area and kelvin source copper-clad area are equipped on the first copper layer of the substrate, the gate and kelvin source of the chip are connected to corresponding copper-clad area by bonding wire, and then directly led out by signal Pin;The application is circularly gathered by parallel chip distribution, and makes gate and kelvin source signal directly lead out by signal Pin, effectively improves the consistency of driving loop parasitic parameter between multiple chips, so as to significantly improve the dynamic uniform flow performance and reliability of power module.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor device technology, specifically to a multi-chip parallel high current sharing power module, and more particularly to a multi-chip parallel high current sharing power module. Background Technology

[0002] Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power modules are integrated modules built based on SiC MOSFET chips, widely used in power conversion, power management, and high-efficiency, high-frequency systems. Compared to traditional silicon-based (Si) power modules, SiC MOSFET power modules have lower on-resistance, faster switching speed, and better thermal conductivity, and can operate stably under extreme conditions such as high temperature, high pressure, high current, and high frequency. SiC MOSFET power modules have become key components in high-end power electronics applications such as main drive inverters for new energy vehicles, industrial motor drives, grid inverters, photovoltaic energy storage systems, high-speed rail traction, wind power converters, and data center power supplies.

[0003] The on-state current of a single SiC MOSFET is limited. For example, the current of a single 1200V SiC MOSFET is typically around 100A, while most applications require hundreds or even thousands of amperes of current output. Therefore, power semiconductor modules are usually packaged with multiple chips connected in parallel to achieve current expansion.

[0004] The characteristics and application scenarios of SiC MOSFET high-frequency switches require that the current passing through different parallel chips be as uniform as possible to improve the overall performance and reliability of the power module. The current sharing performance of the power module is divided into static current sharing and dynamic current sharing. Static current unevenness is mainly due to the on-resistance between chips (…). Inconsistent parameters cause this; while dynamic current imbalance is mainly due to parasitic parameters in the circuits between chips and the gate threshold voltage. ) and transconductance ( Inconsistencies arise because of parasitic parameters in the circuits, which are further divided into power circuit and drive circuit parasitic parameters. Therefore, improving current sharing among chips within a power module can be achieved by enhancing the consistency of parasitic parameters in the drive and power circuits between chips, and by implementing chip parameter grading.

[0005] Layout design is a key factor in improving the current sharing performance of power modules. The design primarily utilizes highly symmetrical layouts to enhance current path consistency and shorten loop lengths. Simultaneously, parallel connection of multiple chips requires consideration of inter-chip thermal coupling. To improve the thermal characteristics of the power module under actual operating conditions, a certain distance needs to be maintained between the power chips to achieve thermal decoupling.

[0006] Existing technologies typically place power chips vertically, with the chip placement area on the substrate forming a long strip. This results in differences in the length and area of ​​the power and drive circuits at different positions within the strip, with the power and drive circuits at the far ends being longer and having larger areas. Ultimately, this leads to inconsistencies in the parasitic parameters of the power and drive circuits between chips, resulting in poor overall dynamic current sharing performance of the module. Consequently, the overall electrical performance of the module deteriorates, potentially causing product failure under extreme application conditions.

[0007] Therefore, there is an urgent need for a power module structure that can improve the consistency of the drive loops among the parallel chips in a multi-chip parallel power module. Summary of the Invention

[0008] This invention addresses the technical problems of inconsistent parasitic parameters in the drive circuit and poor dynamic current sharing performance in existing multi-chip parallel power modules due to unreasonable chip layout. It provides a multi-chip parallel high current sharing power module, aiming to improve the consistency of the drive circuit between multiple parallel chips by optimizing the chip layout structure and signal output method, thereby improving the current sharing performance and reliability of the power module.

[0009] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A multi-chip parallel high current-sharing power module, comprising: The base plate provides heat dissipation, mechanical support, and grounding. A substrate, disposed on the base plate, serves to provide insulation, heat conduction, and current flow for circuit layout. The substrate includes a first copper layer, a ceramic insulating layer, and a second copper layer. The upper bridge chip and the lower bridge chip are multiple SiC MOSFET chips, the upper bridge chip is circularly distributed on one side of the substrate, and the lower bridge chip is circularly distributed on the other side of the substrate; The gate and Kelvin source electrodes of the SiC MOSFET chip are oriented toward the circular center and are clustered together. The first copper layer of the substrate is provided with a gate copper-clad region and a Kelvin source copper-clad region, and the signals of the gate and the Kelvin source are connected to the gate copper-clad region and the Kelvin source copper-clad region through bonding wires. The signal pin and the pin holder are fixed to the corresponding copper-clad area of ​​the first copper layer of the substrate by solder. The signal pin and the pin holder are electrically connected by interference fit. The signals of the gate and the Kelvin source are directly led out through the signal pin.

[0010] As a preferred embodiment of the present invention, the first copper layer of the substrate includes copper plating on the drain of the upper transistor, copper plating on the negative temperature coefficient thermistor, copper plating on the source of the lower transistor, copper plating on the AC output, copper plating on the gate of the upper transistor, copper plating on the Kelvin source of the upper transistor, copper plating on the gate of the lower transistor, and copper plating on the Kelvin source of the lower transistor.

[0011] As a preferred embodiment of the present invention, the power module further includes a negative temperature coefficient thermistor, the two terminals of which are respectively attached to the negative temperature coefficient thermistor copper cladding of the first copper layer of the substrate.

[0012] As a preferred embodiment of the present invention, the power module further includes an upper high-voltage DC positive busbar and a lower DC negative busbar, wherein the upper high-voltage DC positive busbar is connected to the positive terminal of the DC bus capacitor, and the lower DC negative busbar is connected to the negative terminal of the DC bus capacitor.

[0013] As a preferred embodiment of the present invention, the power module further includes a half-bridge midpoint output busbar, which is a half-bridge AC output terminal.

[0014] As a preferred embodiment of the present invention, the power module further includes copper clips, each of which connects the source of a SiC MOSFET chip to the copper-clad area of ​​the substrate.

[0015] As a preferred embodiment of the present invention, the upper bridge chip and the lower bridge chip each comprise five parallel SiC MOSFET chips.

[0016] In a preferred embodiment of the present invention, the substrate is a copper-clad ceramic substrate.

[0017] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects: This invention employs a Kelvin source approach to decouple the source parasitic inductance of the power circuit from the gate parasitic inductance; the Kirchhoff voltage law of the drive circuit can be expressed by formula (1): (Formula 1) in, The voltage of the driving power supply, This refers to the voltage between the gate and source of a single chip. For the current of the drive circuit, For driving resistor, This is the parasitic inductance of the drive circuit; therefore, As shown in formula (2): (Formula 2) The moment it was activated, If positive, it will lead to Decrease; at the moment of shutdown Negative, leading to Increased parasitic inductance can result from inconsistent drive loop lengths and loop areas between parallel chips. Inconsistent; drive voltage between chips during turn-on and turn-off They may also be inconsistent; In this invention, the upper and lower bridge chips are arranged in a circular pattern on the left and right sides, respectively, with their gate and Kelvin source electrodes facing the center of the circle, forming a clustered shape. The signals from the gate and Kelvin source electrodes are directly extracted through signal pins, thereby improving the consistency of the driving circuits among multiple chips. Therefore, the driving voltage between different chips is... With improved consistency, the current sharing performance of the power module is also improved accordingly. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the power module packaging structure provided in the embodiments of this application; Figure 2 A schematic diagram of the power module substrate provided in an embodiment of this application from one viewpoint; Figure 3 A schematic diagram of the power module substrate provided in an embodiment of this application from another perspective; Figure 4 The simulated drain current diagram of a SiC MOSFET power module with dual pulses provided in the embodiments of this application; Figure 5 The following is a simulated turn-on transient drain current diagram of a SiC MOSFET power module provided in this application embodiment; Figure 6 The simulated turn-on drain current diagram of the SiC MOSFET power module provided in this application embodiment is shown below.

[0019] The reference numerals in the attached figures are explained as follows: 1—Base plate; 2—Half-bridge midpoint output busbar; 3—Substrate; 4—Negative temperature coefficient thermistor; 5—Upper MOSFET high voltage DC positive busbar; 6—Lower MOSFET DC negative busbar; 7—Bonding wire; 8—Signal pin; 9—Pin socket; 10—SiC MOSFET chip; 11—Copper clip; 301—Upper MOSFET drain copper plating; 302—Negative temperature coefficient thermistor copper plating; 303—Negative temperature coefficient thermistor copper plating; 304—Ceramic insulating layer; 305—Lower MOSFET source copper plating; 306—Lower MOSFET gate copper plating; 307—Lower MOSFET Kelvin source copper plating; 308—AC output copper plating; 309—Upper MOSFET Kelvin source copper plating; 310—Upper MOSFET gate copper plating; 311—Second copper layer. Detailed Implementation

[0020] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings: The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention. The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments. The purpose and effects of the present invention will become clearer. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0021] To address the aforementioned problems, this invention provides a multi-chip parallel SiC MOSFET power module with high drive circuit symmetry, illustrated by a design example: like Figure 1 The diagram shown is a schematic diagram of the power module packaging structure provided in an embodiment of this application. Figure 2 and Figure 3 These are schematic diagrams of the power module substrate provided in the embodiments of this application from different perspectives.

[0022] This embodiment provides a multi-chip parallel high current sharing power module, which mainly includes a base plate 1, a substrate 3, an upper bridge chip and a lower bridge chip, a signal pin 8 and a pin header 9, etc.

[0023] The base plate 1 provides functions such as heat dissipation, mechanical support, and grounding. The base plate 1 is usually made of metal, which has good thermal conductivity and mechanical strength, and can conduct away the heat generated during the operation of the power module in a timely manner, while providing structural support for the entire module.

[0024] The substrate 3 is mounted on the base plate 1 and undertakes the core functions of insulation, heat conduction, and current flow in the circuit layout of the entire power module. The substrate 3 consists of a first copper layer, a ceramic insulating layer 304, and a second copper layer 311. The first copper layer further includes copper clad at the drain of the upper transistor 301, copper clad at the negative temperature coefficient thermistors 302 and 303, copper clad at the source of the lower transistor 305, copper clad at the AC output 308, copper clad at the gate of the upper transistor 310, copper clad at the Kelvin source of the upper transistor 309, copper clad at the gate of the lower transistor 306, and copper clad at the Kelvin source of the lower transistor 307. Preferably, the substrate 3 is a copper-clad ceramic substrate, i.e., a DBC substrate. The DBC substrate has excellent insulation and thermal conductivity, meeting the insulation and heat dissipation requirements of the power module under high voltage and high current conditions.

[0025] The upper and lower bridge chips are each composed of multiple SiC MOSFET chips 10. In this embodiment, the upper and lower bridge chips each include five SiC MOSFET chips 10 connected in parallel. The actual number of parallel chips can be set according to application requirements, such as 3 to 8, and the corresponding substrate size will also be larger. The upper bridge chips are arranged in a circular pattern on one side of the substrate 3. Figure 1 As shown in the left-hand area, the lower bridge chip is distributed in a circular pattern on the other side of substrate 3. Figure 1 As shown in the right-hand region, the gate and Kelvin source electrodes of each SiC MOSFET chip 10 are clustered together, oriented towards the center of the circle. This circular clustering layout ensures that the drive circuit length and circuit area of ​​each parallel chip are highly consistent, effectively reducing the differences in parasitic parameters of the drive circuits between chips.

[0026] The two terminals of the negative temperature coefficient thermistor 4 are respectively mounted on the negative temperature coefficient thermistor copper layers 302 and 303 of the first copper layer of the substrate 3. The negative temperature coefficient thermistor 4 is used to monitor the temperature of the power module in real time. When the module temperature is too high, the output of the power module can be reduced by the control circuit or protective measures can be taken to prevent the module from being damaged due to overheating.

[0027] The upper high-voltage DC positive busbar 5 is connected to the positive terminal of the DC bus capacitor, and the lower DC negative busbar 6 is connected to the negative terminal of the DC bus capacitor. The upper high-voltage DC positive busbar 5 and the lower DC negative busbar 6 are the positive and negative input terminals of the half-bridge module, respectively, used to introduce the DC bus voltage into the power module.

[0028] The half-bridge midpoint output busbar 2 is the AC output terminal of the half-bridge, which is used to connect loads such as motor windings and transformer primary windings. The half-bridge midpoint output busbar 2 outputs the AC power converted by the power module to the external load.

[0029] Bonding wire 7 is used to realize the electrical connection between the gate signal and the Kelvin source signal of the SiC MOSFET chip 10. The gate and Kelvin source of the SiC MOSFET chip 10 are connected to the corresponding gate copper-clad area and Kelvin source copper-clad area on the first copper layer of the substrate 3 through bonding wire 7.

[0030] Signal pin 8 and pin holder 9 are connected. Pin holder 9 is fixed to the corresponding copper-plated area of ​​the first copper layer of substrate 3 by solder. Signal pin 8 and pin holder 9 are interference-fitted to achieve electrical connection. The signals of the gate and Kelvin source are directly led out to the external driving circuit through signal pin 8.

[0031] The copper clips 11 are used to connect the source of the SiC MOSFET chip 10 to the copper-clad area of ​​the substrate 3. Each copper clip 11 connects to one SiC MOSFET chip 10, and there are 10 copper clips 11 in this embodiment. The copper clips 11 have the advantages of low resistance and low parasitic inductance, which can effectively reduce the parasitic parameters of the power circuit.

[0032] The following is combined with Figures 4 to 6 The flow equalization effect of the present invention will be explained.

[0033] Figures 4 to 6 The image shows the electromagnetic co-simulation results of a dual-pulse test on a 5-parallel SiC MOSFET chip. The dual-pulse test bus voltage is 800V, and the total load current is 560A. Figure 5 As shown, when the second pulse is turned on, the maximum dynamic current difference is 14.6A, and the currents passing through the five parallel chips are 108.3A, 108.8A, 94.1A, 108.7A, and 108.8A, respectively, with a uniformity of less than 11%. Figure 6 As shown, after the second pulse turns on, the static current difference of the five parallel SiC MOSFET chips is 1.4A. The above simulation results fully demonstrate that the power module provided by this invention has excellent current sharing performance.

[0034] A multi-chip parallel connection method with high drive circuit consistency is proposed. The upper and lower bridge chips are arranged in a circle on the left and right sides respectively, with their gate and Kelvin source electrodes facing the center of the circle, forming a clustered shape. The signals from the gate and Kelvin source electrodes are directly led out through signal pins, thereby improving the drive circuit consistency among multiple chips.

[0035] Inconsistent parasitic inductance in the drive circuits of parallel SiC chips can cause problems such as inconsistent chip turn-on sequence, inconsistent overcurrent, and voltage spikes during the turn-on and turn-off phases, ultimately reducing module reliability and lifespan.

[0036] By employing a Kelvin source approach, the parasitic inductance of the power circuit's source is decoupled from the parasitic inductance of the gate circuit. Kirchhoff's voltage law for the drive circuit can be expressed by equation (1): (Formula 1) in, The voltage of the driving power supply, Voltage between the gate and the source For the current of the drive circuit, For driving resistor, This is the parasitic inductance of the drive circuit. Therefore, As shown in formula (2): (Formula 2) The moment it was activated, If positive, it will lead to Decrease; at the moment of shutdown Negative, leading to Increased parasitic inductance can result from inconsistent drive loop lengths and loop areas between parallel chips. Inconsistent. The drive voltage between the chips during turn-on and turn-off. There will also be inconsistencies.

[0037] In this invention, the upper and lower bridge chips are arranged in a circular pattern on the left and right sides, respectively, with their gate and Kelvin source electrodes facing the center of the circle, forming a clustered shape. The signals from the gate and Kelvin source electrodes are directly extracted through signal pins, thereby improving the consistency of the drive circuits among multiple chips. Therefore, the drive voltage between different chips is... With improved consistency, the current sharing performance of the power module is also improved accordingly.

[0038] It will be understood by those skilled in the art that the above descriptions are merely preferred examples of the invention and are not intended to limit the invention. Although the invention has been described in detail with reference to the foregoing examples, those skilled in the art can still modify the technical solutions described in the foregoing examples or make equivalent substitutions for some of the technical features. All modifications and equivalent substitutions made within the spirit and principles of the invention should be included within the scope of protection of the invention. All technical features in this embodiment can be freely combined according to actual needs.

[0039] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A multi-chip parallel high current-sharing power module, characterized in that, include: The base plate (1) provides heat dissipation, mechanical support and grounding carrier; The substrate (3) is disposed on the base plate (1) and undertakes the functions of insulation, heat conduction and circuit layout current conduction. The substrate (3) includes a first copper layer, a ceramic insulating layer (304) and a second copper layer (311). The upper bridge chip and the lower bridge chip are multiple SiC MOSFET chips (10), the upper bridge chip is circularly distributed on one side of the substrate (3), and the lower bridge chip is circularly distributed on the other side of the substrate (3); The gate and Kelvin source electrodes of the SiC MOSFET chip (10) are oriented toward the circular center and are clustered together. The first copper layer of the substrate (3) is provided with a gate copper-clad region and a Kelvin source copper-clad region. The signals of the gate and the Kelvin source are connected to the gate copper-clad region and the Kelvin source copper-clad region through bonding wires (7). Signal Pin (8) and Pin Socket (9), the Pin Socket (9) is fixed to the corresponding copper-plated area of ​​the first copper layer of the substrate (3) by soldering, the signal Pin (8) and the Pin Socket (9) are electrically connected by interference fit, and the signals of the gate and Kelvin source are directly led out through the signal Pin (8).

2. The multi-chip parallel high current sharing power module according to claim 1, characterized in that, The first copper layer of the substrate (3) includes copper cladding on the drain of the upper transistor (301), copper cladding on the negative temperature coefficient thermistor (302, 303), copper cladding on the source of the lower transistor (305), copper cladding on the AC output (308), copper cladding on the gate of the upper transistor (310), copper cladding on the Kelvin source of the upper transistor (309), copper cladding on the gate of the lower transistor (306), and copper cladding on the Kelvin source of the lower transistor (307).

3. The multi-chip parallel high current sharing power module according to claim 1, characterized in that, It also includes a negative temperature coefficient thermistor (4), the two terminals of which are respectively attached to the negative temperature coefficient thermistor copper cladding (302) and the negative temperature coefficient thermistor copper cladding (303) of the first copper layer of the substrate (3).

4. The multi-chip parallel high current sharing power module according to claim 1, characterized in that, It also includes an upper high-voltage DC positive busbar (5) and a lower DC negative busbar (6), wherein the upper high-voltage DC positive busbar (5) is connected to the positive terminal of the DC bus capacitor, and the lower DC negative busbar (6) is connected to the negative terminal of the DC bus capacitor.

5. The multi-chip parallel high current sharing power module according to claim 1, characterized in that, It also includes a half-bridge midpoint output busbar (2), which is the AC output terminal of the half-bridge.

6. The multi-chip parallel high current sharing power module according to claim 1, characterized in that, It also includes copper clips (11), each of which connects the source of a SiC MOSFET chip (10) to the copper-clad area of ​​the substrate (3).

7. The multi-chip parallel high current sharing power module according to claim 1, characterized in that, The upper bridge chip and the lower bridge chip each include five parallel SiC MOSFET chips (10).

8. The multi-chip parallel high current sharing power module according to any one of claims 1 to 7, characterized in that, The substrate (3) is a copper-clad ceramic substrate.

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