A method for preparing a pattern of a copper-plated PCB board and application thereof

Abstract

The application discloses a kind of pattern preparation method and application of copper-plated PCB, comprising: scanning the circuit board that has completed drilling and copper deposition, obtains the three-dimensional feature data of circuit board surface;Three-dimensional feature data is input to the preset electroplating simulation system and the board surface current density atlas of circuit board is obtained;According to board surface current density atlas, exposure and development are formed on the substrate that has pasted photosensitive dry film Line pattern;According to the three-dimensional feature data of circuit board, determine the multiple partitions of line pattern, and according to multiple partitions, dynamic electroplating is carried out using different electroplating processes, and the line pattern of circuit board is formed.The application carries out partition dynamic control to electroplating process, carries out differential treatment for via / blind hole area, line area and gold finger area, solves the problems of "bubble type hole break" and "hole filling depression" of micro hole, eliminates the risk of "film clamping" and "leaching" of fine line, significantly improves product yield and reliability.

Description

Technical Field

[0001] This invention belongs to the field of electronic technology, and in particular relates to a method for preparing patterns on copper-plated PCB boards and its application. Background Technology

[0002] In recent years, PCBs (Printed Circuit Boards) with ultra-thick copper or embedded copper blocks have provided necessary electrical connections and mechanical support for electronic components, and have broad market prospects.

[0003] Currently, PCB pattern plating is the mainstream pattern fabrication method. However, this method suffers from the following technical problems: In-hole defects: When plating tiny blind holes (diameter ≤ 0.1mm), chemical bubbles are difficult to expel, causing "hole breakage." Uneven current distribution leads to hole filling depressions, affecting the reliability of the stack-up. Fine line defects: When line width / spacing is ≤ 50μm, the dry film thickness limitation causes lateral growth of the plated copper layer ("film trapping"), or chemical seepage into the bottom of the dry film ("bleed-in plating"), causing short circuits or open circuits. Poor surface copper uniformity: Over-plating the board surface to ensure sufficient plating thickness for small holes results in uneven copper thickness, wasting material and increasing the difficulty of subsequent etching. Summary of the Invention

[0004] This invention provides a method for fabricating patterns on a copper-plated PCB board, comprising: Scan the circuit board that has been drilled and copper plating to obtain three-dimensional feature data of the circuit board surface; The three-dimensional feature data is input into a preset electroplating simulation system to obtain the current density spectrum of the circuit board surface; The circuit pattern is formed by exposure and development on a substrate with a photosensitive dry film already bonded according to the current density spectrum of the board surface. The dry film thickness in the high current density region is greater than a preset value. The high current density region is the region where the current density shown in the current density spectrum of the board surface exceeds the preset value. The circuit pattern is divided into multiple partitions based on the three-dimensional feature data of the circuit board, and dynamic electroplating is performed on the multiple partitions using different electroplating processes to form the circuit pattern of the circuit board.

[0005] Furthermore, the circuit board that has undergone drilling and copper plating is scanned to obtain three-dimensional feature data of the circuit board surface, including: The three-dimensional feature data is obtained by acquiring all hole information, circuit information and gold finger information on the circuit board surface through 3D laser scanning. The hole information includes the hole location, hole diameter and depth-to-diameter ratio; the circuit information includes the line width and line spacing; and the gold finger information includes the location and size of the gold finger area.

[0006] Furthermore, it also includes: The electroplating simulation system uses its built-in fluid dynamics model and electric field distribution model to analyze the three-dimensional feature data and identifies the area indicated by the tip feature as a high current density area. The area indicated by the line information belongs to the high current density area.

[0007] Furthermore, the anode of the electroplating tank includes multiple independently controllable micro anode units, each of which corresponds to multiple micro regions of the circuit pattern, and a programmable ultrasonic oscillation array is provided at the bottom of the circuit board; The step of determining multiple partitions of the circuit pattern based on the three-dimensional feature data of the circuit board, and performing dynamic electroplating using different electroplating processes on the multiple partitions, includes: The via-filling area and fine line area in the circuit board are determined based on the three-dimensional feature data; A high-frequency pulsed current is applied to the microanode unit corresponding to the filling area, and the programmable ultrasonic oscillation array is activated. The average current density of the fine line area is controlled within a preset range, and the current density is adjusted according to the copper plating thickness to ensure that the copper plating thickness of the fine line area is within the preset range.

[0008] Furthermore, it also includes: After the copper plating of the circuit is completed, the film is not removed, and the solution is switched to tin-free plating solution. The gold finger area in the circuit board is determined based on the three-dimensional feature data; Control the electroplating alloy protective layer of the micro-anodine unit corresponding to the circuit board area other than the gold finger area.

[0009] Furthermore, it also includes: The high current density region in the circuit pattern is exposed multiple times so that the thickness of the high density region after development is greater than a preset value.

[0010] Furthermore, it also includes: handling differences in the gold finger area; specifically including: The circuit board is subjected to film stripping and alkaline etching to remove exposed copper foil; Inkjet printing technology is used to print plating-resistant insulating ink in the non-gold finger areas, exposing only the gold finger areas; The circuit board is immersed in a hard gold plating solution, and a hard gold layer is deposited in the gold finger area by jet plating perpendicular to the board surface.

[0011] Furthermore, it also includes: post-processing; specifically including: Remove the alloy protective layer to expose the pure copper traces; Perform solder resist and surface treatment.

[0012] This invention provides a PCB circuit board, which is obtained according to the above-described method for preparing the pattern of a copper-plated PCB board.

[0013] This invention provides an application of the above-described method for preparing patterns on copper-plated PCB boards in the fabrication of electronic devices.

[0014] The copper-plated PCB pattern preparation method disclosed in this invention combines artificial intelligence and Internet of Things pre-analysis models with partitioned dynamic current control technology. The electroplating process is divided into partitioned dynamic circuits, that is, differentiated treatment is performed on the through-hole / blind hole area, fine line area and gold finger area on the board. This effectively solves the problems of "bubble-type hole breakage" and "hole filling depression" of micro holes, eliminates the risks of "film trapping" and "plating penetration" of fine lines, and simultaneously completes the production of highly uniform surface copper and local high wear-resistant gold fingers in one process, significantly improving product yield and reliability. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic flowchart illustrating a method for fabricating a pattern on a copper-plated PCB board, as provided in an embodiment of the present invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0018] like Figure 1 As shown, a method for fabricating a pattern on a copper-plated PCB board includes the following steps: S1. Scan the circuit board that has been drilled and copper plating to obtain the three-dimensional feature data of the circuit board surface; After cleaning the surface of the circuit board that has been drilled and copper plating, a 3D laser scanner is used to scan the circuit board to obtain three-dimensional feature data of all holes on the board surface, including the location, diameter, and aspect ratio of the holes, the line width and spacing of the lines, and the gold fingers. The three-dimensional feature data includes 3D images and parameter values ​​of each hole, line, and gold finger.

[0019] S2. Input the three-dimensional feature data into the preset electroplating simulation system to obtain the current density spectrum of the circuit board surface; The electroplating simulation system incorporates fluid dynamics and electric field distribution models. It analyzes the current density distribution of the circuit board by examining the location, line width, and spacing of holes and lines, thereby obtaining a current density spectrum.

[0020] The electroplating simulation system is an intelligent platform integrating multiphysics simulation, machine learning prediction models, and real-time closed-loop control. Its core function is to simulate "virtual electroplating" on the circuit board before the actual electroplating process, predict the plating layer distribution under different process parameters, and automatically output the optimal zone control process method. The electroplating simulation system includes a current density spectrum prediction model and an electroplating parameter simulation model.

[0021] In the initial state, the current density map prediction model can utilize an AIoT pre-analysis model. Specifically, it calculates the characteristic parameters of the electroplating distribution in each micro-region of the circuit board based on 3D feature data; predicts the current density of each micro-region based on the input characteristic parameters using a pre-defined current density model; and summarizes the current densities of each micro-region in the circuit board to form a current density map. The characteristic parameters include isolation degree, aperture density, and surface area ratio, which directly affect the electroplating distribution. In practical applications, the circuit board can be divided into multiple micro-regions, and the electroplating distribution parameters in each micro-region can be calculated. In practical applications, models such as LightGBM, neural network models, and ResUnet-Trans-CGAN can be used to predict the current density based on the characteristic parameter current density.

[0022] The electroplating parameter simulation model includes: an electric field simulation module, a flow field simulation module, a concentration field simulation module, and a temperature field simulation module. In this model, the Laplace equation is used to simulate the electric field, the Navier-Stokes equation to simulate the flow field, the convection-diffusion equation to simulate the concentration field, and the heat conduction equation to simulate the temperature field. The model simulates and analyzes the initial current density to obtain process parameters such as the coating thickness distribution, surface roughness, and grain size in the micro-region, and controls the electroplating system to perform electroplating according to these process parameters. The model can also employ a conditional latent diffusion model to map electroplating parameters (e.g., current waveform, temperature, additive concentration) to scanning electron microscope images, achieving end-to-end prediction from process parameters to coating morphology (e.g., crack formation).

[0023] The current density spectrum prediction model uses the process parameters output by the electroplating parameter simulation model to perform secondary current density prediction on the micro-area morphology after electroplating, and obtains a secondary current density spectrum. The electroplating parameter simulation model then outputs new process parameters until electroplating is completed.

[0024] The generation of the current density map in S2 of this embodiment is detailed in the processing procedure of the current density map prediction model, that is, the characteristic parameters of the electroplating distribution in each micro-area of ​​the circuit board are calculated based on the three-dimensional feature data; the current density of each micro-area is obtained by predicting the input characteristic parameters according to the preset current density model; and the current density in each micro-area of ​​the circuit board is summarized to form a current density map.

[0025] S3. Expose and develop the photosensitive dry film onto the substrate according to the current density spectrum to form the circuit pattern; In this embodiment, the current density spectrum on the board surface shows the required current density of each area of ​​the circuit pattern, which together constitutes the entire circuit pattern. The entire outline of the circuit pattern can be displayed by exposing and developing the photosensitive dry film.

[0026] Typically, high current density areas in circuit patterns are usually board corners, board edges, isolated or thick lines, and the edges of vias or blind holes. Because these areas have abrupt changes such as "sharp points", their electric field lines are more concentrated and the current density is relatively higher than other areas, which will attract more current, resulting in faster and thicker copper layer deposition at these locations, which can easily cause "film sandwich" defects.

[0027] To address the above issues, in this embodiment, high current density regions are identified in the circuit pattern using image recognition technology. This means that regions where the current density exceeds a preset value are identified from the current density spectrum on the board surface, and the dry film thickness in these high current density regions is set to be greater than the preset value.

[0028] In practical applications, when the copper layer thickness exceeds the dry film thickness during electroplating, the copper will grow laterally, covering the dry film. After film removal, the laterally grown copper will remain between the circuits, easily causing short circuits. Therefore, a thicker dry film provides more vertical growth space for copper deposition. The copper layer needs more time to grow to be flush with the top of the dry film, thus significantly delaying the occurrence of lateral growth and effectively preventing the electroplated copper from spreading laterally across the top of the dry film, thereby avoiding "film trapping" defects. In addition, a thicker dry film allows for a greater range of electroplating time fluctuations. Even if some local deposition is slightly faster, it will not immediately lead to defects, improving the robustness of the production process.

[0029] S4. Determine multiple partitions of the circuit pattern according to the three-dimensional feature data of the circuit board, and perform dynamic electroplating using different electroplating processes according to the multiple partitions to form the circuit pattern of the circuit board.

[0030] In this embodiment, the circuit pattern includes multiple partitions: a via-filling area, a fine-line area, and a gold finger area. Since each partition requires a different electroplating process—for example, the via-filling area is prone to micro-hole defects, the fine-line area may have a risk of "film trapping," and the gold finger area is prone to cross-contamination during electroplating, requiring process transfer—this embodiment of the invention dynamically adjusts the electroplating process for different partitions to avoid the problems mentioned above.

[0031] The copper-plated PCB pattern preparation method of this invention combines artificial intelligence and Internet of Things pre-analysis models with partitioned dynamic current control technology. The electroplating process is divided into partitioned dynamic circuits, that is, differentiated treatment is applied to the through-hole / blind hole area, the fine line area and the gold finger area on the board. This effectively solves the problems of "bubble-type hole breakage" and "hole filling depression" of micro holes, eliminates the risks of "film trapping" and "plating penetration" of fine lines, and simultaneously completes the production of highly uniform surface copper and local high wear-resistant gold fingers in one process, significantly improving product yield and reliability.

[0032] In one embodiment of the present invention, step S1, which involves scanning the circuit board that has undergone drilling and copper plating to obtain three-dimensional feature data of the circuit board surface, specifically includes: 3D laser scanning is used to acquire three-dimensional feature data of all holes, circuit lines, and gold fingers on the circuit board surface. Hole information includes hole location, diameter, and aspect ratio; circuit information includes line width and spacing; and gold finger information includes the location and size of the gold finger area. This complete acquisition of the circuit board's overall morphological features prepares the board for subsequent processes.

[0033] In one embodiment of the present invention, the electroplating simulation system determines the circuit pattern based on three-dimensional feature data and identifies high current density regions and low current density regions, specifically: The electroplating simulation system uses built-in fluid dynamics and electric field distribution models to analyze three-dimensional feature data. It identifies the hole center region indicated by hole information as a low current density region and the region indicated by tip features as a high current density region. The region indicated by line information is a high current density region.

[0034] In practical applications, tip features also include: abrupt changes such as the edge of the orifice and protrusions.

[0035] In some embodiments, the high current density areas in the circuit pattern are exposed multiple times to make the thickness of the high-density areas after development greater than a preset value. This allows for the deposition of a thicker copper layer in the high-density areas, meaning that it takes longer for the copper layer to grow to be flush with the top of the dry film, thereby delaying the occurrence of lateral growth, preventing the lateral spread of electroplated copper, and avoiding "film trapping" defects.

[0036] In one embodiment of the present invention, in order to perform dynamic electroplating on the above-mentioned partitions using different electroplating processes, the anode of the electroplating tank used in this embodiment includes multiple independently controllable micro anode units, each micro anode unit corresponding to multiple micro regions of the circuit pattern, and a programmable ultrasonic oscillation array is provided at the bottom of the circuit board.

[0037] It should be noted that the micro-anodist unit is designed for precise control of the electroplating process in its corresponding patterned circuit area. Specifically, step S4 includes the following steps: Step 1: Determine the via filling area and fine line area in the circuit board based on the three-dimensional feature data; Step 2: Apply a high-frequency pulsed current to the microanode unit corresponding to the filling area and start the programmable ultrasonic oscillation array; Step 3: Control the average current density in the fine line area within the preset range, and adjust the current density according to the copper plating thickness to ensure that the copper plating thickness in the fine line area is within the preset range.

[0038] In this embodiment, during the initial stage of copper plating, i.e., 0-15 minutes after the start of electroplating, a high-frequency pulse current is applied to the anode unit corresponding to the identified hole-filling area (blind hole / through hole area). The frequency can be set to 1000-3000Hz, and the ultrasonic oscillation array at the corresponding position under the circuit board is activated. The ultrasonic oscillation can expel air bubbles in the hole, and the high-frequency pulse current can promote deposition at the bottom of the hole, thus achieving hole filling and avoiding depression.

[0039] The intermediate stage of copper plating mainly involves the electroplating of fine-line areas. 15-45 minutes after plating begins, the average current density across the entire board is reduced to 70%-80% of that in conventional processes, thus entering the slow-speed plating stage. The key to this process is controlling the current density within a small range and dynamically adjusting it according to the copper plating thickness to ensure the thickness of the fine-line areas does not exceed a preset range. In actual electroplating, the current to the corresponding anode unit in this area can be dynamically reduced (or even temporarily shut off) to suppress lateral copper layer growth and avoid "film trapping." In practical applications, for sharp features such as aperture edges and protrusions, the fine-line area electroplating process can be used. During electroplating, the anode micro-units corresponding to the sharp feature areas can be plating within a smaller current density range.

[0040] In some embodiments, for the gold finger area, after the copper layer electroplating of the circuit is completed, no film removal is performed, and the solution is switched to tin-free plating solution; the gold finger area in the circuit board is determined based on the three-dimensional feature data; and the micro-anodist unit corresponding to the circuit board area other than the gold finger area is electroplated with an alloy protective layer.

[0041] In this embodiment, the electroplating bath is switched to a low-stress tin-free plating solution. By controlling the micro-anodist unit corresponding to the non-gold finger area, a tin-based alloy protective layer with a thickness of 0.5-1μm is selectively electroplated only on the top of the line in the non-gold finger area for protection during subsequent alkaline etching. The low-stress tin-free plating solution can be a nickel sulfamate plating solution. The temperature is usually maintained at 55-60℃ and the pH value is stable between 3 and 4 during electroplating. A wetting agent (such as sodium dodecyl sulfate) is added to prevent pinholes.

[0042] In some embodiments, the method further includes: gold finger area difference processing; specifically including: The circuit board undergoes a stripping and alkaline etching process to remove exposed copper foil. Inkjet printing technology is used to print plating-resistant insulating ink in the non-gold finger areas, exposing only the gold finger areas. The circuit board is then immersed in a hard gold plating solution (gold-cobalt alloy), and a hard gold layer is deposited in the gold finger areas through jet plating perpendicular to the board surface. Typically, the thickness of the hard gold layer is ≥0.5μm.

[0043] In some embodiments, the method further includes: post-processing; specifically including: removing the alloy protective layer to expose the pure copper circuitry; performing solder resist and surface treatment.

[0044] One embodiment of the present invention includes, on a 300mm × 400mm circuit board: 100 blind vias with a diameter of 0.1mm, a dense bus region with a line width / spacing of 30μm / 30μm, and a standard PCIe gold finger. After 3D scanning, the AI ​​model calculates that the blind via region requires high current density and ultrasonic assistance, while the dense bus region requires strict limitation of current peak value. Using LDI exposure, the dry film thickness of the dense bus region is set to 38μm (conventionally 30μm).

[0045] During the copper electroplating process, for the first 10 minutes, the anode current density for the blind vias was 2.5 ASD, and the ultrasonic power was 50W; the anode current density for the bus area was 0.8 ASD. From 10 to 40 minutes, the current in the blind via area was reduced to 1.2 ASD, while the current in the bus area was maintained at 0.8 ASD and dynamically adjusted. Then, the plating solution was switched to nickel sulfamate plating solution, and tin-based alloy was electroplated onto the top of the non-gold finger circuitry. When preparing the gold finger area, etching and inkjet printing were used to cover the non-gold finger areas, followed by jet electroplating of 0.8 μm of hard gold. This process was tested and showed no hole breakage or film trapping, with a copper surface difference of <3 μm, and a contact resistance change of <5% after 2000 gold finger insertion and removal cycles.

[0046] This invention completely solves the problems of "hole breakage" and hole-filling depression in high aspect ratio microvias by predicting bubble positions and actively intervening with zoned ultrasonic waves and pulsed current. Through dynamic variable anodic current and differentiated dry film thickness, the lateral growth of copper is suppressed at its source, allowing linewidth / spacing to be stably below 25μm / 25μm. Furthermore, it eliminates the need for excessive plating of the entire board to accommodate small holes, and the difference in surface copper thickness can be controlled within ±2μm, significantly saving copper material and reducing etching difficulty. In terms of process flow, by switching the plating solution and anodic control logic on a single plating equipment, thick gold plating of the hole-filling area, fine line area, selective protection, and gold finger area is completed sequentially, reducing the risk of process transfer and cross-contamination.

[0047] This invention provides a PCB circuit board, specifically: suitable for high-density interconnect (HDI) boards, IC carrier boards, and boards with gold finger structures. The fabrication method of this circuit board is detailed in the above-mentioned pattern fabrication method for copper-plated PCB boards, and will not be repeated here.

[0048] The pattern preparation method for copper-plated PCBs disclosed in this invention can be used to process electronic devices.

[0049] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

[0050] The above description is only a partial embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for preparing a pattern on a copper-plated PCB board, characterized in that, include: Scan the circuit board that has been drilled and copper plating to obtain three-dimensional feature data of the circuit board surface; The three-dimensional feature data is input into a preset electroplating simulation system to obtain the current density spectrum of the circuit board surface; The circuit pattern is formed by exposure and development on a substrate with a photosensitive dry film already bonded according to the current density spectrum of the board surface. The dry film thickness in the high current density region is greater than a preset value. The high current density region is the region where the current density shown in the current density spectrum of the board surface exceeds the preset value. The circuit pattern is divided into multiple partitions based on the three-dimensional feature data of the circuit board, and dynamic electroplating is performed on the multiple partitions using different electroplating processes to form the circuit pattern of the circuit board.

2. The method for fabricating the pattern of a copper-plated PCB board according to claim 1, characterized in that, Scan the circuit board that has been drilled and copper plating applied to obtain three-dimensional feature data of the circuit board surface, including: The three-dimensional feature data is obtained by acquiring all hole information, circuit information and gold finger information on the circuit board surface through 3D laser scanning. The hole information includes the hole location, hole diameter and depth-to-diameter ratio; the circuit information includes the line width and line spacing; and the gold finger information includes the location and size of the gold finger area.

3. The method for preparing the pattern of a copper-plated PCB board according to claim 2, characterized in that, Also includes: The electroplating simulation system uses its built-in fluid dynamics model and electric field distribution model to analyze the three-dimensional feature data and identifies the area indicated by the tip feature as a high current density area. The area indicated by the line information belongs to the high current density area.

4. The method for preparing the pattern of a copper-plated PCB board according to claim 1, characterized in that, The anode of the electroplating tank includes multiple independent and controllable micro anode units, each of which corresponds to multiple micro regions of the circuit pattern, and a programmable ultrasonic oscillation array is provided at the bottom of the circuit board; The step of determining multiple partitions of the circuit pattern based on the three-dimensional feature data of the circuit board, and performing dynamic electroplating using different electroplating processes on the multiple partitions, includes: The hole-filling area and the fine line area in the circuit board are determined based on the three-dimensional feature data; A high-frequency pulsed current is applied to the microanode unit corresponding to the filling area, and the programmable ultrasonic oscillation array is activated. The average current density of the fine line area is controlled within a preset range, and the current density is adjusted according to the copper plating thickness to ensure that the copper plating thickness of the fine line area is within the preset range.

5. The method for preparing the pattern of a copper-plated PCB board according to claim 1, characterized in that, Also includes: After the copper plating of the circuit is completed, the film is not removed, and the solution is switched to tin-free plating solution. The gold finger area in the circuit board is determined based on the three-dimensional feature data; Control the electroplating alloy protective layer of the micro-anodine unit corresponding to the circuit board area other than the gold finger area.

6. The method for preparing the pattern of a copper-plated PCB board according to claim 1, characterized in that, Also includes: The area outside the high current density region in the circuit pattern is exposed multiple times so that the thickness of the high density region after development is greater than a preset value.

7. The method for preparing the pattern of a copper-plated PCB board according to claim 5, characterized in that, Also includes: Difference handling in the gold finger area; specifically including: The circuit board is subjected to film stripping and alkaline etching to remove exposed copper foil; Inkjet printing technology is used to print plating-resistant insulating ink in the non-gold finger areas, exposing only the gold finger areas; The circuit board is immersed in a hard gold plating solution, and a hard gold layer is deposited in the gold finger area by jet plating perpendicular to the board surface.

8. The method for preparing the pattern of a copper-plated PCB board according to claim 5, characterized in that, Also includes: Post-processing; specifically including: Remove the alloy protective layer to expose the pure copper traces; Perform solder resist and surface treatment.

9. A PCB circuit board, characterized in that, The copper-plated PCB board is obtained by the pattern preparation method according to any one of claims 1 to 9.

10. An application of the pattern preparation method of the copper-plated PCB board according to any one of claims 1 to 9 in the processing of electronic devices.

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