Symmetrical laminated structure AI computing card plate and pressing method thereof

Abstract

The application discloses an AI computing card plate with a symmetrical laminated structure and a pressing method thereof, the AI computing card plate comprises a symmetrical laminated structure, a thick copper power layer region is arranged in the middle, thin copper signal layer regions are symmetrically distributed on both sides, the thick copper power layer region comprises a power conductive layer with a copper thickness of not less than 2 oz, the thin copper signal layer region comprises a signal conductive layer with a copper thickness of not more than 1 / 3 oz, and the insulating dielectric layers are all made of M6 high-speed BT resin-based materials. The pressing method comprises four stages of preheating and exhausting, pressure filling, curing and cross-linking and cooling and pressure releasing, wherein the pressure filling stage is constant-temperature and pressure-increasing to above 360 psi at a temperature window of 180 DEG C, and the cooling and pressure releasing stage is stepwise cooling and pressure releasing. Through the synergistic effect of the low CTE and high flowability of the M6 high-speed BT resin-based material and the symmetrical laminated structure, the AI computing card BGA region flatness is within 3 mil, and the requirements of high-speed signal integrity and SMT furnace reliability are met.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board manufacturing technology, specifically to an AI computing power card and its lamination method, and more particularly to an AI computing power card that uses BT resin-based material and achieves ultra-high flatness in the BGA area through a symmetrical stacked structure design, and its lamination method in the manufacturing process. Background Technology

[0002] AI computing cards are the core hardware carriers in artificial intelligence computing clusters. The GPUs or AI acceleration chips they carry are typically interconnected with the PCB board in BGA packaging. As chip integration increases, the size of BGA packages continues to grow, placing stringent requirements on the flatness of the BGA area on the PCB board. It usually needs to be controlled within 3mil; otherwise, defects such as cold solder joints and bridging will occur during SMT reflow soldering, leading to a decrease in assembly yield.

[0003] In PCB substrate material selection, BT resin-based copper clad laminates are commonly used in the IC substrate field. BT materials have a high glass transition temperature (Tg) and a low coefficient of thermal expansion (CTE), exhibiting good material stability and achieving good BGA flatness. However, the resin formulation of traditional BT materials for IC substrates is a highly cross-linked, low-flow pure BMI-triazine system. In multilayer board lamination processes, the resin flow window is extremely narrow, easily leading to the following problems: uneven dielectric layer thickness, insufficient fiberglass cloth wetting, and localized resin enrichment or deficiency. These defects result in significant differences in the dielectric loss factor (Df) at different locations on the PCB, with some areas having a Df of 0.002 while others reach 0.005. Although the overall average Df index of the board is acceptable, in actual high-speed signal transmission, the loss differences caused by signals passing through different Df paths can severely degrade signal integrity, failing to meet the high-speed signal transmission requirements of AI computing cards.

[0004] On the other hand, while using a conventional FR-4 material system, combined with an M6-grade high-speed formulation, can meet the uniformity requirements of dielectric properties to some extent, the X / Y axis CTE of FR-4 material is typically 13-18 ppm / ℃, and the Z-axis CTE (α1) is typically as high as 50-70 ppm / ℃, far exceeding that of BT material. Under the peak SMT reflow soldering temperature of 245℃, the Z-axis expansion and contraction of FR-4 board material is large. For AI computing power boards containing thick copper inner layers for high current power supply, the difference in expansion and contraction between the thick and thin copper layers can significantly increase the risk of reliability failures such as hole ring cracking and blind hole wall copper cracking.

[0005] Therefore, in existing technologies, there is an inherent contradiction between BT and FR-4 material solutions: BT material achieves good flatness but cannot meet the requirements of high-speed signal uniformity, while FR-4 material can meet high-speed performance but suffers from poor flatness and reliability. The industry lacks an AI computing power card structure solution and manufacturing process that can simultaneously achieve both ultra-high flatness of BGA and high-speed signal integrity. Summary of the Invention

[0006] The purpose of this invention is to provide an AI computing power card with a symmetrical stacked structure and its lamination method, to solve the technical problem that existing technologies cannot simultaneously meet the requirements of ultra-high flatness and high-speed signal integrity of BGA. In this invention, M6-grade high-speed BT resin-based material refers to BT resin-based copper-clad laminate material that meets the following performance parameters: dielectric loss factor Df≤0.005 at 10GHz frequency, X / Y axis thermal expansion coefficient CTE≤12ppm / ℃, Z axis thermal expansion coefficient CTEα1≤30ppm / ℃, and glass transition temperature Tg≥200℃.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows: An AI computing power card board, comprising a board body formed by alternating and laminating multiple conductive layers and insulating dielectric layers, the AI ​​computing power card board comprising: a symmetrical stacked structure, which includes a thick copper power layer region located in the middle and thin copper signal layer regions symmetrically distributed on both sides of the thick copper power layer region; the thick copper power layer region includes at least one power conductive layer with a copper thickness ≥ 2 oz; the thin copper signal layer regions include at least one signal conductive layer with a copper thickness ≤ 1 / 3 oz; wherein, the insulating dielectric layers in the thick copper power layer region and the thin copper signal layer region are both made of M6 grade high-speed BT resin-based material. This solution, by using M6 grade high-speed BT resin-based material in conjunction with a symmetrical stacked structure design, reduces the amount of thermally induced dimensional changes from the material source, while utilizing the symmetrical structure to uniformly distribute thermal stress, thus achieving both 3mil ultra-high flatness and high-speed signal integrity in the BGA area of ​​the AI ​​computing power card board.

[0008] In the AI ​​computing power card of this invention, the M6-grade high-speed BT resin-based material is Taiguang EM-528 BT material. Taiguang EM-528 is a typical M6-grade high-speed BT resin-based material with Df@10GHz≤0.005, Tg≥200℃, X / Y axis CTE≤12ppm / ℃, Z axis CTEα1≤30ppm / ℃, and possesses significantly better flowability than traditional IC substrate BT materials.

[0009] Furthermore, the insulating dielectric layer in the thick copper power layer region includes BT core layers alternately stacked with the power conductive layer, and the insulating dielectric layer in the thin copper signal layer region includes BT prepreg layers alternately stacked with the signal conductive layer. The BT core layers provide a stable dielectric thickness reference, and the BT prepreg layers melt and flow during lamination to fill the gaps between the conductive layers. Together, they achieve precise interlayer dielectric thickness control.

[0010] In a preferred embodiment, the board body has an 18-layer structure, which consists of, from top to bottom, a first solder mask layer, a first thin copper signal layer region located below the first solder mask layer, a thick copper power layer region located below the first thin copper signal layer region, a second thin copper signal layer region located below the thick copper power layer region, and a second solder mask layer located below the second thin copper signal layer region.

[0011] Furthermore, the copper thickness of the power conductive layer is 2 oz, and the copper thickness of the signal conductive layer is 1 / 3 oz. The 2 oz thick copper layer provides the AI ​​chip with high current power supply capability, while the 1 / 3 oz thin copper layer meets the requirements of fine circuit etching processing.

[0012] On the other hand, the present invention also provides a pressing method for an AI computing card, used for pressing a laminated board using M6 grade high-speed BT resin-based material. The pressing method includes: S1 preheating and degassing stage, in which the laminated board is heated from room temperature to 135°C at a heating rate of 2.5-3.5°C / min, and a contact pressure of 100 psi is applied under vacuum conditions; S2 pressure increasing and filling stage, in which the temperature is gradually increased from 135°C to 220°C, and the pressure is gradually increased from 100 psi to a main pressure of 400 psi, wherein the temperature is kept constant at 180°C and the pressure is increased to above 360 ​​psi; S3 curing and crosslinking stage, in which the main pressure of 400 psi is maintained at a constant temperature of 220°C to complete the crosslinking and curing of the resin body; S4 cooling and depressurization stage, in which the temperature is gradually reduced from 220°C to room temperature, and the pressure is gradually depressurized from 400 psi to zero. This pressing method is specifically adapted to the high flowability of M6 grade high-speed BT resin-based materials: S1 involves slow heating combined with vacuum and low contact pressure to fully expel interlayer volatiles and uniformly preheat; S2 involves maintaining a constant temperature within a 180°C temperature window and increasing the pressure to over 360 psi, utilizing the lowest viscosity state to achieve full filling of interlayer gaps and internal voids within the glass fiber bundles; S3 involves completing full cross-linking and curing at a temperature higher than the material's Tg; and S4 involves stepwise pressure release and temperature gradient to release internal stress.

[0013] In a preferred embodiment, the cooling and depressurization phase includes: a first cooling stage, reducing the temperature from 220°C to 215°C and depressurizing to 300 psi; a second cooling stage, reducing the temperature from 215°C to 165°C and depressurizing to 100 psi; a third cooling stage, reducing the temperature from 165°C to 130°C and maintaining at 100 psi; a fourth cooling stage, reducing the temperature from 130°C to 100°C and maintaining at 100 psi while closing the vacuum; and a fifth cooling stage, reducing the temperature from 100°C to 70°C and maintaining at 100 psi.

[0014] Furthermore, the pressurization filling stage includes maintaining a constant temperature of 180°C for at least 5 minutes, and during this stage, increasing the pressure to 400 psi.

[0015] In the aforementioned AI computing power card, the M6 ​​grade high-speed BT resin-based material has a dielectric loss factor Df≤0.005 at 10GHz, an X / Y axis thermal expansion coefficient CTE≤12ppm / ℃, and a Z axis thermal expansion coefficient CTEα1≤30ppm / ℃.

[0016] Correspondingly, in the above-mentioned pressing method, the M6 ​​grade high-speed BT resin-based material used has a dielectric loss factor Df≤0.005 at 10GHz, an X / Y axis thermal expansion coefficient CTE≤12ppm / ℃, and a Z axis thermal expansion coefficient CTEα1≤30ppm / ℃.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: Effect 1: BGA area flatness ≤3mil. Mechanism: The low CTE of M6 grade high-speed BT resin-based material, combined with a symmetrical stacked structure, reduces thermally induced dimensional changes from the material source. Simultaneously, the symmetrical structure ensures symmetrical distribution of thermal stress, reducing board warpage during SMT reflow thermal shock. This cannot be achieved by a single feature. Selecting only the material without changing the structure results in insufficient CTE symmetry; changing the structure without changing the material results in a still large absolute CTE value. Only through the synergy of both can a flatness of ≤3mil be achieved. Those skilled in the art before the application date could not have foreseen that the improved BT material and symmetrical stacked structure could produce such a significant flatness effect on a structure with both thick and thin copper layers.

[0018] Effect 2: High-speed signal integrity meets requirements. Mechanism: The high fluidity of M6-grade high-speed BT resin-based material ensures full resin filling during lamination, uniform dielectric layer thickness, sufficient glass fiber wetting, and no local resin enrichment or deficiency. The spatial consistency of the dielectric layer (Df) is significantly better than that of traditional BT materials. No existing technology indicates that this effect can be achieved by improving the lamination flow of BT materials to control the spatial consistency of Df.

[0019] Effect 3: Improved SMT reflow reliability. Mechanism: The combination of low CTE materials and symmetrical stack-up design results in minimal Z-axis expansion and contraction and symmetrical stress distribution, significantly reducing the risk of hole ring cracking and blind via wall copper cracking; the step-by-step pressure relief and cooling pressing process keeps residual stress in the board low. These two factors work synergistically to ensure reflow reliability, an effect not found in existing technologies.

[0020] Effect 4: Good mass production capability. Based on existing commercially available M6-grade high-speed BT materials and vacuum laminators, no special equipment or customized materials are required, making it suitable for mass production scenarios of AI computing cards. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of an 18-layer symmetrical stacked structure according to an embodiment of the present invention. Detailed Implementation

[0023] Unless otherwise stated, the term "BT resin-based material" as used herein refers to bismaleimide-triazine resin-based copper-clad laminate material. The following description uses Taiguang EM-528 BT material as an example, combined with an 18-layer symmetrical stacked structure, to provide a detailed explanation of the AI ​​computing power card and its lamination method of this invention. It should be understood that the scope of protection of this invention is not limited to the specific grade EM-528. All materials that meet the performance parameter definitions of M6-grade high-speed BT resin-based materials, as well as other numbers of layers and specific stacked configurations based on the same inventive concept, fall within the scope of protection of this invention. Example 1

[0024] Figure 1This embodiment demonstrates the stacked structure of the AI ​​computing power card. The board has 18 layers, arranged from top to bottom as follows: The first solder mask layer L1 is located at the top of the board, protecting the outer circuitry and defining the soldering area. Below the first solder mask layer are the first thin copper signal layer regions L2-L6, which contain five conductive layers: L2, L3, L4, L5, and L6. Each layer has a copper thickness of 1 / 3 oz, and the conductive layers are separated by 1078 type BT prepreg layers as insulating dielectric layers. Before lamination, the prepreg layers are made of fiberglass cloth pre-impregnated with M6 grade high-speed BT resin. During lamination, the resin melts and flows to fill the gaps between the conductive layers. The L2-L6 layer region is mainly used for high-speed signal traces and reference planes of the AI ​​computing power card. The thin copper design facilitates fine circuit processing and impedance control, while the thin fiberglass cloth provides a lower dielectric thickness, meeting the design requirements for tight coupling between high-speed signal layers. Below the first thin copper signal layer area lies the thick copper power layer area L7-L12, which contains six conductive layers: L7, L8, L9, L10, L11, and L12, each with a copper thickness of 2 oz. Between L7 and L8, L9 and L10, and L11 and L12, there is a 0.076 mm thick BT core board layer. These BT core boards are pre-cured from M6-grade high-speed BT resin-based material, providing a precise dielectric thickness reference. Between L8 and L9, and between L10 and L11, there are two 1078-type BT prepreg layers, which are molten and filled during the lamination process. The thick copper power layer area is primarily used for high-current power network distribution in AI computing cards. The 2 oz copper thickness provides a low-resistance path to meet the power supply requirements of AI chips, which can easily reach hundreds of amperes. The interconnects in this area are buried vias, connecting only within the thick copper power layer area and not penetrating the entire board. Located below the thick copper power layer area is the second thin copper signal layer area, L13-L17. Its stack-up structure is symmetrical to the first thin copper signal layer area about the board's neutral plane. It also contains five conductive layers: L13, L14, L15, L16, and L17, each with a copper thickness of 1 / 3 oz. A 1078 type BT prepreg layer is used as the insulating dielectric layer. This area is also used for high-speed signal traces and reference planes. Finally, the bottom surface of the board is the second solder mask layer, L18. The design intent of this symmetrical stack-up structure is that, with the thick copper power layer area as the center, the thin copper signal layer areas on both sides are completely symmetrical in terms of the number of layers, copper thickness, and dielectric material, ensuring that the thermal expansion characteristics of the board along the thickness direction are symmetrical about the neutral plane. At the SMT reflow soldering peak temperature of 245°C, the expansion and contraction on the top and bottom sides of the board are equal, without generating additional bending moments, thus ensuring the flatness of the BGA area.

[0025] In another implementation, the aforementioned symmetrical stacked structure is not limited to strict mirror symmetry. Due to the actual functional requirements of AI computing power cards, the number of signal layers and copper thickness on the top and bottom sides may differ. For example, the top side may require more signal layers to support direct interconnection with the GPU chip, while the number of signal layers on the bottom side can be appropriately reduced. In this case, an equal-mass distribution symmetrical scheme can be adopted: keeping the thick copper power layer area centered, and adjusting the copper thickness and dielectric layer thickness of each layer in the thin copper signal layer area to make the total copper mass, total dielectric mass, and total CTE contribution of the thin copper areas on the top and bottom sides symmetrical about the neutral plane. Although this scheme has an asymmetrical number of layers, it can still achieve a BGA area flatness of ≤3mil due to the overall symmetry of thermal expansion characteristics about the neutral plane. This extended scheme proves that the core inventive point of this invention does not lie in the well-known design principle of mirrored layer count, but in elevating the principle of symmetry from formal symmetry to functional symmetry, and combining it with the low CTE characteristics of M6-grade high-speed BT resin-based materials. Example 2

[0026] This embodiment uses the lamination method of the 18-layer AI computing power card described in the first embodiment as an example to explain in detail the four-stage, 13-segment lamination process. Layer preparation stage: The core boards and prepregs with completed inner layer patterns are laminated according to the lamination sequence. The BT core board layers corresponding to L7, L9, and L11 have been pre-etched with thick copper power patterns, and the copper foils corresponding to L2-L6 and L13-L17 have completed blind via copper filling and fine circuit fabrication. 1078-type BT prepreg layers are placed between the layers according to the design; one layer is placed between each layer in the thin copper signal layer area, and two layers are placed and stacked between the core boards in the thick copper power layer area. This is a lower-level implementation of the BT prepreg layer. As an alternative, other thin fiberglass cloth BT prepregs can be used, or a pure resin film without fiberglass cloth reinforcement can be used, as long as its resin system is M6 grade high-speed BT resin. Lamination execution stage: The laminated board blank is sent into a vacuum laminator to execute the four-stage, 13-segment lamination program.

[0027] Stage 1: Preheating and Exhausting. Stage 1: Heating rate is 3.0℃ / min, taking 5 minutes to raise the temperature from room temperature to 135℃. The pressure is set to 100psi, and the vacuum is activated. 100psi is the contact pressure, ensuring close contact between the layers but before significant resin flow. The vacuum environment, combined with slow heating, ensures that residual air, moisture, and volatile components in the resin are fully expelled before significant resin flow. Stage 2: The temperature continues to rise from 135℃ to 160℃ at a rate of approximately 5℃ / min, while the pressure increases from 100psi to 250psi. The 250psi pressure initiates the initial flow of the softened resin, causing it to begin wetting the fiberglass cloth surface. The vacuum remains activated to continue expelling deep-seated volatiles. Alternatively, heating rates of 2.5℃ / min or 3.5℃ / min can be selected, depending on the laminate thickness and number of layers. In another implementation, the process parameters for the preheating and degassing stage can employ a segmented pressure application scheme: during the temperature rise from room temperature to 80°C, only a light contact pressure of 50 psi is applied, and when the temperature reaches above 80°C and the resin begins to soften significantly, the pressure is increased to 100 psi. This scheme is more beneficial for the preheating uniformity of thick laminates. Alternatively, a segmented vacuum control scheme can be used: maintaining a high vacuum level before reaching 100°C to ensure sufficient dehumidification, and appropriately reducing the vacuum level in the 100-135°C range to prevent excessive volatilization of low molecular weight resin components.

[0028] Stage Two: Pressure Increment Filling. Section 3: Temperature increases from 160℃ to 180℃, and pressure increases from 250psi to 360psi. After reaching 180℃, maintain this temperature for 5 minutes. 180℃ is the optimal flow window temperature for EM-528 BT resin; at this temperature, the resin viscosity is at its lowest, and flowability is optimal. The 360psi pressure drives the low-viscosity resin to fully flow into the microscopic gaps between the copper wires in each conductive layer and between it and the fiberglass cloth. Section 4: Under the 180℃ constant temperature condition, the pressure is further increased from 360psi to a main pressure of 400psi and maintained for 1 minute. 400psi is the maximum working pressure of this pressing method, completing the final filling and locking. Section 5: Temperature increases from 180℃ to 195℃, maintaining a main pressure of 400psi. Upon reaching 195℃, the resin begins a cross-linking reaction, forming chemical bonds between molecular chains, and the resin viscosity gradually increases. Section 6: Temperature increases from 195℃ to 220℃, maintaining a main pressure of 400psi. 220℃ is close to or reaches the glass transition temperature of EM-528 BT resin, ensuring sufficient resin chain mobility and accelerating the crosslinking reaction. In stage two above, the 180℃ isothermal control is a core process step adapted to the high flowability characteristics of M6-grade high-speed BT materials. Traditional BT materials, due to their poor resin flowability at this temperature, cannot achieve an equivalent filling effect even with extended isothermal time. In another embodiment, the 180℃ temperature window in the pressurized filling stage can be replaced with a 190℃ or 175℃ temperature window, the specific choice depending on the actual rheological properties of the M6-grade high-speed BT resin-based material used. Dynamic mechanical analysis and rotational rheometer testing show that the complex viscosity of EM-528 BT material is at its lowest plateau in the 170-195℃ range, with 180℃ corresponding to the lowest viscosity point. However, when using M6-grade high-speed BT materials from other suppliers, the optimal flow window may shift to 175℃ or 190℃. A constant temperature window can be selected within the temperature range of 175-190℃, and this temperature window can be used instead of 180℃ to still achieve an equivalent filling uniformity effect.

[0029] Stage 3 Curing and Crosslinking. Stage 7: Maintain a constant temperature of 220℃ and a main pressure of 400psi. This stage is the core curing stage of the entire pressing process, with a cumulative constant temperature time of approximately 3 hours and 27 minutes. Maintaining a temperature above the Tg for an extended period allows the resin molecular chains to fully crosslink, forming a dense three-dimensional network structure. Full crosslinking ensures that the board reaches the design Tg value, while also ensuring that the dielectric properties and heat resistance meet product specifications. Stage 8: The temperature is slowly reduced from 220℃ to 215℃, and the pressure is released from 400psi to 300psi. This stage is a post-curing stress release transition stage. The temperature is still above the Tg, allowing the resin to undergo supplementary crosslinking and structural adjustment. The initial reduction in pressure begins to release some of the internal stress accumulated during pressing.

[0030] Phase Four: Cooling and Pressure Relief. Stage 9: Temperature drops from 215℃ to 165℃, pressure is reduced from 300psi to 100psi. Rapid cooling lowers the overall temperature of the board from above Tg to below Tg, allowing the resin cross-linking network to set. Stage 10: Temperature drops from 165℃ to 130℃, pressure remains at 100psi. A constant-temperature platform is used in this stage to ensure uniform temperature across the board. Stage 11: Temperature drops from 130℃ to 100℃, pressure remains at 100psi, vacuum is closed. The constant-temperature platform further releases internal stress. Stage 12: Temperature drops from 100℃ to 70℃, pressure remains at 100psi. Cooling to a safe furnace exit temperature. Stage 13: Pressure and temperature return to zero. The pressing cycle ends, and the board is cured and shaped. This step-by-step cooling and pressure relief strategy is crucial for ensuring the flatness of the board surface in this pressing method. Taking five-stage cooling as an example, this is the first lower-level implementation of step-by-step cooling and pressure relief. If other step-by-step strategies are adopted, such as three-stage or four-stage cooling, similar effects can be achieved as long as the principle of reducing pressure with each cooling step and setting a constant-temperature platform to release stress is followed. In another implementation, a continuous slow-decreasing scheme is used instead of the stepped step-by-step cooling scheme in the cooling and pressure relief stage: after the curing and cross-linking stage, the temperature is uniformly reduced from 220℃ to 70℃ at a continuous cooling rate of 0.5-1.0℃ / min, while simultaneously the pressure is continuously reduced from 400psi to zeropsi in a linearly temperature-dependent manner. The entire cooling and pressure relief process takes 2.5-5 hours. The continuous slow-decreasing scheme has lower requirements for the press control system and is suitable for small-batch trial production or scenarios where production efficiency requirements are not high.

[0031] It is worth noting that the selection of the aforementioned 180°C temperature window is not something that can be easily determined by those skilled in the art through conventional experiments. The technical difficulty lies in two aspects: First, M6-grade high-speed BT resin-based materials are modified BT materials. Their resin system differs fundamentally from traditional pure BMI-triazine BT materials in molecular chain structure and crosslinking behavior. The optimal flow window for traditional BT materials is typically between 160-170°C, and this window is extremely narrow. 180°C is close to the crosslinking acceleration temperature range for traditional BT materials, where the resin viscosity has already begun to rise rather than reaching its lowest point. Based on their experience with traditional BT materials, those skilled in the art would not have considered setting the pressing and filling window at 180°C. Second, even if those skilled in the art have conducted rheological tests on EM-528 materials, they typically only perform single-point viscosity-temperature measurements. However, this invention has found that EM-528 operates on a low-viscosity plateau within a relatively wide temperature range of 170-195°C, exhibiting a rare wide flow window characteristic, with 180°C precisely located at the center of this plateau. This discovery requires coupled testing of three parameters: heating rate, temperature, and pressure. It cannot be derived from existing processes simply by replacing materials. Third, under actual mass production conditions, the relationship between the isothermal duration and pressure within the 180°C window is also affected by the layer thickness, fiberglass cloth type, and resin content. The parameter combination provided by this invention is the result of coupled optimization of material rheological properties, heat transfer kinetics, and filling kinetics, and therefore has non-obvious implications.

[0032] Regarding the optimization of process parameters, this invention also provides the following preferred sub-ranges: First, the preferred sub-range for the 180°C temperature window is 175-185°C, which corresponds to the core range of the lowest viscosity platform of the EM-528 BT resin material. Second, the preferred sub-range for the isothermal time is 4-10 minutes at 180°C, with the lower limit of 4 minutes ensuring complete filling of all interlayer gaps, and the upper limit preventing excessive flow that could lead to resin loss at the edges. Third, the preferred sub-range for the dielectric loss factor Df is Df@10GHz≤0.004, suitable for higher-speed AI computing card links. Fourth, the preferred sub-range for CTE is X / Y axis CTE≤10ppm / °C, and Z axis CTEα1≤25ppm / °C, providing design margins for higher BGA density and larger chip package size.

[0033] Besides Taiguang EM-528 BT material, other BT resin-based materials that meet the performance parameter definitions of M6-grade high-speed BT resin-based materials are also applicable to the solutions of this invention, such as equivalent M6-grade high-speed BT materials from other suppliers. In another embodiment, an M6-grade high-speed BT resin-based material containing inorganic fillers can also be used. By dispersing and adding nano-sized silica fillers in the BT resin matrix, the Z-axis CTE of the material can be further reduced to below 25 ppm / ℃ while maintaining high fluidity, and the uniformity of the dielectric layer thickness can be improved. In another embodiment, the BT prepreg layer can also be a BT prepreg containing nano-fillers, in which nano-sized inorganic fillers are pre-dispersed in the BT resin prepreg. These fillers fill the gaps between the conductive layers along with the resin during the compression flow process, and are uniformly distributed in the dielectric layer after curing, further reducing the Z-axis CTEα1 of the cured prepreg layer to 22-25 ppm / ℃, thus reducing the CTE difference with the BT core layer. In another embodiment, the fiberglass cloth in the BT prepreg layer can be replaced with a low-roughness fiberglass cloth instead of the conventional E-glass 1078 type fiberglass cloth to reduce the roughness of the resin-fiberglass interface and reduce additional losses in high-speed signal scenarios.

[0034] To clarify the irreplaceable nature of M6-grade high-speed BT resin-based materials in this invention, a comparison is made with other high-frequency material systems. PTFE-based high-frequency materials have extremely low flow rate (Df), theoretically solving the high-speed signal uniformity problem. However, PTFE's Z-axis CTEα1 is as high as 80-120 ppm / ℃, far exceeding that of BT materials, making it impossible to achieve 3mil BGA flatness. Furthermore, PTFE's low modulus makes it difficult to meet the mechanical support requirements of large-size AI computing power cards. Hydrogen resin-based high-frequency materials have a better CTE than PTFE but still higher than BT materials. Hydrogen resins typically have a Tg of only 160-180℃, resulting in insufficient thermal stability at a curing temperature of 220℃ and a peak SMT temperature of 245℃. The reason this invention chooses M6-grade high-speed BT resin-based materials is based on a systematic evaluation of their comprehensive performance across four dimensions: CTE, flowability, Df consistency, and processability. They cannot be simply replaced by PTFE or hydrocarbon resin materials.

[0035] After lamination and cooling, the board undergoes subsequent processing steps, including standard PCB manufacturing processes such as outer layer drilling, blind via copper filling, outer layer pattern creation, solder mask printing, and surface treatment. Because the laminated board already possesses excellent flatness (BGA area coplanarity ≤3mil), this flatness is maintained during subsequent SMT assembly, eliminating the need for additional leveling.

Claims

1. A symmetrically stacked AI computing power card, comprising a board body formed by alternating and pressing multiple conductive layers and insulating dielectric layers, characterized in that, The AI ​​computing power card includes a symmetrical stacked structure, comprising a thick copper power layer region in the middle and thin copper signal layer regions symmetrically distributed on both sides of the thick copper power layer region; the thick copper power layer region includes at least one power conductive layer with a copper thickness ≥ 2 oz; the thin copper signal layer region includes at least one signal conductive layer with a copper thickness ≤ 1 / 3 oz; wherein the insulating dielectric layer in both the thick copper power layer region and the thin copper signal layer region is made of M6 grade high-speed BT resin-based material.

2. The AI ​​computing power cardboard according to claim 1, characterized in that, The M6 ​​grade high-speed BT resin-based material is Taiguang EM-528 BT material.

3. The AI ​​computing power card according to claim 1, characterized in that, The insulating dielectric layer of the thick copper power layer region includes BT core board layers that are alternately stacked with the power conductive layer, and the insulating dielectric layer of the thin copper signal layer region includes BT prepreg layers that are alternately stacked with the signal conductive layer.

4. The AI ​​computing power card according to claim 3, characterized in that, The board has an 18-layer structure, consisting of the following layers from top to bottom: a first solder mask layer (L1), a first thin copper signal layer region (L2-L6) located below the first solder mask layer (L1), a thick copper power layer region (L7-L12) located below the first thin copper signal layer region (L2-L6), a second thin copper signal layer region (L13-L17) located below the thick copper power layer region (L7-L12), and a second solder mask layer (L18) located below the second thin copper signal layer region (L13-L17).

5. The AI ​​computing power card according to claim 1, characterized in that, The copper thickness of the power conductive layer is 2 oz, and the copper thickness of the signal conductive layer is 1 / 3 oz.

6. A method for laminating an AI computing card, used for laminating a laminated board made of M6 grade high-speed BT resin-based material, characterized in that, The pressing method includes: S1: Preheating and degassing stage, heating the laminate from room temperature to 135°C at a heating rate of 2.5-3.5°C / min, and applying a contact pressure of 100 psi under vacuum conditions; S2: Pressure increasing and filling stage, gradually increasing the temperature from 135°C to 220°C, and simultaneously gradually increasing the pressure from 100 psi to a main pressure of 400 psi, wherein the temperature is kept constant at 180°C and the pressure is increased to above 360 ​​psi; S3: Curing and crosslinking stage, maintaining a main pressure of 400 psi at a constant temperature of 220°C to complete the crosslinking and curing of the resin matrix; S4: Cooling and depressurization stage, gradually reducing the temperature from 220°C to room temperature, and gradually depressurizing the pressure from 400 psi to zero.

7. The pressing method according to claim 6, characterized in that, The cooling and depressurization stages include: a first cooling stage, reducing the temperature from 220°C to 215°C and depressurizing to 300 psi; a second cooling stage, reducing the temperature from 215°C to 165°C and depressurizing to 100 psi; a third cooling stage, reducing the temperature from 165°C to 130°C and maintaining 100 psi; a fourth cooling stage, reducing the temperature from 130°C to 100°C and maintaining 100 psi while closing the vacuum; and a fifth cooling stage, reducing the temperature from 100°C to 70°C and maintaining 100 psi.

8. The pressing method according to claim 6, characterized in that, The pressurization filling stage includes maintaining a constant temperature of 180°C for at least 5 minutes, and during this stage, increasing the pressure to 400 psi.

9. The AI ​​computing power card according to any one of claims 1 to 5, characterized in that, The M6 ​​grade high-speed BT resin-based material has a dielectric loss factor Df≤0.005 at 10GHz, an X / Y axis thermal expansion coefficient CTE≤12ppm / ℃, and a Z axis thermal expansion coefficient CTEα1≤30ppm / ℃.

10. The pressing method according to any one of claims 6 to 8, characterized in that, The M6 ​​grade high-speed BT resin-based material has a dielectric loss factor Df≤0.005 at 10GHz, an X / Y axis thermal expansion coefficient CTE≤12ppm / ℃, and a Z axis thermal expansion coefficient CTEα1≤30ppm / ℃.

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