A method of manufacturing a multi-layer coil board

Abstract

The application discloses a manufacturing method of a multilayer coil board and relates to the technical field of printed circuit board manufacturing. The method takes the minimum insulation distance of adjacent insulation layers meeting the required redundancy of target withstand voltage as the target and is cooperatively executed. At least two semi-cured sheets are stacked to bear the withstand voltage redundancy. New kraft paper is used for pressing and the intermediate layer pressure is reduced, and the layer deviation is compensated according to the coefficient. The alignment is hierarchically controlled according to the number of layers, the unified stacking reference of drilling and outer layer exposure is established, the fullness of the hole, the hole filling depression, the uniformity of copper thickness and the amount of lamp core are controlled, the copper foil in the weak insulation area is locally micro-textured and the thickness gradient is set to homogenize the electric field. The measured expansion coefficient, layer deviation and minimum insulation distance are transferred online to the subsequent process, and the subsequent process parameters are dynamically updated in the batch iteration mode, so that the cumulative deviation converges with the batch. The withstand voltage consistency under high pressure working conditions is improved, and the yield is also considered.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board (PCB) manufacturing technology, and more particularly to a method for manufacturing a multilayer coil board. Background Technology

[0002] Multilayer coil boards are formed by laminating and pressing a substrate with multiple layers of prepreg (PP), undergoing processes such as inner layer patterning, lamination, drilling, outer layer exposure, electroplating, resin plugging, solder masking, and molding. Under high-voltage conditions, its insulation reliability mainly depends on the minimum insulation distance between adjacent insulation layers and the internal quality of the insulation layers.

[0003] Chinese invention publication number CN 117769132 A discloses a method and system for manufacturing coil boards. The coil board manufacturing method and scheme of this application features a reasonable manufacturing process. Furthermore, by optimizing the inner layer process, pressing process, solder mask process, and testing process, it improves the coil board's withstand voltage defects and increases the product yield. This solution reduces the proportion of coil board withstand voltage defects from 80 PPM to 40 PPM, resulting in a 50% decrease in product defect rate and significantly reducing costs.

[0004] This existing technology addresses the problems of "foreign matter residue in the production process causing short circuits, foreign matter trapped in the insulation layer during lamination, and arcing and explosion during high-voltage testing." It primarily employs foreign matter control measures in the production environment, including ultrasonic cleaning and vacuum dust removal, Teflon-coated robotic arms for handling, plastic rivets, vacuum printing of solder resist, and secondary withstand voltage testing after baking. These methods reduce the withstand voltage failure rate from 80 PPM to 40 PPM. Therefore, its technical approach is "removing external contaminants to restore the inherent withstand voltage of the insulation layer."

[0005] However, this existing technology still has the following shortcomings:

[0006] (i) Limited solution path. Existing technologies focus on "cleanliness and safety control" and fail to build withstand voltage reliability from the perspective of structural-process synergy, including material stacking, electric field distribution, pressing process parameters, and insulation distance. When cleanliness is close to the upper limit of the process, the benefits of continuing to improve withstand voltage along this path are limited.

[0007] (ii) Commonly used parameters are isolated and not bound together. High Tg substrate, via fullness, copper thickness uniformity, alignment grade, etc. are mostly independent inspection items, lacking unified coordination with "minimum insulation distance to meet withstand voltage redundancy" as the common target.

[0008] (iii) Lack of data closure and dynamic classification. The existing secondary withstand voltage test is a pass / fail judgment under a fixed process. It does not transfer and feedback process characteristic quantities between batches, nor does it dynamically allocate downgraded products within the grade. As a result, there is a loss of yield and the cumulative deviation cannot be converged.

[0009] Given this situation, improvement is urgently needed. Summary of the Invention

[0010] To address the shortcomings of the existing technologies, this invention provides a method for manufacturing a multilayer coil board. With the goal of ensuring that the minimum insulation distance between adjacent insulation layers meets the redundancy required for the target withstand voltage, a quantifiable and graded closed-loop process for withstand voltage reliability is formed, thereby improving withstand voltage consistency, reducing high-voltage failure rate, and balancing yield and electrical parameter consistency.

[0011] This invention provides a method for manufacturing a multilayer coil board, comprising the following steps:

[0012] Step A: Select substrate material according to the target withstand voltage level, and match and stack at least two prepregs. The stack is used as the main structure to bear the withstand voltage redundancy. The number of layers and the thickness of a single layer of the prepreg are determined according to the minimum insulation distance required for the target withstand voltage.

[0013] Step B: Use new kraft paper as a padding layer and reduce the pressure of the intermediate layer during lamination. When there are multiple laminations and the safety gap is less than 7mil, perform dynamic compensation according to the average lamination coefficient.

[0014] Step C: After pressing, control the interlayer alignment of the plates according to the number of layers, and establish a unified minimum insulation distance standard for the stacking of through-holes and outer layer exposure.

[0015] Step D: Quantitatively control the fullness and depression of the filling after resin plugging, as well as the uniformity of copper thickness and the amount of wick after electroplating, so as to meet the requirements of the minimum insulation distance stacking benchmark.

[0016] Step E: In the weak insulation region between adjacent conductive layers with potential difference, perform local micro-texturing treatment on the critical region of the copper foil, and set a thickness gradient for the insulation layer in the weak insulation region to homogenize the electric field distribution in the region.

[0017] Step F: Transfer the measured expansion and contraction coefficients, layer deviations, and minimum insulation distance characteristics of each process to the subsequent processes online, and dynamically update the processing parameters of the subsequent processes in an inter-batch iterative manner so that the cumulative deviations converge with each batch.

[0018] Step G: Perform graded pressure resistance verification on the finished plates according to the target pressure resistance level, and remap the plates that do not meet the current pressure resistance level but meet the adjacent lower level to the lower level stack.

[0019] Among them, steps A to G are executed collaboratively with the minimum insulation distance between adjacent insulation layers satisfying the redundancy required for the target withstand voltage as the common target.

[0020] Furthermore, the substrate meets the following requirements: glass transition temperature Tg≥150℃, thermal decomposition temperature Td≥325℃, peel strength≥6lb / in, dielectric constant≤5.4, Z-axis expansion coefficient≤60ppm, HVLP copper foil is used and its surface roughness Rz<2.0μm.

[0021] Furthermore, in step C, the interlayer alignment is controlled in stages according to the number of layers: 5mil for 6-layer boards, 4mil for 8-layer boards, and 2mil for 10 layers and above; the interlayer alignment of inner layers is controlled at ±1mil, and the alignment accuracy of outer layer circuits is controlled at ±1mil.

[0022] Furthermore, in step C, short-circuit protection test holes are set on the inner layer process edge or broken edge. Graded full interception verification is performed according to two levels: -1mil and -2mil minimum hole-to-line gap. The boards are graded and stacked according to half the distance from the inner layer hole to the copper and isolation ring. The first drilled part and the self-drilled part are inspected by X-ray. The minimum hole of this part number is drilled at the center of the concentric circle as the alignment measurement and evaluation benchmark. The alignment is controlled at 3mil, and the hole position accuracy is ±2mil and CPK≥1.33.

[0023] Furthermore, the drilling process reuses the stacking benchmark, and the layers are graded and stacked according to the average value of the actual thickness and expansion / contraction of the pressed plate, and a drilling coefficient is given; the outer layer exposure is aligned and produced according to the drilling stacking coefficient.

[0024] Furthermore, in step D, the resin plugging fullness is ≥95%, the filling depression is ≤3mil, the copper plating thickness uniformity is ≤10%, and the lamp wick thickness is ≤100μm; and the thickness tolerance and plate thickness tolerance in the lamination process are both controlled within ±10%.

[0025] Furthermore, in step E, the local microtexture is a roughness gradient formed by chemical micro-etching in the critical region, and the setting of the thickness gradient and the roughness gradient reduces the local peak electric field intensity in the weak insulation region.

[0026] Furthermore, in step F, the coefficients of subsequent processes in the (m+1)th batch are updated using the following formula:

[0027] Coef_(m+1) = Coef_m × avg(Δ_m / Δ_target),

[0028] Where Δ is the measured deviation (mil) of the minimum insulation distance between adjacent insulation layers of a unit board, Δ_target is the controlled allowable deviation (mil) corresponding to the target minimum insulation distance of the board, avg is the arithmetic mean of all measurement points in the same batch; Coef_1 is 1.00, and iteration stops when |Δ_avg - Δ_target| < 0.5mil for 3 consecutive batches.

[0029] The beneficial effects of this invention are as follows:

[0030] First, this invention constructs withstand voltage reliability through six methods: material stacking (step A), lamination process (step B), alignment and grading (step C), hole plugging effect (step D), electric field equalization (step E), and closed-loop feedback (step F). It takes "the minimum insulation distance between adjacent insulation layers meets the redundancy required for the target withstand voltage" as the unified target throughout the entire process, so as to realize a quantifiable and graded withstand voltage reliability closed loop.

[0031] Secondly, in existing technologies, high Tg substrates, via filling fullness, copper thickness uniformity, and alignment grading are mostly independent inspection items. This invention integrates them into a unified quantitative judgment criterion of "minimum insulation distance meets withstand voltage redundancy" for coordinated execution, making the parameters of each process interconnected and convergent layer by layer, significantly improving withstand voltage consistency, and further reducing the high voltage failure rate compared to single-item control.

[0032] Third, steps A–D mainly ensure the “thickness and internal quality” of the insulation layer, while step E optimizes the interface for the electric field distribution in areas with large potential differences: by making local micro-textures in the critical region of the copper foil and superimposing the insulation layer thickness gradient, the electric field in the weak area is homogenized and the local peak electric field intensity is reduced. From the dimension of “electric field distribution”, the surface / dielectric breakdown is suppressed, which makes up for the problem of local field concentration that existing technologies cannot solve by relying solely on cleanroom control.

[0033] Fourth, existing technologies rely on static control within a fixed process, which cannot converge the accumulated layer deviation and expansion / contraction deviations across batches. This invention transmits the measured expansion / contraction coefficient, layer deviation, and minimum insulation distance online between processes and iteratively updates subsequent process parameters between batches using the formula Coef_(m+1)=Coef_m×avg(Δ_m / Δ_target). This causes the accumulated deviation to decrease with each batch and converge to the allowable range of the stacking reference, significantly improving the consistency of multi-batch production.

[0034] Fifth, existing technologies use a fixed "pass / fail" criterion for products that fail to meet pressure resistance standards, resulting in yield loss. This invention performs graded verification based on the target pressure resistance level, remapping boards that do not meet the current level but meet the adjacent lower level to the lower level stack. This ensures redundancy in pressure resistance at each level while recovering downgraded products, improving overall yield and batch production efficiency. Detailed Implementation

[0035] To further understand the features, technical means, and specific objectives and functions achieved by the present invention, the present invention will be described in further detail below with reference to specific embodiments.

[0036] In this document, 1 mil ≈ 0.0254 mm, Tg and Td are in °C, peel strength is in lb / in, Z-axis expansion coefficient is in ppm, and Rz is the ten-point height roughness of the profile (μm). The scope of protection of this invention is defined by the claims. The following embodiments are merely illustrative and not exhaustive.

[0037] Example 1: Selection of Substrate and Copper Foil

[0038] In this embodiment, the substrate material is selected with the following preferably characteristics: glass transition temperature Tg ≥ 150℃, thermal decomposition temperature Td ≥ 325℃, peel strength ≥ 6 lb / in, dielectric constant (1MHz) ≤ 5.4, and Z-axis coefficient of thermal expansion ≤ 60ppm, to obtain a good foundation for heat resistance, dimensional stability, and insulation. HVLP copper foil is used, with a surface roughness Rz < 2.0 μm, to balance insulation withstand voltage and high-frequency loss characteristics.

[0039] All parameters of the substrate material and copper foil were measured according to industry-standard methods: Tg was measured by DSC (Differential Scanning Calorimetry), Td by TGA (Thermogravimetric Analysis), peel strength was measured by a 90° peel test between the copper foil and the substrate, dielectric constant was measured by an impedance / dielectric tester, Z-axis coefficient of thermal expansion was measured by TMA (Thermomechanical Analysis), and Rz was measured by a surface roughness tester. These methods are well-known in the field and will not be elaborated further here.

[0040] Example 2: Stacked Pressure-Resistant Redundancy Design

[0041] The substrate and prepreg (PP) are selected based on the target withstand voltage rating. At least two prepreg sheets are stacked on both sides of the substrate to form a laminate, which serves as the main structure for bearing the withstand voltage redundancy. The number of prepreg layers and the thickness of each layer are determined based on the minimum insulation distance required for the target withstand voltage: that is, the redundancy is set according to the principle that "the total thickness of the laminated insulation layer is not less than the minimum insulation distance required for the target withstand voltage rating."

[0042] The minimum insulation distance required for the target withstand voltage in this embodiment is calculated from the insulation thickness required for the stack at the highest operating voltage and safety factor (the conversion relationship and safety factor are determined according to well-known insulation design specifications in the art). The prepreg uses conventional PP with a high resin content, which forms a dense insulating layer after lamination. The advantage of this stack is that even if there are minor defects in some areas, the overall withstand voltage redundancy can still be maintained by the thickness of the multi-layer PP stack, avoiding the risk of breakdown caused by insufficient thickness of a single PP layer.

[0043] Example 3: Synergistic effect of pressing process

[0044] Before lamination, the substrate and multilayer PP are stacked together as required and placed into the press. To reduce the risk of contamination introduced by the lamination medium, this embodiment uses brand new kraft paper as the lamination pad and does not use recycled pads, so as to avoid foreign objects carried by the pads being pressed into the insulation layer under high temperature and pressure; at the same time, the pressure of the intermediate layer is reduced, so that the pressure distribution in the middle section of the lamination tends to be uniform, avoiding local pressure concentration that causes cavitation, delamination or uneven thickness of the insulation layer.

[0045] Layer misalignment is detected before and after lamination to monitor alignment changes during the lamination and pressing process. When multiple laminations are involved (e.g., step-by-step lamination of inner layers followed by overall lamination) and the safety clearance is less than 7 mil, a lamination averaging coefficient is used for dynamic compensation. Preferably, the lamination averaging coefficient is calculated as the arithmetic mean of the ratio of the measured dimensions before and after lamination at each measuring point.

[0046] K_avg = (1 / n)·Σ i (D i ,after / D i (before)

[0047] Where n is the number of measurement points, D i before, D i ,after represents the measured dimensions of measuring point i before and after lamination, respectively; K_avg is used to correct the reference for subsequent drilling and exposure. During the lamination process, the dielectric thickness tolerance and the plate thickness tolerance are both controlled within ±10% to ensure the stable realization of the insulation layer thickness and stack redundancy.

[0048] Example 4: Alignment-based hierarchical coordination and minimum insulation distance stacking benchmark

[0049] After lamination, the alignment between layers of the boards is controlled in stages according to the number of layers: 5mil for 6-layer boards, 4mil for 8-layer boards, and 2mil for 10 layers and above. That is, the more layers there are, the stricter the control is, in order to reduce the cumulative alignment error of multiple layers. At the same time, the alignment between inner layers is controlled at ±1mil, and the alignment accuracy of outer layer circuits is controlled at ±1mil.

[0050] Based on this, a unified "minimum insulation distance clustering standard" is established that runs through subsequent drilling and outer layer exposure:

[0051] (1) Short-circuit test holes are set on the inner process edge or the broken edge. The short-circuit test holes are via / test hole structures used to verify whether the minimum insulation distance between adjacent conductive layers meets the standard. The hole-to-line or hole-to-copper spacing is used as the criterion for whether the minimum insulation distance of the board falls into the stacking benchmark after graded verification. Graded full interception verification is carried out according to two levels: "minimum hole-to-line gap -1mil" and "-2mil". Interception judgment is performed on each board.

[0052] (2) The boards are graded and stacked according to "half the distance from the inner hole to the copper and the isolation ring" to form boards with different alignment accuracy levels.

[0053] Example 5: Cascaded application of borehole alignment with outer layers

[0054] The drilling process reuses the above-mentioned stacking criteria: the plates are graded and stacked according to the average value of the actual measured thickness and expansion / contraction during pressing, and a drilling coefficient is given accordingly; the first piece and the self-drilled piece are inspected using X-ray, and the smallest hole of this part number is drilled at the center of a concentric circle as the alignment measurement and evaluation criterion. Among them, the alignment accuracy is controlled at 3mil, the hole position accuracy is controlled at ±2mil, and the process capability index CPK≥1.33.

[0055] The outer layer exposure is aligned and produced according to the drilling stacking coefficient. As a result, the inner layer verification, lamination stacking, drilling alignment and outer layer alignment share the same stacking benchmark, which limits the cumulative alignment error to the minimum insulation distance allowable range, and ensures that the minimum insulation distance between the final adjacent insulation layers is guaranteed.

[0056] Example 6: Synergistic Effect of Pore Plug

[0057] Quantitative control is implemented on the boards after resin plugging: the filling fullness is ≥95% and the filling depression is ≤3mil, to avoid defects such as incomplete plugging or depression introducing air gaps and thin copper surface; the filling fullness and depression amount are obtained by microscopic observation and measurement of the filling rate and the depression depth of the hole after electroplating section grinding.

[0058] After electroplating, the copper thickness uniformity is controlled to be ≤10% and the electroplated lamp core is ≤100μm to ensure uniform conductive layer thickness and avoid local current density concentration. The copper thickness uniformity is characterized by the percentage ratio of the range to the mean obtained by multi-point thickness measurement of the whole board. The electroplated lamp core is obtained by measuring the length of the lamp core penetrating into the insulating layer under a microscope by slicing.

[0059] The above indicators are judged based on meeting the "minimum insulation distance / withstand voltage redundancy stacking benchmark". Those exceeding the allowable range are returned or rectified before entering the subsequent process, so as to achieve the unified connection between hole plugging, electroplating efficiency and step C benchmark.

[0060] Example 7: Design of Electric Field Equalization Interface

[0061] For weak insulation regions between adjacent conductive layers with potential differences (such as high potential difference areas like via rings between adjacent layers or convergence of inner layer traces), a local roughness gradient (i.e., local microtexture) is created in this critical region of the copper foil through chemical micro-etching. Simultaneously, a thickness gradient is applied to the insulating layer in this region. This combination of microtexture and thickness gradient alters the electric field distribution at the interface of the weak region, homogenizing the local electric field that was originally concentrated at the edges / corners, reducing the local peak electric field intensity in this region, and thus suppressing surface discharge and dielectric breakdown induced by electric field concentration.

[0062] An example of an achievable method is as follows: When fabricating the inner copper foil pattern, the critical area intended for high-voltage bearing is pre-etched locally with controlled depth using a micro-etching solution to create a roughness gradient from sparse to dense. During lamination, a thickness gradient is created by locally thickening the polypropylene (PP) layer in this area or by adding an insulating compensation layer. The effect of "reducing the local peak electric field" can be confirmed through electric field simulation or withstand voltage measurement comparison. Through electric field simulation and withstand voltage measurement verification, after the above-mentioned local micro-texturing and thickness gradient treatment, the local peak electric field intensity at the interface of the weak insulation area is reduced by approximately 15% to 25% compared to the untreated state, and the surface discharge initiation voltage is correspondingly increased, verifying the electric field homogenization effect.

[0063] Example 8: Online Transfer of Process Feature Quantities and Batch-to-Batch Adaptive Compensation

[0064] In this embodiment, the measured expansion and contraction coefficients, layer offsets, and minimum insulation distances of each process are transmitted online to subsequent processes, and the processing parameters of subsequent processes are dynamically updated in an inter-batch iterative manner.

[0065] As a preferred implementation, the coefficients for subsequent processes are updated using the following formula:

[0066] Coef_(m+1) = Coef_m × avg(Δ_m / Δ_target),

[0067] Where Δ is the measured value (mil) of the minimum insulation distance between adjacent insulation layers of a unit board, Δ_target is the target minimum insulation distance (mil) of the board, avg is the arithmetic mean of all measurement points in the same batch, and m is the current batch number.

[0068] The aforementioned coefficients are used for batch-to-batch correction of the alignment reference for subsequent lamination thickness, drilling, and outer layer exposure. When the measured minimum insulation distance Δ_m is greater than the target value Δ_target, it indicates that the current lamination is too thick or the alignment reference is too loose. In this batch, the ratio avg(Δ_m / Δ_target) > 1, and the corresponding amplification coefficient is used to tighten the alignment and appropriately compress the insulation thickness compensation in subsequent processes, so that the actual minimum insulation distance falls back to the target value. Conversely, the coefficient is reduced to avoid overcompensation. After multiple batch iterations, the measured minimum insulation distance gradually approaches the target value and falls within the ±0.5mil allowable range. The iteration stops when the distance stabilizes for three consecutive batches.

[0069] Initial value and convergence condition: The initial coefficient Coef_1 is set to 1.00; when three consecutive batches satisfy |Δ_avg -Δ_target| < 0.5mil, the iteration stops and subsequent processes continue production using the current coefficient.

[0070] Example: Assume the target minimum insulation distance Δ_target = 10.0 mil, and the measured average of the first batch Δ_avg = 10.5 mil. Then Coef_2 = 1.00 × (10.5 / 10.0) = 1.05. After tightening the alignment and thickness compensation with a coefficient of 1.05 in the second batch, the measured average drops to 10.2 mil, so Coef_3 = 1.05 × (10.2 / 10.0) = 1.071. The measured average of the third batch further drops to 10.05 mil, so Coef_4 = 1.071 × (10.05 / 10.0) = 1.076... After several batches of iteration, the measured minimum insulation distance gradually approaches the target value of 10.0 mil from the first batch's average of 10.5 mil. The range between batches narrows by about 40% compared to the first batch, and the cumulative deviation converges with each batch. The method for determining Δ_m is the same as that described in Example 6, that is, the measured value of the minimum insulation distance between adjacent insulation layers is obtained by slicing / microscopic measurement.

[0071] Example 9: Gradientized withstand voltage verification and reactor remapping

[0072] Finished boards are graded and tested for withstand voltage according to their target withstand voltage rating. Those that meet the highest target withstand voltage rating are assigned to the corresponding higher-level stack; those that do not meet the current withstand voltage rating but meet the adjacent lower withstand voltage rating are remapped to the lower-level stack and rechecked according to the minimum insulation distance redundancy corresponding to the lower-level rating before leaving the factory; downgraded products that meet both the current rating and the lower rating are thus recycled across ratings.

[0073] This step ensures the pressure resistance redundancy of each grade of board while recycling downgraded products, improving the overall yield and batch production utilization rate, and avoiding yield loss caused by "one-size-fits-all" scrapping.

[0074] Example 10: End-to-End Collaborative Effect

[0075] This embodiment executes steps A through G sequentially: The stacking structure (A) determines the target minimum insulation distance; pressing (B) ensures the internal quality and layer misalignment control of the insulation layer; alignment grading (C) establishes and implements a stacking benchmark; via hole plugging (D) satisfies this benchmark; electric field equalization (E) suppresses local breakdown in weak areas; closed-loop feedback (F) causes cumulative deviations to converge with batches; gradient verification (G) balances yield while ensuring redundancy, ultimately ensuring the minimum insulation distance between adjacent insulation layers meets the redundancy required for the target withstand voltage. The parameters involved in each step (Tg≥150℃, Td≥325℃, HVLP copper foil Rz<2.0μm, short-circuit protection test holes, layer alignment control, and pressing average coefficient, etc.) and the measurement methods are detailed in Examples 1 through 9. Those skilled in the art can implement this invention based on the above descriptions; all values ​​are preferred examples and do not limit the scope of the claims.

[0076] The embodiments described above merely illustrate the preferred implementation of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for manufacturing a multilayer coil board, characterized in that, Includes the following steps: Step A: Select substrate material according to the target withstand voltage level, and match and stack at least two prepregs. The stack is used as the main structure to bear the withstand voltage redundancy. The number of layers and the thickness of a single layer of the prepreg are determined according to the minimum insulation distance required for the target withstand voltage. Step B: Use new kraft paper as a padding layer and reduce the pressure of the intermediate layer during lamination. When there are multiple laminations and the safety gap is less than 7mil, perform dynamic compensation according to the average lamination coefficient. Step C: After pressing, control the interlayer alignment of the plates according to the number of layers, and establish a unified minimum insulation distance standard for the stacking of through-holes and outer layer exposure. Step D: Quantitatively control the fullness and depression of the filling after resin plugging, as well as the uniformity of copper thickness and the amount of wick after electroplating, so as to meet the requirements of the minimum insulation distance stacking benchmark. Step E: In the weak insulation region between adjacent conductive layers with potential difference, perform local micro-texturing treatment on the critical region of the copper foil, and set a thickness gradient for the insulation layer in the weak insulation region to homogenize the electric field distribution in the region. Step F: Transfer the measured expansion and contraction coefficients, layer deviations, and minimum insulation distance characteristics of each process to the subsequent processes online, and dynamically update the processing parameters of the subsequent processes in an inter-batch iterative manner so that the cumulative deviations converge with each batch. Step G: Perform graded pressure resistance verification on the finished plates according to the target pressure resistance level, and remap the plates that do not meet the current pressure resistance level but meet the adjacent lower level to the lower level stack. Among them, steps A to G are executed collaboratively with the minimum insulation distance between adjacent insulation layers satisfying the redundancy required for the target withstand voltage as the common target.

2. The method for manufacturing a multilayer coil board according to claim 1, characterized in that, The substrate meets the following requirements: glass transition temperature Tg≥150℃, thermal decomposition temperature Td≥325℃, peel strength≥6lb / in, dielectric constant≤5.4, Z-axis expansion coefficient≤60ppm, and uses HVLP copper foil with surface roughness Rz<2.0μm.

3. The method for manufacturing a multilayer coil board according to claim 1, characterized in that, In step C, the interlayer alignment is controlled according to the number of layers: 5 mil for 6-layer boards, 4 mil for 8-layer boards, and 2 mil for 10 layers and above; the interlayer alignment of inner layers is controlled at ±1 mil, and the alignment accuracy of outer layer circuits is controlled at ±1 mil.

4. The method for manufacturing a multilayer coil board according to claim 1, characterized in that, In step C, short-circuit protection test holes are set at the inner layer process edge or broken edge. Graded full interception verification is performed according to two levels: -1mil and -2mil minimum hole-to-line gap. The boards are graded and stacked according to half the distance from the inner layer hole to the copper and isolation ring. The first drilled part and the self-drilled part are inspected by X-ray. The minimum hole of this part number is drilled at the center of the concentric circle as the alignment measurement and evaluation benchmark. The alignment is controlled at 3mil, and the hole position accuracy is ±2mil and CPK≥1.

33.

5. The method for manufacturing a multilayer coil board according to claim 4, characterized in that, The drilling process reuses the stacking benchmark, and the plates are graded and stacked according to the average value of the actual thickness and expansion / contraction of the pressed plates, and a drilling coefficient is given; the outer layer exposure is aligned and produced according to the drilling stacking coefficient.

6. The method for manufacturing a multilayer coil board according to claim 1, characterized in that, In step D, the resin plugging fullness is ≥95%, the filling depression is ≤3mil, the copper plating thickness uniformity is ≤10%, and the lamp wick thickness is ≤100μm; and the thickness tolerance and plate thickness tolerance in the lamination process are both controlled within ±10%.

7. The method for manufacturing a multilayer coil board according to claim 1, characterized in that, In step E, the local microtexture is a roughness gradient formed by chemical micro-etching in the critical region. The setting of the thickness gradient and the roughness gradient reduces the local peak electric field intensity in the weak insulation region.

8. The method for manufacturing a multilayer coil board according to claim 1, characterized in that, In step F, the coefficients of subsequent processes in the (m+1)th batch are updated using the following formula: Coef_(m+1) = Coef_m × avg(Δ_m / Δ_target), Where Δ is the measured deviation (mil) of the minimum insulation distance between adjacent insulation layers of a unit board, Δ_target is the controlled allowable deviation (mil) corresponding to the target minimum insulation distance of the board, avg is the arithmetic mean of all measurement points in the same batch; Coef_1 is 1.00, and iteration stops when |Δ_avg - Δ_target| < 0.5mil for 3 consecutive batches.