Airborne electronic equipment based on hierarchical cooperative electromagnetic compatibility architecture and design method thereof

Abstract

The present application relates to airborne electronic equipment electromagnetic compatibility design technical field, disclose based on hierarchical collaborative electromagnetic compatibility architecture's airborne electronic equipment and its design method.The equipment includes shell protection level, printed circuit board protection level and power supply and device protection level;The inner wall of the shell is provided with a flexible wave-absorbing structure, and a sealing structure containing a periodic metal via array is arranged at the joint surface;Embedded electromagnetic bandgap structures are arranged between the ground reference layers, and an isolation band is formed between the digital circuit area and the analog circuit area;The power supply inlet is provided with a common mode filter stage, a differential mode filter stage and an active compensation circuit in sequence, and the key integrated circuit power supply node is provided with a frequency division decoupling capacitor group. The parameters of each level are set according to the interference spectrum of the same target interference set, and the three levels jointly accept electromagnetic compatibility verification;When the verification does not meet the level target, the structure parameters or circuit parameters of the corresponding level are adjusted and verified again, so as to reduce the protection gap and parameter mismatch caused by layered independent design.

Description

Technical Field

[0001] This invention relates to the field of electromagnetic compatibility design technology for airborne electronic equipment, and more specifically to airborne electronic equipment based on a hierarchical collaborative electromagnetic compatibility architecture and its design method. Background Technology

[0002] As avionics systems evolve towards higher integration and higher frequencies, airborne electronic equipment may be subject to both external radiated interference and radiated or conducted interference generated by internal digital, analog, and power circuits. The housing mating surfaces, circuit board grounding layers, power inputs, and device power supply nodes each constitute different interference coupling paths, posing electromagnetic compatibility design requirements across structural and circuit levels.

[0003] Existing designs typically employ separate measures for housing shielding, printed circuit board grounding, power supply filtering, and device decoupling. Even when the parameters of each measure are determined independently, leakage paths may still form at the housing junctions, parasitic resonances may occur on the ground reference layer, noise from the digital circuit area may couple to the analog circuit area, and conducted interference may remain at the power input and critical integrated circuit power supply nodes.

[0004] Furthermore, when various protective measures are verified separately, the parameters obtained may not correspond to the same set of external radiation, internal interference, and conducted interference. Adjusting the parameters of one level may change the interference state faced by other levels. Therefore, it is necessary to treat the three protection levels—enclosure, printed circuit board, and power supply and devices—as continuous design objects and set them together for joint verification. Summary of the Invention

[0005] The purpose of this invention is to provide airborne electronic equipment and its design method based on a hierarchical collaborative electromagnetic compatibility architecture, so that housing protection, printed circuit board protection and power supply and device protection are driven by the same target interference set, and form interconnected parameter configurations through joint verification.

[0006] To achieve the above objectives, this invention provides an airborne electronic device based on a hierarchical collaborative electromagnetic compatibility architecture, comprising: a housing protection layer, including a housing with a flexible absorbing structure on its inner wall and a joint surface sealing structure at the joint surface, the joint surface sealing structure comprising a periodic array of metal through holes; a printed circuit board protection layer, including an embedded electromagnetic bandgap structure disposed between ground reference layers of a multilayer printed circuit board and an electromagnetic bandgap isolation band formed by the embedded electromagnetic bandgap structure and located between the digital circuit region and the analog circuit region; and a power supply and device protection layer, including a common-mode filter stage, a differential-mode filter stage, and an active compensation circuit arranged sequentially at the power supply inlet, as well as a frequency-division decoupling capacitor group for the power supply nodes of key integrated circuits; the structural parameters or circuit parameters of each protection layer are set according to the corresponding interference spectrum in the same target interference set, and the three protection layers together constitute a joint electromagnetic compatibility verification object, the parameters including parameter values ​​determined according to the verification results.

[0007] Preferably, the flexible absorbing structure is a layered structure formed by sequentially stacking a conductive thin-film open resonant ring array, a flexible dielectric substrate, and a resistive thin film.

[0008] Preferably, the mating surface sealing structure includes a conductive elastomer sealing strip located at the mating surface of the housing, the conductive elastomer sealing strip having a periodic array of metal through holes, and the contact surface between the conductive elastomer sealing strip and the housing being conductively treated.

[0009] Preferably, the embedded electromagnetic bandgap structure includes a periodic metal patch array disposed on a first ground reference layer and a metallized via array connecting the periodic metal patch array to an adjacent second ground reference layer. The digital circuit region adopts a multi-point grounding grid, the analog circuit region adopts a single-point grounding, and the power layer is disposed adjacent to a ground reference layer to form an interlayer planar capacitance.

[0010] Preferably, the common-mode filtering stage includes a common-mode choke and a Y capacitor, and the differential-mode filtering stage includes a differential-mode inductor and an X capacitor; the active compensation circuit includes a noise sampling circuit, an inverting processing circuit, and a compensation signal injection circuit. The noise sampling circuit collects the residual noise signal at the power output terminal, the inverting processing circuit generates an inverted compensation signal based on the residual noise signal, and the compensation signal injection circuit injects the inverted compensation signal into the power bus; the frequency band decoupling capacitor bank includes tantalum electrolytic capacitors, ceramic capacitors, and embedded planar capacitors, with the decoupling frequency bands of the three increasing sequentially.

[0011] This invention also provides a hierarchical collaborative electromagnetic compatibility (EMC) design method for airborne electronic equipment, comprising: analyzing the electromagnetic environment of the airborne electronic equipment and determining the target interference set; designing structural or circuit parameters for a housing protection level with a flexible absorbing structure and a joint surface sealing structure, a printed circuit board protection level with an embedded electromagnetic bandgap structure and an electromagnetic bandgap isolation band, and a power supply and device protection level with a common-mode filter stage, a differential-mode filter stage, an active compensation circuit, and a frequency-division decoupling capacitor bank, based on the target interference set; incorporating the three protection levels into the same EMC verification; determining the protection levels that do not meet the target based on the verification results, adjusting the structural or circuit parameters of the protection levels that do not meet the target, and performing EMC verification again.

[0012] Preferably, the target interference set includes the external radiation threat spectrum, the internal interference source spectrum, and the conducted interference spectrum. The analysis also includes decomposing the overall electromagnetic compatibility target of the airborne electronic equipment into hierarchical targets corresponding to the housing protection level, the printed circuit board protection level, and the power supply and device protection level, respectively.

[0013] Preferably, the structural parameter design of the printed circuit board protection layer includes: selecting the unit parameters of the embedded electromagnetic bandgap structure according to the resonant frequency of the ground layer of the printed circuit board or the internal interference frequency, determining the multi-point grounding grid of the digital circuit area and the single-point grounding of the analog circuit area, and setting an electromagnetic bandgap isolation band between the digital circuit area and the analog circuit area.

[0014] Preferably, the circuit parameter design for the power supply and device protection layers includes: selecting the filtering parameters of the common-mode filter stage and the differential-mode filter stage based on the conducted interference spectrum, determining the sampling bandwidth and gain range of the active compensation circuit, and configuring frequency-division decoupling capacitor groups at the power supply nodes of key integrated circuits, which respectively act on the low-frequency, mid-frequency, and high-frequency bands.

[0015] Preferably, the electromagnetic compatibility verification includes: establishing a verification object in the same verification scenario that includes a housing protection level, a printed circuit board protection level, and a power supply and device protection level; applying external radiation excitation to the housing protection level and applying internal interference excitation to the internal ports of the airborne electronic equipment; and returning to the parameter design process of the corresponding protection level for adjustment when the verification result does not meet the target of the corresponding level.

[0016] Beneficial effects 1. The flexible wave-absorbing structure on the inner wall of the shell and the sealing structure at the joint surface act on the electromagnetic waves inside the shell and the leakage path at the joint surface, respectively, which helps to reduce the radiation coupling left by the shell layer.

[0017] 2. The embedded electromagnetic bandgap structure between the ground reference layers, in conjunction with the electromagnetic bandgap isolation bands between the digital circuit region and the analog circuit region, helps to suppress the propagation or resonance of the ground reference layer and the high-frequency interference coupling between regions.

[0018] 3. The common-mode filter stage, differential-mode filter stage, and active compensation circuit at the power input, in conjunction with the frequency division decoupling capacitor bank at the key integrated circuit power supply node, help suppress conducted noise at the power input and device power supply node respectively.

[0019] 4. The three protection levels are set with parameters based on the same target interference set and undergo electromagnetic compatibility verification together. This allows the verification results to be fed back to the protection level that does not meet the target, which helps to reduce protection gaps and parameter mismatches caused by independent layered design. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the overall structure of the hierarchical collaborative electromagnetic compatibility architecture for airborne electronic equipment provided in a preferred embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram of a partial structure of the shell protection layer provided in a preferred embodiment of the present invention.

[0022] Figure 3 This is a schematic diagram of an embedded electromagnetic bandgap structure and hybrid grounding layout provided in a preferred embodiment of the present invention.

[0023] Figure 4 This is a schematic diagram of a power supply and device protection layer circuit architecture provided in a preferred embodiment of the present invention.

[0024] Figure 5 This is a flowchart of a hierarchical collaborative electromagnetic compatibility design method provided in a preferred embodiment of the present invention. Detailed Implementation

[0025] The following embodiments are used to illustrate the technical solutions of the present invention and do not constitute a limitation on the scope of protection. The structures and processes in the embodiments revolve around the established housing protection level, printed circuit board protection level, power supply and device protection level, and the common verification relationship among the three.

[0026] Example 1

[0027] This embodiment focuses on airborne electronic equipment. The equipment includes a housing, a multilayer printed circuit board, a power input, and power supply nodes for critical integrated circuits. These three protection levels respectively provide radiation protection for the housing, grounding and area isolation for the printed circuit board, and suppression of conducted interference for the power supply and device power supply nodes, and all undergo electromagnetic compatibility verification. Figure 1As shown in the figure, the three-level protection architecture is unfolded according to the following three protection levels and joint verification relationships.

[0028] The housing protection layer includes a housing with a flexible wave-absorbing structure on the inner wall and a joint surface sealing structure at the joint surface, wherein the joint surface sealing structure includes a periodic array of metal through holes.

[0029] The housing provides space for the internal components of airborne electronic equipment. A flexible absorbing structure is located on the inner wall of the housing to absorb electromagnetic waves entering or propagating within it. A joint sealing structure is located at the joint surface of the housing to block leakage paths formed therein. A periodic array of metal through-holes is included in the joint sealing structure, and its array parameters are structural parameters belonging to the housing protection layer. The flexible absorbing structure is positioned relative to the housing via its location on the inner wall, and the joint sealing structure is positioned relative to the housing via its location at the joint surface.

[0030] The enclosure protection layers are configured with protection targets according to the propagation path inside the enclosure and the leakage path at the joint surface. Electromagnetic waves entering the enclosure, as well as electromagnetic waves generated by internal components and propagating inside the enclosure, are first absorbed by the flexible absorbing structure located on the inner wall; the electromagnetic energy reaching the enclosure joint surface is absorbed by the joint surface sealing structure. These two types of structures function specifically for the internal space and the joint surface location, respectively, giving the enclosure protection layers a structural division of labor oriented towards different propagation locations, and providing a basis for subsequently determining structural parameters according to the corresponding interference spectrum.

[0031] The implementation information of the flexible absorbing structure includes the structural identity and hierarchical order of each functional layer within the layered structure, as well as the arrangement characteristics of the open-ended resonant ring array. The conductive thin-film open-ended resonant ring array serves as a periodic resonant structure, the flexible dielectric substrate as the dielectric layer, and the resistive thin film as the resistive layer. These three types of functional layers are stacked sequentially to form the same flexible absorbing structure, enabling electromagnetic waves propagating inside the shell to be processed within the combined action path formed by the periodic resonant structure, the dielectric structure, and the resistive structure.

[0032] The implementation information of the mating surface sealing structure includes the mating surface location, the sealing strip carrier, the periodic array of metal through holes inside the sealing strip, and the treatment status of the contact surface between the sealing strip and the housing. The mating surface location is used to determine the effective area of ​​the leakage path, the sealing strip is used to form the sealing structure in this area, the periodic array of metal through holes is used to form a periodic structure inside the sealing strip, and the conductive treatment of the contact surface is used to maintain the conductive contact state at the contact point between the sealing strip and the housing. The above information together constitutes the identifiable structural chain of the mating surface sealing structure.

[0033] like Figure 2As shown, the local structure of the shell protection layer includes a flexible absorbing structure disposed on the inner wall of the shell and a joint surface sealing structure disposed at the shell joint surface. The flexible absorbing structure is formed by sequentially stacking a conductive thin film open resonant ring array, a flexible dielectric substrate, and a resistive thin film; the joint surface sealing structure includes a conductive elastomer sealing strip located at the shell joint surface, the conductive elastomer sealing strip having a periodic array of metal through holes, and the contact surface between the conductive elastomer sealing strip and the shell being conductively treated. Figure 2 The hierarchical order of the three types of functional layers on the inner wall of the shell and the structural relationship between the sealing strip, the through hole array and the conductive contact surface at the joint surface are respectively expressed.

[0034] In a preferred embodiment, in the above-mentioned shell protection layer, the flexible absorbing structure is a layered structure formed by sequentially stacking a conductive thin film open resonant ring array, a flexible dielectric substrate, and a resistive thin film.

[0035] The reason for using this preferred limitation on the inner wall of the shell is that the three types of structures stacked in sequence can clearly distinguish the hierarchical relationship between the resonant structure, the dielectric support layer and the resistive layer within the same flexible wave-absorbing structure.

[0036] This layered structure allows the periodic resonant structure and resistive thin film to work together in a layered system of flexible dielectric substrate to absorb electromagnetic waves inside the shell.

[0037] The aforementioned layered structure is a preferred configuration of the flexible absorbing structure and belongs to a non-unique boundary; its technical content is that a conductive thin film open resonant ring array, a flexible dielectric substrate, and a resistive thin film are stacked sequentially to form a layered structure.

[0038] The sealing structure at the joint surface can use a conductive elastomer sealing strip as a carrier. A periodic array of metal through-holes is located within the conductive elastomer sealing strip, and a conductivity treatment is applied to the contact surface between the conductive elastomer sealing strip and the housing. This treatment is used to maintain conductive contact at the joint surface; the technical content involves the conductive treatment of the contact surface between the conductive elastomer sealing strip and the housing.

[0039] In a preferred embodiment, in the above-mentioned housing protection layer, the mating surface sealing structure includes a conductive elastomer sealing strip located at the mating surface of the housing, the conductive elastomer sealing strip having the periodic metal through-hole array therein, and the contact surface between the conductive elastomer sealing strip and the housing being conductively treated.

[0040] The reason for using this preferred definition in the joint sealing structure is that the conductive elastomer sealing strip provides the same structural carrier for the sealing structure at the joint surface and the periodic metal through-hole array, and clarifies the target of the contact surface treatment.

[0041] This setting acts simultaneously on both the sealing path and the electromagnetic leakage path at the housing mating surface, helping to suppress electromagnetic leakage coupling at the mating surface.

[0042] The relationship between the sealing strip, the through-hole array, and the contact surface treatment described above is a preferred configuration and is not a unique boundary; its structural boundary is that the sealing strip is located at the shell joint surface, the through-hole array is located inside the sealing strip, and the contact surface is treated with conductivity.

[0043] The printed circuit board protection layer includes an embedded electromagnetic bandgap structure disposed between ground reference layers of a multilayer printed circuit board and an electromagnetic bandgap isolation band formed by the embedded electromagnetic bandgap structure and located between the digital circuit region and the analog circuit region.

[0044] The multilayer printed circuit board comprises multiple conductive layers, at least two of which serve as ground reference layers. An embedded electromagnetic bandgap structure is located between the ground reference layers, and its periodic structure is used to suppress electromagnetic wave propagation or parasitic resonance between the ground reference layers. Digital circuit regions and analog circuit regions are divided according to the type of circuits they carry. An electromagnetic bandgap isolation band, formed by the embedded electromagnetic bandgap structure and located between the two types of regions, is used to reduce the coupling of high-frequency interference from the digital circuit region to the analog circuit region.

[0045] The printed circuit board (PCB) shielding layers simultaneously address propagation issues between ground reference layers and regional coupling issues between digital and analog circuit regions. For propagation paths between ground reference layers, the embedded electromagnetic bandgap structure is positioned between the ground reference layers; for inter-region coupling paths, the electromagnetic bandgap isolation band is positioned between the digital and analog circuit regions. Thus, the same electromagnetic bandgap structure serves both as a periodic structure between ground reference layers and as an isolation band between the two types of circuit regions, with the two operational positions corresponding to inter-layer propagation and inter-region coupling, respectively.

[0046] A periodic metal patch array and a metallized via array together form the elemental relationship of an embedded electromagnetic bandgap structure. The periodic metal patch array is disposed on the first ground reference layer, and the metallized via array connects the patch array to the adjacent second ground reference layer, so that each type of array has a defined structural object between two adjacent ground reference layers. When selecting element parameters, the ground layer resonant frequency or the internal interference frequency is used as the selection basis, and the obtained element parameters are used to form an electromagnetic bandgap structure configuration corresponding to that frequency.

[0047] The multi-point grounding grid in the digital circuit area provides multiple grounding locations, while the single-point grounding in the analog circuit area converges the grounding wires of that area to a single grounding point. Both grounding methods are set up separately for each circuit area, with an electromagnetic bandgap isolation band located between the two types of areas, thus combining the area grounding method with inter-area high-frequency isolation within the same printed circuit board protection layer. When the power layer and a ground reference layer are placed adjacent to each other, the two layers form an interlayer planar capacitance. This structure serves as a high-frequency decoupling component on the printed circuit board, and together with the hybrid grounding layout and electromagnetic bandgap structure, constitutes the parameter output of the printed circuit board protection layer.

[0048] like Figure 3 As shown, two adjacent ground reference layers can be referred to as the first ground reference layer and the second ground reference layer, respectively. "First" and "second" serve only as distinguishing labels between the two adjacent ground reference layers. A periodic metal patch array is disposed on the first ground reference layer, and a metallized via array connects the periodic metal patch array to the adjacent second ground reference layer. The digital circuit area uses a multi-point grounding grid, while the analog circuit area uses a single-point grounding, with an electromagnetic bandgap isolation band maintained between them. The power layer is disposed adjacent to a ground reference layer, and the two layers constitute an interlayer planar capacitance.

[0049] In a preferred embodiment, in the above-mentioned printed circuit board protection layer, the embedded electromagnetic bandgap structure includes a periodic metal patch array disposed on a first ground reference layer and a metallized via array connecting the periodic metal patch array to an adjacent second ground reference layer. The digital circuit area adopts a multi-point grounding grid, the analog circuit area adopts a single-point grounding, and the power layer is disposed adjacent to a ground reference layer to form an interlayer planar capacitance.

[0050] The reason for using this preferred limitation in the protection layer of the printed circuit board is that the periodic structure of the surface mount and vias, the different grounding methods of the digital and analog areas, and the adjacent power layers and ground reference layers can form a complete grounding and decoupling layout in the same multilayer printed circuit board.

[0051] This layout is used to suppress electromagnetic wave propagation or parasitic resonance between ground reference layers and to reduce high-frequency interference coupling between digital circuit regions and analog circuit regions through electromagnetic bandgap isolation.

[0052] The combination of the above-mentioned surface mount, via, hybrid ground, and interlayer planar capacitance is a preferred configuration and belongs to a non-unique boundary; its technical boundary is constituted by the relationship between surface mount and via, the grounding method of digital and analog areas, and the adjacent power layer and ground reference layer.

[0053] The power supply and device protection layers include a common-mode filter stage, a differential-mode filter stage, and an active compensation circuit arranged sequentially at the power input, as well as a frequency-division decoupling capacitor bank for the power supply nodes of key integrated circuits.

[0054] The power input is the point where external power enters the airborne electronic equipment. Common-mode filtering, differential-mode filtering, and active compensation circuitry are arranged in the aforementioned order to handle common-mode interference, differential-mode interference, and residual noise retained after passive filtering, respectively. The critical integrated circuit power supply node is located downstream of the power input filtering chain, and a group of frequency-band decoupling capacitors acts on different frequency band power supply noise at this node. This arrangement forms a continuous protection chain from the power input to the device power supply node.

[0055] The processing chain at the power input is arranged in order according to the interference pattern and processing stage. The common-mode filter stage first receives common-mode interference occurring along the power supply path, the differential-mode filter stage continues to receive differential-mode interference, and the active compensation circuit treats the residual noise retained after the aforementioned filtering. This order ensures that common-mode filtering, differential-mode filtering, and residual noise compensation each have corresponding input objects, and places the active compensation circuit in the power supply path after the passive filtering stage.

[0056] Signal processing in the active compensation circuit begins with the residual noise signal. The noise sampling circuit acquires the residual noise signal at the power supply output and sends it to the inverting processing circuit. The inverting processing circuit generates an inverted compensation signal based on this signal, and the compensation signal injection circuit then sends the generated inverted compensation signal to the power bus. This input, generation, and injection relationship enables the active compensation circuit to process the noise retained after passive filtering, using the compensation signal from the power bus as the output of this processing chain.

[0057] At critical integrated circuit power supply nodes, the frequency-division decoupling capacitor bank is configured according to the frequency band order of power supply noise. The decoupling frequency bands of tantalum electrolytic capacitors, ceramic capacitors, and embedded planar capacitors increase sequentially, allowing the three types of capacitors to respectively absorb power supply noise at different frequency bands. Located at critical integrated circuit power supply nodes, the frequency-division decoupling capacitor bank continues to act on the device power supply location after filtering and compensation at the power input, forming a protective chain extending from the input processing to the node processing.

[0058] The output parameters for the power supply and device protection levels can be divided into four groups based on the structural object: filter parameters for the common-mode filter stage, filter parameters for the differential-mode filter stage, sampling bandwidth and gain range of the active compensation circuit, and frequency band configuration of the decoupling capacitor bank. All four groups of parameters use the conducted interference spectrum as the design input and are respectively implemented in the common-mode choke and Y capacitor, differential-mode inductor and X capacitor, sampling to the injection signal chain, and the three types of decoupling capacitors. Therefore, the conducted interference spectrum can correspond to different processing objects at the power supply input and device power supply nodes.

[0059] like Figure 4As shown, the common-mode filtering stage may include a common-mode choke and a Y capacitor, while the differential-mode filtering stage may include a differential-mode inductor and an X capacitor. The noise sampling circuit in the active compensation circuit takes the residual noise signal at the power supply output as input, the inverting processing circuit generates an inverted compensation signal based on this, and the compensation signal injection circuit injects the inverted compensation signal into the power bus. The processing boundary of the active compensation circuit consists of a signal chain of sampling, inverting processing, and injection. The tantalum electrolytic capacitors, ceramic capacitors, and embedded planar capacitors in the frequency band decoupling capacitor bank have a sequential relationship of increasing decoupling frequency bands.

[0060] In a preferred embodiment, in the above power supply and device protection layers, the common-mode filtering stage includes a common-mode choke and a Y capacitor, and the differential-mode filtering stage includes a differential-mode inductor and an X capacitor; the active compensation circuit includes a noise sampling circuit, an inverting processing circuit, and a compensation signal injection circuit. The noise sampling circuit collects the residual noise signal at the power output terminal, the inverting processing circuit generates an inverted compensation signal based on the residual noise signal, and the compensation signal injection circuit injects the inverted compensation signal into the power bus; the frequency band decoupling capacitor bank includes tantalum electrolytic capacitors, ceramic capacitors, and embedded planar capacitors, with the decoupling frequency bands of the three increasing sequentially.

[0061] The reason for adopting this preferred limitation at the power supply and device protection level is that the common-mode, differential-mode, and active compensation structures at the power supply inlet and the frequency-division decoupling structures at the key integrated circuit power supply nodes can respectively undertake the tasks of suppressing conducted interference at the inlet and decoupling at the nodes.

[0062] This combination enables residual noise signals to be processed along the signal path of sampling, inversion, and compensation injection, and allows three types of capacitors to act on critical integrated circuit power supply nodes in sequentially increasing decoupling frequency bands.

[0063] The above-mentioned combination of filtering, compensation and decoupling is a preferred configuration and belongs to a non-unique boundary; its technical boundary is constituted by the interstage order of the power supply inlet, the signal chain from sampling to injection, and the decoupling frequency band order of the three types of capacitors.

[0064] Joint verification relationship: The structural or circuit parameters of each protection level are set according to the corresponding interference spectrum in the same target interference set. The three protection levels together constitute the joint electromagnetic compatibility verification object. The parameters include parameter values ​​determined according to the verification results.

[0065] The target interference set is used to collect information on external radiated interference, internal interference, and conducted interference that the equipment needs to handle. The structural parameters of the housing protection layer correspond to external radiation and interference states within the housing and at joint surfaces; the structural parameters of the printed circuit board protection layer correspond to ground reference layer resonance or internal interference; and the circuit parameters of the power supply and device protection layer correspond to conducted interference and decoupling requirements for critical integrated circuit power supply nodes. This correspondence is defined by the technical boundary of the corresponding parameters driven by the interference spectrum related to the target at each layer within the same set.

[0066] The target interference set is not three isolated design inputs, but rather a set of inputs shared by three protection levels. For the housing protection level, spectral information related to external radiation, internal housing propagation, and leakage locations at joint surfaces is obtained from the set. For the printed circuit board protection level, spectral information related to internal interference and ground plane resonance is obtained from the set. For the power supply and device protection level, spectral information related to conducted interference and power supply node noise is obtained from the set. Each level uses the portion of the set corresponding to its own target, maintaining the source association with the same target interference set.

[0067] The parameter setting process unfolds as a chain of correspondence between spectral information, protected object, and parameter type. Spectral information related to the housing is incorporated into the structural parameter settings for the flexible absorbing structure and the sealing structure of the joint surface; spectral information related to the printed circuit board is incorporated into the structural parameter settings for the electromagnetic bandgap unit, grounding layout, and isolation strip; and spectral information related to the conduction path is incorporated into the circuit parameter settings for filtering, compensation, and decoupling. This correspondence chain translates the information obtained from environmental analysis into specific physical structures or circuits, and the resulting parameter configurations are then jointly verified along with the three protection levels.

[0068] In joint verification, each level retains its own hierarchical objective while also appearing as a collective equipment-level verification object. External radiation excitations act on the enclosure protection level, while internal interference excitations act on the internal ports of airborne electronic equipment. The verification process yields results corresponding to enclosure protection, printed circuit board protection, and power supply and device protection, respectively. A one-to-one correspondence is maintained between the results and the hierarchical objectives, enabling the joint verification results to pinpoint the protection level that generated those results.

[0069] When determining parameter values ​​after verification, the corresponding protection level is first determined based on results that do not meet the target. Then, the interference information corresponding to that result is returned to the parameter setting object for that level. Returning to the housing protection level processes the corresponding structural parameters; returning to the printed circuit board protection level processes electromagnetic bandgap or grounding layout parameters; and returning to the power supply and device protection level processes filtering, compensation, or decoupling parameters. The three adjusted levels continue to be treated as the same verification object, and the current parameter value is determined by the results of the re-verification.

[0070] When the three protection levels are used as the same verification object, the verification inputs include external radiated excitations targeting the enclosure and internal interference excitations targeting the internal ports of airborne electronic equipment. The verification outputs characterize whether enclosure protection, printed circuit board protection, and power supply and device protection meet the objectives, respectively, according to the protection level targets. The verification results are used to identify protection levels that do not meet the objectives and feed back the determined values ​​of the corresponding structural or circuit parameters to the equipment configuration. Figure 1 The verification relationship in the system consists of co-inclusion and targeted feedback.

[0071] Example 2

[0072] This embodiment illustrates how to configure parameters for three protection levels based on the electromagnetic environment of airborne electronic equipment. The process input, layered parameter design, joint verification, and targeted callback sequentially form four top-level steps, as follows: Figure 5 As shown. The output of each step proceeds to the next step; if the hierarchical objective is still not met after re-verification, the process returns to the corresponding parameter design process.

[0073] Step S1: Analyze the electromagnetic environment of airborne electronic equipment and determine the target interference set.

[0074] Electromagnetic environment analysis focuses on the environment in which airborne electronic equipment operates and its internal operating conditions. The external radiation threat spectrum describes the frequency information of radiated interference reaching the equipment from outside the casing; the internal interference source spectrum describes the frequency information of interference generated by digital circuits, analog circuits, or other internal sources within the equipment; and the conducted interference spectrum describes the frequency information of interference propagating along the power input or internal ports. These three types of spectra together constitute the target interference set and serve as common inputs for the design of the parameters for the three protection levels.

[0075] When forming a target interference set, the spectral information can be organized according to the location of the interference's arrival or origin. Spectral information arriving at the device from outside the casing is classified as the external radiation threat spectrum; spectral information generated by internal digital circuits, analog circuits, or other internal sources is classified as the internal interference source spectrum; and spectral information propagating along the power inlet or internal ports is classified as the conducted interference spectrum. Each type of spectrum retains its corresponding interference location and target, so that subsequent parameter design can read the corresponding information hierarchically.

[0076] The output of step S1 includes a target interference set and three levels of targets. The target interference set records three types of spectra and their correspondence with the protected object; the three levels of targets record the judgment objects after the overall electromagnetic compatibility target is decomposed into the housing, printed circuit board, and power supply and device levels. The above two types of outputs are jointly fed into step S2, where the spectrum information serves as the basis for parameter design, and the level targets serve as the basis for the judgment and verification results in steps S3 and S4.

[0077] The overall electromagnetic compatibility (EMC) target addresses the overall protection requirements of airborne electronic equipment. It is decomposed into hierarchical targets at the enclosure protection level, printed circuit board protection level, and power supply and device protection level, ensuring that each level corresponds to its target object and the observed result. The decomposition results are used in subsequent verification to locate results that do not meet the target to the corresponding protection level.

[0078] In a preferred embodiment, in step S1 above, the target interference set includes the external radiation threat spectrum, the internal interference source spectrum, and the conducted interference spectrum. The analysis also includes decomposing the overall electromagnetic compatibility target of the airborne electronic equipment into hierarchical targets corresponding to the housing protection level, the printed circuit board protection level, and the power supply and device protection level, respectively.

[0079] The reason for adopting this preferred limitation in step S1 is that the three types of spectrum respectively characterize the main types of interference that need to be dealt with at the three protection levels, and the level targets provide a basis for level-based judgment for subsequent joint verification.

[0080] This analysis and decomposition allows the three protection levels to have common inputs from the same set of target interferences, and enables the verification results to be mapped to specific level targets.

[0081] The above-mentioned target interference set composition and target decomposition is a preferred organization method and belongs to a non-unique boundary; its technical boundary is that the target interference set is composed of three types of spectrum, and the overall electromagnetic compatibility target is decomposed into three levels of targets.

[0082] Step S2: Based on the target interference set, design the structural parameters or circuit parameters of the following: a shell protection layer with a flexible absorbing structure and a joint surface sealing structure; a printed circuit board protection layer with an embedded electromagnetic bandgap structure and an electromagnetic bandgap isolation band; and a power supply and device protection layer with a common-mode filter stage, a differential-mode filter stage, an active compensation circuit, and a frequency-division decoupling capacitor bank.

[0083] The design inputs for the enclosure protection layer are the interference spectra corresponding to external radiation and leakage paths within the enclosure and at the joint surfaces, all within the target interference set. The design objects include the structural parameters of the flexible absorbing structure and the structural parameters of the periodic metal through-hole array in the joint surface sealing structure. The design outputs are the parameter configurations for the corresponding structures on the inner wall of the enclosure and at the joint surfaces, for joint verification.

[0084] The parameter design of the enclosure protection layer is carried out according to two structural branches. The first structural branch takes the electromagnetic waves propagating inside the enclosure as the target, and determines the hierarchical structure of the flexible absorbing structure and the corresponding structural parameters of the conductive thin film open resonant ring array. The second structural branch takes the leakage path of the joint surface as the target, and determines the corresponding structural parameters of the joint surface sealing structure and its periodic metal through-hole array. The parameter configurations of both branches are included in the enclosure protection layer and are regarded as the structural state of the same layer when entering the joint verification.

[0085] The design input for the printed circuit board (PCB) shielding layer is either the PCB ground plane resonant frequency or the internal interference frequency. Based on this input, the unit parameters of the embedded electromagnetic bandgap structure are selected, and the digital circuit region, analog circuit region, and their grounding layout are determined. The digital circuit region uses a multi-point grounding grid, while the analog circuit region uses a single-point grounding. An electromagnetic bandgap isolation band is placed between the two types of regions. The design output includes the electromagnetic bandgap structure parameters, grounding layout, and isolation band configuration.

[0086] The parameter design of the printed circuit board (PCB) shielding layer involves two interdependent aspects: the ground reference layer structure and the circuit area layout. The ground layer resonant frequency or internal interference frequency is used to select the unit parameters of the electromagnetic bandgap structure; the circuit types of the digital and analog circuit areas are used to determine the location of multi-point grounding grids, single-point grounding, and the isolation band between the two types of areas. The interlayer planar capacitance formed by the power layer and the adjacent ground reference layer serves as a decoupling component for this layer and is included in the verification process along with the aforementioned structural parameters and area layout.

[0087] In a preferred embodiment, in step S2 above, the structural parameter design of the printed circuit board protection layer includes: selecting the unit parameters of the embedded electromagnetic bandgap structure according to the resonant frequency of the ground layer of the printed circuit board or the internal interference frequency, determining the multi-point grounding grid of the digital circuit area and the single-point grounding of the analog circuit area, and setting an electromagnetic bandgap isolation band between the digital circuit area and the analog circuit area.

[0088] The reason for adopting this preferred limitation in step S2 is that the grounding layer resonant frequency or internal interference frequency provides a basis for selecting the electromagnetic bandgap unit parameters, while the grounding layout of the digital and analog regions determines the effective location of the isolation zone.

[0089] This design enables the embedded electromagnetic bandgap structure to simultaneously handle the tasks of suppressing ground reference layer propagation or resonance and high-frequency isolation between digital and analog regions.

[0090] The above-mentioned selection of unit parameters and hybrid grounding layout is a preferred design method, which is not a unique boundary; its technical boundary is to select unit parameters according to the grounding layer resonant frequency or internal interference frequency and form a hybrid grounding layout of digital and analog areas.

[0091] The design input for the power supply and device protection layers is the conducted interference spectrum. Based on the conducted interference spectrum, the filter parameters for the common-mode and differential-mode filter stages are selected. The sampling bandwidth and gain range required for the active compensation circuit to acquire and process residual noise are determined. Frequency-division decoupling capacitor banks are configured at key integrated circuit power supply nodes. The design output includes the power supply input filtering and compensation circuit parameters and the decoupling configuration of the device power supply nodes.

[0092] The parameter design for the power supply and device protection layers is derived from the conducted interference spectrum, forming input parameters and node parameters. Input parameters include the filtering parameters of the common-mode and differential-mode filtering stages, as well as the sampling bandwidth and gain range of the active compensation circuit. Node parameters include the frequency band configuration of tantalum electrolytic capacitors, ceramic capacitors, and embedded planar capacitors. Input parameters affect the filtering and compensation chain starting from the power supply input, while node parameters affect the power supply nodes of critical integrated circuits. Together, they form the circuit parameter configuration submitted for joint verification at this layer.

[0093] After step S2 is completed, the outputs of the three levels use the same level identifier to proceed to step S3. The parameter configurations for the inner wall absorbing structure and joint sealing structure of the housing protection level output; the parameter configurations for the electromagnetic bandgap structure, hybrid grounding, and interlayer planar capacitance of the printed circuit board protection level output; and the parameter configurations for the input filtering compensation and node decoupling of the power supply and device protection level output. The level identifier is used to maintain the correspondence between parameter configurations and level targets in the verification results.

[0094] In a preferred embodiment, in step S2 above, the circuit parameter design of the power supply and device protection level includes: selecting the filtering parameters of the common-mode filter stage and the differential-mode filter stage according to the conducted interference spectrum, determining the sampling bandwidth and gain range of the active compensation circuit, and configuring frequency division decoupling capacitor groups that act on the low-frequency band, the mid-frequency band and the high-frequency band respectively at the power supply node of the key integrated circuit.

[0095] The reason for adopting this preferred limitation in step S2 is that the conducted interference spectrum provides a common basis for selecting the passive filtering parameters, active compensation parameters, and decoupling configuration of the power supply nodes of the power input.

[0096] This design enables common-mode and differential-mode filtering, active compensation, and decoupling configurations for low-frequency, mid-frequency, and high-frequency bands to form a continuous parameter output from the power input to the critical integrated circuit power supply node.

[0097] The above parameter selection and frequency band configuration is a preferred design approach, but it is not a unique boundary. Its technical boundary is the configuration of conducted interference spectrum driving filter parameters, sampling bandwidth, gain range, and frequency band decoupling capacitor bank.

[0098] Step S3: Incorporate the three protection levels into the same electromagnetic compatibility verification.

[0099] Joint verification can employ a verification scenario encompassing three protection levels. The verification objects include the flexible absorbing structure and joint sealing structure of the housing protection level, the embedded electromagnetic bandgap structure and electromagnetic bandgap isolation band of the printed circuit board protection level, and the common-mode filter stage, differential-mode filter stage, active compensation circuit, and frequency-band decoupling capacitor bank of the power supply and device protection level. Verification inputs include external radiated excitations applied to the housing protection level and internal interference excitations applied to the internal ports of airborne electronic equipment.

[0100] The verification process obtains verification results corresponding to the three target levels. The technical boundary for joint verification is that the three protection levels are in the same verification scenario and have results that can be mapped to the target level. The verification results serve as the input for step S4 to identify those that do not meet the target level.

[0101] In the same verification scenario, the housing protection layer appears with the current parameter configuration of a flexible absorbing structure and a joint sealing structure; the printed circuit board protection layer appears with the current parameter configuration of an embedded electromagnetic bandgap structure, hybrid grounding, and isolation bands; and the power supply and device protection layer appears with the current parameter configuration of filtering, compensation, and frequency band decoupling. The three layers retain their respective structural or circuit states in the same verification, ensuring that the verification object encompasses a complete protection chain from the housing to the printed circuit board and then to the power supply and device power supply nodes.

[0102] External radiation excitation corresponds to the enclosure protection level, while internal interference excitation corresponds to the internal ports of airborne electronic equipment. Verification results are recorded separately for three levels: enclosure protection, printed circuit board protection, and power supply and device protection, and correspond to the three level targets established in step S1. This recording relationship allows step S4 to identify specific non-compliant target levels from the equipment-level joint verification results, while retaining the participation status of other levels in this verification.

[0103] Step S4: Based on the verification results, determine the protection level that does not meet the target, adjust the structural or circuit parameters of the protection level that does not meet the target, and perform the electromagnetic compatibility verification again.

[0104] The verification results are matched item by item with the hierarchical targets formed in step S1. If the verification result of a certain level does not meet the target of that level, the level is marked as a level to be adjusted, and the non-compliance status and corresponding interference information are returned to the parameter design process of that level in step S2. The structural parameters of the flexible absorbing structure or the sealing structure of the joint surface are called back for the housing protection level; the structural parameters of the embedded electromagnetic bandgap structure, grounding layout or isolation strip are called back for the printed circuit board protection level; and the circuit parameters of filtering, compensation or decoupling are called back for the power supply and device protection level.

[0105] The identification of the adjustment level is based on the corresponding record of the level target and the level verification result. The enclosure protection result corresponds to the enclosure protection level, the printed circuit board protection result corresponds to the printed circuit board protection level, and the power supply and device protection result corresponds to the power supply and device protection level. When the corresponding result does not meet the level target, the returned information includes the level identifier, the non-compliance status, and the interference information related to the status, for step S2 to select the structural parameters or circuit parameters of the level.

[0106] Parameter callbacks maintain the object correspondence within the hierarchy. Results related to propagation within the housing return parameters for the flexible absorbing structure; results related to joint leakage return parameters for the joint sealing structure; results related to propagation from the ground reference layer or coupling between digital and analog regions return parameters for the electromagnetic bandgap structure or grounding layout; results related to conducted interference or device power supply nodes return filtering, compensation, or decoupling parameters. After parameter adjustments are complete, the updated configuration replaces the configuration used in the previous verification for that hierarchy.

[0107] After parameter adjustment, the three protection levels are again included in the electromagnetic compatibility verification in step S3. This loop only judges whether the verification results of each level meet the corresponding level's objectives. The final output is the configuration of the structural or circuit parameters of the three protection levels determined by the current verification results.

[0108] The re-verification process continues to utilize the verification relationship shared by all three levels, obtaining results corresponding to the objectives of each level. Levels that have not been adjusted participate in the verification with their current parameter configurations, while levels awaiting adjustment participate with their updated parameter configurations. This allows for observation of the current state of the device-level verification object after the parameter callback. The re-verification results are still recorded by level; if a level fails to meet its objective, it is returned to the corresponding parameter design process until a parameter configuration determined by the current verification results is achieved.

[0109] In a preferred embodiment, in steps S3 and S4 above, the electromagnetic compatibility verification includes: establishing a verification object in the same verification scenario that includes a housing protection level, a printed circuit board protection level, and a power supply and device protection level; applying external radiation excitation to the housing protection level and applying internal interference excitation to the internal ports of the airborne electronic equipment; and returning to the parameter design process of the corresponding protection level for adjustment when the verification result does not meet the target of the corresponding level.

[0110] The reason for adopting this preferred limitation in steps S3 and S4 is that the same verification scenario can incorporate three protection levels into a continuous verification process, and the two types of incentives and level targets provide a corresponding relationship for result location and parameter callback.

[0111] This verification and callback relationship allows results that do not meet the objectives to be returned to the parameter design process of the corresponding protection level, thereby maintaining a continuous flow of analysis, layered design, co-verification, and re-verification.

[0112] The above verification scenario, incentive, and callback relationship is a preferred verification method and belongs to a non-unique boundary; its technical boundary is that the three levels are all in the verification scenario, the two types of incentives act on the corresponding objects, and the design process of the return parameters of the level that does not meet the goal.

[0113] Without altering the aforementioned three-level protection objects, common inputs, and verification callback relationships, any equivalent substitutions or conventional transformations made to specific structural or circuit parameters can be used to form corresponding implementation methods.

Claims

1. An airborne electronic device based on a hierarchical collaborative electromagnetic compatibility architecture, characterized in that, include: The housing protection layer includes a housing with a flexible wave-absorbing structure on the inner wall and a joint surface sealing structure at the joint surface, wherein the joint surface sealing structure includes a periodic array of metal through holes; The printed circuit board protection layer includes an embedded electromagnetic bandgap structure disposed between ground reference layers of a multilayer printed circuit board and an electromagnetic bandgap isolation band formed by the embedded electromagnetic bandgap structure and located between the digital circuit region and the analog circuit region. The power supply and device protection layers include a common-mode filter stage, a differential-mode filter stage, and an active compensation circuit arranged sequentially at the power input, as well as a frequency-division decoupling capacitor bank for the power supply nodes of key integrated circuits. The structural or circuit parameters of each protection level are set according to the corresponding interference spectrum in the same target interference set. The three protection levels together constitute a joint electromagnetic compatibility verification object, and the parameters include parameter values ​​determined based on the verification results.

2. The airborne electronic equipment according to claim 1, characterized in that, The flexible absorbing structure is a layered structure formed by sequentially stacking a conductive thin-film open resonant ring array, a flexible dielectric substrate, and a resistive thin film.

3. The airborne electronic equipment according to claim 1, characterized in that, The joint sealing structure includes a conductive elastomer sealing strip located at the joint surface of the housing. The conductive elastomer sealing strip has the periodic metal through-hole array inside, and the contact surface between the conductive elastomer sealing strip and the housing is conductively treated.

4. The airborne electronic equipment according to claim 1, characterized in that, The embedded electromagnetic bandgap structure includes a periodic metal patch array disposed on a first ground reference layer and a metallized via array connecting the periodic metal patch array to an adjacent second ground reference layer. The digital circuit region adopts a multi-point grounding grid, the analog circuit region adopts a single-point grounding, and the power layer is disposed adjacent to a ground reference layer to form an interlayer planar capacitance.

5. The airborne electronic equipment according to claim 1, characterized in that, The common-mode filtering stage includes a common-mode choke and a Y capacitor, and the differential-mode filtering stage includes a differential-mode inductor and an X capacitor. The active compensation circuit includes a noise sampling circuit, an inverting processing circuit, and a compensation signal injection circuit. The noise sampling circuit collects the residual noise signal at the power output terminal, the inverting processing circuit generates an inverted compensation signal based on the residual noise signal, and the compensation signal injection circuit injects the inverted compensation signal into the power bus. The frequency-band decoupling capacitor bank includes tantalum electrolytic capacitors, ceramic capacitors, and embedded planar capacitors, with the decoupling frequency bands of the three increasing sequentially.

6. A hierarchical collaborative electromagnetic compatibility design method for airborne electronic equipment, characterized in that, include: Analyze the electromagnetic environment of airborne electronic equipment and determine the target interference set; Based on the target interference set, design the structural parameters or circuit parameters of the following: a shell protection layer with a flexible absorbing structure and a joint sealing structure; a printed circuit board protection layer with an embedded electromagnetic bandgap structure and an electromagnetic bandgap isolation band; and a power supply and device protection layer with a common-mode filter stage, a differential-mode filter stage, an active compensation circuit, and a frequency-division decoupling capacitor bank. Incorporate the three protection levels into the same electromagnetic compatibility verification; Based on the verification results, determine the protection level that does not meet the target, adjust the structural or circuit parameters of the protection level that does not meet the target, and perform the electromagnetic compatibility verification again.

7. The design method according to claim 6, characterized in that, The target interference set includes the external radiation threat spectrum, the internal interference source spectrum, and the conducted interference spectrum. The analysis also includes decomposing the overall electromagnetic compatibility target of airborne electronic equipment into hierarchical targets corresponding to the housing protection level, the printed circuit board protection level, and the power supply and device protection level, respectively.

8. The design method according to claim 6, characterized in that, The structural parameter design of the printed circuit board protection layer includes: selecting the unit parameters of the embedded electromagnetic bandgap structure according to the resonant frequency of the ground layer of the printed circuit board or the internal interference frequency, determining the multi-point grounding grid of the digital circuit area and the single-point grounding of the analog circuit area, and setting an electromagnetic bandgap isolation band between the digital circuit area and the analog circuit area.

9. The design method according to claim 6, characterized in that, The circuit parameter design of the power supply and device protection layer includes: selecting the filtering parameters of the common-mode filter stage and the differential-mode filter stage according to the conducted interference spectrum, determining the sampling bandwidth and gain range of the active compensation circuit, and configuring frequency division decoupling capacitor groups that act on the low-frequency band, mid-frequency band and high-frequency band respectively at the power supply nodes of key integrated circuits.

10. The design method according to claim 6, characterized in that, The electromagnetic compatibility verification includes: establishing a verification object in the same verification scenario that includes a housing protection level, a printed circuit board protection level, and a power supply and device protection level; applying external radiation excitation to the housing protection level and applying internal interference excitation to the internal ports of airborne electronic equipment; and returning to the parameter design process of the corresponding protection level for adjustment when the verification result does not meet the target of the corresponding level.

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