Semiconductor device, semiconductor device structure, and method of forming the same

Abstract

Semiconductor devices, semiconductor device structures, and methods of formation are provided. A frontside global source power supply voltage grid is integrated between a memory array and a peripheral connection region to provide a low resistance charge rebalancing path in plasma-based etch processes. After formation of the frontside interconnects, the wafer backside is thinned, a backside dielectric is deposited, and feedthrough and backside contact vias are patterned by plasma-based anisotropic etching to expose source / drain components and frontside peripheral contacts. Conductive fill forms the feedthrough and backside contact structures and builds a backside global source power supply voltage grid. The resulting dual grid structure establishes parallel current paths above and below the source region layer containing, enabling fast discharge of plasma accumulated charge, reducing voltage drop, suppressing ground bounce, and improving read margin uniformity. Upper interconnect layers and pads complete the wiring to provide stable power delivery and enhance resilience to plasma-induced damage in the array and peripheral circuitry.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices, semiconductor device structures, and methods of forming the same. Background Technology

[0002] Plasma-based etching processes used to pattern the upper dielectric layer and upper metal interconnect structure can damage sensitive components of static random access memory (SRAM) devices, such as the gate dielectric. Therefore, appropriate protection for these sensitive components is necessary. Furthermore, ground bounce voltage can reduce the available window of operating logic voltages. Improvements to the global source power supply voltage grid structure are needed to help provide a wider operating voltage window. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, a method for forming a semiconductor device structure is provided, comprising: forming a first field-effect transistor (FET) and a second field-effect transistor (FET) on a substrate, wherein each of the first FET and the second FET includes a corresponding channel region laterally surrounded by an isolation component, a corresponding gate structure formed on the corresponding channel region, a corresponding source / drain component, and a dielectric layer covering an etch stop layer, wherein the etch stop layer covers the isolation component and the source / drain component, wherein the height and width of the corresponding source / drain component are different, and the width of the corresponding source / drain component is greater than the width of the corresponding channel region, such that a portion of the corresponding source / drain component hangs over the isolation component, wherein the first FET includes a first source / drain component, and the second FET includes a second source / drain component; forming a front dielectric over the first FET and the second FET. A material layer and a front metal interconnect structure, wherein the front metal interconnect structure includes a front global source power supply voltage grid structure extending through a memory array region and a peripheral connection region and formed on a first source / drain component; forming an interconnect structure including interconnect layers, wherein each of the interconnect layers includes a metal line disposed in a dielectric layer, wherein at least one of the metal lines includes a barrier layer adjoining the dielectric layer and a fill metal spaced apart from the dielectric layer by the barrier layer, wherein the conductivity of the barrier layer is less than the conductivity of the fill metal, wherein at least one of the metal lines includes a curved top surface in a cross-sectional view; providing an assembly including an interconnect structure, a first field-effect transistor and a second field-effect transistor, and a back contact level dielectric layer by removing a back side portion of the substrate at least after forming the interconnect structure; and forming a through-hole structure that passes through the back contact level dielectric layer on the bottom surface of the first component of the front global source power supply voltage grid structure in the peripheral connection region.

[0004] According to another aspect of the embodiments of this application, a method of manufacturing a semiconductor device includes: forming active regions and isolation components on a substrate, wherein each of the active regions includes a corresponding channel region and a corresponding source / drain region adjacent to the corresponding channel region; forming a gate structure, wherein each of the gate structures is in contact with at least three surfaces of a corresponding one of the channel regions; forming an epitaxial component above the source / drain region, wherein the epitaxial component includes a first source / drain component configured to be biased at a global source power supply voltage and a second source / drain component configured to be biased at a global drain power supply voltage; forming a front-side global source power supply voltage grid structure on the epitaxial component, wherein the front-side global source power supply voltage grid structure is electrically connected to the first source / drain component through a front-side source / drain contact via structure; and forming a front-side global source power supply voltage grid structure. An interconnect structure is fabricated on a source power supply voltage grid structure, wherein the interconnect structure includes interconnect layers, each of the interconnect layers including a metal line disposed in a respective dielectric layer, wherein at least one of the metal lines includes a curved top surface in a cross-sectional view; after fabricating the interconnect structure, a flat back-side surface is formed on the back side of the active region by removing at least a back-side portion of the substrate; an assembly is disposed on a chuck in a plasma-based etching apparatus, the assembly including the interconnect structure, the active region, at least one material layer and a patterned photoresist layer, and the assembly is oriented such that the front-side global source power supply voltage grid structure is electrically connected to the chuck; and the back-side surface of a first source / drain component is exposed by performing a back-side anisotropic etching process, wherein the back-side anisotropic etching process forms a back-side contact via cavity through at least one material layer.

[0005] According to another aspect of the embodiments of this application, a semiconductor device structure includes: a first field-effect transistor and a second field-effect transistor, laterally surrounded by an isolation component, wherein each of the first and second field-effect transistors includes a corresponding channel region laterally surrounded by the isolation component, a corresponding gate structure located on the channel region, and a source / drain component as an epitaxial component connected to a corresponding sidewall of the channel region, wherein an etch stop layer covers the isolation component and the epitaxial component, and a dielectric layer covers the etch stop layer, wherein each of the epitaxial components includes a first layer adjacent to a corresponding sidewall of the channel region and a second layer away from the sidewall of the channel region, wherein the composition of the first layer is different from the composition of the second layer; an interconnect layer including a front dielectric material layer, a front metal interconnect structure, and a front-side global source power supply voltage grid structure located on the front side of the isolation component, wherein the front-side global source power supply voltage grid structure extends through a memory array region and the periphery. The connection region, and the front-side global source power supply voltage grid structure includes a first front contact via structure contacting a first subset of the source / drain components of the first field-effect transistor, wherein a second subset of the source / drain components of the first field-effect transistor is electrically isolated from the front-side global source power supply voltage grid structure, wherein each of the interconnect layers includes a metal line disposed in a corresponding dielectric layer, wherein at least one of the metal lines includes a barrier layer connected to the corresponding dielectric layer and a fill metal isolated from the corresponding dielectric layer through the barrier layer, wherein the conductivity of the barrier layer is less than the conductivity of the fill metal; the back-side global source power supply voltage grid structure is disposed on the back side of the first field-effect transistor, the second field-effect transistor and the isolation component, and includes a back-side contact via structure contacting the back-side surface of the first subset of the source / drain components, and also includes a feedthrough via structure contacting the bottom surface of the first component of the front-side global source power supply voltage grid structure. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Various features of the components may not be drawn to scale, and some components may be omitted from the drawings for clarity.

[0007] Figure 1A This is a plan view of a substrate including a first carrier wafer and a semiconductor material layer according to an embodiment of the present disclosure. Figure 1B It is along Figure 1A A vertical cross-sectional view of the substrate in the vertical plane B-B'. Figure 1C This is a plan view of a semiconductor die having a first exemplary layout according to an embodiment of the present disclosure. Figure 1D This is a plan view of a semiconductor die having a second exemplary layout according to an embodiment of the present disclosure.

[0008] Figure 2AThis is a schematic plan view of a region of a semiconductor die after the formation of the field-effect transistor and the peripheral semiconductor material portion, according to an embodiment of the present disclosure. For clarity, Figure 2A Only the transistor semiconductor nanosheet, peripheral region semiconductor nanosheet, and isolation component of the field-effect transistor are shown. Figure 2B It is along Figure 2A The vertical cross-sectional view of the vertical plane B-B'. Figure 2C It is along Figure 2B A vertical cross-sectional view of the semiconductor die region in the vertical plane C-C'.

[0009] Figure 3A This is a schematic plan view of a region of a semiconductor die after the formation of a front-side first line-level metal interconnect structure, according to an embodiment of the present disclosure. Figure 3B It is along Figure 3A The vertical cross-sectional view of the vertical plane B-B'. Figure 3C It is along Figure 3B A vertical cross-sectional view of the semiconductor die region in the vertical plane C-C'.

[0010] Figure 4A This is a schematic plan view of a region of a semiconductor die after the formation of the front-side second line-level metal interconnect structure, according to an embodiment of the present disclosure. Figure 4B It is along Figure 4A The vertical cross-sectional view of the vertical plane B-B'.

[0011] Figure 5A This is a schematic plan view of the region of the first configuration of the semiconductor die after the formation of the front third line layer metal interconnect structure, according to an embodiment of the present disclosure. Figure 5B It is along Figure 5A The vertical cross-sectional view of the vertical plane B-B'.

[0012] Figure 6A This is a schematic plan view of the region of the second configuration of the semiconductor die after the formation of the front third line layer metal interconnect structure, according to an embodiment of the present disclosure. Figure 6B It is along Figure 6A The vertical cross-sectional view of the vertical plane B-B'.

[0013] Figure 7A This is a schematic plan view of the region of the second configuration of the semiconductor die after the formation of the front fourth line level metal interconnect structure, according to an embodiment of the present disclosure. Figure 7B It is along Figure 7A The vertical cross-sectional view of the vertical plane B-B'.

[0014] Figure 8A This is a schematic plan view of the region of the third configuration of the semiconductor die after the formation of the front fourth line level metal interconnect structure, according to an embodiment of the present disclosure. Figure 8B It is along Figure 8A The vertical cross-sectional view of the vertical plane B-B'. Figure 8C It is an enlarged vertical cross-sectional view of a metal line that can be formed on a semiconductor die along its width.

[0015] Figure 9 This is a vertical cross-sectional view of a plasma-based etching apparatus including a substrate during a plasma-based etching process according to an embodiment of the present disclosure.

[0016] Figure 10 This is a vertical cross-sectional view of the semiconductor die region after the formation of the upper dielectric material layer, the upper metal interconnect structure, and the front pad, according to an embodiment of the present disclosure.

[0017] Figure 11A This is a vertical cross-sectional view of the assembly of the first carrier wafer, the device wafer, and the second carrier wafer according to an embodiment of the present disclosure. Figure 11B yes Figure 11A A magnified view of the component's area.

[0018] Figure 12 This is a vertical cross-sectional view of the assembly after the first carrier wafer has been removed from the device wafer and the semiconductor material layer has been removed, according to an embodiment of the present disclosure.

[0019] Figure 13 This is a vertical cross-sectional view of a region of the semiconductor die in the device wafer after the semiconductor material layer has been removed, according to an embodiment of the present disclosure.

[0020] Figure 14 This is a vertical cross-sectional view of the semiconductor die region after the deposition of the back-side contact layer dielectric layer according to an embodiment of the present disclosure.

[0021] Figure 15A This is a perspective plan view of the semiconductor die region after the formation of the through-hole cavity, according to an embodiment of the present disclosure. Figure 15B It is along Figure 15A A vertical cross-sectional view of the semiconductor die region in the vertical plane B-B'. Figure 15C This is a vertical cross-sectional view of a plasma-based etching apparatus containing a substrate during a first back-side plasma-based etching process for forming a feedthrough cavity, according to an embodiment of the present disclosure.

[0022] Figure 16A This is a perspective plan view of the semiconductor die region after the back-side contact via cavity is formed, according to an embodiment of the present disclosure. Figure 16B During the formation of the back-side contact via cavity, after the first step of the back-side anisotropic etching process, along... Figure 16A A vertical cross-sectional view of the semiconductor die region in the vertical plane B-B'. Figure 16CThis is a vertical cross-sectional view of a plasma etching apparatus containing a substrate during a second back-side plasma etching process for forming a back-side contact via cavity, according to an embodiment of the present disclosure. Figure 16D It is the second step after the anisotropic etching process on the back side of the semiconductor die. Figure 16A The vertical cross-sectional view of the vertical plane B-B' shows that this process further shapes the shape of the back contact through-hole cavity. Figure 16E Following the second step of the back-side anisotropic etching process that further shapes the back-side contact via cavity, along... Figure 16A A vertical cross-sectional view of the alternative configuration region of the semiconductor die in the vertical plane B-B'.

[0023] Figure 17A This is a perspective plan view of the semiconductor die region after the formation of the through-hole structure and the back contact through-hole structure according to an embodiment of the present disclosure. Figure 17B It is along Figure 17A A vertical cross-sectional view of the semiconductor die region in the vertical plane B-B'.

[0024] Figure 18 This is a schematic perspective view of a front-side global source power supply voltage grid structure, a feedthrough via structure, and a back-side contact via structure having a first configuration according to an embodiment of the present disclosure.

[0025] Figure 19 This is a schematic perspective view of a front-side global source power supply voltage grid structure, a feedthrough via structure, and a back-side contact via structure having a second configuration according to an embodiment of this disclosure.

[0026] Figure 20 This is a schematic perspective view of a front-side global source power supply voltage grid structure, a feedthrough via structure, and a back-side contact via structure having a third configuration according to an embodiment of the present disclosure.

[0027] Figure 21 This is a schematic perspective view of a front-side global source power supply voltage grid structure, a feedthrough via structure, and a back-side contact via structure having a fourth configuration according to an embodiment of this disclosure.

[0028] Figure 22A This is a perspective plan view of a region of a semiconductor die after the formation of a first back-side metal line, according to an embodiment of the present disclosure. Figure 22B It is along Figure 22A A vertical cross-sectional view of the semiconductor die region in the vertical plane B-B'.

[0029] Figure 23A This is a perspective plan view of a region of a semiconductor die after the formation of a second back-side metal line, according to an embodiment of the present disclosure. Figure 23B It is along Figure 23AA vertical cross-sectional view of the semiconductor die region in the vertical plane B-B'.

[0030] Figure 24 This is a vertical cross-sectional view of a plasma-based etching apparatus for a substrate during a plasma etching process on the back side of a substrate, according to an embodiment of the present disclosure.

[0031] Figure 25 This is a vertical cross-sectional view of the semiconductor die region after the formation of an additional back-side dielectric material layer, an additional back-side metal interconnect structure, and a back-side pad, according to embodiments of the present disclosure.

[0032] Figure 26 This is a schematic circuit diagram of a static random access memory (SRAM) cell disclosed herein.

[0033] Figure 27A This is a graph showing the relative magnitudes of ground bounce voltages with different configurations for the global source power supply voltage grid. Figure 27B This is a graph showing the relative read margin voltages observed under different configurations of the global source power supply voltage grid.

[0034] Figure 28 This is a vertical cross-sectional view of the region of the first alternative configuration of the semiconductor die after the removal of the first carrier wafer, according to an embodiment of the present disclosure.

[0035] Figure 29 This is a vertical cross-sectional view of a region of a first alternative configuration of a semiconductor die after the deposition of a back-side contact layer dielectric layer, according to an embodiment of the present disclosure.

[0036] Figure 30 This is a vertical cross-sectional view of the region of a first alternative configuration of a semiconductor die after the formation of the through-hole cavity, the back-side contact through-hole cavity, and the back-side insulating spacer, according to embodiments of the present disclosure.

[0037] Figure 31 This is a vertical cross-sectional view of a region of a first alternative configuration of a semiconductor die after the formation of an additional back-side dielectric layer, a back-side metal interconnect structure, and a back-side pad, according to embodiments of the present disclosure.

[0038] Figure 32 This is a vertical cross-sectional view of a region of an alternative embodiment of a first alternative configuration of a semiconductor die after the formation of an additional back-side dielectric material layer, a back-side metal interconnect structure, and a back-side pad, according to embodiments of the present disclosure.

[0039] Figure 33 This is a vertical cross-sectional view of a region of a second alternative configuration of a semiconductor die after the formation of a front-side global source power supply voltage grid structure, according to an embodiment of the present disclosure.

[0040] Figure 34 This is a vertical cross-sectional view of the region of the second alternative configuration of the semiconductor die after the removal of the first carrier wafer, according to an embodiment of the present disclosure.

[0041] Figure 35 This is a vertical cross-sectional view of the region of a second alternative configuration of the semiconductor die after the formation of the through-hole cavity, the back-side contact through-hole cavity, and the back-side insulating spacer, according to embodiments of the present disclosure.

[0042] Figure 36 This is a vertical cross-sectional view of a region of a second alternative configuration of a semiconductor die after the formation of an additional back-side dielectric layer, a back-side metal interconnect structure, and a back-side pad, according to embodiments of the present disclosure.

[0043] Figure 37 This is a vertical cross-sectional view of a region of an alternative embodiment of a second alternative configuration of a semiconductor die after the formation of an additional back-side dielectric material layer, a back-side metal interconnect structure, and a back-side pad, according to embodiments of the present disclosure.

[0044] Figure 38A and Figure 38B A first flowchart is shown, illustrating general processing steps for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0045] Figure 39A and Figure 39B A second flowchart is shown, illustrating general processing steps for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0046] Figure 40A and Figure 40B A third flowchart is shown, illustrating general processing steps for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0047] Figure 41A and Figure 41B A fourth flowchart is shown, illustrating general processing steps for manufacturing a semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0048] The following disclosure provides several embodiments illustrating various possible implementations of the disclosed subject matter. Specific components and configurations are described to provide technical clarity and illustrative support, but are not intended to limit the scope of the invention. Unless explicitly stated otherwise, elements identified by the same reference numerals refer to the same parts and are assumed to have the same material composition and fall within the same thickness range. Unless explicitly excluded, all features disclosed in any embodiment should be understood to be present in derivative embodiments. Therefore, the features described in conjunction with any embodiment or drawings provide written description support for use in any other embodiment. Unless explicitly limited to a single instance, embodiments including multiple instances of the described features are contemplated. Similarly, embodiments in which non-essential features are omitted may be considered even if not specifically shown, provided that such configurations are known to those skilled in the art.

[0049] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” and “lower,” “above,” and “higher,” and similar expressions are used to indicate the relative positions of the elements shown. This spatial description is relative to a given orientation of the structure, not absolute; for example, if the structure is rotated, a surface described as the “top surface” in one direction may become the “bottom surface.” The claims should be interpreted in the context of a correctly oriented configuration of the structure. The first physical element is said to be “embedded” within the second physical element if the entire volume of the first element is contained within an imaginary volume defined by a minimum-area surface surrounding the second element and is topologically equivalent to a sphere. Any openings on the outer surface of the second element are considered to be covered by a minimum-area patch that closes the opening without altering the topology. These spatial descriptors are intended to cover alternative orientations that may arise during use or manufacture, not just those shown in the figures. Unless otherwise stated, components with the same reference numerals are considered to have the same material composition and comparable thickness ranges. Similarly, unless explicitly stated otherwise, each material region is assumed to have a uniform composition.

[0050] As used herein, removal of the first material is "selective" for the second material if the removal rate of the first material is at least three times that of the second material. Unless otherwise specified, "selective removal" means that the selectivity ratio can be equal to or greater than 3, 10, 100, or even 1000. The first and second surfaces are "perpendicularly coincident" when one surface lies directly above or below another surface such that a vertical or substantially vertical plane encompasses both surfaces. A vertical plane is defined as a two-dimensional surface consisting of an uncountable infinite number of vertical lines having a uniform one-dimensional horizontal cross-section that remains unchanged under vertical translation. If the cross-section is linear, the plane is a Euclidean plane; otherwise, it is a non-Euclidean plane. A substantially vertical line is a line that deviates from a perfectly vertical direction by less than 5 degrees. A substantially vertical plane comprises a set of such lines.

[0051] Embodiments of this disclosure relate to semiconductor devices including a front-side global source power voltage grid structure and a back-side global source power voltage grid structure interconnected via a through-hole structure. The front-side global source power voltage grid structure includes a subset of low-level metal interconnect structures and is electrically connected to a subset of the source / drain components of pull-down transistors to provide a global source power voltage to the subset of the source / drain components of the pull-down transistors. The front-side global source power voltage grid structure can span memory array regions and peripheral connection regions, providing a uniform source power potential distribution and a low-resistance charge rebalancing path that can be used during a plasma-based etching process. This etching process can be used to pattern the upper dielectric layer, upper metal interconnect structure, back-side dielectric layer, and back-side metal interconnect structure to reduce plasma damage to sensitive device components.

[0052] A back-side global source power supply voltage grid structure can be formed after thinning the substrate and physically exposing the back side containing the source region layer. The back-side global source power supply voltage grid structure is electrically connected to the front-side global source / power supply voltage grid structure via a through-hole structure and a first subset of the source / drain components of the first field-effect transistor spanning the memory array region and the peripheral connection region. The back-side global source power supply voltage grid structure includes a back-side contact via structure connected to a subset of the source / drain components of the pull-down transistor. Additional electrical connections between the back-side global source power supply voltage grid structure and the front-side global source power supply voltage grid structure can be established via a through-hole structure that can be formed in the peripheral connection region. The combination of the back-side global source power supply voltage grid structure and the front-side global source power supply voltage grid structure can provide a dual-grid configuration including parallel current paths above and below the layer containing the source region for voltage transfer of the source power supply. The dual-grid configuration of various embodiments of this disclosure can reduce voltage drop during global source power supply voltage supply, suppress ground bounce, and improve read margin, particularly in bit cells far from the voltage supply entry point provided in the peripheral connection region. A front-side global source power voltage grid structure can provide a low-resistance charge rebalancing path during plasma-based etching processes and mitigate plasma charging of sensitive device components. The charge rebalancing path during back-side anisotropic etching processes includes a first source / drain component electrically connected to the metal interconnect structure within the front-side global source power voltage grid structure via a first front-side source / drain contact via structure, enabling rapid discharge of plasma-induced charges. A back-side global source power voltage grid structure can improve voltage stability and power delivery. The combination of the front-side and back-side global source power voltage grid structures can reduce the total resistance in the global source power voltage distribution wiring, suppress transient noise during operation, and improve read stability. The number of metal interconnect layers used for the front-side global source power voltage grid structure and through-hole via structure layout can include various configurations based on performance, power, and / or wiring footprint. The dual-grid configurations of various embodiments of this disclosure can be used for various SRAM cell configurations and various power rail layouts to provide stable global power voltage distribution. Various embodiments of this disclosure are now described with reference to the accompanying drawings.

[0053] Figure 1A According to embodiments of this disclosure, it includes a first carrier wafer 411 ( Figure 1B (shown) and a plan view of the substrate 1000 of the top semiconductor layer 128. Figure 1B It is substrate 1000 along Figure 1A The vertical cross-sectional view of the vertical plane B-B'. Figure 1C This is a plan view of a semiconductor die having a first exemplary layout according to an embodiment of the present disclosure. Figure 1DThis is a plan view of a semiconductor die having a second exemplary layout according to an embodiment of the present disclosure.

[0054] Reference Figures 1A-1D A substrate 1000 is provided, comprising a top semiconductor layer 128. The substrate 1000 has a front side and a back side. The substrate 1000 includes a top semiconductor layer 128 comprising a semiconductor material at least on its front side. In one embodiment, the substrate 1000 may include a combination of the top semiconductor layer 128 and a first carrier wafer 411 attached to the back side of the top semiconductor layer 128. In one embodiment, the top semiconductor layer 128 may be a semiconductor-on-insulator (SOI) layer, and the first carrier wafer 411 may be a combination of a processing wafer and an insulating layer bonded to the back side of the top semiconductor layer 128. In this embodiment, the thickness of the top semiconductor layer 128 may be in the range of 100 nm to 1000 nm, but smaller or larger thicknesses may also be used. Alternatively, the substrate 1000 may be a bulk semiconductor wafer, wherein the entire substrate 1000 is the top semiconductor layer 128. In this embodiment, the thickness of the top semiconductor layer 128 may be in the range of 500 micrometers to 1000 micrometers, but smaller or larger thicknesses may also be used.

[0055] The top semiconductor layer 128 may include a single-crystal semiconductor material layer having an overall single-crystal epitaxial arrangement. In one embodiment, the top semiconductor layer 128 may be a single-crystal silicon layer. The top semiconductor layer 128 may include a semiconductor material layer that may subsequently be patterned to provide various single-crystal semiconductor material portions, such as semiconductor nanosheets and / or single-crystal semiconductor material portions.

[0056] The substrate 1000 includes a two-dimensional array of unit regions corresponding to a subsequently formed two-dimensional array of semiconductor dies 700. The combination of regions of the semiconductor die 700 and surrounding notched regions constitutes repeating units RU that repeat along two different horizontal directions. In one embodiment, each region of the semiconductor die 700 includes a static random access memory (SRAM) region (100, 200) for forming a static random access memory (SRAM) array. The SRAM regions (100, 200) include a memory array region 100 and at least one peripheral connection region 200 for providing a vertically extending electrical connection between a front-side global source power supply voltage grid structure and a back-side global source power supply voltage grid structure. Figure 1C In the first exemplary layout shown, the SRAM regions (100, 200) may include two peripheral connection regions 200, which are laterally separated from each other by the memory array region 100. Figure 1DIn the second exemplary layout shown, the SRAM regions (100, 200) may include a memory array region 100 and a single peripheral connection region 200 located only on one side of the memory array region 200.

[0057] Figure 2A According to embodiments of this disclosure, in the portion forming the field-effect transistor and the peripheral semiconductor material (to illustrate the lateral extent of the peripheral semiconductor nanosheet 36), Figure 2A A schematic plan view of the area of ​​the semiconductor die after (not shown in the image). For clarity, Figure 2A Only the transistor semiconductor nanosheet 32, the peripheral region semiconductor nanosheet 36, and the isolation component 31 of the field-effect transistor are shown. Figure 2B It is along Figure 2A The vertical cross-sectional view of the vertical plane B-B'. Figure 2C It is along Figure 2B A vertical cross-sectional view of the semiconductor die region in the vertical plane C-C'.

[0058] Reference Figures 2A to 2C Semiconductor devices can be formed by performing front-end process (FEOL) processes on and above the top semiconductor layer 128. As used herein, a front-end process (FEOL) refers to fabrication steps performed on or above the top semiconductor layer 128 to form semiconductor device assemblies, including but not limited to transistor active regions, transistor gate structures, isolation components (such as shallow trench isolation), doping, epitaxial growth, oxidation, and any associated planarization or annealing operations, including but not limited to forming metal interconnect structures. Transistor active regions may include any structure that can serve as a semiconductor channel (e.g., a planar channel portion of a planar field-effect transistor, a channel portion of a semiconductor fin, and a channel portion of a semiconductor nanosheet, etc.) and / or source / drain components (including first and second source / drain components known in the art). Additional semiconductor devices, such as diodes, resistors, capacitors, etc., may be formed on, above, and / or from the top semiconductor layer 128.

[0059] According to one aspect of this disclosure, a plurality of field-effect transistors (T1, T2, T3) can be formed in a memory array region 100. In one embodiment, the memory array region 100 may include a two-dimensional array of unit cells UC. In one embodiment, each unit cell UC may include a static random access memory (SRAM) cell. In conventional SRAM designs, the number of field-effect transistors (T1, T2, T3) in each cell UC may be 6, but may also be 8, 10, 12, or 4 as known in the art. Generally, any known SRAM design using any known type of field-effect transistor can be used to provide the SRAM cells in each unit cell UC.

[0060] In one embodiment, the top semiconductor layer 128 may be patterned to provide a semiconductor material layer 28, which is an unpatterned, continuous semiconductor material layer of uniform thickness, while the patterned semiconductor material portion originates from the upper portion of the top semiconductor layer 28. In one embodiment, the patterned semiconductor material portion may include transistor semiconductor nanosheets 32 formed in the memory array region 100 and peripheral region semiconductor nanosheets 36 formed in the peripheral connection region 200. A gate dielectric 33, a gate electrode 34, a dielectric gate spacer 35, and various source / drain components 38 may be formed in the memory array region to provide various field-effect transistors (T1, T2, T3). Each combination of the gate dielectric 33, the gate electrode 34, and the dielectric gate spacer 35 includes a gate structure (33, 34, 35). The gate structures (33, 34, 35) may be formed using methods known in the art. For example, in the case where the active region includes a transistor semiconductor nanosheet 32, the gate replacement process uses a gate dielectric material layer 6G, which can serve as a dielectric matrix, acting as a template for forming the gate electrode 34 as the replacement structure. The gate dielectric material layer 6G is one of the preceding dielectric material layers 60 formed on the isolation component.

[0061] An isolation component 31, comprising a dielectric matrix material (such as silicon oxide), may be formed around the field-effect transistors (T1, T2, T3) and around the semiconductor structure formed in each peripheral connection region 200. In one embodiment, the isolation component 31 may comprise a single continuous dielectric matrix that extends laterally through each semiconductor die 700 and laterally surrounds each semiconductor device formed in the semiconductor die 700.

[0062] The transistor semiconductor nanosheet 32 ​​can be used as the channel of a field-effect transistor (T1, T2, T3), and the source / drain component 38 can be used as the source / drain component of the field-effect transistor. The source / drain component 38 may include a single-crystal doped semiconductor material portion epitaxially aligned to a corresponding one of the transistor semiconductor nanosheets 32, as known in the art. A doped semiconductor material portion 37 having the same material composition as a subset of the source / drain components 38 may be formed on the peripheral region semiconductor nanosheet 36. In one embodiment, unit cells UC in the memory array region 100 may be repeated along a first horizontal direction hd1, and rows of unit cells UC may be arranged along a second horizontal direction hd2 to provide a two-dimensional array of unit cells UC. In one embodiment, the boundary between each of the memory array region 100 and at least one peripheral connection region 200 may extend laterally along the first horizontal direction hd1.

[0063] The peripheral semiconductor nanosheets 36 can be arranged as clusters of peripheral semiconductor nanosheets 36, such that the clusters are laterally spaced from each other along the first horizontal direction hd1. Figures 2A to 2C In the exemplary layout shown, each cluster of peripheral semiconductor nanosheets 36 comprises four peripheral semiconductor nanosheets 36. Typically, a cluster of peripheral semiconductor nanosheets 36 may contain two or more peripheral semiconductor nanosheets 36, such that the subsequently formed through-hole structure can provide low resistance. Alternatively, a single peripheral semiconductor nanosheet 36 may be used for each cluster of peripheral semiconductor nanosheets 36.

[0064] In one embodiment, each unit cell UC includes a first field-effect transistor T1, a second field-effect transistor T2, and a third field-effect transistor T3. The first field-effect transistor T1 has an electrical node (e.g., a first source / drain component 381) configured to be electrically biased at a global source supply voltage. The second field-effect transistor T2 has an electrical node (e.g., a second source / drain component 382) configured to be electrically biased at a global drain supply voltage. The third field-effect transistor T3 is not directly connected to the global source supply voltage or the global drain supply voltage, but may be connected to a corresponding intermediate voltage control device inserted between the third field-effect transistor T3 and the corresponding one of the global drain supply voltage and the global source supply voltage. As used herein, "global supply voltage" refers to the potential corresponding to the binary logic value "0", typically at or near ground potential (e.g., 0 V or in the range of 0 to 0.3 V, depending on the technology node). "Global drain supply voltage" refers to the potential corresponding to the binary logic value "1", typically at or near the supply voltage level (e.g., 0.7 V, 1.0 V, or 1.2 V, depending on the technology node and device operating conditions). The global drain supply voltage is typically denoted as Vdd, and the global source supply voltage is typically denoted as Vss. In one embodiment, during the operation of an SRAM cell, the global source and global drain supply voltages can be selectively applied to the source / drain components and gate electrodes of the field-effect transistors (T1, T2, T3) to establish and maintain a bistable logic state within a cross-coupled inverter structure, or to provide access to stored data through bit line and word line activation.

[0065] Typically, multiple transistors can be disposed on the front side of a substrate including a semiconductor material layer 28. The semiconductor material layer 28 can be a thin single-crystal semiconductor material layer disposed on a first carrier wafer 411 via a first adhesive layer 413, or it can be a bulk single-crystal semiconductor wafer. The transistors (T1, T2, T3) include a first source / drain component 381 configured to be biased under a global source power supply voltage, a second source / drain component 382 configured to be biased under a global drain power supply voltage, and additional source / drain components (e.g., a third source / drain component 383, a fourth source / drain component 384, and a fifth source / drain component 385) configured to be at different voltages during semiconductor device operation in each unit cell UC.

[0066] In one embodiment, each source / drain component 38 may be an epitaxial structure formed by growing at least one epitaxial semiconductor material from a physically exposed semiconductor surface in an active region. In an illustrative example, where the channel region includes a transistor semiconductor nanosheet 32, the source / drain component 38 may be grown in a region adjacent to the transistor semiconductor nanosheet 32 ​​(which is the source / drain region) by performing at least one epitaxial growth process (which may include multiple epitaxial growth processes). In one embodiment, each source / drain component 38 may have a corresponding first epitaxial layer 38A and a corresponding second epitaxial layer 38B. The corresponding first epitaxial layer 38A and the corresponding second epitaxial layer 38B are doped with dopants such that the dopant concentration in the corresponding first epitaxial layer 38A is different from the dopant concentration in the corresponding second epitaxial layer 38B. In a cross-sectional view, the thickness of each source / drain component 38 may be different from the width of the source / drain component 381.

[0067] In one embodiment, the duration of at least one epitaxial growth process can be selected such that a portion of the source / drain component 38 is grown above a horizontal plane including the top surface of the isolation component 31 and can be overhanging an adjacent portion of the isolation component 31. The vertical distance vd between the top surface of the source / drain component 38 and the horizontal plane including the top surface of the isolation component 31 can be in the range of 0.3 nm to 50 nm, for example, 3 nm to 30 nm, but smaller or larger vertical distances can also be used. The width we of the source / drain component 38 can be in the range of 10 nm to 60 nm, but smaller or larger widths can also be used. The lateral distance between the outermost edge of each overhanging portion of the source / drain component 38 and an adjacent sidewall of the isolation component 31 can be in the range of 0.3 nm to 50 nm, for example, 3 nm to 30 nm, but smaller or larger lateral distances can also be used.

[0068] Metal silicide portions 48 may be formed on the physically exposed surface of the source / drain components 38. The thickness of the metal silicide portions 48 may range from 5 nm to 20 nm, but smaller or larger thicknesses may also be used. In one embodiment, an etch stop layer 29 may be formed over the source / drain components 38 prior to the deposition of the gate dielectric material layer 6G. The etch stop layer 29 may include a dielectric material that can be effectively used as an etch stop structure during the subsequent formation of the front-side source / drain contact via cavities. For example, the etch stop layer 29 may include silicon nitride, silicon carbonitride, dielectric metal oxide, or combinations thereof. The thickness of the etch stop layer 29 may range from 3 nm to 30 nm, but smaller or larger thicknesses may also be used. The etch stop layer 29 may contact the entire surface segment of each source / drain component 38 located above a horizontal plane including the top surface of the isolation component 31.

[0069] Typically, each transistor may include a channel region (which includes a plurality of corresponding transistor semiconductor nanosheets 32); a gate structure (33, 34, 35) located above the channel region; a pair of epitaxial components (including source / drain components 38) in contact with the corresponding sidewalls of the channel region; an etch stop layer 29 located above the pair of epitaxial components; and a dielectric layer (e.g., a gate dielectric layer 6G) located above the etch stop layer 29. Each epitaxial structure is doped with a dopant. In one embodiment, each epitaxial structure includes a first layer (i.e., a first epitaxial layer 38A) adjacent to the sidewalls of the channel region and a second layer (i.e., a second epitaxial layer 38B) away from the sidewalls of the channel region. The dopant concentration in the first layer may differ from the dopant concentration in the second layer.

[0070] Typically, each field-effect transistor (FET) may include source / drain regions containing structures that serve as source and drain nodes for the FET. Typically, the source / drain regions may comprise portions of doped semiconductor material embedded within a substrate (in the case of planar FETs and fin FETs), or may be space occupied by source / drain components (e.g., source / drain components 38) formed on a transistor semiconductor nanosheet 32. The term "active region" refers to a combination of the channel region, source region, and drain region. Therefore, a transistor typically includes a channel region and two source / drain regions (one used as the source region and the other as the drain region).

[0071] The source / drain component 38 may include an epitaxial component. In one embodiment, each transistor includes: an active region disposed on a substrate; and an epitaxial component disposed above the source / drain region of the active region and including a doped layer, wherein the epitaxial component includes a first layer (e.g., a first epitaxial layer 38A) and a second layer (e.g., a second epitaxial layer 38B), the first layer being adjacent to a channel region of the active region, and the second layer being separated from the channel region of the active region by the first layer. The dopant concentration in the first layer is different from the dopant concentration in the second layer.

[0072] In one embodiment, the gate structures (33, 34, 35) may be connected to at least three surfaces of the channel region. In an example where the active region includes multiple transistor semiconductor nanosheets 32, the gate structures (33, 34, 35) may be connected to four surfaces of the channel region. Epitaxial components (including source / drain components 38) are adjacent to corresponding sidewalls of the channel region. In, for example... Figure 2C In the cross-sectional view shown in the vertical cross-section, the thickness (measured along the vertical direction) of each source / drain component 38 may be different from the width of the source / drain component 38.

[0073] In one embodiment, the etch stop layer 29 covers the isolation member 31 and the source / drain member 38, and a dielectric layer (e.g., the gate dielectric material layer 6G) covers the etch stop layer 29. The height H_E of the corresponding source / drain member 38 and the width W_E of the corresponding source / drain member (e.g., along the horizontal direction perpendicular to the length direction of the channel region) are different, and the width W_E of the corresponding source / drain member 38 is greater than the width W_C of the corresponding channel region, such that a portion of the source / drain member 38 hangs over the isolation member 31.

[0074] In one embodiment, each unit cell UC includes an SRAM device. Within each unit cell UC, a first field-effect transistor T1 may include a pair of pull-down (PD) transistors of a static random access memory (SRAM) cell, a second field-effect transistor T2 may include a pair of pull-up (PU) transistors of an SRAM cell, and a third field-effect transistor T3 may include a pair of transmission gate (PG) transistors of an SRAM cell. In this embodiment, a third source / drain component 383 may be a shared source / drain component between a corresponding one of the first field-effect transistors T1 and a corresponding one of the third field-effect transistors T3, a fourth source / drain component 384 may be a source / drain component of the second field-effect transistor T2, and a fifth source / drain component 385 may be an additional source / drain component of the third field-effect transistor T3. Although this disclosure is described using a configuration of a six-transistor SRAM cell, embodiments of this disclosure can be used in any SRAM cell design.

[0075] The collection of all components covering the semiconductor material layer 28 is referred to herein as the source region layer 30. The active regions of the field-effect transistors (T1, T2, T3) include transistor semiconductor nanosheets 32 and source / drain components 38. The source region layer 30 includes the field-effect transistors (T1, T2, T3), peripheral semiconductor nanosheets 36, doped semiconductor material portions 37, and isolation components 31. Typically, the top semiconductor layer 128 may be patterned as a channel region (which may include, for example, transistor semiconductor nanosheets 32) formed in the memory array region 100 and a peripheral semiconductor material portion 37 formed in the peripheral connection region 200. The isolation component 31 may be formed around the peripheral semiconductor material portion 37, the transistor semiconductor nanosheets 32, the source / drain components 38, and the doped semiconductor material portion 37.

[0076] Figure 3A This is a schematic plan view of a region of the semiconductor die 700 after the formation of the front-side first line layer metal interconnect structure (81, 181) according to an embodiment of the present disclosure. Figure 3B It is along Figure 3A The vertical cross-sectional view of the vertical plane B-B'. Figure 3C It is along Figure 3B A vertical cross-sectional view of the semiconductor die region in the vertical plane C-C'.

[0077] Reference Figures 3A to 3C A front dielectric layer 60 and a front metal interconnect structure 80 may be formed on the front side of the substrate 1000. During the formation of the front dielectric layer 60 and the front metal interconnect structure 80, the substrate 1000 may include a semiconductor material layer 28 and an optional first carrier wafer 411. Each front dielectric layer 60 may include a corresponding dielectric material, such as undoped silicate glass, doped silicate glass, porous or non-porous organosilicon glass, dielectric oxide, silicon nitride, silicon carbonitride, or combinations thereof, and may optionally include an etch stop layer, a diffusion barrier layer, or an adhesion promoter layer between successive dielectric layers.

[0078] According to one aspect of this disclosure, the front metal interconnect structure 80 includes a front global source power supply voltage grid structure 180 extending through the memory array region 100 and the peripheral connection region 200. Specifically, a first subset of the front metal interconnect structures 80 electrically connected to the first source / drain component 381 constitutes the front global source power supply voltage grid structure 180, while a second subset not electrically connected to the first source / drain component 381 does not belong to the front global source power supply voltage grid structure 180. Therefore, although all components of the front global source power supply voltage grid structure 180 are front metal interconnect structures 80, the subset of front metal interconnect structures 80 not electrically connected to the first source / drain component 381 is not a component of the front global source power supply voltage grid structure 180.

[0079] The front dielectric layer 60 and the front metal interconnect structure 80 can be formed layer by layer from bottom to top. For example, the front dielectric layer 60 may include a front contact level dielectric layer 6C, a front local interconnect level dielectric layer 6L, a front local interconnect via level dielectric layer 6D, a front first line level dielectric layer 61, and a dielectric layer for forming... Figure 3A and Figure 3B The additional dielectric material layer is formed subsequently after the processing steps of the structure shown. The front local interconnect layer dielectric material layer 6L, the front local interconnect via layer dielectric material layer 6D, and the front first line layer dielectric material layer 61 can be collectively referred to as the front first interconnect layer dielectric material layer (6L, 6D, 61). The front metal interconnect structure 80 may include front contact via structures (8C1, 8C2, 8C3, 8C4, 8C5, 18C), front local interconnect line layer metal lines (8L, 18L), front local interconnect via layer metal via structures (8D, 18D), front first line layer metal lines, and materials used to form... Figure 3A and Figure 3B The additional front-side metal interconnect structure is formed after the fabrication process steps of the structure.

[0080] It should be noted that the lateral extensions of the front local interconnect layer metal lines (8L, 18L) and the front first line layer metal lines have been arbitrarily modified to represent the various electrical connections provided in the front local interconnect layer metal lines, the front local interconnect via layer metal via structures, the front first line layer metal lines, and the additional front metal interconnect structures. The actual lateral extensions of the front local interconnect layer metal lines and the front first line layer metal lines are not shown. Typically, the lateral extension directions of adjacent metal lines are perpendicular to each other.

[0081] The subset of front contact via structures in memory array region 100 includes front source / drain contact via structure 8C1, front source / drain contact via structure 8C2, front source / drain contact via structure 8C3, front source / drain contact via structure 8C4, and front source / drain contact via structure 8C5. The front source / drain contact via structure 8C1, front source / drain contact via structure 8C2, front source / drain contact via structure 8C3, front source / drain contact via structure 8C4, and front source / drain contact via structure 8C5 may include a first front source / drain contact via structure 8C1 containing a first source / drain component 381, a second front source / drain contact via structure 8C2 containing a second source / drain component 382, ​​a third front source / drain contact via structure 8C3 containing a third source / drain component 383, a fourth front source / drain contact via structure 8C4 containing a fourth source / drain component 384, and a fifth front source / drain contact via structure 8C5 containing a fifth source / drain component 385. A subset of the front-side contact via structures (8C1, 8C2, 8C3, 8C4, 8C5, 18C) in the peripheral connection region 200 includes the peripheral contact via structure 18C that contacts the doped semiconductor material portion 37. The peripheral contact via structure 18C can constitute a first component of the front-side global source power supply voltage grid structure 180. The first front-side source / drain contact via structure 8C1 can constitute a second component of the front-side global source power supply voltage grid structure 180.

[0082] The front contact via structures (8C1, 8C2, 8C3, 8C4, 8C5, 18C) are formed by etching the front contact via cavity and filling it with at least one conductive material (e.g., at least one metal filler material). The front contact via cavity is formed through the front contact level dielectric material layer 6C, the gate dielectric material layer 6G, and the etch stop layer 29 to expose the top surfaces of the source / drain component 38 and the doped semiconductor material portion 37. The physically exposed portions of the source / drain component 38 and the doped semiconductor material portion 37 may have concave sections that are vertically recessed relative to a horizontal plane (including the top surface of the front contact level dielectric material layer 6C). At least one metal filler material is deposited in the front contact via cavity, and excess portions of the at least one metal filler material are removed above the horizontal plane including the top surface of the front contact level dielectric material layer 6C. At least one conductive material is deposited simultaneously in the back contact via cavity along with the deposition in the via cavity. The remaining portion of at least one conductive material in the back-side contact via cavity comprises a back-side contact via structure. At least one metal filler material may comprise a combination of a metal barrier pad material and a metal filler material. Therefore, each front-side contact via structure (8C1, 8C2, 8C3, 8C4, 8C5, 18C) may comprise a corresponding combination of a metal barrier pad 8A and a metal filler material portion 8B. The front-side contact via structure (8C1, 8C2, 8C3, 8C4, 8C5, 18C) may have a flat top surface coplanar with the top surface of the front contact level dielectric material layer 6C, and a convex bottom surface projecting downwards from a horizontal surface (containing the bottom surface of the front contact level dielectric material layer 6C).

[0083] Front local interconnect layer metal lines (8L, 18L) can be formed in the front local interconnect layer dielectric material layer 6L on the corresponding subsets of the front contact via structures (8C1, 8C2, 8C3, 8C4, 8C5, 18C). When forming the complete structure of the front global source power supply voltage grid structure 180, the subset of front local interconnect layer metal lines (8L, 18L) of the component configured as the front global source power supply voltage grid structure 180 is referred to as the local interconnect source connection layer metal line 18L. The subset of front local interconnect layer metal lines (8L, 18L) of the component configured as not of the front global source power supply voltage grid structure 180 is referred to as the front local interconnect layer metal line 8L.

[0084] Front local interconnect via-level via structures (8D, 18D) can be formed in a front local interconnect via-level dielectric material layer 6D, which is located on a corresponding subset of the front local interconnect metal lines (8L, 18L). When forming the complete structure of the front global source power supply voltage grid structure 180, the subset of front local interconnect via-level via structures (8D, 18D) of the component configured as the front global source power supply voltage grid structure 180 is referred to as the interconnect via-level source connection local via structure 18D. The subset of front local interconnect via-level via structures (8D, 18D) of the component configured as not part of the front global source power supply voltage grid structure 180 is referred to as the front local interconnect via-level via structure 8D.

[0085] The front-side first line layer metal lines (81, 181) can be formed in the front-side first line layer dielectric material layer 61, which is located on the corresponding subsets of the front-side local interconnect via layer via structures (8D, 18D). When forming the complete structure of the front-side global source power voltage grid structure 180, the subset of the front-side first line layer metal lines (81, 181) of the component configured as the front-side global source power voltage grid structure 180 is referred to as the first line layer source connection metal lines 181. The subset of the front-side first line layer metal lines (81, 181) of the component configured as not of the front-side global source power voltage grid structure 180 is referred to as the front-side first line layer interconnect metal lines 81.

[0086] The front interconnect wiring pattern of the front first line level metal lines (81, 181) can be selected based on the SRAM cell design, therefore, various configurations are possible in the plan view. The approximate area of ​​the front first line level metal lines (81, 181) is... Figure 3A The plan view is shown. It should be understood that the actual pattern area occupied by the front first line level metal lines (81, 181) in the memory array region 100 is smaller than the area marked "81 / 181 (80 / 180)" and can have various shapes depending on the design of the SRAM cells in the plan view. Each front first line level interconnect metal line 81 is a component of the front metal interconnect structure 80, but not a component of the front global source power supply voltage grid structure 180. Each first line level source connection metal line 181 is a component of the front metal interconnect structure 80 and a component of the front global source power supply voltage grid structure 180. The front first line level metal lines (81, 181) can typically extend along a first horizontal direction hd1. The first line level source connection metal lines 181 can extend laterally along the first horizontal direction hd1 and can be formed in the peripheral connection region 200 and completely outside the memory array region 100.

[0087] Typically, a first subset of the source / drain components 38 of the first field-effect transistor T1 (e.g., the first source / drain component 381) constitutes a component of the front-side global source power supply voltage grid structure 180, and therefore, they are electrically connected to the front-side global source power supply voltage grid structure 180. A second subset of the source / drain components 38 of the first field-effect transistor T1 (e.g., the third source / drain component 383) can be configured to be electrically isolated from the front-side global source power supply voltage grid structure 180.

[0088] A peripheral contact via structure 18C can be formed in the peripheral connection region 200 simultaneously with the formation of the front contact via structures (8C1, 8C2, 8C3, 8C4, 8C5). The front contact via structures (8C1, 8C2, 8C3, 8C4, 8C5) may include a first front source / drain contact via structure 8C1, a second front source / drain contact via structure 8C2, a third front source / drain contact via structure 8C3, a fourth front source / drain contact via structure 8C4, and a fifth front source / drain contact via structure 8C5. The peripheral contact via structure 18C is formed on the top surface of the peripheral semiconductor material portion 37.

[0089] A first front-side source / drain contact via structure 8C1 is formed on the first source / source component 381. The first front-side source / drain contact via structure 8C1 includes components of the front-side global source power supply voltage grid structure 180, which will be completed in subsequent processing steps. A second front-side source / drain contact via structure 8C2 is formed on the second source / source component 382. The second front-side source / drain contact via structure 8C2 is electrically isolated from the front-side global source power supply voltage grid structure 180.

[0090] Figure 4A This is a schematic plan view of a region of the semiconductor die 700 after the formation of the front-side second line-level metal interconnect structure, according to an embodiment of the present disclosure. Figure 4B It is along Figure 4A The vertical cross-sectional view of the vertical plane B-B'.

[0091] Reference Figure 4A and Figure 4BThe front dielectric layer 60 may include a front second interconnect layer dielectric material 62. Front first via layer via structures (91, 191) and front second line layer metal lines (82, 182) may be formed in the front second interconnect layer dielectric material layer 62. In one embodiment, the front first via layer via structures (91, 191) and front second line layer metal lines (82, 182) may be formed as an integrated line and via structure using a dual damascene process. In this embodiment, each front first via layer via structure (91, 191) overlaps with one of the corresponding front second line layer metal lines (82, 182). The front second interconnect layer dielectric material layer 62 may include a single dielectric material layer laterally surrounding the integrated line and via structure. Alternatively, the front first via layer via structures (91, 191) and front second line layer metal lines (82, 182) may be formed sequentially using two single damascene processes. In this embodiment, the front second interconnect layer dielectric material layer 62 may include a stack of dielectric material laterally surrounding the front first via layer via structure (91, 191) and additional dielectric material laterally surrounding the front second line layer metal lines (82, 182).

[0092] The front-side first via-level via structures (91, 191) can be formed on corresponding subsets of the front-side first line-level metal lines (81, 181). When forming the complete structure of the front-side global source power supply voltage grid structure 180, the subset of the front-side first via-level via structures (91, 191) of the components configured as the front-side global source power supply voltage grid structure 180 is referred to as the first via-level source connection via structure 191. The subset of the front-side first via-level via structures (91, 191) of the components configured as components not of the front-side global source power supply voltage grid structure 180 is referred to as the front-side interconnect first via-level via structure 91.

[0093] The front-side second-level line metal lines (82, 182) can be formed on corresponding subsets of the front-side first-level via structure (91, 191). When forming the complete structure of the front-side global source power supply voltage grid structure 180, the subset of the front-side second-level line metal lines (82, 182) of the component configured as the front-side global source power supply voltage grid structure 180 can be referred to as the second-level line-level source connection metal lines 182. The subset of the front-side second-level line metal lines (82, 182) of the component configured as not of the front-side global source power supply voltage grid structure 180 can be referred to as the front-side second-level line-level interconnect metal lines 82.

[0094] The routing pattern of the front second-level interconnect metal line 82 can be selected based on the SRAM cell design, thus allowing for various configurations in the plan view. The approximate area of ​​the front second-level interconnect metal line 82 is... Figure 4A The plan view is shown. It should be understood that the actual pattern of the front second line level interconnect metal lines 82 in the memory array region 100 occupies an area smaller than the area marked "82 (80)" and can have various shapes depending on the design of the SRAM cells in the plan view. Each front second line level interconnect metal line 82 is a component of the front metal interconnect structure 80, but not a component of the front global source power supply voltage grid structure 180. Each second line level source connection metal line 182 is a component of the front metal interconnect structure 80 and a component of the front global source power supply voltage grid structure 180. The front second line level metal lines (82, 182) can generally extend along the second horizontal direction hd2. The second line level source connection metal lines 182 can extend laterally along the second horizontal direction hd2 and extend laterally through the memory array region 100 and into at least one peripheral connection region 200. In an example providing two peripheral connection regions 200, the second line-level source connection metal line 182 may extend laterally between and into the two peripheral connection regions 200 along a second horizontal direction hd2. In one embodiment, a first subset of the front second line-level metal lines (82, 182), including the second line-level source connection metal line 182, may be formed on the front first line-level metal lines (81, 181) and extend laterally from the peripheral connection region 200 through the memory array region 100 along the second horizontal direction hd2.

[0095] The combination of all metal portions electrically connected to the peripheral contact via structure 18C constitutes the front-side global source power supply voltage grid structure 180. The front-side global source power supply voltage grid structure 180 extends through the memory array region 100 and the peripheral connection region 200 in a plan view and is electrically connected to all electrical nodes of the SRAM cells configured to be electrically biased under the global source power supply voltage. Specifically, the front-side global source power supply voltage grid structure 180 is electrically connected to the first source / drain component 381 via the first front-side source / drain contact via structure 8C1. Furthermore, the front-side global source power supply voltage grid structure 180 can be electrically connected to the substrate 1000 via the first front-side source / drain contact via structure 8C1, which contacts a first subset of the source / drain components 38 (i.e., the first source / drain components 381).

[0096] A subset of the dielectric material layers embedded in the front-side global source power supply voltage grid structure 180 is referred to herein as lower-level dielectric materials (6C, 6L, 6D, 61, 62). In one embodiment, the lower-level dielectric material layers (6C, 6L, 6D, 61, 62) include a front contact-level dielectric material layer 6C, a front local interconnect-level dielectric material layer 6L, a front local interconnect via-level dielectric material layer 6D, a front-side first line-level dielectric material layer 61, and a front-side second interconnect-level dielectric material layer 62. Various metal interconnect structures formed in the lower-level dielectric material layers (6C, 6L, 6D, 61, 62) are referred to herein as lower-level metal interconnect structures, which include lower-level line-level metal wire structures and lower-level metal via structures.

[0097] The front-side global source power supply voltage grid structure 180 includes a subset of lower-level metal line structures formed in multiple metal interconnect layers and interconnected with each other through a subset of lower-level metal via structures. For example, the front-side global source power supply voltage grid structure 180 may include a peripheral contact via structure 18C contacting the doped semiconductor material portion 37, a first front-side source / drain contact via structure 8C1 contacting the first source / drain component 381, a local interconnect source connection layer metal line 18L, an interconnect drain connection local via structure 18D, a first line layer source connection metal line 181, a first via layer source connection via structure 191, and a second line layer source connection metal line 182. The first line layer source connection metal line 181 is a first subset of the front-side first line layer metal lines (81, 181), extends laterally along the first horizontal direction hd1, and is formed in the peripheral connection region 200 and outside the memory array region 100. The second line level source connection metal line 182 is a first subset of the front second line level metal lines (82, 182), formed on the front first line level metal lines (81, 181), and extends laterally from the peripheral connection area 200 through the memory array area 100 along the second horizontal direction hd2.

[0098] Figure 5A This is a schematic plan view of the region of the first configuration of the semiconductor die 700 after the formation of the front third line level metal interconnect structure 83, according to an embodiment of the present disclosure. Figure 5B It is along Figure 5A The vertical cross-sectional view of the vertical plane B-B'.

[0099] Reference Figure 5A and Figure 5BThe front dielectric layer 60 may include a front third interconnect layer dielectric material 63. A front second via layer via structure (including a second via layer interconnect via structure 92) and a front third line layer metal line (including a third line layer interconnect metal line 83) may be formed in the front third interconnect layer dielectric material layer 63. In a first configuration of the semiconductor die 700, the vertical extent of the front global source power supply voltage grid structure 180 in the memory array region 100 may be limited below the horizontal plane (including the top surface of the front second interconnect layer dielectric material layer 62). In other words, in the region of the memory array region 100, the front global source power supply voltage grid structure 180 does not protrude above the horizontal plane including the top surface of the front second interconnect layer dielectric material layer 62. In one embodiment, within the region of the peripheral connection region 200, a subset of the front-side second via-level via structure and the front-side third line-level metal lines may be connected to the front-side global source power supply voltage grid structure 180 to provide electrical bias of the front-side global source power supply voltage grid structure 180 from the front. In an alternative embodiment, in an instance where the front-side global source power supply voltage grid structure 180 is configured to be electrically biased from the back side (i.e., from below the source region layer 30), the front-side global source power supply voltage grid structure 180 may not be connected to any conductive structure above the top surface of the front-side second interconnect level dielectric material layer 62 in the memory array region 100 and the peripheral connection region 200.

[0100] In one embodiment, the second via-level interconnect via structure 92 and the third line-level interconnect metal line 83 can be formed as an integrated wire and via structure using a dual damascene process. In this embodiment, each second via-level interconnect via structure 92 can overlap with one of the corresponding third line-level interconnect metal lines 83. The front third interconnect level dielectric layer 63 can include a single dielectric layer laterally surrounding the integrated wire and via structure. Alternatively, the second via-level interconnect via structure 92 and the third line-level interconnect metal line 83 can be formed sequentially using two single damascene processes. In this embodiment, the front third interconnect level dielectric layer 63 can include a stack of dielectric layers laterally surrounding the second via-level interconnect via structure 92 and additional dielectric layers laterally surrounding the third line-level interconnect metal line 83.

[0101] The second via-level interconnect structure 92 can be formed on a corresponding subset of the front-side second-level interconnect metal lines 82. The third-level interconnect metal lines 83 can be formed on a corresponding subset of the second via-level interconnect structure 92. In one embodiment, the wiring pattern of the third-level interconnect metal lines 83 can be selected based on the design of the SRAM cells; therefore, various configurations are possible in the plan view. The approximate area of ​​the third-level interconnect metal lines 83 is... Figure 5AThe plan view is shown. It should be understood that the actual pattern of the third line level interconnect metal line 83 occupies an area smaller than the area marked "83 / (80)" and can have various shapes depending on the design of the SRAM cell in the plan view. Each third line level interconnect metal line 83 is a component of the front metal interconnect structure 80, but not a component of the front-side global source power supply voltage grid structure 180.

[0102] The front-side global source power supply voltage grid structure 180 includes: at least one first global source voltage metal line (including a first line-level source connection metal line 181) extending laterally along a first horizontal direction hd1 and located in the peripheral connection region 200 and outside the memory array region 100; and a second global source voltage metal line (including a second line-level source connection metal line 182) extending laterally along a second horizontal direction hd2 above the first global source voltage metal line 181 and extending above the peripheral connection region 200 and the memory array region 100. Figure 5A and Figure 5B In the first configuration shown, the front third line level metal lines (including the third line level interconnect metal lines 83) extend along the first horizontal direction hd1 above the front second line level metal lines 82 and 182, so that the front global source power supply voltage grid structure 180 is electrically isolated from each front third line level metal line.

[0103] Figure 6A This is a schematic plan view of the region of the second configuration of the semiconductor die 700 after the formation of the front third line level metal interconnect structure, according to an embodiment of the present disclosure. Figure 6B It is along Figure 6A The vertical cross-sectional view of the vertical plane B-B'.

[0104] Reference Figure 6A and Figure 6B By forming an additional front-side metal interconnect structure, the second configuration of the semiconductor die 700 can be achieved from... Figure 4A and Figure 4BThe first configuration of the semiconductor die shown is derived. The front dielectric layer 60 may include a front third interconnect level dielectric layer 63. Front second via level via structures (92, 192) and front third line level metal lines (83, 183) may be formed in the front third interconnect level dielectric layer 63. In one embodiment, the front second via level via structures (92, 192) and front third line level metal lines (83, 183) may be formed as integrated line and via structures using a dual damascene process. In this embodiment, each front second via level via structure (92, 192) is overlaid with a corresponding one in the front third line level metal lines (83, 183). The front third interconnect level dielectric layer 63 may include a single dielectric layer laterally surrounding the integrated line and via structures. Alternatively, two single-damascene processes can be used to sequentially form the front second via-level via structures (92, 192) and the front third interconnect-level metal lines (83, 183). In this embodiment, the front third interconnect-level dielectric layer 63 may include a stack of dielectric material layers laterally surrounding the front second via-level via structures (92, 192) and additional dielectric material layers laterally surrounding the front third interconnect-level metal lines (83, 183).

[0105] The front-side second via-level via structures (92, 192) can be formed on corresponding subsets of the front-side second line-level metal lines (82, 182). When forming the complete structure of the front-side global source power supply voltage grid structure 180, the subset of the front-side second via-level via structures (92, 192) of the component configured as the front-side global source power supply voltage grid structure 180 is referred to as the second via-level source connection via structure 192. The subset of the front-side second via-level via structures (92, 192) of the component configured as a component not configured as the front-side global source power supply voltage grid structure 180 is referred to as the second via-level interconnect via structure 92.

[0106] The front third-level line metal lines (83, 183) can be formed on corresponding subsets of the front second-level via structures (92, 192). When forming the complete structure of the front global source power supply voltage grid structure 180, the subset of the front third-level line metal lines (83, 183) of the component configured as the front global source power supply voltage grid structure 180 is referred to as the third-level line-level source connection metal lines 183. The subset of the front third-level line metal lines (83, 183) of the component configured as not in the front global source power supply voltage grid structure 180 is referred to as the third-level line-level interconnect metal lines 83.

[0107] The wiring pattern of the third-level interconnect metal line 83 can be selected based on the design of the SRAM cell, and therefore, various configurations can be available in the plan view. Figure 6AThe plan view illustrates an example of a third-level interconnect metal line 83. In this example, the third-level source connection metal line 183 extends laterally along a first horizontal direction hd1. The third-level source connection metal line 183 and the third-level interconnect metal line 83 are staggered along a second horizontal direction hd2.

[0108] Each of the third-level interconnect metal lines 83 is a component of the front-side metal interconnect structure 80, but not a component of the front-side global source power supply voltage grid structure 180. Each of the third-level source connection metal lines 183 is a component of the front-side metal interconnect structure 80 and the front-side global source power supply voltage grid structure 180. The third-level source connection metal lines 183 may be entirely located within the memory array region 100, or they may be located within the memory array region 100 and at least one peripheral connection region 200.

[0109] The front-side global source power supply voltage grid structure 180 includes: at least one first global source voltage metal line (including a first line-level source connection metal line 181) extending laterally along a first horizontal direction hd1 and located in the peripheral connection area 200 and outside the memory array area 100; and a second global source voltage metal line (including a second line-level source connection metal line 182) extending laterally along a second horizontal direction hd2 above the first global source voltage metal line 181 and extending above the peripheral connection area 200 and the memory array area 100. In a second configuration, the front-side third line-level metal lines (83, 183) extend along the first horizontal direction hd1 above the front-side second line-level metal lines (82, 182).

[0110] In one embodiment, for each static random access memory (SRAM) cell located in the corresponding cell UC, the first field-effect transistor T1 includes a pair of pull-down (PD) transistors for the SRAM cell, the second field-effect transistor T2 includes a pair of pull-up (PU) transistors for the SRAM cell, and the third field-effect transistor T3 includes a pair of transmission gate (PG) transistors for the SRAM cell. The front-side global source power supply voltage grid structure 180 includes a first subset of the front-side third line-level metal lines (83, 183). The second subset of the front-side third line-level metal lines (83, 183) includes the front-side third line-level metal interconnect structure 83, which includes word lines of the SRAM cell. In one embodiment, the word lines of the SRAM cell may intersect with the first subset of the front-side third line-level metal lines (83, 183) along a second horizontal direction hd2.

[0111] Figure 7AThis is a schematic plan view of the region of the second configuration of the semiconductor die 700 after the formation of the front fourth line level metal interconnect structure, according to an embodiment of the present disclosure. Figure 7B It is along Figure 7A The vertical cross-sectional view of the vertical plane B-B'.

[0112] The front dielectric layer 60 may include a front fourth interconnect level dielectric layer 64. A front third via level via structure (including a third via level interconnect via structure 93) and a front fourth line level metal line (including a front fourth line level interconnect metal line 84) may be formed in the front fourth interconnect level dielectric layer 64. In a second configuration of the semiconductor die 700, in the memory array region 100, the vertical extent of the front global source power supply voltage grid structure 180 may be limited below the horizontal plane including the top surface of the front third interconnect level dielectric layer 63. In other words, in the region of the memory array region 100, the front global source power supply voltage grid structure 180 does not protrude above the horizontal plane including the top surface of the front third interconnect level dielectric layer 63. In one embodiment, a subset of the front-side third via-level via structure and the front-side fourth line-level metal lines can be connected to the front-side global source power supply voltage grid structure 180 within the region of the peripheral connection region 200 to provide electrical bias for the front-side global source power supply voltage grid structure 180 from the front. In an alternative embodiment, if the front-side global source power supply voltage grid structure 180 is configured to be electrically biased from the back side (i.e., from below the source region layer 30), then the front-side global source power supply voltage grid structure 180 may not be connected to any conductive structure above the top surface of the front-side third interconnect layer dielectric material layer 63 in the memory array region 100 and the peripheral connection region 200.

[0113] In one embodiment, the third via-level interconnect via structure 93 and the front fourth line-level interconnect metal line 84 can be formed as an integrated wire and via structure using a dual damascene process. In this embodiment, each third via-level interconnect via structure 93 is overlaid with a corresponding one of the front fourth line-level interconnect metal lines 84. The front fourth interconnect level dielectric layer 64 can include a single dielectric layer laterally surrounding the integrated wire and via structure. Alternatively, the third via-level interconnect via structure 93 and the front fourth line-level interconnect metal line 84 can be formed sequentially using two single damascene processes. In this embodiment, the front fourth interconnect level dielectric layer 64 can include a stack of dielectric material laterally surrounding the third via-level interconnect via structure 93 and additional dielectric material laterally surrounding the front fourth line-level interconnect metal line 84.

[0114] The third via-level interconnect structure 93 can be formed on a corresponding subset of the third line-level interconnect metal lines 83. The front-side fourth line-level interconnect metal lines 84 can be formed on a corresponding subset of the third via-level interconnect structure 93. In one embodiment, the wiring pattern of the front-side fourth line-level interconnect metal lines 84 can be selected based on the design of the SRAM cells; therefore, various configurations are possible in the plan view. The approximate area of ​​the front-side fourth line-level interconnect metal lines 84 is... Figure 7A The plan view is shown. It should be understood that the actual pattern of the front fourth line level interconnect metal lines 84 occupies an area smaller than the area marked "84 / (80)" and can have various shapes depending on the design of the SRAM cells in the plan view. Each of the front fourth line level interconnect metal lines 84 is a component of the front metal interconnect structure 80, but not a component of the front global source power supply voltage grid structure 180.

[0115] The front-side global source voltage grid structure 180 includes: at least one first global source voltage metal line (including a first line-level source connection metal line 181) extending laterally along a first horizontal direction hd1 and located in the peripheral connection region 200 and outside the memory array region 100; and a second global source voltage metal line (including a second line-level source connection metal line 182) extending laterally along a second horizontal direction hd2 above the first global source voltage metal line 181 and extending above the peripheral connection region 200 and the memory array region 100. In a second configuration, the front-side global source voltage grid structure 180 further includes a third global source voltage metal line (including a third line-level source connection metal line 183) extending laterally along the first horizontal direction hd1 and extending into the memory array region 100, and optionally extending over the peripheral connection region 200.

[0116] Figure 8A This is a schematic plan view of the region of the third configuration of the semiconductor die 700 after the formation of the front fourth line level metal interconnect structure, according to an embodiment of the present disclosure. Figure 8B It is along Figure 8A The vertical cross-sectional view of the vertical plane B-B'. Figure 8C This is an enlarged view of the metal lines that can be formed on a semiconductor die.

[0117] Reference Figures 8A-8C By forming an additional front-side metal interconnect structure, the third configuration of the semiconductor die 700 can be achieved from... Figure 6A and Figure 6BDerived from the second configuration of the semiconductor die shown. Specifically, the front dielectric layer 60 may include a front fourth interconnect level dielectric 64. Front third via level via structures (93, 193) and front fourth line level metal lines (84, 184) may be formed in the front fourth interconnect level dielectric layer 64. In one embodiment, the front third via level via structures (93, 193) and front fourth line level metal lines (84, 184) may be formed as integrated line and via structures using a dual damascene process. In this embodiment, each front third via level via structure (93, 193) is overlaid with a corresponding one in the front fourth line level metal lines (84, 184). The front fourth interconnect level dielectric layer 64 may include a single dielectric layer laterally surrounding the integrated line and via structures. Alternatively, two single damascene processes can be used to sequentially form the front third via layer via structures (93, 193) and the front fourth interconnect layer metal lines (84, 184). In this embodiment, the front fourth interconnect layer dielectric material layer 64 may include a stack of dielectric material laterally surrounding the front third via layer via structures (93, 193) and additional dielectric material laterally surrounding the front fourth interconnect layer metal lines (84, 184).

[0118] The front third via-level via structures (93, 193) can be formed on corresponding subsets of the front third line-level metal lines (83, 183). When forming the complete structure of the front global source power supply voltage grid structure 180, the subset of the front third via-level via structures (93, 193) of the component configured as the front global source power supply voltage grid structure 180 is referred to as the third via-level source connection via structure 193. The subset of the front third via-level via structures (93, 193) of the component configured as a component not configured as the front global source power supply voltage grid structure 180 is referred to as the third via-level interconnect via structure 93.

[0119] The front fourth line level metal lines (84, 184) can be formed on corresponding subsets of the front third via level via structures (93, 193). When forming the complete structure of the front global source power supply voltage grid structure 180, the subset of the front fourth line level metal lines (84, 184) of the component configured as the front global source power supply voltage grid structure 180 is referred to as the front fourth line level global source voltage metal lines 184. The subset of the front fourth line level metal lines (84, 184) of the component configured as not part of the front global source power supply voltage grid structure 180 is referred to as the front fourth line level interconnect metal lines 84.

[0120] The wiring pattern of the front fourth line level interconnect metal line 84 can be selected based on the design of the SRAM cell, and therefore, various configurations can be available in the plan view. Figure 8A The plan view shows an example of the front fourth line level interconnect metal line 84. In this example, the front fourth line level global source voltage metal line 184 extends laterally along the second horizontal direction hd2, and the front fourth line level interconnect metal line 84 extends laterally along the second horizontal direction hd2. The front fourth line level global source voltage metal line 184 and the front fourth line level interconnect metal line 84 are arranged alternately along the first horizontal direction hd1.

[0121] In one embodiment, various interconnect metal structures 80 can be formed by an inlay process, wherein a wire cavity is formed in a corresponding dielectric layer and then filled with a combination of a barrier layer 80A and a metal filler 80B to form the interconnect metal structure 80. Removal of excess portions of the barrier layer 80A and the metal filler 80B can be achieved by a chemical mechanical polishing (CMP) process, which bends the top surface 80T along a direction different from the length direction.

[0122] Typically, semiconductor devices can be formed on a substrate within a device region. Interconnect structures can be formed on the device region. The interconnect structures include interconnect layers, each interconnect layer including metal lines disposed in a dielectric layer. In one embodiment, the metal lines extend along their respective length directions. At least one and / or each metal line may include a bent end. For example, at least one and / or each metal line may include a bent top surface 80T (e.g., a width direction) along a direction different from the length direction. Figure 8C (As shown in the diagram). In one embodiment, at least one metal line includes a barrier layer 80A adjoining the dielectric layer and a fill metal 80B separated from the dielectric layer by the barrier layer 80A. The conductivity of the barrier layer 80A is less than that of the fill metal 80B. Typically, metal lines located in vertically adjacent layers extend laterally along different horizontal directions, which can be perpendicular to each other. Therefore, in instances where two metal lines are perpendicularly spaced between an odd number of layers, the two metal lines of the interconnect layer can extend in different directions.

[0123] Each front-side fourth-level interconnect metal line 84 is a component of the front-side metal interconnect structure 80, but not a component of the front-side global source power supply voltage grid structure 180. Each of the front-side fourth-level global source voltage metal lines 184 is a component of the front-side metal interconnect structure 80 and the front-side global source power supply voltage grid structure 180. The front-side fourth-level global source voltage metal lines 184 may be entirely located within the memory array region 100, or they may be located within the memory array region 100 and at least one peripheral connection region 200.

[0124] The front-side global source power supply voltage grid structure 180 includes: at least one first global source voltage metal line (including a first line-level source connection metal line 181) which extends laterally along a first horizontal direction hd1 and is located in the peripheral connection area 200 and outside the memory array area 100; and a second global source voltage metal line (including a second line-level source connection metal line 182) which extends laterally along a second horizontal direction hd2 above the first global source voltage metal line 181 and extends above the peripheral connection area 200 and the memory array area 100. In the third configuration, the front global source power supply voltage grid structure 180 further includes: a third global source voltage metal line (including a third line-level source connection metal line 183), which extends laterally along the first horizontal direction hd1 and extends into the memory array region 100, and optionally extends above the peripheral connection region 200; and a fourth global source voltage metal line (including a front fourth line-level global source voltage metal line 184), which extends laterally along the second horizontal direction hd2, extends into the memory array region 100, and optionally extends above the peripheral connection region 200.

[0125] In one embodiment, for each static random access memory (SRAM) cell located in the corresponding cell UC, the first field-effect transistor T1 includes a pair of pull-down (PD) transistors for the SRAM cell, the second field-effect transistor T2 includes a pair of pull-up (PU) transistors for the SRAM cell, and the third field-effect transistor T3 includes a pair of transmission gate (PG) transistors for the SRAM cell. The front-side global source power supply voltage grid structure 180 includes a first subset of the front-side third line level metal lines (83, 183). The second subset of the front-side third line level metal lines (83, 183) includes the front-side third line level metal interconnect structure 83, which includes word lines of the SRAM cell. In one embodiment, the word lines of the SRAM cell may be staggered with the first subset of the front-side third line level metal lines (83, 183) along the second horizontal direction hd2.

[0126] According to various embodiments of this disclosure, a front-side global source power voltage grid structure 180 extending through the memory array region 100 and the peripheral connection region 200 can be formed. The front-side global source power voltage grid structure 180 is electrically connected to the substrate 1000 via a front-side source / drain contact via structure 8C1 contacting a first subset of the source / drain components 38 (i.e., the first source / drain component 381) and via a peripheral contact via structure 18C. The front-side global source power voltage grid structure 180 includes a subset of lower-level metal line structures formed in a plurality of metal interconnect layers (e.g., a layer of front-side first-level metal lines (81, 181), a front-side second-level metal lines, and optionally a layer of front-side third-level metal lines and / or a layer of front-side fourth-level metal lines). The subsets of lower-level metal line structures are interconnected with each other via subsets of lower-level metal via structures.

[0127] Typically, as referenced Figure 5A and Figure 5B , Figure 7A and Figure 7B as well as Figure 8A and Figure 8B Provided in the various configurations described, the front-side global source power voltage grid structure 180 includes a first charge rebalancing path that extends vertically from the topmost component of the front-side global source power voltage grid structure 180 to the bottommost component of the front-side global source power voltage grid structure 180. As used herein, a charge rebalancing path refers to a conductive path that, during any process generating localized charges, redistributes these localized charges within a volume containing the path and any conductive coupling elements (including, for example, chucks or ground peripheries) to achieve charge balance between connected devices and mitigate charge-induced damage, such as plasma-induced damage (PID). As will be described in detail below, during any plasma-based process (such as a plasma-based etching process), the first charge rebalancing path can be used to discharge accumulated charges to the substrate 1000 or a chuck disposed on the substrate 1000.

[0128] In one embodiment, the front-side global source power supply voltage grid structure 180 includes a first front-side source / drain contact via structure 8C1, and a subset of the first charge rebalancing paths includes the first front-side source / drain contact via structure 8C1. A peripheral contact via structure 18C is formed on a patterned semiconductor material portion of the semiconductor material layer 28. A subset of the first charge rebalancing paths includes the peripheral contact via structure 18C.

[0129] A first subset (e.g., first source / source component 381) of the source / drain components 38 of the first field-effect transistor T1 is electrically connected to the front-side global source power supply voltage grid structure 180. A second subset (e.g., third source / source component 383) of the source / drain components 38 of the first field-effect transistor T1 is electrically isolated from the front-side global source power supply voltage grid structure 180.

[0130] The peripheral contact via structure 18C in the peripheral connection area 200 is formed simultaneously with the formation of the first front source / drain contact via structure 8C1, the second front source / drain contact via structure 8C2, the third front source / drain contact via structure 8C3, the fourth front source / drain contact via structure 8C4, and the fifth front source / drain contact via structure 8C5.

[0131] A front-side global source power supply voltage grid structure 180 is formed in two or more front-side interconnect layers, including a front-side local interconnect layer (if present), a front-side first interconnect layer (i.e., the layer of the front-side first line-level dielectric material layer 61), and a front-side second interconnect layer (i.e., the layer of the front-side second line-level dielectric material layer 62). The front-side global source power supply voltage grid structure 180 includes (18C, 8C1, 18L, 18D, 181, 191, 182). The front-side global source power supply voltage grid structure 180 extends from the memory array region 100 into the peripheral connection region 200 to form a continuous global source power supply voltage distribution network connecting the global source power supply voltage nodes of the memory array region 100 and the peripheral connection region 200. The front-side global source power supply voltage grid structure 180 reduces the power supply / ground resistance of the individual transistors in the memory array region 100 and the peripheral connection region 200. The cross-cell connections within the memory array region 100 are provided by a combination of front metal interconnect structures in the front local interconnect layer, the front first interconnect layer, and the front second interconnect layer to improve lateral conductivity and minimize local voltage differences.

[0132] During the fabrication of interconnect layers above the second interconnect layer, a plasma-based etching process can be used to pattern the front-side third interconnect layer dielectric material layer 63 and the front-side fourth interconnect layer dielectric material layer 64, as well as the third line layer interconnect metal lines 83 and the front-side fourth line layer interconnect metal lines 84. The plasma-based etching process may generate charge imbalances or undesirable voltage stresses, thereby causing plasma-induced damage in sensitive components of the static random access memory cell. During this plasma-based etching process, the front-side global source power supply voltage grid structure 180 (including 18C, 8C1, 18L, 18D, 181, 191, 182) provides a low-resistance charge rebalancing path between the etched regions in the upper dielectric layer and the substrate 1000, thereby mitigating plasma-induced charge damage. Therefore, a set of components of the front-side global source power supply voltage grid structure 180 located in or below the second interconnect layer can be used as a first charge rebalancing path during the structure patterning of the third interconnect layer or above. The front-side global source power supply voltage grid structure 180 equalizes the potential on these regions and provides charge balance during plasma-based etching processes to mitigate plasma-induced damage.

[0133] The configuration of the front-side global source voltage grid structure 180 can be selected to include or exclude the addition of higher interconnect layers above the front-side second interconnect layer to further reduce resistance. Excluding the front-side interconnect layer can increase the word line width, thereby improving switching speed. The area occupied by the peripheral contact via structure 18C can be reduced to decrease the total area of ​​the combination of memory array region 100 and peripheral connection region 200 by approximately 0.8%-1%. Alternatively, the area occupied by the peripheral contact via structure 18C can be increased to reduce the resistance between the front-side global source voltage grid structure 180 and the subsequently formed back-side global source voltage grid structure.

[0134] Figure 9 This is a vertical cross-sectional view of a plasma-based etching apparatus 2000 including a substrate 1000 during a plasma-based etching process according to an embodiment of the present disclosure. Figure 10 This is a vertical cross-sectional view of the region of the semiconductor die 700 after the formation of the upper-level dielectric material layer (63, 64, 60U), the upper-level metal interconnect structure (83, 84, 80U), and the front bonding pad 88, according to an embodiment of the present disclosure.

[0135] Common Reference Figure 9 and Figure 10By using material deposition and material patterning processes, upper-level metal interconnect structures (83, 84, 80U) formed within upper-level dielectric material layers (63, 64, 60U) can be fabricated on the front-side global source power supply voltage grid structure 180. The material patterning process can include at least one plasma-based etching process, which can be a variety of plasma-based etching processes. As used herein, a plasma-based etching process refers to a material removal process in which reactive substances generated in a plasma react with one or more materials of the device being processed to transfer a pattern from an overlying patterned mask layer to an underlying material layer. Such plasma-based etching processes can include anisotropic dielectric etching processes that remove dielectric material from unmasked areas of the upper-level dielectric material layers (63, 64, 60U) and anisotropic metal etching processes that remove metal material from unmasked areas of the upper-level metal interconnect structures (83, 84, 80U).

[0136] During the formation of the upper-level metal interconnect structure (83, 84, 80U) and the upper-level dielectric material layer (63, 64, 60U), the substrate 1000 may include, for example: Figure 8B and Figure 10 The combination shown includes the source region layer 30, the semiconductor material layer 28, and the first carrier wafer 411, or may include, for example, Figure 9 The diagram shows a combination containing a source layer 30 and a semiconductor material layer 28. The upper-level metal interconnect structures (83, 84, 80U) may include a front-side third-level metal interconnect structure 83 and / or a front-side fourth-level metal interconnect structure 84, and include a higher-level metal interconnect structure 80U (which includes a front-side i-th level metal interconnect structure, where the integer i can be any value in the range of 5 to 20 or greater). The upper-level dielectric material layers (63, 64, 60U) may optionally include a front-side third-interconnect-level dielectric material layer 63 and / or a front-side fourth-interconnect-level dielectric material layer 64, and include a front-side j-th interconnect-level dielectric layer 60U, where the integer j can be any value in the range of 5 to 20 or greater.

[0137] The higher-level metal interconnect structure 80U (where the integer i can be any value in the range of 5 to 20 or greater) comprises a subset of the metal interconnect structures 80 covering the fourth metal interconnect level. The higher-level metal interconnect structure 80U may include higher-level metal lines (86, 186) and higher-level via structures (96, 196). The dielectric material layer embedded in the higher-level metal interconnect structure 80U is referred to as the higher-level dielectric material layer 60U.

[0138] Higher-level metal lines (86, 186) can be formed in the corresponding wiring layers within the higher-level dielectric material layer 60U. A subset of the higher-level metal lines (86, 186) electrically connected to components below the front-side global source power supply voltage grid structure 180 is referred to as higher-level source connection metal lines 186 and is an additional component of the front-side global source power supply voltage grid structure 180. A subset of the higher-level metal lines (86, 186) configured as components not belonging to the front-side global source power supply voltage grid structure 180 is referred to as higher-level interconnect structure 86.

[0139] Higher-level via structures (96, 196) can be formed in corresponding via layers within the higher-level dielectric material layer 60U. A subset of higher-level via structures (96, 196) electrically connected to components below the front-side global source power supply voltage grid structure 180 is referred to as higher-level source connection via structure 196 and is an additional component of the front-side global source power supply voltage grid structure 180. A subset of higher-level via structures (96, 196) configured as components not of the front-side global source power supply voltage grid structure 180 is referred to as higher-level interconnect via structure 96.

[0140] In the fabrication of the upper-level metal interconnect structures (83, 84, 80U) and the upper-level dielectric material layers (63, 64, 60U), each plasma-based etching process can be performed using a corresponding plasma etching apparatus 2000. The plasma-based etching apparatus 2000 includes a vacuum chamber 2100 with a sealable opening 2110 (e.g., a slit valve). A chuck 2200, such as an electrostatic chuck, is configured to receive a substrate 1000 thereon. A wafer including the substrate 1000 and the semiconductor devices and metal interconnect structures thereon can be loaded on top of the chuck 2200. The wafer may include reference... Figure 5A and Figure 5B , Figure 6A and Figure 6B or Figure 8A and Figure 8B The structure described.

[0141] The plasma-based etching apparatus 2000 may include a nozzle 2300 located above a chuck 2200. The nozzle 2300 is configured to dispense a process gas comprising at least one etchant gas into a plasma region 2310 disposed between the nozzle 2300 and the chuck 2200. A radio frequency (RF) signal generator 2400 may be included in the plasma-based etching apparatus 2000 and may be located above and / or below a vacuum chamber 2100.

[0142] Plasma-based etching processes can be performed by introducing one or more etchant gases into a plasma region 2310 through a nozzle 2300, igniting the plasma by coupling radio frequency power from an RF signal generator 2400 to the process region, and maintaining the plasma while removing material from unmasked areas of the target layer on the substrate 1000. In one embodiment, the plasma-based etching process includes an anisotropic dielectric etching process that removes dielectric material from one of the upper-level dielectric material layers (63, 64, 60U) in areas not covered by a patterned etch mask layer. In another embodiment, the plasma-based etching process includes an anisotropic metal etching process that removes metal material from a subset of the upper-level metal interconnect structures (83, 84, 80U) in areas not covered by a patterned etch mask layer. Plasma-based etching processes can be used to form via cavities extending vertically through one or more upper-level dielectric layers (63, 64, 60U), line cavities extending laterally within one or more upper-level dielectric layers (63, 64, 60U), or to pattern the metal layers of one of the upper-level metal interconnect structures (80U) into discrete wires. Plasma-based etching process parameters, including gas composition, pressure, RF power, and substrate temperature, can be selected to provide directional material removal while maintaining the integrity of the masked area.

[0143] During the plasma-based etching process, a front-side global source power supply voltage grid structure 180 provides a first charge rebalancing path between the etched region and the substrate 1000. The first charge rebalancing path includes conductive elements of the front-side global source power supply voltage grid structure 180, which are connected to the substrate via peripheral contact via structures 18C and patterned portions of the semiconductor material. During the plasma-based etching process, the first charge rebalancing path conducts accumulated charge from the etched region to the substrate. This conduction maintains the potential of the etched components near the substrate potential and prevents voltage differences between the dielectric layers of the static random access memory cells.

[0144] The operation of the first charge rebalancing path is based on a continuous conductive connection between the etched region and the substrate 1000. This connection allows charge to move from the region receiving net ion or electron flux in the plasma to a region at a fixed potential, thereby reducing or eliminating potential differences that could lead to dielectric breakdown or junction damage. The advantage of the first charge rebalancing paths is that they reduce the risk of plasma-induced charge damage without requiring additional protective layers or process steps. This protection is uniformly applied by the arrangement of the front-side global source power supply voltage grid structure 180 across the memory array region 100 and the peripheral connection region 200, thereby maintaining the electrical characteristics and reliability of the semiconductor devices on the substrate 1000.

[0145] Front bonding pads 88 may be formed on the top layer of the front-side metal interconnect structure. In one embodiment, front bonding pads 88 may include metal pads such as copper pads or aluminum pads, and may have a top surface in a horizontal plane (including the top surface of the topmost dielectric material selected from the upper dielectric material layers (63, 64, 60U)). A first subset of the metal pads (i.e., first pads 88) may be components of the front-side global source power voltage grid structure 180. A second subset of the metal pads may be components of the metal interconnect structure 80 and may be electrically isolated from the front-side global source power voltage grid structure 180. The height (i.e., thickness) of the front bonding pads 88 may range from 20 micrometers to 100 micrometers, but smaller or larger thicknesses may also be used.

[0146] Figure 11A This is a vertical cross-sectional view of the assembly of the first carrier wafer 411, the device wafers (30, 60, 80) and the second carrier wafer 421 according to an embodiment of the present disclosure. Figure 11B yes Figure 11A A magnified view of the component's area. (Refer to...) Figure 11A and Figure 11B The second carrier wafer 421 can be attached to the front surface of the device wafers (30, 60, 80) using adhesive layer 423. Adhesive layer 423 comprises a planarizable adhesive formulated to bond the two substrates and withstand planarization processes and post-bonding wet cleaning processes. In the example shown, adhesive layer 423 may comprise an electrically insulating planarizable adhesive having a volume resistivity greater than 1.0 x 10⁻⁶ at 25°C. 12 The adhesive layer has a glass transition temperature (Tg) above 200°C and is chemically compatible with post-bonding wet cleaning and chemical mechanical planarization (CMP). In other embodiments, the adhesive layer 423 is conductive or anisotropically conductive. The adhesive layer 423 is planarizable to obtain a top surface coplanar with the top surface of the previous bonding pad 88 and is chemically compatible with post-bonding cleaning agents.

[0147] In one embodiment, the material of the adhesive layer 423 may be applied to the top surface of the device wafers (30, 60, 80) and may be planarized such that the top surface of the adhesive layer 423 and the front bonding pad 88 (i.e., the metal pad) are coplanar. The adhesive layer 423 may be planarized mechanically or self-planarized. The adhesive layer 423 laterally surrounds the front metal pad 88. In one embodiment, the adhesive layer 423 may contact the sidewall of the front bonding pad 88. In one embodiment, the top surface of the front bonding pad 88 may contact the planar surface of the second carrier wafer 421. In this embodiment, a subset of the metal pads belonging to the front global source power supply voltage grid structure 180 (i.e., the front bonding pad 88) is electrically connected to the second carrier wafer 421. In one embodiment, the second carrier wafer 421 may include a semiconductor material or a conductive material such that a conductive path extends from the first source / drain component 381 to the second carrier wafer 421. In one embodiment, the second carrier wafer 421 comprises a conductive material or doped silicon with a room temperature resistivity of less than 10 Ω·cm (e.g., a room temperature resistivity in the range of 0.001 Ω·cm to 1 Ω·cm), thereby providing a conductive path from the first source / drain component 381 to the second carrier wafer 421. In another embodiment, the second carrier wafer 421 comprises materials with a room temperature resistivity of less than 1 × 10⁻⁶ Ω·cm. -5 Metal or metal stacks with a density of Ω·cm.

[0148] The device wafers (30, 60, 80) include a source region layer 30, a front dielectric material layer 60, and a front metal interconnect structure 80. The second carrier wafer 421 may include any material that can provide mechanical support to the device wafer during subsequent processing steps. In one embodiment, the second carrier wafer 421 may include a semiconductor or conductive material and may be attached to the device wafers (30, 60, 80) by a second adhesive layer (not shown) providing sufficient conductivity, such that the front bonding pads 88 and the front-side global source power supply voltage grid structure 180 are electrically connected to the second carrier wafer 421.

[0149] Figure 12 This is a vertical cross-sectional view of the assembly after the interconnect structure is fabricated on the front side, the first carrier wafer 411 is removed from the device wafers (30, 60, 80), and the semiconductor material layer 28 is removed, according to an embodiment of this disclosure. (Refer to...) Figure 12 For example, by deactivating the first adhesive layer 413, the first carrier wafer 411 can be separated from the device wafers (30, 60, 80). Alternatively, if the substrate includes, for example... Figure 9The semiconductor material layer 28 shown can be removed by, for example, grinding, polishing, at least one anisotropic etching process and / or at least one isotropic etching process. Typically, the substrate 1000 can be thinned from the back side by removing a portion of material located on the back side of the substrate 1000. After the separation / removal operation, a flat back side is formed on the back side of the active region. In some embodiments, forming a planar back side includes one or more of mechanical grinding, lapping, chemical mechanical polishing, and wet or dry etching to reduce morphology and subsurface damage and prepare the back side for subsequent dielectric deposition and patterning.

[0150] The planar back side may or may not include the back side containing the source region layer 30. In the illustrated embodiment, the planar back side includes the back side containing the source region layer 30. In this embodiment, the back side of the source / drain component 38, as well as the back side of the isolation component 31 and the peripheral semiconductor material portion 37, may be physically exposed. In an alternative embodiment described below, the planar back side may not include the back side containing the source region layer 30. In this embodiment, the planar back side may include the back side of the remaining portion of the semiconductor material layer 28. However, alternatively, if a semiconductor-on-insulator (SIA) substrate is used instead of the combination of the first carrier wafer 411, the first adhesive layer 413, and the semiconductor material layer 28, the bulk substrate layer within the SIA substrate can be removed, such that the planar back side can be the bottom surface of the insulating layer within the SIA substrate. In this embodiment, the semiconductor material layer 28 corresponds to the SIA layer within the SIA substrate (i.e., the top semiconductor layer), and in the processing steps described below, the insulating layer of the SIA substrate can be used as a back side contact level dielectric layer. Generally, after fabricating the interconnect structure, a planar back side can be formed on the back side of the active region by removing at least a back side portion of the substrate (e.g., an equivalent portion of the first carrier wafer 411 or an alternative embodiment of the substrate).

[0151] Figure 13 This is a vertical cross-sectional view of a region of the semiconductor die in a device wafer (30, 60, 80) after the removal of semiconductor material layer 28, according to an embodiment of the present disclosure. (Refer to...) Figure 13 Any additional material portion below the source region layer 30 can be removed. For example, a chemical mechanical polishing process can be performed to remove the semiconductor material layer 28 from below the source region layer 30. According to one aspect of this disclosure, at least one material of the substrate 1000 can be removed from the back side of the substrate 1000 to expose the back side of the source region layer 30 in which transistors (T1, T2, T3) are present. In other words, the back side portion of the substrate 1000 can be completely or partially removed to expose the back side of the source region layer 30. The back side surfaces of the doped semiconductor material portion 37, the source / drain component 38, and the isolation component 31 can be physically exposed.

[0152] Figure 14 This is a vertical cross-sectional view of a region of the semiconductor die 700 after the deposition of the back-side contact level dielectric layer 11, according to an embodiment of the present disclosure. (Refer to...) Figure 14 The back-side contact layer dielectric layer 11 includes an interconnect layer dielectric (ILD) material, such as undoped silicate glass, doped silicate glass, silicon nitride, or porous or non-porous organosilicon glass. The thickness of the back-side contact layer dielectric layer 11 can range from 30 nm to 300 nm, for example, 100 nm to 200 nm, but smaller or larger thicknesses are also possible. The back-side contact layer dielectric layer 11 is one of the back-side dielectric material layers 10 formed on the back side containing the source region layer 30.

[0153] Figure 15A This is a perspective plan view of a region of the semiconductor die 700 after the formation of the through-hole cavity 17, according to an embodiment of the present disclosure. Figure 15B It is along Figure 15A A vertical cross-sectional view of the region of semiconductor die 700 in the vertical plane B-B'. Figure 15C This is a vertical cross-sectional view of a plasma-based etching apparatus containing a substrate during a first back-side plasma-based etching process for forming a through-hole cavity 17, according to an embodiment of the present disclosure.

[0154] Reference Figures 15A to 15C The combination of device wafers (30, 60, 80) and a second carrier wafer 421 is inverted, and a first back-side photoresist layer 117 can be applied to the physically exposed back side of the back-side contact level dielectric layer 11. The first back-side photoresist layer 117 can be photolithographically patterned to form openings in regions of peripheral region semiconductor nanosheets 36. In one embodiment, the openings in the first back-side photoresist layer 117 can extend over the central portions of multiple peripheral region semiconductor nanosheets within a cluster of peripheral region semiconductor nanosheets 36. In one embodiment, each cluster of peripheral region semiconductor nanosheets 36 can be laterally aligned along a second horizontal direction hd2, and the lateral extent of the overlay openings in the first back-side photoresist layer 117 along the second horizontal direction can be larger than the corresponding cluster of peripheral region semiconductor nanosheets 36. Figures 15A-15C In the configuration, the patterned first back-side photoresist layer 117 covers at least one material layer (e.g., back-side contact level dielectric layer 11) and an active region containing the source region layer 30.

[0155] An assembly comprising interconnect structures (e.g., upper dielectric material layers 63, 64, 60U and upper metal interconnect structures (83, 84, 80U)), an active region within a source region layer 30, at least one material layer (e.g., a back-side contact layer dielectric layer 11), and a patterned first back-side photoresist layer 117 is disposed on a chuck 2200 of a plasma-based etching apparatus 2000. The assembly is oriented such that a front-side global source power supply voltage grid structure 180 is electrically connected to the chuck 2200, and the patterned photoresist layer 117 covers at least one material layer and the active region. A first back-side anisotropic etching process can then be performed to pass the opening pattern in the first back-side photoresist layer 117 through the back-side contact layer dielectric layer 11, the isolation member 31, and the unmasked portions of the peripheral semiconductor material portion 37 and the peripheral region semiconductor nanosheet 36. During the first back-side anisotropic etching process, the unmasked lower portion of the front contact layer dielectric material layer 6C can be removed in parallel. A through-hole cavity 17 is formed in the volume in which the material of the back contact layer dielectric layer 11, the isolation member 31, the peripheral semiconductor material portion 37, the peripheral region semiconductor nanosheet 36, and the front contact layer dielectric material layer 6C is removed.

[0156] In one embodiment, the first back-side anisotropic etching process may have an etching chemical that is selective to the material of the peripheral contact via structure 18C. In this embodiment, the lower portion of the convex bottom surface and sidewalls of the peripheral contact via structure 18C may be physically exposed to the feedthrough via cavity 17. During the first back-side anisotropic etching process, the peripheral contact via structure 18C (as a first component of the front-side global source power supply voltage grid structure 180) is electrically connected to the chuck 2200 and collects localized charges generated in the region adjacent to the first source / drain components, and conducts these charges to the chuck 2200. The first back-side photoresist layer 117 may then be removed, for example, by ashing.

[0157] According to one aspect of this disclosure, the first back-side anisotropic etching process may include a plasma-based etching process, such as reactive ion etching. In this embodiment, during the first back-side anisotropic etching process, a front-side global source power supply voltage grid structure 180 and upper-level metal interconnect structures (83, 84, 80U) provide a second charge rebalancing path for the chuck 2200 of the plasma-based etching apparatus 2000. Etching is performed while the first source / drain components are electrically connected to the carrier wafer via the front-side global source power supply voltage grid structure 180. In one embodiment, a front bonding pad 88 may be electrically connected to a second carrier wafer 421, which may be a semiconductor or a conductor, and may contact the chuck 2200 of the plasma-based etching apparatus 2000.

[0158] According to one aspect of this disclosure, a through-hole cavity 17 is formed through a back-side contact-level dielectric layer 11 and a source-containing layer 30, such that a first component of a front-side global source power voltage grid structure 180 is exposed to the through-hole cavity 17. In one embodiment, the first component of the front-side global source power voltage grid structure 180 exposed to the through-hole cavity 17 includes a peripheral contact via structure 18C.

[0159] Typically, the via cavity 17 can be formed by applying and patterning a first back-side photoresist layer 117 on the back-side contact layer dielectric layer 11, and by etching portions of the back-side contact layer dielectric layer 11, the source region layer 30, and the bottommost lower-level dielectric material layer (such as the front contact layer dielectric material layer 6C) that are not masked by the first back-side photoresist layer 117. In one embodiment, the bottom surface of the peripheral contact via structure 18C is exposed to the via cavity 17 due to a first back-side anisotropic etching process that passes through at least one material layer (e.g., the back-side contact layer dielectric layer 11). In another embodiment, the via cavity 17 is formed through portions of the back-side contact layer dielectric layer 11, the peripheral semiconductor material portion 37, and the isolation member 31, such that the bottom surface of the peripheral contact via structure 18C is exposed to the via cavity 17.

[0160] Figure 16A This is a perspective plan view of the semiconductor die region after the back-side contact via cavity 19 is formed, according to an embodiment of the present disclosure. Figure 16B During the formation of the back-side contact via cavity 19, after the first step of the back-side anisotropic etching process, along... Figure 16A A vertical cross-sectional view of the semiconductor die region in the vertical plane B-B'. Figure 16C This is a vertical cross-sectional view of a plasma etching apparatus containing a substrate during a second back-side plasma etching process for forming a back-side contact via cavity 19 according to an embodiment of the present disclosure. Figure 16D After the second step of the back-side anisotropic etching process for forming the back-side contact via cavity 19, along... Figure 16A A vertical cross-sectional view of the semiconductor die region in the vertical plane B-B'. Figure 16E Following the second step of the back-side anisotropic etching process that forms the back-side contact via cavity 19, the alternative configuration region of the semiconductor die is along... Figure 16A The vertical cross-sectional view of the vertical plane B-B'.

[0161] Reference Figures 16A-16CThe combination of device wafers (30, 60, 80) and a second carrier wafer 421 serves as substrate 1000'. Substrate 1000' is inverted, and a second back-side photoresist layer 119 can be applied to the physically exposed back-side surface of the back-side contact level dielectric layer 11. The second back-side photoresist layer 119 can be photolithographically patterned to form openings in the region of the first source / drain component 381. The openings in the second back-side photoresist layer 119 may overlap regionally with the first front-side source / drain contact via structure 8C1.

[0162] In completing and Figures 15A to 15C After the corresponding processing, the structure is removed from the first plasma processing chamber, a second back-side photoresist layer 119 is applied and patterned, and then the structure is placed in a new plasma-based processing chamber. In the new chamber, the substrate is configured as follows: an assembly is disposed on a chuck 2200 in a plasma-based etching apparatus 2000, the assembly including an interconnect structure, an active region, at least one material layer and a patterned photoresist layer, and its orientation such that a front-side global source power supply voltage grid structure 180 is electrically connected to the chuck 2200, and the patterned photoresist layer 119 covers at least one material layer and the active region.

[0163] With the components oriented in this manner, a second back-side anisotropic etching process is performed to pass the opening pattern in the second back-side photoresist layer 119 through a portion of the back-side contact-level dielectric layer 11. A back-side contact via cavity 19 is formed in the volume of material removed from the back-side contact-level dielectric layer 11, exposing the back side of the first source / drain component 381 by performing a back-side anisotropic etching process that passes through at least one material layer to form the back-side contact via cavity 19. Etching is performed while the first source / drain component 381 is electrically connected to the carrier wafer 421 via the front-side global source power supply voltage grid structure 180. During the back-side anisotropic etching process, local charges generated in the region adjacent to the first source / drain component 381 flow to the chuck 2200, and the peripheral contact via structure 18C and the patterned portions of the semiconductor material (e.g., peripheral semiconductor material portions 37) are electrically connected to the chuck 2200 to provide peripheral connectivity. In one embodiment, the front bonding pad 88 may be electrically connected to a second carrier wafer 421, which may be a semiconductor or a conductor, and may contact the chuck 2200 of a plasma-based etching apparatus 2000.

[0164] Typically, the back-side contact via 19 can be formed by applying and patterning a second back-side photoresist layer 119 on the back-side contact level dielectric layer 11, and by etching the portion of the back-side contact level dielectric layer 11 not masked by the second back-side photoresist layer 119. In one embodiment, the back-side contact via 19 is formed through a portion of the back-side contact level dielectric layer 11, such that the bottom surface of the first source / drain component 381 is exposed to the back-side contact via 19. In another embodiment, a timed over-etch interval is performed after the initial exposure of the first source / drain component 281 while maintaining the electrical connection of the first source / drain component 381 to the carrier wafer 421 through the front-side global source power supply voltage grid structure 180. No back-side contact via structure or through-hole via structure is formed at this stage; only the back-side contact via 19 and through-hole via 17 exist.

[0165] Figure 16D and Figure 16E The second step of the back-side anisotropic etching process is shown. In one embodiment ( Figure 16D Each back-side contact via cavity 19 includes a truncated cone-shaped recess extending into the corresponding first source / drain component 381, such that the downwardly projecting portion of the first source / drain component 381 laterally surrounds the recess and exhibits a variable horizontal cross-sectional area that increases with the vertical distance toward the interconnect structure. In another embodiment ( Figure 16E Each back-side contact via cavity 19 includes a conical recess extending into a corresponding first source / drain component 381, the similar downwardly projecting geometry of which laterally surrounds the recess. The second etching step can be performed as a timed over-etch under tapering conditions, where directional ion-assisted removal and controlled sidewall passivation create a tapered surface within the back-side contact via cavity 19 while maintaining the conductive path through the front-side global source power supply voltage grid structure 180 to the chuck 2200.

[0166] In one embodiment, an etch chemical that increases the physical exposed surface of the source / drain component 38 can be used to provide improved contact between the source / drain component 38 and the subsequently formed back-side contact metallization. The increase in the physical exposed surface of the source / drain component 38 relative to its horizontal cross-sectional area can be achieved by using a plasma-based etch chemical that forms a tapered surface on the remaining portion of the source / drain component as the etching process proceeds. For example, directional ion-assisted anisotropic dry etching using fluorine- or halogen-containing chemicals in an inductively coupled plasma or reactive ion etching chamber is configured to establish a positive taper on the exposed silicon portion of the source / drain component 38, with angle α ranging from 45 to 85 degrees (measured from a horizontal surface, such as the top surface of the wafer). The sidewalls slope inward with increasing depth (i.e., toward the front bonding pad 88) such that, at a given etch depth, the bottom width is less than the top width. Anisotropic plasma etching includes simultaneous physical sputtering with accelerated ions, chemical etching with neutral particles, and in-situ formation and removal of sidewall passivation films. Process parameters are selected such that a controlled imbalance between these mechanisms produces a monotonic lateral retreat of the upper sidewall region at a rate greater than that of the lower sidewall region, thereby reducing the horizontal width with depth and forming a tapered profile without expanding the lithographically defined footprint. In one embodiment, a timed over-etch interval is performed after the initial exposure of the source / drain components 38 under tapering conditions to increase the area of ​​physically exposed three-dimensional surface available for subsequent metallization while maintaining the electrical and dimensional integrity of the device architecture.

[0167] In the first embodiment, a tapered sidewall between 80 and 85 degrees is created by fluorinated silicon etching, configured to maintain a predominantly vertical bottom etching while allowing limited lateral removal on the upper sidewall. In a non-limiting embodiment, a time-multiplexed Bosch process replaces the SF6 etch subcycle and C4F8 passivation subcycle with a reduced passivation duty cycle, moderate chamber pressure, and low plateau bias, allowing the directional ion energy to maintain the bottom opening while the thickness of the fluorocarbon passivation film on the sidewall remains sufficiently thin to allow incremental chemical etching near the part inlet, resulting in a small positive taper with increasing depth. In another embodiment, a continuous low-temperature SF6 / O2 plasma is operated at a chuck temperature below ambient temperature to reduce oxygen content and plateau bias operation, resulting in a stable and thin fluorinated oxide film on the sidewall, which is more easily removed at the top by scattering flux than at the bottom by directional ions. This maintains the verticality of the part bottom and produces a uniform taper in the 80-85 degree range. In both implementations, an over-etch interval is maintained after the source / drain component 38 is broken to establish a taper, while endpoint control suppresses slotting at the insulating interface.

[0168] In the second approach, a tapered sidewall between 70 and 80 degrees is created by intentionally adjusting passivation, pressure, and ion energy to increase the lateral component of material removal near the part inlet while maintaining the etching directionality at the bottom of the part. In one embodiment, the Bosch process is performed with a fixed or slowly decreasing plateau bias, monotonically reducing the passivation slope over the passivation sub-cycle time and monotonically increasing the total gas pressure over time. This results in a greater difference in sidewall removal near the top compared to the bottom due to the angular spreading of the reaction species and reduced sputter-cleaning, creating a deeper positive taper throughout the via depth. In another embodiment, under cryogenic conditions and with a lower oxygen ratio, the cryogenic SF6 / O2 process operates at a higher chuck temperature while maintaining a low bias, resulting in a thinner passivation film and enhanced lateral chemical penetration to a higher height on the sidewalls, causing the cross-sectional width to decrease measurably with depth. In both implementations, the upper part of the lateral removal bias component is further utilized with aspect ratio-dependent transmission, masking selectivity is maintained by using a hard mask resistant to selected chemicals, and endpoint sequencing includes reducing bias near the insulating stop to maintain the tapered geometry while preventing foot phenomena.

[0169] In the third approach, tapered sidewalls between 45 and 70 degrees are created through dry etching embodiments that increase the lateral material removal of the material, with the process selection determined by the desired etching depth and critical dimension. For embodiments where the exposed silicon thickness is limited to a few micrometers or less, continuous halogen plasma (e.g., HBr / Cl2 / O2 or SF6 / O2) operates at rising pressure with a low plateau bias and controlled sidewall passivation reduction. This allows for a chemical etching process at the top while polymer-mediated protection at the lower sidewalls is preserved relative to the higher sidewalls, resulting in a sidewall angle α approaching 60 degrees in a single continuous dry etching while maintaining shielding fidelity. As the etching depth decreases and the lateral flux ratio increases, the angle can reach close to 45 degrees. For embodiments where the back-side vias extend substantially along the bulk silicon, a multi-step shaping process is used to achieve a first anisotropic silicon etching depth, followed by periodic in-situ sidewall deposition and anisotropic removal, or spacer-assisted trimming that selectively removes material from higher sidewall portions during each cycle, or by biased lateral removal using collimating or Faraday-cage fixtures without controlled-angle incidence ion exposure through wet chemicals. In each embodiment, process parameters are selected to maintain a bottom opening while lateral removal accumulates per cycle beyond the lower sidewalls, resulting in a net positive taper ranging from 45 to 70 degrees, with dimensional control suitable for subsequent metallization. In all third-option embodiments, charge, microloading, and roughness are managed through shielding selection, dummy pattern density control, and chamber pressure and bias adjustment to preserve device-safe sidewalls and uniform wafer-scale angles.

[0170] Typically, the contact resistance between a semiconductor element and a conductive element is inversely proportional to the contact area. In this embodiment, the contact resistance between the source / drain component 38 and the subsequently formed back-side metallization is inversely proportional to the physical exposed area of ​​the source / drain component 38, which exceeds the horizontal cross-sectional area, because the tapered sidewalls and contoured bottom provide additional three-dimensional surface area for the metallization; the disclosed range is 45 degrees to 85 degrees, and the three schemes described herein provide support for the contoured backside with tapered sidewalls to meet metallization and resistance targets. Anisotropic plasma etch conditions are maintained for a calibrated over-etch interval after the initial breakthrough of the source / drain component 38, during which a positive taper is formed without expanding the horizontal footprint defined by the mask. Endpoint control also includes bias and passivation adjustments near the insulating interface to suppress trenching while maintaining the desired taper. The same chamber and hard mask configuration are used in all schemes, the process window is selected according to the target taper angle and depth, and wafer-scale uniformity is maintained by controlling the angular flux distribution, passivation kinetics, and bias power.

[0171] Typically, in instances where the front-side global source power voltage grid structure does not provide charge rebalancing during anisotropic etching, extending the anisotropic etching process after the bottom surface of the source / drain component 38 is exposed will lead to localized charge accumulation in the source / drain component. According to one aspect of this disclosure, the front-side global source power voltage grid structure 180 provides continuous charge rebalancing and further extracts accumulated charge through direct contact with the second carrier wafer 421. Therefore, extending the duration of the anisotropic etching process provides a tapered profile for the physically exposed surface of the source / drain component 38 without compromising process yield.

[0172] Common Reference Figure 15A , Figure 15B and Figures 16A-16E The first back-side anisotropic etching process and the second back-side isotropic etching process may include plasma-based etching processes. During the back-side plasma-based etching process, a second charge rebalancing path is formed to provide a conductive discharge path from the etched back-side components to the substrate 1000'. The second charge rebalancing path includes a first source / drain component 381, a front-side global source power supply voltage grid structure 180, an upper-level metal interconnect structure (83, 84, 80U), and a second carrier wafer 421. The second charge rebalancing path extends continuously from the first source / drain component 381, through the conductive network of the front-side global source power supply voltage grid structure 180 and the upper-level metal interconnect structure, and reaches the second carrier wafer 421 maintained at a fixed potential.

[0173] During the back-side plasma-based etching process, a second charge rebalancing path conducts accumulated charge from the etched back-side components (e.g., through-hole cavity 17 and back-side contact via cavity 19) to the second carrier wafer 421 and chuck 2200. This conductivity mechanism maintains the potential of the etched back-side components near the potential of the second carrier wafer 421, preventing voltage differences between the isolation component 31 and other dielectric layers. Maintaining this potential balance reduces the risk of dielectric breakdown, junction leakage, or other plasma-induced charge damage in the static random access memory cells and peripheral circuitry.

[0174] The second charge rebalancing path operates by providing a continuous low-resistance conductive network from the back-side etched region to the second carrier wafer 421 during plasma exposure. This conductive network provides redistribution and neutralization of the charge generated by the ion and electron fluxes in the plasma. The arrangement of the first source / drain component 381, the front-side global source power supply voltage grid structure 180, the upper-level metal interconnect structure (83, 84, 80U), and the second carrier wafer 421 provides uniform discharge capability for the memory array region 100 and the peripheral connection region 200 during two back-side plasma-based etching stages. This uniform discharge capability maintains the design electrical performance and long-term reliability of the semiconductor devices on the substrate 1000'.

[0175] generally, Figure 15A and Figure 15B The processing steps and Figures 16A-16E The order of the processing steps can be reversed, as long as the feed through-hole cavity 17 and the back contact through-hole cavity 19 have the same structural features as described above.

[0176] Figure 17A This is a perspective plan view of a region of a semiconductor die 700 after the formation of the through-hole structure 21 and the back contact through-hole structure 22, according to an embodiment of the present disclosure. Figure 17B It is along Figure 17A A vertical cross-sectional view of the region of semiconductor die 700 in the vertical plane B-B'.

[0177] Reference Figure 17A and Figure 17B At least one conductive material may be deposited simultaneously in the through-hole cavity 17 and the back contact through-hole cavity 19. The at least one conductive material may comprise a combination of a metal barrier pad material (e.g., TiN, TaN, WN, and / or MoN) and a metal filler material (e.g., Ti, Ta, Mo, W, Cu, Ru, Co, etc.). Subsequently, portions of the at least one conductive material located outside the through-hole cavity 17 and the back contact through-hole cavity 19 are removed, for example, by chemical mechanical planarization. The remaining portion of the at least one conductive material comprises the through-hole structure 21 formed in the through-hole cavity 17 and the back contact through-hole structure 22 formed in the back contact through-hole cavity 19.

[0178] A through-hole structure 21 is formed in the through-hole cavity 17, passing through the back contact level dielectric layer 11 and the source region layer 30, and entering the bottommost lower-level dielectric material layer, such as the front contact level dielectric material layer 6C. The through-hole structure 21 can be formed directly on the bottom surface of the first component including the front global source power supply voltage grid structure 180 of the peripheral contact through-hole structure 18C. In one embodiment, the through-hole structure 21 can be formed on the bottom surface and the lower part of the sidewall of the peripheral contact through-hole structure 18C. The through-hole structure 21 and the back contact through-hole structure 22 are formed through the back contact level dielectric layer 11.

[0179] A through-hole structure 21 extends from the back side through the isolation member 31 to the peripheral contact via structure 18C of the front-side global source power supply voltage grid structure 180. A back-side contact via structure 22 is formed on the back surface of the first source / drain member 381 and extends vertically through the back-side contact level dielectric layer 11 to contact the first source / drain member 281. In one embodiment, after planarization, the flat horizontal bottom surface of the through-hole structure 21 is coplanar with the flat horizontal bottom surface of the back-side contact via structure 22. The front-side global source power supply voltage grid structure 180 includes the peripheral contact via structure 18C in contact with the through-hole structure 21. The through-hole structure 21 and the back-side contact via structure 22 are components of the back-side global source power supply voltage grid structure 120, which supports the power distribution function of the front-side global source power supply voltage grid structure 180 to provide a more stable global source power supply voltage to the semiconductor devices in the semiconductor die 700.

[0180] In one embodiment, the through-hole structure 21 includes a profiled top surface comprising a set of corresponding horizontal surface segments adjacent to a corresponding subset of the profiled surface segments of the peripheral contact via structure 18C. In one embodiment, each through-hole structure 21 may have a profiled top surface comprising a concave segment of the bottom surface of the peripheral contact via structure 18C, a vertical surface segment of the lower portion of the peripheral contact via structure 18C, and a horizontal surface segment of the flat bottom surface segment of the contact bottommost dielectric layer (e.g., the front contact layer dielectric 6C).

[0181] In one embodiment, the through-hole structure 21 has tapered sidewalls such that the lateral extent of the through-hole structure 21 at the back side of the isolation member 31 is greater than the lateral extent at the front side of the isolation member 31. In an embodiment consistent with the geometry of the back-side contact via cavity 19 described above, each back-side contact via structure 22 fills the corresponding back-side contact via cavity 19 and includes a tapered surface that contacts the back surface of the first source / drain member 381, the tapered surface being closer to the interconnect structure than the back surface of the second source / drain member. Typically, the back-side contact via structure 22 has a tapered surface that contacts the back surface of the first source / drain member 381. The tapered surface is closer to the horizontal plane including the top surface of the first field-effect transistor T1 and the second field-effect transistor T2 than the back surface of the second source / drain member 382.

[0182] In one embodiment, each back-side contact via structure 22 includes an inverted truncated cone portion disposed above a horizontal plane and a cylindrical portion disposed below the horizontal plane, the horizontal plane including the bottom surface of a second source / drain component (i.e., a source / drain component other than the first source / drain component 381), wherein the cone surface corresponds to an inclined upper sidewall section of the inverted truncated cone, the inclined upper sidewall being adjacent to a generally cylindrical lower sidewall section of the cylindrical portion. In one embodiment, a downwardly projecting portion of the first source / drain component 381 laterally surrounds the top of the back-side contact via structure 22 and exhibits a variable horizontal cross-sectional area that increases with the vertical distance from the horizontal plane including the bottom surface of the second source / drain component toward the interconnect structure. In one embodiment, a back-side global source power voltage grid structure 120 is disposed on the back side of the back-side contact via structure 22 and electrically connected to the front-side global source power voltage grid structure 180 via a feedthrough via structure 21 and the back-side contact via structure 22.

[0183] Figure 18 This is a schematic perspective view of a front-side global source power supply voltage grid structure 180, a feedthrough via structure 21, and a back-side contact via structure 22 having a first configuration, according to an embodiment of this disclosure. (Refer to...) Figure 18 References can be used Figure 5A and Figure 5B The first configuration of the front-side global source power supply voltage grid structure 180 is described to form a first configuration for the combination of the front-side global source power supply voltage grid structure 180, the through-hole structure 21, and the back-side contact through-hole structure 22. Two peripheral connection regions 200 may be laterally spaced from each other along a second horizontal direction hd2, with the memory array region 100 located between them. The memory array region 100 may include two boundaries extending laterally along a first horizontal direction hd1. Each boundary may be adjacent to a corresponding one of the two peripheral connection regions 200.

[0184] Field-effect transistors (T1, T2, T3) and back-side contact via structures 22 are located in the memory array region 100, and through-hole structures 21 are located in the peripheral connection region 200. A front-side global source voltage grid structure 180 extends through the memory array region 100 and the peripheral connection region 200. The through-hole structures 21 extend vertically through the back-side contact layer dielectric layer 11 and the isolation component 31, and contact the first component of the front-side global source voltage grid structure 180 (including the peripheral contact via structure 18C). In one embodiment, the through-hole structures 21 can be arranged in rows extending laterally along a first horizontal direction hd1 within each peripheral connection region 200. Each row of through-hole structures 21 can be electrically connected to a first global source voltage metal line 181.

[0185] In a first configuration for combining the front-side global source voltage grid structure 180, the through-hole structure 21, and the back-side contact via structure 22, the front-side global source voltage grid structure 180 is formed below a horizontal plane including the top surface of the front-side second interconnect layer dielectric material layer 62 within the region of the memory array region 100. In other words, within the region of the memory array region 100, the front-side global source voltage grid structure 180 does not protrude above the horizontal plane including the top surface of the front-side second interconnect layer dielectric material layer 62. In one embodiment, a subset of the front-side second via layer via structure and the front-side third line layer metal lines can be connected to the front-side global source voltage grid structure 180 within the region of the peripheral connection region 200 to provide electrical bias to the front-side global source voltage grid structure 180 from the front. In another embodiment, where the front global source power supply voltage grid structure 180 is configured to be electrically biased from the back side (i.e. from below the source region layer 30), the front global source power supply voltage grid structure 180 may not be connected to any conductive structure above the top surface of the front second interconnect layer dielectric material layer 62 in the memory array region 100 and the peripheral connection region 200.

[0186] The front-side global source power supply voltage grid structure 180 includes: at least one first global source voltage metal line (including a first line-level source connection metal line 181) which extends laterally along a first horizontal direction hd1 and is located in the peripheral connection area 200 and outside the memory array area 100; and a second global source voltage metal line (including a second line-level source connection metal line 182) which extends laterally along a second horizontal direction hd2 above the first global source voltage metal line 181 and extends above the peripheral connection area 200 and the memory array area 100.

[0187] Figure 19This is a schematic perspective view of a front-side global source power supply voltage grid structure 180, a feedthrough via structure 21, and a back-side contact via structure 22 having a second configuration according to an embodiment of this disclosure. (Refer to...) Figure 19 References can be used Figure 7A and Figure 7B The second configuration of the front-side global source power supply voltage grid structure 180 is described to form a second configuration for the combination of the front-side global source power supply voltage grid structure 180, the through-hole structure 21, and the back-side contact through-hole structure 22. Two peripheral connection regions 200 may be laterally spaced from each other along a second horizontal direction hd2, with the memory array region 100 located between them. The memory array region 100 may include two boundaries extending laterally along a first horizontal direction hd1. Each boundary may be adjacent to a corresponding one of the two peripheral connection regions 200.

[0188] Field-effect transistors (T1, T2, T3) and back-side contact via structures 22 are located in the memory array region 100, and through-hole structures 21 are located in the peripheral connection region 200. A front-side global source voltage grid structure 180 extends through the memory array region 100 and the peripheral connection region 200. The through-hole structures 21 extend vertically through the back-side contact level dielectric layer 11 and the isolation component 31, and contact the first component of the front-side global source voltage grid structure 180 (including the peripheral contact via structure 18C). In one embodiment, the through-hole structures 21 can be arranged in rows extending laterally along a first horizontal direction hd1 within each peripheral connection region 200. Each row of through-hole structures 21 can be electrically connected to a first global source voltage metal line 181.

[0189] In a second configuration of the combination of the front-side global source voltage grid structure 180, the through-hole structure 21, and the back-side contact via structure 22, the vertical range of the front-side global source voltage grid structure 180 in the memory array region 100 may be limited below the horizontal plane including the top surface of the third line level source interconnect metal line 183. In other words, in the region of the memory array region 100, the front-side global source voltage grid structure 180 does not protrude above the horizontal plane including the top surface of the front-side third interconnect level dielectric material layer 63. In one embodiment, a subset of the front-side third via level via structure and the front-side fourth line level metal line may be connected to the front-side global source voltage grid structure 180 in the region of the peripheral connection region 200 to provide electrical bias of the front-side global source voltage grid structure 180 from the front. In an alternative embodiment, if the front global source power supply voltage grid structure 180 is configured to be electrically biased from the back side (i.e. from below the source region layer 30), the front global source power supply voltage grid structure 180 may not be connected to any conductive structure above the top surface of the front third interconnect layer dielectric material layer 63 in the memory array region 100 and the peripheral connection region 200.

[0190] The front-side global source voltage grid structure 180 includes: at least one first global source voltage metal line (including a first line-level source connection metal line 181) extending laterally along a first horizontal direction hd1 and located in the peripheral connection region 200 and outside the memory array region 100; and a second global source voltage metal line (including a second line-level source connection metal line 182) extending laterally along a second horizontal direction hd2 above the first global source voltage metal line 181 and extending above the peripheral connection region 200 and the memory array region 100. In a second configuration, the front-side global source voltage grid structure 180 further includes a third global source voltage metal line (including a third line-level source connection metal line 183) extending laterally along the first horizontal direction hd1 and extending into the memory array region 100, and optionally extending over the peripheral connection region 200.

[0191] Figure 20 This is a schematic perspective view of a front-side global source power supply voltage grid structure 180, a feedthrough via structure 21, and a back-side contact via structure 22 having a third configuration according to an embodiment of this disclosure. (Refer to...) Figure 20 References can be used Figure 8A and Figure 8BThe third configuration of the described front-side global source power supply voltage grid structure 180 forms a third configuration for the combination of the front-side global source power supply voltage grid structure 180, the through-hole structure 21, and the back-side contact through-hole structure 22. Two peripheral connection regions 200 may be laterally spaced from each other along a second horizontal direction hd2, with the memory array region 100 located between them. The memory array region 100 may include two boundaries extending laterally along a first horizontal direction hd1. Each boundary may be adjacent to a corresponding one of the two peripheral connection regions 200.

[0192] Field-effect transistors (T1, T2, T3) and back-side contact via structures 22 are located in the memory array region 100, and through-hole structures 21 are located in the peripheral connection region 200. A front-side global source voltage grid structure 180 extends through the memory array region 200 and the peripheral connection region 200. The through-hole structures 21 extend vertically through the back-side contact layer dielectric layer 11 and the isolation component 31, and contact the first component of the front-side global source voltage grid structure 180 (including the peripheral contact via structure 18C). In one embodiment, the through-hole structures 21 can be arranged in rows extending laterally along a first horizontal direction hd1 within each peripheral connection region 200. Each row of through-hole structures 21 can be electrically connected to a first global source voltage metal line 181.

[0193] In a third configuration combining the front-side global source voltage grid structure 180, the feedthrough via structure 21, and the back-side contact via structure 22, the front-side fourth line level global source voltage metal line 184 (which is a subset of the front-side fourth line level metal lines (84, 184)) constitutes a component of the front-side global source voltage grid structure 180.

[0194] Each front-side fourth-level interconnect metal line 84 is a component of the front-side metal interconnect structure 80, but not a component of the front-side global source power supply voltage grid structure 180. Each of the front-side fourth-level global source voltage metal lines 184 is a component of the front-side metal interconnect structure 80 and the front-side global source power supply voltage grid structure 180. The front-side fourth-level global source voltage metal lines 184 may be entirely located within the memory array region 100, or they may be located within the memory array region 100 and at least one peripheral connection region 200.

[0195] The front-side global source power supply voltage grid structure 180 includes: at least one first global source voltage metal line (including a first line-level source connection metal line 181) which extends laterally along a first horizontal direction hd1 and is located in the peripheral connection area 200 and outside the memory array area 100; and a second global source voltage metal line (including a second line-level source connection metal line 182) which extends laterally along a second horizontal direction hd2 above the first global source voltage metal line 181 and extends above the peripheral connection area 200 and the memory array area 100. In the third configuration, the front global source power supply voltage grid structure 180 also includes a third global source voltage metal line (including a third line-level source connection metal line 183), which extends laterally along the first horizontal direction hd1 and extends into the memory array region 100, and optionally extends above the peripheral connection region 200, and a fourth global source voltage metal line (including a front fourth line-level global source temperature metal line 184), which extends laterally along the second horizontal direction hd2 and extends into the memory array region 100, and optionally extends above the peripheral connection region 200.

[0196] In one embodiment, for each static random access memory (SRAM) cell located in the corresponding cell UC, the first field-effect transistor T1 includes a pair of pull-down (PD) transistors for the SRAM cell, the second field-effect transistor T2 includes a pair of pull-up (PU) transistors for the SRAM cell, and the third field-effect transistor T3 includes a pair of transmission gate (PG) transistors for the SRAM cell. The front-side global source power supply voltage grid structure 180 includes a first subset of the front-side third line level metal lines (83, 183). The second subset of the front-side third line level metal lines (83, 183) includes the front-side third line level metal interconnect structure 83, which includes word lines of the SRAM cell. In one embodiment, the word lines of the SRAM cell may be staggered with the first subset of the front-side third line level metal lines (83, 183) along the second horizontal direction hd2.

[0197] Figure 21 This is a schematic perspective view of a front-side global source power supply voltage grid structure 180, a feedthrough via structure 21, and a back-side contact via structure 22 having a fourth configuration according to an embodiment of this disclosure. (Refer to...) Figure 21 By providing a single peripheral connection area 200 instead of two peripheral connection areas 200, it is possible to... Figure 18 , Figure 19 or Figure 20The first, second, or third configuration shown derives a fourth configuration for the combination of the front-side global source power supply voltage grid structure 180, the feedthrough via structure 21, and the back-side contact via structure 22. In this embodiment, the memory array region 100 includes a first boundary adjacent to the peripheral connection region 200 and parallel to the first horizontal direction hd1, and also includes a second boundary parallel to the first horizontal direction hd1 and laterally spaced from the peripheral connection region 200. The second boundary is laterally offset from the first boundary along the second horizontal direction hd2, and the offset of the farthest surface of the second line-level metal line from the first boundary along the second horizontal direction hd2 is less than the offset of the farthest surface of the second line-level metal line from the first boundary along the first horizontal direction hd1. Rows of feedthrough via structures 21 can be provided in the peripheral connection region 200. Typically, the amplitude of the ground bounce voltage increases with the distance along the second horizontal direction hd2 from the first line-level source connection metal line 181 located in the peripheral connection region 200. In one embodiment, an additional first line level source connection metal line 181 may be provided on the far side of the memory array region 100, away from the peripheral connection region 200.

[0198] Figure 22A This is a perspective plan view of a region of a semiconductor die 700 after the formation of a first back-side metal line, according to an embodiment of the present disclosure. Figure 22B It is along Figure 22A A vertical cross-sectional view of the region of semiconductor die 700 in the vertical plane B-B'. (Refer to...) Figure 22A and Figure 22B The back-side first interconnect level dielectric layer 12 can be deposited on the back side of the back-side contact level dielectric layer 11, the through-hole structure 21, and the back-side contact through-hole structure 22. The back-side first interconnect level dielectric layer 12 includes an interlayer dielectric (ILD) material, such as undoped silicate glass, doped silicate glass, silicon nitride, and / or porous or non-porous organosilicon glass, and may optionally include an etch-stop dielectric material layer. The thickness of the back-side first interconnect level dielectric layer 12 can range from 30 nm to 300 nm, for example, 100 nm to 200 nm, but smaller or larger thicknesses are also possible. The combination of the back-side first interconnect level dielectric layer 12 and the back-side contact level dielectric layer 11 is herein referred to as the back-side first interconnect level dielectric material layer (11, 12). The back-side first interconnect level dielectric layer 12 is another of the back-side dielectric material layers 10 formed on the back side containing the source region layer 30.

[0199] For example, by patterning the trenches therein, filling the trenches with at least one metallic material, and removing excess portions of at least one material from outside the trenches, a back-side first-level circuit layer metal line 24 can be formed in the back-side first-level circuit layer dielectric layer 12. The back-side first-level circuit layer metal line 24 can be formed on the back side of the through-hole structure 21 and the back-side contact via structure 22. The back-side first-level circuit layer metal line 24 is a component of the back-side global source power supply voltage grid structure 120.

[0200] In one embodiment, each back-side first-level wiring layer 24 may extend laterally along a second horizontal direction hd2. In one embodiment, each back-side first-level wiring layer 24 may be formed on a corresponding through-hole structure 21 and a corresponding plurality of back-side contact via structures 22 arranged along the second horizontal direction hd2. In this embodiment, each back-side first-level wiring layer 24 may provide a direct electrical connection between the corresponding through-hole structure 21 and the corresponding plurality of back-side contact via structures 22. Alternatively, the back-side first-level wiring layer 24 may be formed on the corresponding through-hole structure 21 or the corresponding plurality of back-side contact via structures 22, and subsequently formed back-side second-level wiring layer 24 may be used to electrically connect the through-hole structure 21 and the back-side contact via structure 22.

[0201] Typically, a combination of a back-side contact layer dielectric layer 11, a back-side contact via structure 22, and a first back-side global source voltage metal line 24 can be formed on the back side containing the source region layer 30. In one embodiment, the back-side contact via structure 22 is formed on the back-side surface of a first subset of transistors (T1, T2, T3) and is electrically connected to the first back-side global source voltage metal line 24 and the front-side global source power supply voltage grid structure 180. In another embodiment, the back-side contact via structure 22 is formed on the back-side surface of the first source / drain component 381 of the first field-effect transistor T1.

[0202] Figure 23A This is a perspective plan view of a region of a semiconductor die 700 after the formation of a second back-side metal line, according to an embodiment of the present disclosure. Figure 23B It is along Figure 23A A vertical cross-sectional view of the region of semiconductor die 700 in the vertical plane B-B'.

[0203] Reference Figure 23A and Figure 23BThe back-side second interconnect dielectric layer 13 can be deposited on the back side of the back-side first line layer dielectric layer 12 and the back-side first line layer metal line 24. The back-side second interconnect dielectric layer 13 includes an interlayer dielectric (ILD) material, such as undoped silicate glass, doped silicate glass, silicon nitride, and / or porous or non-porous organosilicon glass, and may optionally include an etch-stop dielectric layer. The thickness of the back-side second interconnect dielectric layer 13 can range from 100 nm to 500 nm, for example, 200 nm to 300 nm, but smaller or larger thicknesses can also be used. The back-side second interconnect dielectric layer 13 is another back-side dielectric material layer 10 formed on the back side containing the source region layer 30.

[0204] The back-side first via-layer metal via structure 25 and the back-side second circuit layer metal line 26 can be formed in the back-side second interconnect layer dielectric material layer 13. For example, a combination of photolithographic patterning steps and anisotropic etching steps can be used to form a dual damascene cavity in the back-side second interconnect layer dielectric material layer 13, and it can be partially filled with at least one metal filler material to form the back-side first via-layer metal via structure 25 and the back-side second circuit layer metal line 26. Alternatively, the back-side first via-layer metal via structure 25 can be first formed in the first element dielectric layer of the back-side second interconnect layer dielectric material layer 13, and then the back-side second circuit layer metal line 26 can be formed in the second element dielectric layer of the back-side second interconnect layer dielectric material layer 13. In this embodiment, a combination of two photolithographic patterning steps and two single damascene processes can be used to sequentially form the back-side first via-layer metal via structure 25 and the back-side second circuit layer metal line 26.

[0205] In one embodiment, at least one back-side plasma-based etching process can be used to pattern cavities for forming the back-side first via-level metal via structure 25 and the back-side second line-level metal line 26. In this embodiment, a charge rebalancing path including the front-side global source power supply voltage grid structure 180 can be used to transfer charge from the etched part to the substrate 1000' and the chuck 2200 of the plasma-based etching apparatus 2000.

[0206] In one embodiment, the back-side second line-level metal line 26 may extend laterally along a first horizontal direction hd1 in the memory array region 100 and the peripheral connection region 200. A back-side first via-level metal via structure 25 provides a vertical conductive path between the back-side second line-level metal line 26 and the back-side first line-level metal line 24. The combination of the back-side second line-level metal line 26, the back-side first via-level metal via structure 25, the back-side first line-level metal line 24, the feedthrough via structure 21, and the back-side contact via structure 22 includes a back-side global source power voltage grid structure 120. The back-side global source power voltage grid structure 120 is formed on the back side of the isolation member 31 and is electrically connected to the front-side global source power voltage grid structure 180 via the feedthrough via structure 21 and the first source / drain member 381.

[0207] A back-side global source power supply voltage grid structure 120 is formed on the back side of the isolation component 31. The back-side global source power supply voltage grid structure 120 includes a back-side contact via structure 22 that extends vertically through the back-side contact level dielectric layer 11 and contacts the back side of a first subset of the source / drain components 38 of the first field-effect transistor T1.

[0208] Subsequently, an additional back-side dielectric material layer 10 and an additional back-side metal interconnect structure can be formed on the back side of the back-side global source power supply voltage grid structure 120.

[0209] Figure 24 According to one embodiment of this disclosure, it includes an isolation component 31 (see...) Figure 23B A vertical cross-sectional view of a plasma-based etching apparatus performing a plasma-based etching process on the back side of isolation component 31. (Refer to...) Figure 24 The additional back-side dielectric material layer 10 and the additional back-side metal interconnect structure 20 can be formed using an additional back-side plasma-based etching process. In each of these back-side plasma-based etching processes, the combination of the back-side global source power supply voltage grid structure 120, the through-hole structure 21, and the front-side global source power supply voltage grid structure 180 provides a third charge rebalancing path to protect the semiconductor device in the semiconductor die 700.

[0210] The combination of the back-side global source voltage grid structure 120, the through-hole structure 21, and the front-side global source voltage grid structure 180 provides a third charge rebalancing path. This third charge rebalancing path extends vertically and laterally from the etched components in the additional back-side dielectric layer 10 or the additional back-side metal interconnect structure to the substrate 1000' and the chuck 2200 of the plasma-based etching apparatus 2000. The third charge rebalancing path includes a vertical conductive path through the through-hole structure 21 and the back-side contact via structure 22, and also includes a lateral conductive path through the back-side global source voltage grid structure 120 and the front-side global source voltage grid structure 180. The third charge rebalancing path provides multiple parallel conductive paths with low resistance, such that the charge accumulated in the etched region is discharged during the back-side plasma-based etching process performed after the formation of the back-side global source voltage grid structure 120.

[0211] The advantage of the third charge rebalancing path is that it maintains electrical connectivity between the back-side etched region and the substrate 1000' even when the intermediate conductive structure is partially separated by the back-side dielectric material layer 10 of the attachment. The third charge rebalancing path provides a low-resistance electrical connection between the back-side etched region and the substrate 1000' through a combination of the back-side global source power supply voltage grid structure 120, the through-hole structure 21, and the front-side global source power supply voltage grid structure 180 (including the peripheral contact via structure 18C). This configuration equalizes the potential between the memory array region 100 and the peripheral connection region 200 during the back-side plasma-based etching process, thereby reducing the voltage difference that could cause plasma-induced damage in the static random access memory cells and peripheral circuitry, while maintaining the electrical characteristics and reliability of the semiconductor die 700.

[0212] Figure 25 This is a vertical cross-sectional view of a region of the semiconductor die 700 after the formation of the additional back-side dielectric material layer 10, the additional back-side metal interconnect structure 20, and the back-side pad 220, according to embodiments of the present disclosure. The back-side global source voltage grid structure 120, the through-hole structure 21, and the front-side global source voltage grid structure 180 can be electrically biased by at least one of the back-side pad 220 and the additional back-side metal interconnect structure 20. Alternatively, the second carrier wafer 421 can be removed, and the back-side global source voltage grid structure 120, the through-hole structure 21, and the front-side global source voltage grid structure 180 can be electrically biased by at least one front bonding pad 88.

[0213] The second carrier wafer 421 may be removed from the device wafers (10, 20, 180, 30, 60, 80, 180) or not. The device wafers (10, 20, 180, 30, 60, 80, 180) can then be monolithically processed to provide a plurality of monolithically processed semiconductor dies 700. In one embodiment, each individual semiconductor die 700 may include a corresponding SRAM array.

[0214] Figure 26 This is a circuit diagram of a unit static random access memory (SRAM) cell according to the present disclosure. The unit SRAM cell includes a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first transmission gate transistor PG1, a second transmission gate transistor PG2, a word line WL, a first bit line BL, a complementary bit line BLB, a global drain power supply node Vdd, and a global source power supply node Vss. According to one aspect of the present disclosure, the global source power supply node Vss includes a combination of a back-side global source power supply grid structure 120, a through-hole structure 21, and a front-side global source power supply grid structure 180. In one embodiment, the first pull-up transistor PU1 and the second pull-up transistor PU2 may include p-type field-effect transistors, and the first pull-down transistor PD1, the second pull-down transistor PD2, the first transmission gate transistor PG1, and the second transmission gate transistor PG2 may include n-type field-effect transistors. The first pull-up transistor PU1 and the second pull-up transistor PU2 may include the second field-effect transistor T2 mentioned above; the first pull-down transistor PD1 and the second pull-down transistor PD2 may include the first field-effect transistor T1 mentioned above; and the first transmission gate transistor PG1 and the second transmission gate transistor PG2 may include the third field-effect transistor T3 mentioned above.

[0215] Common Reference Figures 1A-26According to various embodiments of the present disclosure, a static random access memory (SRAM) device is provided, comprising: an isolation component 31 having a front side and a back side; a plurality of transistors (T1, T2, T3) disposed on the front side of the isolation component 31, the transistors (T1, T2, T3) including a first source / drain component 381 configured to be biased under a global source power supply voltage and a second source / drain component 382 configured to be biased under a global drain power supply voltage; a front-side global source power supply voltage grid structure 180 extending through a memory array region 100 and an external... The surrounding connection area 200 includes a front-side global source power supply voltage grid structure 180 electrically connected to a first source / drain component 381 via a first front-side source / drain contact via structure 8C1; a feedthrough via structure 21 extending from the back side through the isolation component 31 to a first component (including the peripheral contact via structure 18C) of the front-side global source power supply voltage grid structure 180; and a back-side global source power supply voltage grid structure 120 disposed on the back side of the isolation component 31 and electrically connected to the front-side global source power supply voltage grid structure 180 via the feedthrough via structure 21.

[0216] In one embodiment, the SRAM device includes: a back-side contact level dielectric layer 11 located on the back side of the isolation member 31; and a back-side contact via structure 22 extending vertically through the back-side contact level dielectric layer 11 and contacting the back-side surface of the first source / drain member 381.

[0217] In one embodiment, the front-side global source power supply voltage grid structure 180 includes a peripheral contact via structure 18C that contacts the feedthrough via structure 21. In one embodiment, the planar horizontal surface of the feedthrough via structure 21 is coplanar with the planar horizontal surface of the back-side contact via structure 22; and the feedthrough via structure 21 includes a contour surface that includes a corresponding set of horizontal surface segments adjacent to the contour surface segments, the contour surface segments contacting a corresponding subset of the peripheral contact via structure 18C.

[0218] In one embodiment, the feed through-hole structure 21 has tapered sidewalls such that the lateral extent of the feed through-hole structure 21 is greater on the back side of the isolation member 31 than on the front side of the isolation member 31.

[0219] According to another aspect of the present invention, a device structure is provided, comprising: a first field-effect transistor T1 and a second field-effect transistor T2 disposed on the front side of an isolation component 31; a front dielectric layer 60 and a front metal interconnect structure 80 located on the front side of the isolation component 31, wherein the front metal interconnect structure 80 includes a front global source power supply voltage grid structure 180 extending through a memory array region 100 and a peripheral connection region 200 and contacting a first subset of the source / drain components 38 of the first field-effect transistor T1, wherein a second subset of the source / drain structure 38 of the first field-effect transistor T1 is electrically isolated from the front global source power supply voltage grid structure 180; a back-side contact level dielectric layer 11 located on the back side of the isolation component 31; and a back-side global source power supply voltage grid structure 120 disposed on the back side of the isolation component 31 and including a back-side contact via structure 22 extending vertically through the back-side contact level dielectric layer 11 and contacting the back surface of the first subset of the source / drain components 38 of the first field-effect transistor T1.

[0220] In one embodiment, the device structure includes a through-hole structure 21 located in the peripheral connection region 200, which extends vertically through the back-side contact level dielectric layer 11 and the isolation component 31, and contacts a first component (including the peripheral contact via structure 18C) of the front-side global source power supply voltage grid structure 180. In one embodiment, a first field-effect transistor T1, a second field-effect transistor T2, and the back-side contact via structure 22 are located in the memory array region 100; the through-hole structure 21 is located in the peripheral connection region 200; and the front-side global source power supply voltage grid structure 180 and the back-side global source power supply voltage grid structure 120 extend through the memory array region 100 and the peripheral connection region 200.

[0221] In one embodiment, the front-side global source power supply voltage grid structure 180 includes: a first global source voltage metal line (including a first line-level source connection metal line 181), which extends laterally along a first horizontal direction hd1 and is located in the peripheral connection area 200 and outside the memory array area 100, the first global source voltage metal line being a subset of the front-side first line-level metal lines (81, 181); and a second global source voltage metal line (including a second line-level source connection metal line 182), which extends laterally along a second horizontal direction hd2 above the first global source voltage metal line (including the first line-level source contact metal line 181) and extends above the peripheral connection area 200 and the memory array area 100, the second global power supply voltage metal line 182 being a subset of the front-side second line-level metal lines (82, 182).

[0222] In one embodiment, the first field-effect transistor T1 includes a pair of pull-down (PD) transistors for a static random access memory (SRAM) cell; the second field-effect transistor T2 includes a pair of pull-up (PU) transistors for the SRAM cell. The device structure includes front-side third line-level metal lines (83, 183) extending laterally above the front-side second line-level metal lines along a first horizontal direction hd1. The front-side global source power supply voltage grid structure 180 includes a first subset of the front-side third line-level metal lines (83, 183).

[0223] In one embodiment, a second subset of the front third line level metal lines (83, 183) includes word lines of SRAM cells; the word lines of SRAM cells are interleaved with the first subset of the front third line level metal lines (83, 183) along the second horizontal direction hd2.

[0224] In one embodiment, the device structure includes a through-hole structure 21 located in the peripheral connection region 200, arranged in a row extending laterally along a first horizontal direction hd1, and electrically connected to a first global source voltage metal line 181. The memory array region 100 includes a first boundary adjacent to the peripheral connection region 200 and parallel to the first horizontal direction hd1, and also includes a second boundary parallel to the first horizontal direction hd1 and laterally spaced from the peripheral connection region 200; and the lateral distance by which the second boundary is laterally offset from the first boundary along the second horizontal direction hd2 is greater than the lateral distance of the farthest surface of the second line level metal line from the first boundary along the second horizontal direction hd2.

[0225] Typically, a back-side global source voltage grid structure 120 is formed on and above the back-side contact-level dielectric layer 11. In this embodiment, the back-side global source voltage grid structure 120 forms an ohmic contact with the through-hole structure 21. The front-side global source voltage grid structure 180 and the back-side global source voltage grid structure 120 extend through the memory array region 100 and the peripheral connection region 200. The dual-grid configuration of this disclosure provides a back-side global source voltage connection for low-resistance power transfer. The dual-grid configuration of this disclosure enhances charge balance and further reduces the risk of plasma-induced damage.

[0226] The dual-grid configuration of this disclosure offers several operational advantages. These advantages may include lower programming resistance on the static random access memory bit cells, reduced ground bounce particularly in the center cell, and improved read margin. The dual-grid configuration of this disclosure reduces plasma-induced damage during plasma-based etching processes of the upper-level dielectric and metal structures. Furthermore, this arrangement allows for flexible options to balance performance, area, and power tradeoffs in the semiconductor die 700.

[0227] Figure 27A This is a graph showing the relative magnitudes of ground bounce voltages observed under different configurations of the global source power supply voltage grid. (Refer to...) Figure 27A For a reference configuration that uses only the front-side global source voltage grid structure 180 and not the back-side global source voltage grid structure 120, the first curve 2610 represents the ground bounce voltage as a function of the distance from the boundary between the memory array region 100 and the peripheral connection region 200. The second curve 2620 represents the ground bounce voltage as a function of the distance from the boundary between the memory array region 100 and the peripheral connection region 200. In this embodiment, the front-side global source voltage grid structure 180 has a reference... Figure 5A , Figure 5B and Figure 18 In the first configuration described, the back-side global source voltage grid structure 120 is connected to the front-side global source voltage grid structure 180 via two sets of through-hole structures 21 located in the two peripheral connection regions 100. The third curve 2630 represents the ground bounce voltage as a function of the distance from the boundary between the memory array region 100 and the peripheral connection region 200. In this embodiment, the front-side global source voltage grid structure 180 has a reference... Figure 6A , Figure 6B and Figure 19 In the second configuration described, the back-side global source voltage grid structure 120 is connected to the front-side global source voltage grid structure 180 via two sets of through-hole structures 21 located in the two peripheral connection regions 100. The fourth curve 2640 represents the ground bounce voltage as a function of the distance from the boundary between the memory array region 100 and the peripheral connection region 200. In this embodiment, the front-side global source voltage grid structure 180 has a reference... Figure 8A , Figure 8B and Figure 20 The third configuration described involves a back-side global source voltage grid structure 120 connected to a front-side global source voltage grid structure 180 via two sets of through-hole structures 21 located in two peripheral connection regions 100. A fifth curve 2650 represents the ground bounce voltage as a function of the distance from the boundary between the memory array region 100 and the peripheral connection region 200. In this embodiment, the front-side global source voltage grid structure 180 has a reference... Figure 21 The fourth configuration is described, and the back-side global source power supply voltage grid structure 120 is connected to the front-side global source power supply voltage grid structure 180 through a single set of feedthrough structures 21 located in a single peripheral connection area 100.

[0228] Figure 27B This is a graph showing the relative read margin voltage observed under different configurations of the global source supply voltage grid. (Refer to...) Figure 27BThe first curve 2710 represents the read margin voltage as a function of the device operating voltage of the SRAM cell, wherein only the front-side global source power supply voltage grid structure 180 is used and the back-side global source / power supply voltage grid structure 120 is not used. The second curve 2720 represents the read margin voltage as a function of the device operating voltage of the SRAM cell with a dual-grid configuration, and includes the front-side global source power supply voltage grid structure 180 and the back-side global source / power supply voltage grid structure 120 connected by the through-hole structure 21.

[0229] According to one aspect of the invention, a back-side global source power supply voltage grid structure 120 is formed on the back side of the isolation member 31. The back-side global source power supply voltage grid structure 120 may include one or more back-side metal interconnect layers and may include vertical conductive connections extending to the first source / drain member 381 of the first field-effect transistor T1, such as back-side contact via structure 22 and through-hole via structure 21. In one embodiment, a global source power supply voltage (e.g., Vss) may be directly applied to the back-side global source power supply voltage grid structure 120, such that the global source power supply voltage reaches the first source / drain member 381 from the back side of the semiconductor die 700.

[0230] In one embodiment, the front-side global source voltage grid structure 180 is maintained together with the back-side global source voltage grid structure 120. The front-side global source voltage grid structure 180 can be connected to the back-side global source voltage grid structure 120 via a through-hole structure 21, making the two structures electrically continuous. The combination of the front-side global source voltage grid structure 180 and the back-side global source voltage grid structure 120 provides multiple parallel conductive paths for current flow. This arrangement reduces the overall resistance of the global power voltage distribution network and allows charge to discharge along multiple paths.

[0231] In one embodiment, the front global source voltage grid structure 180 is maintained even when the back-side global source voltage grid structure 120 is present, thereby maintaining charge balance and providing a low-resistance charge rebalancing path during plasma-based etching processes. The presence of the front global source voltage grid structure 180 mitigates plasma-induced damage by rapidly discharging plasma-induced charges to the substrate 1000' through the peripheral contact via structure 18C and the through-feed via structure 21.

[0232] In one embodiment, a dual-grid configuration including a front-side global source power supply voltage grid structure 180 and a back-side global source power supply voltage grid structure 120 provides design flexibility. Designers can select which front-side interconnect layers to include or exclude based on performance, power, or area considerations. For example, removing selected front-side interconnect layers can allow for wider word lines to improve switching speed. Increasing the number of front-side interconnect layers can reduce resistance, thereby improving power efficiency. Reducing the number of through-hole structures 21 can reduce the macro area by approximately 0.8%–1%.

[0233] In one embodiment, the dual-grid configuration improves voltage stability across the semiconductor die 700. The combined network of the front-side global source power supply voltage grid structure 180 and the back-side global source power supply voltage grid structure 120 reduces ground bounce, particularly in static random access memory (SRAM) cells located far from the global source power supply voltage supply point. Reduced ground bounce improves the read margin and overall stability of the SRAM device.

[0234] Figure 28 This is a vertical cross-sectional view of a region of a first alternative configuration of the semiconductor die after the removal of the first carrier wafer 411, according to an embodiment of the present disclosure. The first alternative configuration of the semiconductor die can be achieved by incomplete removal of the semiconductor material layer 28 from the reference... Figure 12 and Figure 13 This is derived from the description of the semiconductor die. In other words, refer to... Figure 12 and Figure 13 The described processing steps are modified such that at least a portion of the semiconductor material layer 28 exists on the back side of the semiconductor die. Therefore, after removing the first carrier wafer 411, a portion of the semiconductor material layer 28 remains on the back side containing the source region layer 30. In this processing step, the thickness of the semiconductor material layer 28 can be in the range of 20 nm to 100 nm, but smaller or larger thicknesses can also be used. Therefore, the planar back side surface of the semiconductor die can include the back side surface of the semiconductor material layer 28.

[0235] Figure 29This is a vertical cross-sectional view of a region of a first alternative configuration of a semiconductor die after the deposition of a back-side contact layer 11, according to embodiments of the present disclosure. The back-side contact layer 11 is deposited on the planar back-side surface of the remaining portion of the semiconductor material layer 28. The back-side contact layer 11 comprises an interconnect layer-level dielectric (ILD) material, such as undoped silicate glass, doped silicate glass, silicon nitride, or porous or non-porous organosilicon glass, and may have a thickness in the range of 30 nm to 300 nm, for example, 100 nm to 200 nm, but smaller or larger thicknesses may also be used. The physically exposed back-side surface of the back-side contact layer 11 may be a planar surface. Therefore, when depositing the back-side contact layer 11, the planar back-side surface of the semiconductor die may include the back-side surface of the back-side contact layer 11.

[0236] Figure 30 This is a vertical cross-sectional view of the region of a first alternative configuration of the semiconductor die after the formation of the through-hole cavity 17, the back-side contact through-hole cavity 19, and the back-side insulating spacer 922, according to an embodiment of the present disclosure.

[0237] Reference Figure 30 , can execute reference Figure 15A and Figure 15B The described processing steps. For example, a combination of device wafers (30, 60, 80) and a second carrier wafer 421 is disposed as an assembly on the chuck 2200 of a plasma-based etching apparatus 2000. This assembly includes interconnect structures (e.g., upper dielectric material layers 63, 64, 60U and upper metal interconnect structures (83, 84, 80U)), an active region containing the source region layer 30, at least one material layer including the remaining portion of the back-side contact layer dielectric layer 11 and the semiconductor material layer 28, and a patterned back-side photoresist layer 117 (see Figure 15A and 15BThe component is oriented such that the front-side global source power grid structure 180 is electrically connected to the chuck 2200, and a patterned back-side photoresist layer covers at least one material layer and the active region. With the component thus oriented, plasma-based anisotropic dielectric etching creates an opening defined by the photoresist through the back-side contact-level dielectric layer 11 and etches an unmasked portion of the semiconductor material layer 28 to form a through-hole cavity 17 that extends vertically through the isolation member 31 and into the peripheral region to expose the bottom region of the peripheral contact via structure 18C. During the first back-side anisotropic etching process, localized charges generated in the region adjacent to the first source / drain component 381 flow to the chuck 2200 via a conductive charge rebalancing path that includes the first source / drain component 281, the front-side global source power grid structure 180, the upper-level metal interconnect structures (83, 84, 80U), and the second carrier wafer 421. Peripheral bonding is provided by electrically connecting the peripheral contact via structure 18C and patterned portions of the semiconductor material (e.g., peripheral semiconductor material portions 37 and unmasked portions of the semiconductor material layer 28 on the periphery) to the chuck 2200. Etching is performed simultaneously with the first source / drain component 381 being electrically connected to the carrier wafer 421 via the front-side global source power supply voltage grid structure 180.

[0238] Can execute reference Figures 16A-16E The described processing steps include, for example, removing the combination of device wafers (30, 60, 80) and the second carrier wafer 421 from the first plasma-based etching apparatus 2000, applying a new back-side photoresist layer and photolithographically patterning it to form a patterned back-side photoresist layer 119 (see...). Figures 16A-16EThe assembly is then placed as a component on the chuck 2200 of the second plasma-based etching apparatus 2000. This component includes an interconnect structure, an active region containing a source region layer 30, at least one material layer including a back-side contact level dielectric layer 11 and the remainder of a semiconductor material layer 28, and a patterned back-side photoresist layer 119. The component is oriented such that a front-side global source power supply voltage grid structure 180 is electrically connected to the chuck 2200, and the patterned back-side photoresist layer covers at least one material layer and the active region. With the component thus oriented, the second plasma-based anisotropic dielectric etching creates an opening defined by the photoresist through a portion of the back-side contact level dielectric layer 11 and etches an unmasked portion of the remainder of the semiconductor material layer 28, thereby forming a back-side contact via cavity 19 and exposing the back side of the first source / drain component 381 by forming the back-side contact via cavity 19 through at least one material layer. During the second back-side anisotropic etching process, localized charges generated in the region adjacent to the first source / drain component 381 flow to the chuck 2200, and the peripheral contact via structure 18C and the patterned portion of the semiconductor material are electrically connected to the chuck 2200 to provide peripheral connectivity. Etching is performed simultaneously with the first source / drain component 381 being electrically connected to the carrier wafer 421 via the front-side global source power supply voltage grid structure 180.

[0239] In Figure 16D In one corresponding embodiment, each back-side contact via cavity 19 includes a truncated cone-shaped recess extending into the corresponding first source / drain component 381, such that the downwardly projecting portion of the first source / drain component 281 laterally surrounds the top of the back-side contact via cavity 19 and exhibits a variable horizontal cross-sectional area that increases with the vertical distance toward the interconnect structure. Figure 16E In another corresponding embodiment, each back-side contact via cavity 19 includes a tapered recess extending into a corresponding first source / drain component 381 having a similar downwardly projecting geometry. Under tapering conditions (e.g., oriented ion-assisted anisotropic dry etching and timed over-etching with controlled sidewall passivation after initial exposure), a tapered surface is formed on the inner wall of the back-side contact via cavity 19. The tapered surface is closer to the interconnect structure than the back-side surface of the second source / drain component and will contact the back-side surface of the first source / drain component 381 after metallization. Typically, the back-side contact via structure 22 has a tapered surface that contacts the back-side surface of the first source / drain component 381. The tapered surface is closer to the horizontal plane including the topmost surface of the first field-effect transistor T1 and the second field-effect transistor T2 than the back-side surface of the second source / drain component 382.

[0240] In one embodiment, the lateral area of ​​each back-side contact via cavity 19 is larger than that of the reference cavity. Figures 16A-16EIn the described embodiment, the lateral area is such that, in a plan view, a portion of the subsequently formed back-side dielectric spacer 922 lies laterally outside the area occupied by the first source / drain component 381. This configuration preserves the geometry of the tapered cavity while positioning the back-side dielectric spacer 922 in the area laterally surrounding (but not overlapping) the back-side surface of the first source / drain component 381.

[0241] After forming the through-hole cavities 17 and back-side contact via cavities 19, dielectric spacers (921, 922) can be formed along the peripheral sidewall sections of the through-hole cavities 17 and 19. The through-hole dielectric spacer 921 is formed along the peripheral sidewall section of each through-hole cavity 17, and the back-side dielectric spacer 922 is formed along the peripheral sidewall section of each back-side contact via cavity 19. In various embodiments, the through-hole dielectric spacers 921 and 922 comprise silicon nitride (Si3N4), silicon nitride (SiCN), silicon oxynitride (SiON), and aluminum oxide (Al2O3), conformally deposited by atomic layer deposition or plasma-enhanced chemical vapor deposition followed by directional etching to leave spacer sections on the sidewalls while maintaining etched openings for subsequent conductive filling. The radial thickness of each through-hole dielectric spacer 921 is in the range of 3 nm to 20 nm, for example, 5 nm to 10 nm. The radial thickness of each back-side dielectric spacer 922 is in the range of 3 nm to 20 nm, for example, 5 nm to 10 nm. In the large-area embodiment of the second part, the back-side dielectric spacers 922 are laterally disposed outside the region of the first source / drain component 381 in the plan view, thereby providing isolation around the cavity without encroaching on the back-side surface of the first source / drain component 281. The feedthrough dielectric spacers 921 and the back-side dielectric spacers 922 provide lateral electrical isolation, maintain the cavity geometry established by the plasma-based anisotropic dielectric etching process, and define controlled interface surfaces for defining the metal barrier pad material and metal filler material to be deposited in subsequent processing steps. In conjunction with the tapered inner surface created for the back-side contact via cavity 19 in the second part, the spacer geometry maintains a relatively vertical orientation, so that after filling, the back-side contact via structure 22 has a tapered surface that contacts the back side of the first source / drain component 381 and is closer to the interconnect structure than the back side surface of the second source / drain component. The downwardly projecting portion of the first source / drain component 381 laterally surrounds the top of the back-side contact via structure 22 with a variable horizontal cross-section that increases upward toward the interconnect structure. Typically, the back-side contact via structure 22 has a tapered surface that contacts the back side surface of the first source / drain component 381. The tapered surface is closer to the horizontal plane including the topmost surfaces of the first field-effect transistor T1 and the second field-effect transistor T2 than the back side surface of the second source / drain component 382.

[0242] Figure 31 This is a vertical cross-sectional view of a region of a first alternative configuration of a semiconductor die after the formation of an additional back-side dielectric layer, a back-side metal interconnect structure, and back-side pads, according to embodiments of the present disclosure. Reference can be performed. Figures 17A-25 The described processing steps. In one embodiment, the back-side contact through-hole cavity 19 has an inverted truncated conical recess at its top (corresponding to...). Figure 16D The subsequent conductive filling forms a back-side contact via structure 22, the upper part of which conforms to an inverted truncated conical cavity geometry (i.e., having a planar or substantially planar top surface, a conical surface adjacent to the periphery of the planar top surface, and a smaller cylindrical or substantially cylindrical or conical lower sidewall segment). The feed-through via structure 21 and the back-side first line layer metal line 24 are formed as described herein. (Refer to...) Figures 23A to 25 As described above, additional dorsal structures can be formed.

[0243] Figure 32 This is a vertical cross-sectional view of an alternative embodiment of a first alternative configuration of a semiconductor die after the formation of an additional back-side dielectric material layer, a back-side metal interconnect structure, and a back-side pad, according to embodiments of the present disclosure. In this alternative embodiment, the back-side contact via cavity 19 has a tapered recess at its top (corresponding to...). Figure 16E The subsequent conductive filling forms a back-side contact via structure 22, the upper part of which conforms to a conical cavity geometry (i.e., has a conical surface at the top, connecting to a generally cylindrical lower sidewall segment). The feed-through via structure 21 and the back-side first circuit layer metalline 24 are formed as described herein. (Refer to...) Figures 23A to 25 As described above, an additional dorsal structure can be formed.

[0244] Figure 33 This is a vertical cross-sectional view of a region of a second alternative configuration of a semiconductor die after the removal of the bulk semiconductor layer 411 of a semiconductor-on-insulator (SOI) wafer, according to embodiments of the present disclosure. In the second alternative configuration, the substrate 1000 may include an SOI wafer comprising a semiconductor material layer 28, an insulating layer, and a bulk semiconductor layer including a back-side contact level dielectric layer 11. This bulk semiconductor layer serves as the first carrier wafer 411 and is subsequently removed. The insulating layer including the back-side contact level dielectric layer 11 may comprise a dielectric material such as silicon oxide and may have a uniform thickness throughout the process. The thickness of the insulating layer including the back-side contact level dielectric layer 11 may range from 10 nm to 200 nm, for example, from 20 nm to 100 nm, but smaller or larger thicknesses may also be used. (Refer to...) Figures 14-33 In the described processing steps, the insulating layer of the back contact level dielectric layer 11 can be used as the back contact level dielectric layer 11.

[0245] Figure 34This is a vertical cross-sectional view of a region of the second alternative configuration of the semiconductor die after the removal of the first carrier wafer, according to an embodiment of the present disclosure. (Refer to...) Figure 34 , refer to Figures 2A to 13 The described processing steps can be modified so that the removal of the bulk semiconductor layer of the SOI wafer (equivalent to the first carrier wafer 411) is performed, such that at least a portion of the insulating layer (i.e., the back contact level dielectric layer 11) remains on the back side of the semiconductor die. Therefore, the planar back surface of the semiconductor die is the back surface of the back contact level dielectric layer 11. Figure 34 The structure can be functionally equivalent to Figure 14 The structure includes a back-side contact layer dielectric layer 11 that provides a planar back-side surface formed on the back side containing the source region layer 30.

[0246] Figure 35 This is a vertical cross-sectional view of the region of a second alternative configuration of the semiconductor die after the formation of the through-hole cavity 17, the back-side contact through-hole cavity 19, and the back-side insulating spacer 922, according to embodiments of the present disclosure. (Refer to...) Figure 35 , can execute reference Figure 15A and Figure 15B The described processing steps. For example, a combination of device wafers (30, 60, 80) and a second carrier wafer 421 can be set as an assembly on the chuck 2200 of a plasma-based etching apparatus 2000. This assembly includes interconnect structures (e.g., upper dielectric material layers 63, 64, 60U and upper metal interconnect structures (83, 84, 80U)), active regions in the source region layer 30, at least one material layer including an insulating layer comprising a back-side contact layer dielectric layer 11, and a patterned back-side photoresist layer 117 (see...). Figure 15A and Figure 15BThe component can be oriented such that the front-side global source power grid structure 180 is electrically connected to the chuck 2200, and a patterned back-side photoresist layer covers at least one material layer and the active region. With the component so oriented, plasma-based anisotropic dielectric etching can transfer the photoresist-defined opening through the insulating layer including the back-side contact-level dielectric layer 11, and can etch the unmasked portion of the semiconductor material layer 28 to form a through-hole cavity 17, which can extend vertically through the isolation member 31 and into the peripheral region to expose the bottom region of the peripheral contact via structure 18C. During this first back-side anisotropic etching process, localized charges generated in the region adjacent to the first source / drain member 381 can flow to the chuck 2200 through a conductive charge rebalancing path including the first source / drain member 381, the front-side global source power grid structure 180, the upper-level metal interconnect structures (83, 84, 80U), and the second carrier wafer 421. Peripheral bonding can be provided because the peripheral contact via structure 18C and the patterned portions of the semiconductor material (e.g., the peripheral semiconductor material portion 37 and the unshielded portion of the semiconductor material layer 28 on the periphery) can be electrically connected to the chuck 2200. Etching can be performed simultaneously with the first source / drain component 381 being electrically connected to the carrier wafer 421 via the front-side global source power supply voltage grid structure 180.

[0247] Then you can execute the reference. Figures 16A-16E The described processing steps. For example, the combination of device wafers (30, 60, 80) and second carrier wafer 421 can be removed from the first plasma-based etching apparatus 2000, and a new back-side photoresist layer can be applied and photolithographically patterned to form a patterned back-side photoresist layer 119 (see...). Figures 16A-16EThen, this assembly can be disposed on the chuck 2200 of the second plasma-based etching apparatus 2000 as an assembly including an interconnect structure, an active region containing a source region layer 30, at least one material layer including an insulating layer, and a patterned back-side photoresist layer 119, the insulating layer including a back-side contact level dielectric layer 11 and the remainder of the semiconductor material layer 28. The assembly can be oriented such that a front-side global source power supply voltage grid structure 180 is electrically connected to the chuck 2200, and the patterned back-side photoresist layer covers at least one material layer and the active region. With the assembly thus oriented, the second plasma-based anisotropic dielectric etching can transfer the photoresist-defined opening through a portion of the insulating layer including the back-side contact level dielectric layer 11, and can etch the unmasked portion of the remainder of the semiconductor material layer 28, thereby forming a back-side contact via cavity 19, and exposing the back-side surface of the first source / drain component 381 by forming the back-side contact via cavity 19 through at least one material layer. During this second back-side anisotropic etching process, localized charges generated in the region adjacent to the first source / drain component 381 can flow to the chuck 2200, and the peripheral contact via structure 18C and the patterned portion of the semiconductor material can be electrically connected to the chuck 2200 to provide peripheral bonding. Etching can be performed simultaneously with the first source / drain component 381 being electrically connected to the carrier wafer 421 via the front-side global source power supply voltage grid structure 180.

[0248] In Figure 16D In one corresponding embodiment, each back-side contact via cavity 19 may include a truncated recess extending into the corresponding first source / drain component 381, such that the downwardly projecting portion of the first source / drain component can laterally surround the top of the back-side contact via cavity 19, and can present a variable horizontal cross-sectional area that increases with the vertical distance toward the interconnect structure. Figure 16E In another corresponding embodiment, each back-side contact via cavity 19 may include a tapered recess extending into a corresponding first source / drain component 381 having a similar downwardly projecting geometry. Under tapering conditions (e.g., oriented ion-assisted anisotropic dry etching and timed over-etching with controlled sidewall passivation after initial exposure), a tapered surface can be formed on the inner wall of the back-side contact via cavity 19; the tapered surface may be closer to the interconnect structure than the back-side surface of the second source / drain component and may contact the back-side surface of the first source / drain component 381 after metallization. Typically, the back-side contact via structure 22 has a tapered surface that contacts the back-side surface of the first source / drain component 381. The tapered surface is closer to the horizontal plane including the topmost surfaces of the first field-effect transistor T1 and the second field-effect transistor T2 than the back-side surface of the second source / drain component 382.

[0249] Figure 36 This is a vertical cross-sectional view of a region of a second alternative configuration of a semiconductor die after the formation of an additional back-side dielectric layer, a back-side metal interconnect structure, and back-side pads, according to embodiments of this disclosure. Reference can be performed. Figures 17A-25 The described processing steps. In one embodiment, the back-side contact through-hole cavity 19 may have a truncated cone-shaped recess at its top (corresponding to...). Figure 16D The subsequent conductive filling can form a back-side contact via structure 22, the upper part of which conforms to the geometry of an inverted truncated cone cavity (i.e., having a planar or substantially planar top surface, a conical surface adjacent to the periphery of the planar top surface, and a smaller cylindrical or substantially cylindrical or conical lower sidewall segment). The feed-through via structure 21 and the back-side first circuit layer metal line 24 can be formed as described herein. (Refer to...) Figures 23A to 25 As described above, an additional dorsal structure can be formed.

[0250] Figure 37 This is a vertical cross-sectional view of a region of an alternative embodiment of a second alternative configuration of a semiconductor die after the formation of an additional back-side dielectric material layer, a back-side metal interconnect structure, and a back-side pad, according to embodiments of the present disclosure. In this alternative embodiment, the back-side contact via cavity 19 may have a tapered recess at its top (corresponding to...). Figure 16E The subsequent conductive filling can form a back-side contact via structure 22, the upper part of which conforms to the geometry of a conical cavity (i.e., has a conical surface at the top, connecting to a generally cylindrical lower sidewall segment). The feed-through via structure 21 and the back-side first circuit layer metal line 24 can be formed as described herein. (Refer to...) Figures 23A to 25 As described above, an additional dorsal structure can be formed.

[0251] Figure 38A and Figure 38B A first flowchart is shown, illustrating general processing steps for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0252] Refer to steps 3810 and Figures 1A-2C , Figure 28 and Figure 33 An active region and an isolation component 31 are formed on the substrate. Each active region includes a corresponding channel region 32 and a corresponding source / drain region adjacent to the corresponding channel region 32.

[0253] Refer to step 3820 and Figures 1A-2C , Figure 28 and Figure 33 A gate structure (33, 34, 35) is formed, wherein each gate structure (33, 34, 35) is connected to at least three surfaces of a corresponding one of the channel regions 32.

[0254] Refer to step 3830 and Figures 2A-2C, Figure 28 and Figure 33 An epitaxial component is formed above the source / drain region, wherein the epitaxial component includes a first source / source component 381 configured to be biased under the global source power supply voltage and a second source / drain component 382 configured to be biased under the global drain power supply voltage.

[0255] Refer to step 3840 and Figures 3A to 10 , Figure 28 and Figure 33 A front-side global source power supply voltage grid structure 180 is formed above the epitaxial component, wherein the front-side global source power supply voltage grid structure 180 is electrically connected to the first source / drain component 381 through the front-side source / drain contact via structure 8C1.

[0256] Refer to step 3850 and Figures 3A-10 , Figure 28 and Figure 33 An interconnect structure is fabricated on a front-side global source power supply voltage grid structure 180, wherein the interconnect structure includes interconnect layers, wherein each interconnect layer includes a metal line disposed in a corresponding dielectric layer, wherein at least one metal line includes a curved top surface 80T in a cross-sectional view.

[0257] Refer to step 3860 and Figures 11A-13 , Figure 28 and Figure 34 After fabricating the interconnect structure, a planar back-side surface is formed on the back side of the active region by removing at least one back-side portion of the substrate.

[0258] Refer to step 3870 and Figures 14-16C , Figure 29 , Figure 30 , Figure 34 and Figure 35 In a plasma-based etching apparatus 2000, an assembly including an interconnect structure, an active region, at least one material layer (11, optional 28) and a patterned photoresist layer 119 is disposed on a chuck 2200 and oriented such that a front-side global source power supply voltage grid structure 180 is electrically connected to the chuck 2200, and the patterned photoresist layer (117, 119) covers at least one material layer (11) and the active region.

[0259] Refer to step 3880 and Figures 16A-27B , Figures 30-32 and Figures 35-37 The back side surface of the first source / drain component 381 is exposed by performing a back-side anisotropic etching process, which forms a back-side contact via 19 through at least one material layer (11, optionally 28).

[0260] Figure 39A and Figure 39BThis is a second flowchart illustrating general processing steps for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0261] Refer to steps 3910 and Figures 1A-2C , Figure 28 and Figure 33 An isolation component 31 and an active region are formed on the substrate, each active region including a corresponding channel region 32.

[0262] Refer to step 3920 and Figures 2A to 2C , Figures 19 to 20 , Figure 28 and Figure 33 A first source / drain component 381 and a second source / drain component 382 are formed, wherein each of the first source and the second drain component 382 has a corresponding first epitaxial layer and a corresponding second epitaxial layer, wherein the corresponding first epitaxial layer and the corresponding second epitaxial layer are doped with dopants, wherein the dopant concentration in the corresponding first epitaxial layer is different from the dopant concentration in the corresponding second epitaxial layer, wherein in a cross-sectional view, the thickness of a source / drain component (381, 382) is different from the width of a source / drain component (381).

[0263] Refer to step 3930 and Figures 3A-30 , Figure 28 and Figure 33 This forms a front-side global source power supply voltage grid structure 180, which is electrically connected to the first source / drain component 381 and electrically isolated from the second source / drain component 382.

[0264] Refer to step 3940 and Figures 3A-30 , Figure 28 and Figure 33 The interconnect structure includes interconnect layers, wherein each interconnect layer includes a metal line disposed in a respective dielectric layer, wherein the metal line extends along a respective length direction, wherein at least one metal line includes a curved top surface 80T along a direction different from the respective length direction, and wherein the front-side global source power supply voltage grid structure 180 includes a metal pad located at the top layer of the interconnect structure.

[0265] Refer to step 3950 and Figure 11A , Figure 11B , Figure 28 and Figure 33 The attachment carrier wafer (e.g., a second carrier wafer 421) is such that a subset of the metal pads directly contacts the carrier wafer, and an adhesive layer 423 is laterally surrounding the metal pads.

[0266] Refer to step 3960 and Figure 12 , Figure 13 , Figure 28 and Figure 33After attaching the carrier wafer (e.g., the second carrier wafer 421), at least the back side portion of the substrate (e.g., the first carrier wafer 411) is removed.

[0267] Refer to step 3970 and Figures 14-16C , Figure 29 , Figure 30 , Figure 34 and Figure 35 An assembly is set in a plasma-based etching apparatus 2000, the assembly including a carrier wafer 411, an interconnect structure, an active region, a back-side contact level dielectric layer 11 disposed on the back side of the active region, and a patterned photoresist layer 119.

[0268] Refer to step 3980 and Figures 16A-27B , Figures 30-32 and Figures 35-37 By performing a back-side anisotropic etching process in the region of the first source / drain component 381, the back-side contact via cavity 19 is etched through the back-side contact level dielectric layer 11. At the same time, the first source / drain component 381 is electrically connected to the carrier wafer 411 through the front-side global source power supply voltage grid structure 180.

[0269] Figure 40A and Figure 40B This is a third flowchart illustrating general processing steps for manufacturing a semiconductor structure according to embodiments of the present disclosure.

[0270] Refer to step 4010 and Figures 1A-2C , Figure 28 and Figure 33 A first field-effect transistor T1 and a second field-effect transistor T2 are formed on a substrate 1000. Each first field-effect transistor T1 and T2 includes a corresponding channel region 32 laterally surrounded by an isolation component 31, a corresponding gate structure (33, 34, 35) formed on the corresponding channel region 32, and a corresponding source / drain component 38. An etch stop layer 29 covers the isolation component 31 and the source / drain component 38, and a dielectric layer 6G covers the etch stop layer 29. The height H_E and width W_E of the corresponding source / drain component 38 are different, and the width W_E of the corresponding source / drain component 38 is greater than the width W_C of the corresponding channel region 32, such that a portion of the corresponding source / drain component 38 hangs over the isolation component 31. The first field-effect transistor T1 includes a first source / drain component 381 in the source / drain component 38, and the second field-effect transistor T2 includes a second source / drain component 382 in the source / drain structure 38.

[0271] Refer to step 4020 and Figures 3A-10 , Figure 28 and Figure 33A front dielectric material layer 60 and a front metal interconnect structure 80 are formed above the first field-effect transistor T1 and the second field-effect transistor T2. The front metal interconnect structure 80 includes a front-side global source power supply voltage grid structure 180, which extends through the memory array region 100 and the peripheral connection region 200 and is formed on the first source / drain component 381.

[0272] Refer to step 4030 and Figures 3A to 10 , Figure 28 and Figure 33 An interconnect structure is formed including interconnect layers, wherein each interconnect layer includes a metal line disposed in a dielectric layer, wherein at least one metal line includes a barrier layer 80A connected to the dielectric layer and a fill metal 80B separated from the dielectric layer by the barrier layer 80A, wherein the conductivity of the barrier layer 80B is less than the conductivity of the fill metal 80A, and wherein at least one metal line includes a curved top surface 80T in a cross-sectional view.

[0273] Refer to step 4040 and Figures 11A-13 , Figure 29 and Figure 33 The assembly comprising the interconnect structure, the first field-effect transistor T1 and the second field-effect transistor T2, and the back-side contact layer dielectric layer 11 is provided, at least by removing the back side portion of the substrate 1000 after the interconnect structure is formed.

[0274] Refer to steps 4050 and Figures 14-27B , Figures 30-32 and Figures 34-37 In the peripheral connection area 200, a feedthrough via structure 21 is formed on the back contact level dielectric layer 11 on the bottom surface of the first component (8C1, 8C2, 8C3, 8C4, 8C5, 18C) passing through the front global source power supply voltage grid structure 180.

[0275] Figure 41A and Figure 41B This is a fourth flowchart illustrating general processing steps for manufacturing a semiconductor structure according to embodiments of the present disclosure.

[0276] Refer to step 4110 and Figures 1A-2C , Figure 28 and Figure 33A first field-effect transistor T1 and a second field-effect transistor T2 are formed on a substrate 1000. Each of the first field-effect transistor T1 and the second field-effect transistor T2 includes a corresponding semiconductor structure (e.g., a transistor semiconductor nanosheet 32). The semiconductor structure extends longitudinally over the substrate 1000 along a first direction and includes a corresponding width along a second direction different from the first direction. It is laterally surrounded by an isolation member 31 and a corresponding source / drain member 38 disposed above the corresponding semiconductor structure. The width W_E of the corresponding source / drain member 38 is greater than the width W_C of the corresponding semiconductor structure, such that a portion of the corresponding source / drain member 38 is doped with a dopant. Each source / drain member 38 includes a first layer (38A) and a second layer (38B), wherein the dopant concentration in the first layer is different from the dopant concentration in the second layer.

[0277] Refer to step 4120 and Figures 3A to 10 , Figure 28 and Figure 33 An interconnect structure is formed above the first field-effect transistor T1 and the second field-effect transistor T2. The interconnect structure includes an interconnect layer and a front-side global source power supply voltage grid structure 180. Each interconnect layer includes a metal line disposed in a dielectric layer. At least one metal line includes a barrier layer 80A connected to the dielectric layer and a fill metal 80B spaced apart from the dielectric layer by the barrier layer 80A. The conductivity of the barrier layer 80B is less than the conductivity of the fill metal 80B. At least one metal line includes a curved top surface 80T. The front-side global source power supply voltage grid structure 180 extends through the memory array region 100 and the peripheral connection region 200 and includes a first front contact via structure (8C1, 8C2, 8C3, 8C4, 8C5) of a first subset of the source / drain components 38 of the first field-effect transistor T1, and a peripheral contact via structure 18C formed in the peripheral connection region 200.

[0278] Refer to step 4130 and Figures 14-27B , Figures 30-32 and Figures 34-37 A back-side global source power supply voltage grid structure is formed above the back side of the first field-effect transistor T1 and the second field-effect transistor T2. The back-side global source power supply voltage grid structure includes a feedthrough via structure 21 formed on the back side of the peripheral contact via structure 18C and a back-side contact via structure 22 formed on the back side of the first subset (e.g., the first source / drain component 381) of the source / drain component 38.

[0279] Refer to all appendices Figures 1A to 41BAccording to various embodiments of this disclosure, a semiconductor device is provided comprising a plurality of transistors laterally surrounded by an isolation member 31. Each transistor includes a corresponding active region, the active region including a corresponding channel region and a corresponding source / drain region, and a corresponding epitaxial member 38 disposed above the source / drain region and including a dopant. Each epitaxial member 38 includes a corresponding first layer and a corresponding second layer, the corresponding first layer contacting the corresponding channel region, and the corresponding second layer being separated from the corresponding channel region by the corresponding first layer. The dopant concentration in the corresponding first layer is different from the dopant concentration in the corresponding second layer. The epitaxial member 38 includes a first source / drain member 381 configured to be biased under a global source power supply voltage and a second source / drain member 382 configured to be biased under a global drain power supply voltage. A front-side global source power supply voltage grid structure 180 covers the plurality of transistors and includes a first front-side source / drain contact via structure contacting the first source / drain member 381. An interconnect structure covers the front-side global source power supply voltage grid structure 180 and includes interconnect layers. Each interconnect layer includes a metal line disposed in a corresponding dielectric layer, wherein at least one metal line includes a barrier layer adjoining the dielectric layer and a fill metal spaced apart from the dielectric layer by the barrier layer, and wherein the conductivity of the barrier layer is less than the conductivity of the fill metal. The back-side contact via structure 22 has a tapered surface contacting the back surface of the first source / drain component 381, the tapered surface being closer to the interconnect structure than the back surface of the second source / drain component 382. Typically, the back-side contact via structure 22 has a tapered surface that contacts the back surface of the first source / drain component 381. The tapered surface is closer to the horizontal plane including the topmost surface of the first field-effect transistor T1 and the second field-effect transistor T2 than the back surface of the second source / drain component 382.

[0280] In one embodiment, the first source / drain component 381 includes a corresponding downwardly projecting portion laterally surrounding the top of the back-side contact via structure 22. In one embodiment, each downwardly projecting portion of the first source / drain component 381 has a corresponding variable horizontal cross-sectional area that increases toward the interconnect structure with increasing vertical distance from the horizontal plane including the bottom surface of the second source / drain component 382.

[0281] In one embodiment, the semiconductor device further includes a back-side global source power supply voltage grid structure 120 disposed on the back-side surface of the back-side contact via structure 22 and electrically connected to the front-side global source / power supply voltage grid structure 180 through the back-side contact via structure 22.

[0282] In one embodiment, the semiconductor device further includes a through-hole structure 21 extending vertically through the isolation member 31 and contacting the bottom surface of the component of the front-side global source power supply voltage grid structure 180. The planar horizontal surface of the through-hole structure 21 is coplanar with the planar horizontal surface of the back-side contact via structure 22. The through-hole structure 21 includes a profile surface comprising a corresponding set of horizontal surface segments adjacent to the profile surface segments, these profile surface segments contacting the peripheral contact via structures 18C in the front-side global source power supply voltage grid structure 180. The through-hole structure 21 has tapered sidewalls such that the lateral extent of the through-hole structure 21 is greater on the back side of the isolation member 31 than on the front side of the isolation member 31.

[0283] Refer to all appendices Figures 1A to 41B According to various embodiments of this disclosure, a semiconductor device is provided, comprising a first field-effect transistor T1 and a second field-effect transistor T2 laterally surrounded by an isolation member 31. Each of the first field-effect transistor T1 and the second field-effect transistor T2 includes a respective channel region laterally surrounded by the isolation member 31, a respective gate structure located on the channel region, and a source / drain member 38 as an epitaxial member in contact with a respective sidewall of the channel region. An etch stop layer 29 covers the isolation member 31 and the epitaxial member 38, and a dielectric layer 6G covers the etch stop layer 29. Each epitaxial member 38 includes a first layer adjacent to a respective sidewall of the channel region and a second layer away from the sidewall of the channel region, wherein the composition of the first layer is different from the composition of the second layer. The interconnect layer includes a front dielectric material layer 60, a front metal interconnect structure 80, and a front global source power supply voltage grid structure 180 located in front of the isolation component 31. The front global source power supply voltage grid structure 180 extends through the memory array region 100 and the peripheral connection region 200, and includes a first front contact via structure that contacts a first subset of the source / drain components 38 of the first field-effect transistor T1. A second subset of the source / drain structures 38 of the first field-effect transistor T1 is electrically isolated from the front global source power supply voltage grid structure 180. Each interconnect layer includes a metal line disposed in a corresponding dielectric layer. At least one metal line includes a barrier layer 80A connected to the corresponding dielectric layer and a fill metal 80B spaced apart from the corresponding dielectric layer by the barrier layer 80A. The conductivity of the barrier layer 80A is less than the conductivity of the fill metal 80B. The back-side global source power supply voltage grid structure 120 is disposed on the back side of the first field-effect transistor T1, the second field-effect transistor T2 and the isolation component 31, and includes a back-side contact via structure 22 on the back-side surface of the first subset of the source / drain component 38, and also includes a feedthrough via structure 21 on the bottom surface of the first component of the front-side global source power supply voltage grid structure 180.

[0284] In one embodiment, a first component of the front-side global source power supply voltage grid structure 180 includes a peripheral contact via structure 18C having a top surface located within a horizontal plane including the top surface of the first front contact via structure. In one embodiment, a first field-effect transistor T1, a second field-effect transistor T2, and a back-side contact via structure 22 are located in the memory array region 100; a through-hole structure 21 is located in the peripheral connection region 200; the front-side global source power supply voltage grid structure 180 and the back-side global source power supply voltage grid structure 120 extend through the memory array region 100 and the peripheral connection region 200.

[0285] In one embodiment, the front-side global source power supply voltage grid structure 180 includes a first metal line and a second metal line. The first metal line extends laterally along a first horizontal direction hd1, is located in the peripheral connection area 200 and outside the memory array area 100, and the second metal line is located above the first metal line, extends laterally along a second horizontal direction hd2, and extends above the peripheral connection area 100 and the memory array area 200.

[0286] In one embodiment, the first field-effect transistor T1 includes a pair of pull-down transistors for a static random access memory (SRAM) cell, the second field-effect transistor T2 includes a pair of pull-up transistors for the SRAM cell, and the device structure further includes a third metal line located above the second metal line and extending laterally along a first horizontal direction hd1. The front-side global source power supply voltage grid structure 180 includes a first subset of the third metal line. In one embodiment, the second subset of the third metal line includes word lines of the SRAM cell, and the word lines of the SRAM cell are staggered with the first subset of the third metal line along a second horizontal direction hd2.

[0287] In one embodiment, the through-hole structure 21 is located in the peripheral connection region 200, arranged in a row extending laterally along the first horizontal direction hd1, and electrically connected to the first metal line. The memory array region 100 includes a first boundary adjacent to the peripheral connection region 200 and parallel to the first horizontal direction hd1, and a second boundary parallel to the first horizontal direction hd1 and laterally spaced from the peripheral connection region 200. The second boundary is laterally offset from the first boundary by a lateral distance along the second horizontal direction hd2 greater than the lateral distance of the farthest surface of the second metal line from the first boundary along the second horizontal direction hd2.

[0288] In various embodiments, the front-side global source power supply voltage grid structure 180 and the back-side global source power supply voltage grid structure 120 are electrically interconnected via a through-hole structure 21 to form a dual-grid configuration. The dual-grid configuration extends through the memory array region 100 and the peripheral connection region 200, providing multiple parallel conductive paths between the global source power supply voltage supply point and the first source / drain component 381 of the first field-effect transistor T1. These multiple conductive paths reduce overall distributed resistance, improve voltage stability, and maintain a low-resistance charge rebalancing path for plasma-induced charges during plasma-based etching processes. The topology can be customized by selecting which front-side interconnect layers to retain or remove, adding higher-level metal lines, and adjusting the number and location of the through-hole structures 21 to optimize performance, power efficiency, and area utilization, while maintaining reduced ground bounce, improved read margin, and enhanced protection of the static random access memory cells and peripheral circuitry from plasma-induced damage. The number and location of the through-hole structures 21 can be selected to balance the macro area with the conductive path density, and the front interconnect layers can be selected based on performance, power efficiency and area trade-offs.

[0289] In one embodiment, the back-side global source power supply voltage grid structure 120 includes a back-side first line layer metal line located on the back side of the back-side contact layer dielectric layer 11, a back-side second line layer global source voltage metal line located above the back-side first line layer metal line, and a back-side contact via structure 22 extending vertically through the back-side contact layer dielectric layer 11 to contact the back side of the first source / drain component 381 of the first field-effect transistor T1.

[0290] In one embodiment, the back-side global source voltage grid structure 120 is electrically connected to the front-side global source voltage grid structure 180 via a plurality of feedthrough via structures 21, which extend through the isolation member 31 and are located in the peripheral connection area 200.

[0291] In one embodiment, at least one of the back-side global source power grid structure 120 and the front-side global source power grid structure 180 is electrically biased via the back-side pad 220. In another embodiment, at least one of the back-side global source power grid structure 120 and the front-side global source power grid structure 180 is electrically biased via the front bonding pad 88.

[0292] According to one aspect of this disclosure, active regions and isolation components 31 are formed on a substrate, and each active region includes a corresponding channel region 32 and a corresponding source / drain region adjacent to the channel region 32. Gate structures (33, 34, 35) are formed, and each gate structure is in contact with at least three surfaces of a corresponding one of the channel regions 32. Epitaxial components are formed on the source / drain regions, including a first source / drain component 381 configured to be biased under a global source power supply voltage and a second source / drain component 382 configured to be biased under a global drain power supply voltage. A front-side global source power supply voltage grid structure 180 is formed over the epitaxial components and electrically connected to the first source / drain component 381 through a front-side source / drain contact via structure 8C1. Interconnect structures are fabricated over the front-side global source power supply voltage grid structure 180; the interconnect structures include interconnect layers, each interconnect layer having a metal line disposed in a dielectric layer, and at least one metal line having a curved top surface 80T in cross-section. After fabricating the interconnect structure, a planar back-side surface is formed by removing a back-side portion of the substrate. An assembly including the interconnect structure, active regions, at least one material layer (11, optionally 28), and patterned photoresist layers (117, 119) is disposed on a chuck 2200 in a plasma-based etching apparatus 2000 and oriented such that a front-side global source power supply voltage grid structure 180 is electrically connected to the chuck 2200, and the patterned photoresist layers (117, 119) cover at least one material layer (11) and the active regions. The back side of the first source / drain component 381 is then exposed by performing a back-side anisotropic etching process, which forms a back-side contact via cavity 19 through at least one material layer (11, optionally 28).

[0293] According to one aspect of this disclosure, the semiconductor device of this disclosure provides a low-resistance charge rebalancing path during a plasma-based etching process via a first source / drain component 381 and a front-side global source power supply voltage grid structure 180, thereby reducing plasma damage to memory cells and peripheral circuitry. Multiple conductive paths within the grid reduce overall distributed resistance and improve voltage stability between the memory array region 100 and the peripheral connection region 200, which in turn reduces ground bounce and improves read margin. The curved top surface 80T and barrier layer / pad configuration within the interconnect stack promote reliable metal integrity during the planarization process and enables dense wiring without compromising connectivity. The orientation of the front-side global source power supply voltage grid structure 180 electrically coupled to the chuck 2200 during back-side etching maintains a stable reference potential, thereby mitigating charge buildup and arcing risk. Back-side anisotropic etching forming the back-side contact via cavity 19 enables controlled exposure of the back-side interface and subsequent metallization, improving contact uniformity and long-term reliability. This sequence allows for process flexibility to select the presence and thickness of material layers (11, optionally 28), adjust via geometry, and adjust the use of interconnect layers, supporting optimization of performance, power efficiency, and area without sacrificing device robustness.

[0294] According to another aspect of the invention, a first field-effect transistor T1 and a second field-effect transistor T2 are formed above a substrate 1000. Each transistor includes a corresponding semiconductor structure extending longitudinally along a first direction and having a width along a different second direction, laterally surrounded by an isolation member 31, with a corresponding source / drain member 38 disposed above the semiconductor structure. The width W_E of each source / drain member 38 is greater than the width W_C of the corresponding semiconductor structure, such that a portion of the source / drain member 38 hangs over the isolation member 31. The source / drain member 38 is doped with a dopant, and each source / drain member 38 includes a first layer and a second layer with different dopant concentrations. An interconnect structure is formed above the transistor and includes interconnect layers and a front-side global source power supply voltage grid structure 180. Each interconnect layer has a metal line in a dielectric layer, at least one of which includes a barrier layer 80A connected to the dielectric layer and a fill metal 80B separated by a barrier layer 80B. The conductivity of the barrier layer 80A is lower than that of the fill metal 80B, and at least one metal line has a curved top surface 80T. The front-side global source power supply voltage grid structure 180 extends through the memory array region 100 and the peripheral connection region 200 and includes a first front contact via structure (8C1, 8C2, 8C3, 8C4, 8C5) of a first subset of the source / drain components 38 of the first field-effect transistor T1 and a peripheral contact via structure 18C formed in the peripheral connection region 200. A back-side global source power supply voltage grid structure 120 is formed on the back side, and includes a feedthrough via structure 21 on the back side of the peripheral contact via structure 18C and a back-side contact via structure 22 on the back side of the first subset of the source / drain components 38 (e.g., the first source / source component 381).

[0295] According to one aspect of this disclosure, a dual-grid configuration formed by a front-side global source power voltage grid structure 180 and a back-side global source power voltage grid structure 120 provides multiple parallel conductive paths that reduce IR drop and stabilize the global source potential between the memory array region 100 and the peripheral connection region 200. Through-hole structures 21 create short, low-impedance stitching paths through isolation components 31, improving distribution uniformity and providing robust rebalancing paths during plasma-based processes from either wafer side. Overhanging multilayer doped source / drain components 38 enhance the back-side landing area of ​​the back-side contact via structure 22, improving contact resistance and current diffusion to the first source / drain component 381. Barrier separation metal lines (80A / 80B) with controlled-bend top surfaces 80T support reliable integration at close pitch and maintain line integrity during planarization and subsequent processing. Dividing the front-side components into a first front contact via structure and a peripheral contact via structure 18C allows for independent optimization of array routing and peripheral feed, facilitating pad and strip placement without interfering with critical cell geometry. The ability to select the interconnect hierarchy used by the front-side global source power grid structure 180 and to adjust the number and placement of the feedthrough via structures 21 provides design flexibility to balance macro-area with conductive path density. Overall, these properties improve readout stability and noise margin, reduce sensitivity to ground bounce, enhance robustness against ESD and plasma etching, and support sustained long-term reliability under operational and cyclic stress.

[0296] In some embodiments, a method of forming a semiconductor device structure includes: forming a first field-effect transistor (FET) and a second field-effect transistor (FET) over a substrate, wherein each of the first FET and the second FET includes a respective channel region laterally surrounded by an isolation component, a respective gate structure formed on the respective channel region, a respective source / drain component, and a dielectric layer covering an etch stop layer, wherein the etch stop layer covers the isolation component and the source / drain component, wherein the height and width of the respective source / drain component are different, and the width of the respective source / drain component is greater than the width of the respective channel region, such that a portion of the respective source / drain component hangs over the isolation component, wherein the first FET includes a first source / drain component, and the second FET includes a second source / drain component; forming a front dielectric layer and a [missing information - likely a layer of dielectric material] over the first FET and the second FET. A front metal interconnect structure, comprising a front global source power supply voltage grid structure extending through a memory array region and a peripheral connection region and formed on a first source / drain component; forming an interconnect structure including interconnect layers, wherein each interconnect layer includes a metal line disposed in a dielectric layer, wherein at least one of the metal lines includes a barrier layer adjoining the dielectric layer and a fill metal spaced apart from the dielectric layer by the barrier layer, wherein the conductivity of the barrier layer is less than the conductivity of the fill metal, wherein at least one of the metal lines includes a curved top surface in a cross-sectional view; providing an assembly including an interconnect structure, a first field-effect transistor and a second field-effect transistor, and a back contact level dielectric layer by removing a back side portion of the substrate at least after forming the interconnect structure; and forming a through-hole structure that passes through the back contact level dielectric layer on the bottom surface of the first assembly of the front global source power supply voltage grid structure in the peripheral connection region.

[0297] In some embodiments, the method further includes: physically exposing a first component of the front-side global source power supply voltage grid structure by etching a feedthrough cavity through the back-side contact level dielectric layer and the isolation component; depositing at least one conductive material in the feedthrough cavity; and removing an excess portion of the at least one conductive material from outside the feedthrough cavity, wherein the remaining portion of the at least one conductive material within the feedthrough cavity comprises the feedthrough structure.

[0298] In some embodiments, the method further includes: forming a back-side contact via structure that passes through a back-side contact level dielectric layer on the bottom surface of a first source / drain component in the memory array region.

[0299] In some embodiments, the method further includes: physically exposing the back surface of the first source / drain component by etching a back contact via cavity that extends at least through the back contact layer dielectric layer, wherein the back contact via structure is formed in the back contact via cavity.

[0300] In some embodiments, the method further includes: etching a feedthrough via cavity through a back-side contact level dielectric layer and an isolation component; depositing at least one conductive material in the feedthrough via cavity and the back-side contact via cavity; and removing excess portions of the at least one conductive material from outside the feedthrough via cavity and from the back-side contact via cavity, wherein a first remaining portion of the at least one conductive material filling the feedthrough via cavity comprises a feedthrough via structure, and a second remaining portion of the at least one conductive material filling the back-side contact via cavity comprises a back-side contact via structure.

[0301] In some embodiments, the method further includes forming a back-side global source power supply voltage grid structure, the back-side global source power supply voltage grid structure including a combination of a back-side contact via structure, a feedthrough via structure and a subset of back-side metal lines formed on the back side of the back-side contact level dielectric layer, wherein the back-side global source power supply voltage grid structure is electrically connected to the front-side global source power supply voltage grid structure through a first source / drain component in the memory array region.

[0302] In some embodiments, the substrate includes a semiconductor material layer; the method includes patterning the semiconductor material layer into a channel region formed in a memory array region and a peripheral semiconductor material portion formed in a peripheral interconnect region; a first component of a front-side global source power supply voltage grid structure includes a peripheral contact via structure formed on the top surface of the peripheral semiconductor material portion; and an isolation member laterally surrounding the peripheral semiconductor material portion.

[0303] In some embodiments, the method further includes forming a through-hole cavity by etching a portion through the peripheral semiconductor material portion, thereby exposing the bottom surface of the peripheral contact via structure, wherein the through-hole structure is formed on the bottom surface of the peripheral contact via structure and on the lower portion of the sidewall of the peripheral contact via structure.

[0304] In some embodiments, a method of manufacturing a semiconductor device includes: forming active regions and isolation components on a substrate, wherein each of the active regions includes a corresponding channel region and a corresponding source / drain region adjacent to the corresponding channel region; forming a gate structure, wherein each of the gate structures is in contact with at least three surfaces of a corresponding one of the channel regions; forming an epitaxial component over the source / drain region, wherein the epitaxial component includes a first source / drain component configured to be biased at a global source power supply voltage and a second source / drain component configured to be biased at a global drain power supply voltage; forming a front-side global source power supply voltage grid structure on the epitaxial component, wherein the front-side global source power supply voltage grid structure is electrically connected to the first source / drain component through a front-side source / drain contact via structure; and forming a front-side global source power supply voltage grid structure on the epitaxial component. An interconnect structure is fabricated on a voltage grid structure, wherein the interconnect structure includes interconnect layers, each of the interconnect layers including a metal line disposed in a respective dielectric layer, wherein at least one of the metal lines includes a curved top surface in a cross-sectional view; after fabricating the interconnect structure, a flat back-side surface is formed on the back side of the active region by removing at least a back-side portion of the substrate; an assembly is disposed on a chuck in a plasma-based etching apparatus, the assembly including the interconnect structure, the active region, at least one material layer and a patterned photoresist layer, and the assembly is oriented such that a front-side global source power supply voltage grid structure is electrically connected to the chuck; and the back-side surface of a first source / drain component is exposed by performing a back-side anisotropic etching process, wherein the back-side anisotropic etching process forms a back-side contact via cavity through at least one material layer.

[0305] In some embodiments, the component is disposed on a chuck in a plasma-based etching apparatus; and during a back-side anisotropic etching process, a front-side global source power supply voltage grid structure is electrically connected to the chuck.

[0306] In some embodiments, at least one material layer includes a back-side contact layer dielectric layer; and a back-side anisotropic etching process etches a back-side contact via cavity through the back-side contact layer dielectric layer, such that the back-side surface of the first source / drain component is exposed to the back-side contact via cavity.

[0307] In some embodiments, the method further includes: forming a back-side contact via structure in a back-side contact via cavity on the back-side surface of the first source / drain component; and forming a back-side global source power supply voltage grid structure on the back-side contact via structure.

[0308] In some embodiments, the first source / drain component and the front-side global source power supply voltage grid structure include a charge rebalancing path through which local charges generated in the region adjacent to the first source / drain component flow to the chuck during a back-side anisotropic etching process; at least one material layer includes a semiconductor material layer; and the back-side anisotropic etching process includes a plasma-based anisotropic dielectric etching process that etches unmasked portions of the semiconductor material layer that are not masked by a patterned photoresist layer.

[0309] In some embodiments, a semiconductor device structure includes: a first field-effect transistor and a second field-effect transistor, laterally surrounded by an isolation component, wherein each of the first and second field-effect transistors includes a respective channel region laterally surrounded by the isolation component, a respective gate structure located on the channel region, and a source / drain component as an epitaxial component in contact with a respective sidewall of the channel region, wherein an etch stop layer covers the isolation component and the epitaxial component, and a dielectric layer covers the etch stop layer, wherein each of the epitaxial components includes a first layer adjacent to a respective sidewall of the channel region and a second layer away from the sidewall of the channel region, wherein the composition of the first layer is different from the composition of the second layer; an interconnect layer including a front dielectric material layer, a front metal interconnect structure, and a front-side global source power supply voltage grid structure located on the front side of the isolation component, wherein the front-side global source power supply voltage grid structure extends through a memory array region and a peripheral connection region. Furthermore, the front-side global source power supply voltage grid structure includes a first front contact via structure that contacts a first subset of the source / drain components of the first field-effect transistor, wherein a second subset of the source / drain components of the first field-effect transistor is electrically isolated from the front-side global source power supply voltage grid structure, wherein each of the interconnect layers includes a metal line disposed in a corresponding dielectric layer, wherein at least one of the metal lines includes a barrier layer connected to the corresponding dielectric layer and a filler metal isolated from the corresponding dielectric layer through the barrier layer, wherein the conductivity of the barrier layer is less than the conductivity of the filler metal; the back-side global source power supply voltage grid structure is disposed on the back side of the first field-effect transistor, the second field-effect transistor and the isolation component, and includes a back-side contact via structure that contacts the back surface of the first subset of the source / drain components, and also includes a feedthrough via structure that contacts the bottom surface of the first component of the front-side global source power supply voltage grid structure.

[0310] In some embodiments, a first component of the front global source power supply voltage grid structure includes a peripheral contact via structure having a top surface located in a horizontal plane, the horizontal plane including the top surface of the first front contact via structure.

[0311] In some embodiments, the first field-effect transistor, the second field-effect transistor, and the back-side contact via structure are located in the memory array region; the feedthrough via structure is located in the peripheral connection region; and the front-side global source power supply voltage grid structure and the back-side global source power supply voltage grid structure extend through the memory array region and the peripheral connection region.

[0312] In some embodiments, the front-side global source power supply voltage grid structure includes: a first metal line extending laterally along a first horizontal direction and located in the peripheral connection region and outside the memory array region; and a second metal line located above the first metal line and extending laterally along a second horizontal direction above the first metal line, and extending above the peripheral connection region and the memory array region.

[0313] In some embodiments, the first field-effect transistor includes a pair of pull-down transistors of a static random access memory (SRAM) cell; the second field-effect transistor includes a pair of pull-up transistors of an SRAM cell; the device structure includes a third metal line located above the second metal line and extending laterally along a first horizontal direction; and the front-side global source power supply voltage grid structure includes a first subset of the third metal line.

[0314] In some embodiments, the through-hole structure is located in the peripheral connection region and is arranged in a row extending laterally along a first horizontal direction and electrically connected to the first metal line, wherein: the memory array region includes a first boundary adjacent to the peripheral connection region and parallel to the first horizontal direction, and a second boundary parallel to the first horizontal direction and laterally spaced from the peripheral connection region; and the second boundary is laterally offset from the first boundary along the second horizontal direction, the lateral distance between the second boundary and the first boundary being greater than the lateral distance between the farthest surface of the second metal line and the first boundary along the second horizontal direction.

[0315] In some embodiments, the planar horizontal surface of the feedthrough via structure is coplanar with the planar horizontal surface of the back contact via structure; the feedthrough via structure includes a profile surface, the profile surface including a group of corresponding horizontal surface segments adjacent to the profile surface segments, the profile surface segments contacting the peripheral contact via structures in the front global source power supply voltage grid structure; and the feedthrough via structure has tapered sidewalls such that the lateral extent of the feedthrough via structure on the back side of the isolation member is greater than the lateral extent on the front side of the isolation member.

[0316] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Unless expressly stated otherwise herein, each embodiment described using the term "comprising" also inherently discloses other embodiments in which the word "comprising" is replaced by "consistent with" or "comprises from". When two or more elements are listed as alternatives in the same or different paragraphs, a Markus group comprising those two or more elements is also implicitly disclosed. In this disclosure, whenever the auxiliary verb "may" is used to describe the formation of an element or the execution of a process step, embodiments in which that element or process step is not performed are also explicitly contemplated, provided that the resulting apparatus or device can provide equivalent results. Therefore, when omitting the execution of the formation or processing step of an element can provide the same or equivalent results, the auxiliary verb "may" used to describe the execution of the element formation or processing step should also be interpreted as "may" or "may or may not". Equivalent results include slightly better and slightly worse results. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that they can be modified, replaced, and altered in various ways within this disclosure without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device structure, comprising: A first field-effect transistor and a second field-effect transistor are formed above a substrate, wherein each of the first field-effect transistor and the second field-effect transistor includes a corresponding channel region laterally surrounded by an isolation component, a corresponding gate structure formed on the corresponding channel region, a corresponding source / drain component, and a dielectric layer covering an etch stop layer, wherein the etch stop layer covers the isolation component and the source / drain component, wherein the height and width of the corresponding source / drain component are different, and the width of the corresponding source / drain component is greater than the width of the corresponding channel region, such that a portion of the corresponding source / drain component hangs over the isolation component, wherein the first field-effect transistor includes a first source / drain component, and the second field-effect transistor includes a second source / drain component; A front dielectric material layer and a front metal interconnect structure are formed above the first field-effect transistor and the second field-effect transistor. The front metal interconnect structure includes a front global source power supply voltage grid structure, which extends through the memory array region and the peripheral connection region and is formed on the first source / drain component. An interconnect structure is formed including interconnect layers, wherein each of the interconnect layers includes a metal line disposed in a dielectric layer, wherein at least one of the metal lines includes a barrier layer connected to the dielectric layer and a filler metal spaced apart from the dielectric layer by the barrier layer, wherein the conductivity of the barrier layer is less than the conductivity of the filler metal, and wherein, in a cross-sectional view, at least one of the metal lines includes a curved top surface. An assembly comprising the interconnect structure, the first field-effect transistor, the second field-effect transistor, and a back-side contact-level dielectric layer is provided, at least by removing a back-side portion of the substrate after forming the interconnect structure; and A feedthrough via structure is formed, wherein the feedthrough via structure passes through the back contact level dielectric layer on the bottom surface of the first component of the front global source power supply voltage grid structure in the peripheral connection area.

2. The method according to claim 1, further comprising: The first component of the front-side global source power voltage grid structure is physically exposed by etching through the feedthrough cavity through the back-side contact level dielectric layer and the isolation component; At least one conductive material is deposited in the feed through-hole cavity; as well as Excess portion of the at least one conductive material is removed from the outside of the feed through-hole cavity, wherein the remaining portion of the at least one conductive material within the feed through-hole cavity comprises the feed through-hole structure.

3. The method according to claim 1, further comprising: A back-side contact via structure is formed, wherein the back-side contact via structure passes through the back-side contact level dielectric layer on the bottom surface of the first source / drain component in the memory array region.

4. The method according to claim 3, further comprising: The back surface of the first source / drain component is physically exposed by etching a back contact via cavity that extends at least through the back contact layer dielectric layer, wherein the back contact via structure is formed in the back contact via cavity.

5. The method according to claim 4, further comprising: Etching through the feedthrough cavity that passes through the back contact level dielectric layer and the isolation component; At least one conductive material is deposited in the feed through-hole cavity and the back contact through-hole cavity; as well as Excess portions of at least one conductive material are removed from the outside of the feed through-hole cavity and the back contact through-hole cavity, wherein a first remaining portion of the at least one conductive material filling the feed through-hole cavity includes the feed through-hole structure, and a second remaining portion of the at least one conductive material filling the back contact through-hole cavity includes the back contact through-hole structure.

6. The method according to claim 2, wherein: The substrate includes a semiconductor material layer; The method includes patterning the semiconductor material layer into a channel region formed in the memory array region and a peripheral semiconductor material portion formed in the peripheral interconnect region; The first component of the front-side global source power supply voltage grid structure includes a peripheral contact via structure formed on the top surface of the peripheral semiconductor material portion; as well as The isolation component laterally surrounds the outer portion of the semiconductor material.

7. A method for manufacturing a semiconductor device, comprising: Active regions and isolation components are formed on a substrate, wherein each of the active regions includes a corresponding channel region and a corresponding source / drain region adjacent to the corresponding channel region; A gate structure is formed, wherein each of the gate structures is in contact with at least three surfaces of a corresponding one of the channel regions; An epitaxial component is formed above the source / drain region, wherein the epitaxial component includes a first source / source component configured to be biased at a global source power supply voltage and a second source / source component configured to be biased at a global drain power supply voltage; A front-side global source power supply voltage grid structure is formed above the epitaxial component, wherein the front-side global source power supply voltage grid structure is electrically connected to the first source / drain component through a front-side source / drain contact via structure; An interconnect structure is fabricated on the front-side global source power supply voltage grid structure, wherein the interconnect structure includes interconnect layers, wherein each of the interconnect layers includes a metal line disposed in a respective dielectric layer, wherein, in a cross-sectional view, at least one of the metal lines includes a curved top surface; After fabricating the interconnect structure, a flat back-side surface is formed on the back side of the active region by removing at least a back-side portion of the substrate. An assembly is disposed on a chuck in a plasma-based etching apparatus, the assembly including the interconnect structure, the active region, at least one material layer, and a patterned photoresist layer, and the assembly is oriented such that the front-side global source power supply voltage grid structure is electrically connected to the chuck; and The back surface of the first source / drain component is exposed by performing a back-side anisotropic etching process, wherein the back-side anisotropic etching process forms a back-side contact via cavity through the at least one material layer.

8. A semiconductor device structure, comprising: A first field-effect transistor and a second field-effect transistor are laterally surrounded by an isolation component. Each of the first and second field-effect transistors includes a corresponding channel region laterally surrounded by the isolation component, a corresponding gate structure located on the channel region, and a source / drain component as an epitaxial component in contact with a corresponding sidewall of the channel region. An etch stop layer covers the isolation component and the epitaxial component, and a dielectric layer covers the etch stop layer. Each of the epitaxial components includes a first layer adjacent to a corresponding sidewall of the channel region and a second layer away from the sidewall of the channel region. The composition of the first layer is different from the composition of the second layer. An interconnect layer includes a front dielectric material layer, a front metal interconnect structure, and a front global source power voltage grid structure located on the front side of the isolation component. The front global source power voltage grid structure extends through the memory array region and the peripheral connection region. The front global source power voltage grid structure includes a first front contact via structure contacting a first subset of the source / drain components of the first field-effect transistor. A second subset of the source / drain components of the first field-effect transistor is electrically isolated from the front global source power voltage grid structure. Each interconnect layer includes a metal line disposed in a corresponding dielectric layer. At least one of the metal lines includes a barrier layer connected to the corresponding dielectric layer and a fill metal isolated from the corresponding dielectric layer through the barrier layer. The conductivity of the barrier layer is less than the conductivity of the fill metal. A back-side global source power supply voltage grid structure is disposed on the back side of the first field-effect transistor, the second field-effect transistor, and the isolation component, and includes a back-side contact via structure that contacts the back-side surface of a first subset of the source / drain components, and also includes a feedthrough via structure that contacts the bottom surface of a first component of the front-side global source power supply voltage grid structure.

9. The semiconductor device structure according to claim 8, wherein, The front-side global source power supply voltage grid structure includes: A first metal line extends laterally along a first horizontal direction and is located within the peripheral connection area and outside the memory array area; and The second metal line is located above the first metal line and extends laterally above the first metal line along a second horizontal direction, and extends above the peripheral connection area and the memory array area.

10. The semiconductor device structure according to claim 9, wherein: The first field-effect transistor includes a pair of pull-down transistors for a static random access memory cell; The second field-effect transistor includes a pair of pull-up transistors of the static random access memory cell; The semiconductor device structure includes a third metal line, which is located above the second metal line and extends laterally along the first horizontal direction. as well as The front-side global source power supply voltage grid structure includes a first subset of the third metal lines.

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