Integrated circuit device and method of manufacturing the same

Abstract

Embodiments of the present invention provide an integrated circuit device and a method of manufacturing an integrated circuit. A first interconnect element of a first interconnect layer of an interconnect structure is located in a memory cell region of an integrated circuit device. The first interconnect element extends in a first direction in a top view. A second interconnect element is disposed in the first interconnect layer and is located in a peripheral region of the integrated circuit device. The second interconnect element extends in the first direction. The second interconnect element is not aligned with the first interconnect element in the top view in a second direction that is different from the first direction. A third interconnect element is disposed in the first interconnect layer. The third interconnect element spans the memory cell region and the peripheral region and is coupled to the first interconnect element and the second interconnect element.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the semiconductor field, and more specifically, to integrated circuit devices and methods of manufacturing the same. Background Technology

[0002] The electronics industry has an ever-increasing demand for smaller, faster electronic devices capable of supporting a large number of increasingly complex and sophisticated functions. Therefore, the semiconductor industry continues to pursue the manufacture of low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been largely achieved by shrinking the size of semiconductor ICs (e.g., the smallest component size), thereby increasing production efficiency and reducing associated costs. However, this approach also increases the complexity of semiconductor processes. Therefore, similar advancements in semiconductor processes and technologies are needed to enable the continued progress of semiconductor ICs and devices.

[0003] As IC device sizes shrink, device parasitic effects (e.g., parasitic resistance and / or parasitic capacitance) can become problematic. If not adequately addressed, these parasitic effects can degrade IC device performance, resulting in slower speeds and / or excessive power consumption. Therefore, while existing IC devices are generally sufficient for their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0004] An embodiment of the present invention provides an integrated circuit device comprising: a first interconnect element disposed in a dielectric material of a first interconnect layer of an interconnect structure, wherein: the first interconnect element is located in a first region of the integrated circuit device; the first interconnect element extends along a first horizontal direction in a top view; and the dielectric constant of the dielectric material is less than 3.9; a second interconnect element disposed in the dielectric material of the first interconnect layer of the interconnect structure, wherein: the second interconnect element is located in a second region of the integrated circuit device adjacent to the first region; the second interconnect element extends along the first horizontal direction in the top view; and the second interconnect element is not aligned with the first interconnect element in a second horizontal direction different from the first horizontal direction in the top view; and a third interconnect element disposed in the dielectric material of the first interconnect layer of the interconnect structure, wherein: the third interconnect element spans the first region and the second region and is coupled to the first interconnect element and the second interconnect element; and at least one of the first interconnect element, the second interconnect element, or the third interconnect element has a bent end portion in the top view.

[0005] Another embodiment of the present invention provides an integrated circuit manufacturing method, comprising: forming a first segment of a signal line in a first interconnect layer, wherein: the first interconnect layer is the bottom layer of a multilayer interconnect structure in a first region of an integrated circuit device; and the first segment of the signal line extends along a first direction; forming a second segment of the signal line in a second interconnect layer of the multilayer interconnect structure in the first region; and an island-shaped connection structure, wherein: the second interconnect layer is located above the first interconnect layer; the second segment of the signal line extends along the first direction, while the island-shaped connection structure extends along a second direction different from the first direction; and the second segment of the signal line and the island-shaped connection structure. The signal line is electrically coupled to a first segment via a first conductive via and a second conductive via located between the first interconnect layer and the second interconnect layer, respectively; and a third segment of the signal line is formed in a second region of the integrated circuit device, wherein: the third segment of the signal line extends along the first direction and crosses the boundary between the first region and the second region; the third segment of the signal line is formed in a third interconnect layer of the multilayer interconnect structure, the third interconnect layer being located on top of the second interconnect layer; and the third segment of the signal line is electrically coupled to the island-shaped connection structure via a third conductive via located between the second interconnect layer and the third interconnect layer.

[0006] Another embodiment of the present invention provides an integrated circuit manufacturing method, comprising: forming a first signal line and a first segment of a second signal line in a memory device, wherein: the first signal line and the first segment of the second signal line are both formed in a first interconnect layer of a multilayer interconnect structure; the first signal line extends along a first direction; the first segment of the second signal line extends along a second direction different from the first direction; the first signal line is formed in a first region of the memory device; and the first segment of the second signal line is formed in the first region of the memory device and a second region adjacent to the first region; forming a second segment of the second signal line in a second interconnect layer of the multilayer interconnect structure in the first region, wherein: the second interconnect layer is located on top of the first interconnect layer; and the main portion of the second segment of the second signal line extends along the second direction and is connected by a first conductive path. A third segment of the second signal line is formed in a third interconnect layer of the multilayer interconnect structure in the first region, wherein: the third interconnect layer is located on top of the second interconnect layer; and the main portion of the third segment of the second signal line extends along the second direction and is electrically coupled to the second segment of the second signal line through a second conductive via; and an island-shaped connection structure is formed in the first interconnect layer, wherein: the island-shaped connection structure is located between the first signal line and the first segment of the second signal line in the second direction; and the island-shaped connection structure is electrically coupled to the second segment of the second signal line through a third conductive via; wherein at least one of the first signal line, the first segment of the second signal line, the second segment of the second signal line, or the third segment of the second signal line includes a bent end portion. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1A This is a schematic 3D diagram of a semiconductor device.

[0009] Figure 1B This is a top view diagram of a semiconductor device.

[0010] Figure 1C This is a cross-sectional side view of a semiconductor device.

[0011] Figure 2 This is a circuit diagram of an SRAM cell.

[0012] Figures 3A to 3B These are top and perspective views of super SRAM devices according to various embodiments of the present disclosure.

[0013] Figures 4A to 4B A top view illustrating signal routing according to some embodiments of this disclosure.

[0014] Figures 5A to 5C A top view illustrating signal routing according to some other embodiments of this disclosure.

[0015] Figure 6 A top view illustrating signal routing according to other embodiments of this disclosure.

[0016] Figure 7 Top views illustrating various embodiments of the interconnection structures according to the present disclosure.

[0017] Figure 8 A cross-sectional side view is provided to illustrate various embodiments of the IC device including an interconnect structure according to the present disclosure.

[0018] Figure 9 This is a block diagram of a semiconductor manufacturing system.

[0019] Figures 10 to 12 Flowcharts illustrating various methods according to the various embodiments of this disclosure. Detailed Implementation

[0020] This invention provides numerous different embodiments or examples for implementing various components of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components do not need to be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for the purpose of brevity and clarity and does not specify the relationship between the various embodiments and / or configurations discussed. Moreover, embodiments in this disclosure of forming a component on, connected to, and / or coupled to another component may include embodiments formed by direct contact between components, and may also include embodiments that can form additional components between components, such that the components do not need to be in direct contact. Additionally, spatially related terms (e.g., “lower,” “higher,” “horizontal,” “vertical,” “above,” “above,” “below,” “under,” “upward,” “downward,” “top,” “bottom,” etc., and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.)) are used to facilitate the description of the relationship between one component and another. Spatially related terms are intended to cover different orientations of the device containing the components. Furthermore, when numbers or ranges of numbers are described using terms such as “about,” “approximately,” etc., it is intended to cover numbers within a reasonable range of the described numbers, for example, within + / -10% of the described numbers or other values ​​understood by those skilled in the art. For example, the term "about 5 nanometers (nanometers)" encompasses a size range from 4.5 nanometers to 5.5 nanometers. However, other ranges are possible, as is known to those skilled in the art and may depend on the process.

[0022] In recent years, advanced transistors (e.g., FinFET devices and / or Gate All-Around (GAA) devices) have been used to implement various types of integrated circuit (IC) applications, including electronic memory applications (e.g., Static Random Access Memory (SRAM) devices). However, some types of SRAM devices still use interconnect schemes that can lead to inefficiencies (e.g., slower device speeds and / or excessive power consumption). This disclosure addresses these problems with various novel interconnect schemes, such as the electrical routing of bit lines (BL), anti-phase lines (BLB), or word lines (WL) signals from a memory cell region of an SRAM device to a surrounding region (e.g., a region corresponding to circuitry outside the memory cell array), referred to in more detail below as Super SRAM.

[0023] Now for reference Figures 1A to 1C This section will describe the basic structures of exemplary FinFET and GAA devices that can be used to implement SRAM devices. Specifically, Figure 1A and Figure 1BA three-dimensional perspective view and a top view of a portion of an IC device 90 in the form of a FinFET are illustrated. The IC device 90 may be an intermediate device manufactured during the manufacture of an IC (or a portion thereof) and may include portions of an SRAM device. It should be understood that the IC device 90 may also be used to implement other types of devices, including but not limited to logic circuits, communication circuits, processors, or passive components (e.g., resistors, capacitors, and inductors). Furthermore, although the illustrated IC device 90 is a three-dimensional FinFET device, the concepts of this disclosure are also applicable to planar FET devices and GAA devices.

[0024] refer to Figure 1A The IC device 90 includes a substrate 110. The substrate 110 may contain elemental (single-element) semiconductors, such as silicon, germanium, and / or other suitable materials; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors, such as silicon germanium, gallium arsenide phosphide, indium aluminum arsenide, aluminum gallium arsenide, indium gallium arsenide, indium gallium arsenide, indium gallium phosphide, indium gallium arsenide phosphide, and / or other suitable materials. The substrate 110 may be a single-layer material with a uniform composition. Alternatively, the substrate 110 may contain multiple material layers with similar or different compositions suitable for IC device fabrication. In one example, the substrate 110 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 may contain a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions (e.g., source / drain regions) may be formed in or on the substrate 110. Depending on design requirements, the doped regions may be doped with n-type dopants (e.g., phosphorus or arsenic) and / or p-type dopants (e.g., boron). The doped regions may be formed directly on the substrate 110, in a p-type well structure, in an N-type well structure, in a double-well structure, or using a raised structure. The doped regions may be formed using dopant implantation, in-situ doped epitaxial growth, and / or other suitable techniques.

[0025] A three-dimensional active region 120 is formed on the substrate 110. The active region 120 is an elongated fin-like structure protruding upward beyond the substrate 110. Therefore, the active region 120 may also be referred to hereinafter as the fin structure 120. It should be noted that in the case of a GAA device, the active region may include channels formed above the fin base / mesa, but not the fin base / mesa itself. Conversely, the active region of a GAA device, which will be discussed in more detail below, includes nanostructures, such as nanosheets. In any case, the fin structure 120 can be fabricated using suitable processes, including photolithography and etching processes. The photolithography process may include forming a photoresist layer over the substrate 110, exposing the photoresist layer to a pattern, performing a post-exposure baking process, and developing the photoresist layer to form a mask element (not shown) containing the photoresist. Then, using the mask element, grooves are etched in the substrate 110, leaving the fin structure 120 on the substrate 110. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 may be formed using a dual-patterning or multi-patterning process. Generally, dual-patterning or multi-patterning processes combine photolithography and self-aligned processes to allow the creation of patterns with smaller pitches than that achievable using a single direct photolithography process. As an example, a layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed on the sides of the patterned layer using a self-aligned process. The layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 120.

[0026] The IC device 90 also includes source / drain components 122 formed over the fin structure 120. The source / drain components 122 may comprise an epitaxial layer epitaxially grown on the fin structure 120. The IC device 90 further includes an isolation structure 130 formed over the substrate 110. The isolation structure 130 electrically isolates various components of the IC device 90. The isolation structure 130 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-dielectric-coefficient dielectric materials, and / or other suitable materials. In some embodiments, the isolation structure 130 may comprise shallow trench isolation (STI) components. In one embodiment, the isolation structure 130 is formed by etching trenches in the substrate 110 during the formation of the fin structure 120. The trenches can then be filled with the isolation material described above, followed by a chemical mechanical planarization (CMP) process. Other isolation structures (e.g., field oxide, localized silicon oxide (LOCOS), and / or other suitable structures) may also be implemented as the isolation structure 130. Alternatively, the isolation structure 130 may comprise a multi-layer structure, for example, having one or more thermal oxide pad layers.

[0027] IC device 90 also includes a gate structure 140 formed above fin structures 120 and bonded to three sides of each fin structure 120. The gate structure 140 may be a dummy gate structure (e.g., including an oxide gate dielectric layer and a polysilicon gate electrode), or a high-dielectric-coefficient metal gate (HKMG) structure including a high-dielectric-coefficient gate dielectric layer and a metal gate electrode, wherein the HKMG structure is formed by replacing the dummy gate structure. Although not shown herein, the gate structure 140 may include additional material layers, such as an interface layer, a capping layer, other suitable layers, or combinations thereof, above the fin structures 120.

[0028] refer to Figure 1B Multiple fin structures 120 are longitudinally oriented along the X direction (e.g., their dimensions in the X direction are larger than their dimensions in other directions), and multiple gate structures 140 are longitudinally oriented along the Y direction (e.g., their dimensions in the Y direction are larger than their dimensions in other directions), that is, substantially perpendicular to the fin structures 120. In many embodiments, the IC device 90 includes additional components, such as gate spacers disposed along the sidewalls of the gate structures 140, a hard mask layer disposed above the gate structures 140, and multiple other components.

[0029] Figure 1C This is a schematic cross-sectional side view illustrating a portion of an IC device 200 in the form of a GAA device (hereinafter also referred to as GAA device 200). It should be understood that in some embodiments, the GAA device 200 may be an NFET, or in other embodiments, it may be a PFET. The GAA device 200 may also be used to implement at least multiple portions of an SRAM device according to various embodiments of this disclosure.

[0030] refer to Figure 1C The cross-sectional view of the GAA device 200 is taken along the X to Z plane, where the X direction (and...) Figure 1A The X direction is the same as the horizontal direction, and the Z direction is the same as the horizontal direction. Figure 1AThe Z-direction is the vertical direction. The GAA device 200 includes a substrate 110 and a vertically projecting fin structure 120 protruding from the substrate 110. This fin structure 120 may be similar to the fin structure 120 discussed above. In some embodiments, the fin structure 120 comprises a semiconductor material, such as silicon. The GAA device 200 includes source / drain components 220, which may be similar to the source / drain components 122 discussed above. It should be noted that the source / drain component 220 may refer to either the source or the drain, individually or simultaneously, depending on the context. The source / drain components 220 are formed above the fin structure 120, and a portion 220' of each source / drain component 220 may protrude downwards (in the Z-direction) into the fin structure 120. In embodiments where the GAA device 200 is an NFET, the source / drain components 220 comprise silicon phosphide. In embodiments where the GAA device 200 is a PFET, the source / drain component 220 comprises silicon germanium.

[0031] The GAA device 200 includes multiple channels, for example, Figure 1C The channel 230 shown is an example. Each channel 230 contains a semiconducting material, such as silicon or a silicon compound. The channel 230 is a nanostructure (e.g., in the size range of a few nanometers) and may also have an elongated shape and extend along the X direction. In some embodiments, the channel 230 may each have a nanowire shape, a nanosheet shape, or a nanotube shape, etc. The cross-sectional profile of the nanowire, nanosheet, or nanotube may be circular, square, rectangular, hexagonal, elliptical, or a combination thereof.

[0032] In some embodiments, the lengths of the channels 230 (e.g., measured in the X direction) may be different from each other. For example, the length of one channel 230 may be less than the length of another channel 230. In some embodiments, each channel 230 may have a different thickness.

[0033] In some embodiments, the spacing (e.g., measured in the Z direction) between channels 230 (each channel and its adjacent channels) is in the range of about 2 nanometers to about 12 nanometers. In some embodiments, the thickness (e.g., measured in the Z direction) of each channel 230 is in the range of about 5 nanometers to about 2 nanometers. In some embodiments, the width (e.g., in the Z direction) of each channel 230 is in the range of about 5 nanometers to about 2 nanometers. Figure 1A (Measured in the Y direction) in the range of approximately 15 nanometers to approximately 150 nanometers. Multiple interfacial layers (ILs) may also be formed on the upper and lower surfaces of the channel 230.

[0034] The GAA device 200 also includes a gate structure disposed above and between channels 230. The gate structure may include a gate dielectric layer 250. In some embodiments, the gate dielectric layer 250 includes a high-dielectric-coefficient gate dielectric layer. The gate structure further includes one or more metal gate electrodes 260. The metal gate electrodes may include work function metal layers. In embodiments where the GAA device 200 is an NFET, the one or more work function metal layers include N-type work function metal layers, such as TiAlC. In embodiments where the GAA device 200 is a PFET, the multiple work function metal layers may include P-type work function metal layers, such as TiN.

[0035] The metal gate electrode also includes filler metal. In portions of the gate structure formed above channel 230, filler metal is formed above one or more work function metal layers. In some embodiments, the one or more work function metal layers may be U-shaped and surround the filler metal, and the gate dielectric layer 250 may also be U-shaped and surround the one or more work function metal layers. In portions of the gate structure formed between channels 230, the filler metal (in cross-sectional view) is circumferentially surrounded by one or more work function metal layers, and the one or more work function metal layers are subsequently circumferentially surrounded by the gate dielectric layer 250. It should be understood that the gate structure may also include an adhesive layer formed between the one or more work function metal layers and the filler metal to increase adhesion. However, for simplicity, this adhesive layer is not specifically described here.

[0036] The GAA device 200 also includes a dielectric material 265 and internal spacers 270 disposed on the sidewalls of the gate dielectric layer 250. In some embodiments, the dielectric material 265 may include gate spacers and / or etch stop layers. The internal spacers 270 are also disposed perpendicularly in the Z direction between the channels 230. The gate spacers and internal spacers 270 may include dielectric materials, such as low dielectric constant materials (e.g., SiOCN, SiON, SiN, or SiOC). It is worth noting that the formation of the internal spacers (including the corresponding manufacturing steps described above) may be optional. That is, in some embodiments, the formation of the internal spacers may be omitted, and the internal spacers may not be present in the final structure.

[0037] Additional dielectric layers (e.g., dielectric layers 275 and 280) may be formed over the gate electrode 260 and the dielectric material 265. As a non-limiting example, these dielectric layers may include interlayer dielectric (ILD), mask layers, or etch stop layers. Conductive vias or conductors extending vertically through dielectric layers 275 and 280 of the GAA device 200 may be formed to provide electrical connections to components of the GAA device. For example, the GAA device 200 may include source / drain contacts 285 formed over source / drain portions 220. Source / drain contacts 285 may contain conductive materials, such as cobalt, copper, aluminum, tungsten, or combinations thereof. Source / drain contacts 285 are surrounded by one or more layers, such as barrier layers, which help prevent or reduce material diffusion from and into source / drain contacts 285. In some embodiments, the barrier layers comprise TiN and SiN. A silicide layer 290 may also be formed between the source / drain component 220 and the source / drain contact 285 to reduce the source / drain contact resistance. In some embodiments, the silicide layer 290 may comprise a metal silicide material, such as cobalt silicide. Similarly, a gate contact 295 is formed over one of the gate electrodes 260 to establish an electrical connection with the gate structure. In some embodiments, the gate contact 295 may comprise a conductive material similar to that of the source / drain contact 285.

[0038] Figure 2 An example type of electronic memory device is described, in which transistors (e.g., planar transistors, FinFET transistors, or GAA transistors, etc.) may be implemented. Figure 2 In a specific example, a circuit diagram of an exemplary SRAM device is illustrated, such as a single-ended SRAM cell (e.g., a 1-bit SRAM cell) 299. The single-ended SRAM cell 299 includes pull-up transistors PU1 and PU2, pull-down transistors PD1 and PD2, a transmission gate transistor PG1, and a transmission gate transistor PG2. As shown in the circuit diagram, transistors PU1 and PU2 are P-type transistors, and transistors PG1, PG2, PD1, and PD2 are N-type transistors. According to various embodiments of this disclosure, the transmission gate transistors PG1, PG2, PD1, and PD2 are implemented using thinner spacers than the pull-up transistors PU1 and PU2. In the illustrated embodiment, since the SRAM cell 299 contains six transistors, it can also be referred to as a 6T SRAM cell. In any case, transistors (e.g., FinFET or GAA transistors) can be used to implement transmission gate transistor PG1, transmission gate transistor PG2, pull-down transistor PD1, pull-down transistor PD2, pull-up transistor PU1 and / or pull-up transistor PU2.

[0039] The drains of pull-up transistor PU1 and pull-down transistor PD1 are coupled together, and the drains of pull-up transistor PU2 and pull-down transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form a first data latch. The gates of transistors PU2 and PD2 are coupled together and to the drains of transistors PU1 and PD1 to form a first storage node SN1, and the gates of transistors PU1 and PD1 are coupled together and to the drains of transistors PU2 and PD2 to form a complementary first storage node SNB1. The sources of pull-up transistors PU1 and PU2 are coupled to the power supply voltage Vcc (also known as Vdd), and the sources of pull-down transistors PD1 and PD2 are coupled to voltage Vss, which may be electrically grounded in some embodiments.

[0040] The first storage node SN1 of the first data latch is coupled to a signal line called BL via a transmission gate transistor PG1, and the complementary first storage node SNB1 is coupled to a complementary signal line called BLB via a transmission gate transistor PG2. The first storage node SN1 and the complementary first storage node SNB1 are complementary nodes and are generally at opposite logic levels (logic high or logic low). The gates of transmission gate transistors PG1 and PG2 are coupled to WL, which can be used to select memory cells in a specific column. The SRAM device (e.g., SRAM cell 299) can be implemented using a "planar" transistor device, a FinFET device, and a / GAA device.

[0041] Figure 3A and Figure 3B The illustrations provide partial top views and partial three-dimensional perspective views of the IC device 300 according to various embodiments of the present disclosure. Figure 3A The top view illustrates the horizontal plane defined by the X and Y directions in the horizontal direction, and Figure 3B The three-dimensional diagram is defined by the horizontal X and Y directions, and the vertical Z direction. The IC device 300 may include the components discussed above. Figure 2 The SRAM cell 299, and the SRAM cell 299 may be at least partially accessed via the reference above. Figures 1A to 1C The discussion focuses on implementing GAA or FinFET transistors.

[0042] Figures 3A to 3B This section partially describes the various layers of the multilayer interconnect (MLI) structure of the IC device 300. The MLI structure may include at least one interconnect layer (also referred to as a metal layer) disposed on the back side (BS) of the IC device. Figure 3AThe layer is denoted as BMO. The MLI structure further includes multiple interconnect layers disposed on the front side (FS) of the IC device, with the front side opposite the back side. As a non-limiting example, the interconnect layers (M0, M1, M2, and M3) are illustrated as the front interconnect layers of the MLI structure. In this context, the M0 layer is the bottommost interconnect layer of the interconnect structure and is located vertically in the Z direction directly above the various microelectronic components (e.g., transistors) of the IC device 300. The M1 layer is vertically located in the Z direction above the M0 layer, the M2 layer is vertically located in the Z direction above the M1 layer, and the M3 layer is vertically located in the Z direction above the M2 layer. In other words, the M0 layer (as the bottom layer) is disposed closest to the microelectronic components of the IC device 300, the M1 layer is located further away from the microelectronic components of the IC device 300 than the M0 layer, the M2 layer is located further away from the microelectronic components of the IC device 300 than the M1 layer, and the M3 layer is located further away from the microelectronic components of the IC device 300 than the M2 layer.

[0043] Each interconnect layer in the MLI structure can be used to provide electrical routing, establish electrical connections, and / or transmit / carry various signals for the components of the IC device 300. For example, the M0 layer can be configured to transmit the power supply voltage Vdd, the ground voltage Vss, and the BL and / or BLB signals of the SRAM. The M0 and M1 layers can be configured to transmit the BL and / or BLB signals of the SRAM. The M2 and M3 layers can be configured to transmit the WL signals of the SRAM.

[0044] It should be noted that the IC device 300 of this paper implements an SRAM called Super SRAM, which utilizes a unique layout scheme to reduce device parasitic effects. In this regard, while other devices (including other types of SRAM devices) may orient metal lines in adjacent interconnect layers in a vertical-horizontal direction, the Super SRAM scheme of this paper does not use this method in layers M1 and M2. For example, in other types of devices, metal lines in layer M0 may extend in the X direction, metal lines in layer M1 may extend in the Y direction, metal lines in layer M2 may extend in the X direction, and metal lines in layer M3 may extend in the Y direction. Conversely, in the Super SRAM scheme, although metal lines in layer M0 may still extend in the X direction (similar to other types of devices), metal lines in layer M1 may also extend in the X direction (opposite to the Y direction), and metal lines in layer M2 may extend in the Y direction (opposite to the X direction). However, in the M3 layer, according to the Super SRAM scheme, the metal lines can be restored to "normal" orientation and extend along the Y direction, similar to other types of SRAM devices.

[0045] Another component of the Super SRAM solution is that the BL and BLB signal lines (e.g., implemented as metal lines extending in the X direction) can be decomposed and distributed across layers M0 and M1. More specifically, other types of SRAM devices typically implement the BL and BLB signal lines as continuous metal lines extending in the X direction in layer M0 (e.g., continuously penetrating the memory cell area of ​​the SRAM device), and the WL signal line as a continuous metal line extending in the Y direction in layer M1 (e.g., continuously penetrating the memory cell area). However, adjacent BL and / or BLB signal lines can act as conductive plates separated by a dielectric material (e.g., an insulating material disposed between the metal lines corresponding to the BL and / or BLB signal lines), thus mimicking a capacitor that generates parasitic capacitance. As device sizes continue to shrink, the parasitic capacitance derived from such capacitors may increasingly reduce device performance, potentially leading to slower speeds and / or excessive power consumption.

[0046] To address the parasitic capacitance issue discussed above, the super SRAM solution decomposes the BL and / or BLB signal lines in the M0 layer and utilizes the metal lines in the M1 layer to route the BL and BLB signals. For example, as... Figure 3A As shown, the BL signal line, which was originally intended to be implemented as a continuous metallic line in layer M0, is decomposed into BL signal line segment 310A in layer M0 and multiple BL signal line segments 310B in layer M1 above. More specifically, a portion of the BL signal line originally intended to be implemented on the other side (in the X direction) of BL signal line segment 310A in layer M0 is implemented as BL signal line segment 310B in layer M1. Missing portions of these BL signal line segments in layer M0 are indicated by dashed / broken lines in layer M0. It should be noted that, for simplicity, only one of the BL signal line segments 310B is shown in layer M1, but it should be understood that multiple BL signal line segments 310B can be implemented in layer M1, for example, one on each side of BL signal line segment 310A (which itself is still located in layer M0).

[0047] As another example, the BLB signal line, originally intended to be implemented as a continuous metallic line in layer M0, is broken down into BLB signal line segments 312A and 312B in layer M0 and BLB signal line segment 312C in layer M1 above. More specifically, a portion of the BLB signal line originally intended to be implemented in layer M0 between BLB signal line segments 312A and 312B (in the X direction) is implemented as BLB signal line segment 312C in layer M1. The absence of this portion of the BLB signal line segment in layer M0 is indicated by a dashed line / dashed box in layer M0.

[0048] It should be understood that, in the examples of BL and BLB discussed above, conductive vias can be implemented between the M0 and M1 layers to electrically connect BL signal line segments 310A and 310B together, and to electrically connect BLB signal line segments 312A, 312B, and 312C together. Because the two opposing conductive plates (e.g., metal wires for implementing BL and / or BLB signal lines) are no longer located in the same interconnect layer, but in different interconnect layers (e.g., M0 layer to M1 layer), the Super SRAM scheme provides reduced parasitic capacitance.

[0049] One consequence of implementing portions of the BL and BLB signal lines on layer M1 is that components previously implemented on layer M1 may need to be moved upwards (e.g., to other interconnect layers above layer M1). For example, other types of SRAM devices may implement the WL signal line on layer M1. However, since layer M1 is used to implement the BL and BLB signal lines according to the Super SRAM scheme, the WL signal line 320 is moved upwards to layer M2 and implemented as a metal line extending in the Y direction on layer M2. It should be noted that layer M3 can also be used to implement the WL signal line. For example, as Figure 3B As shown, the WL signal line in layer M2 is electrically and physically connected to the WL signal line in layer M3 via the V2 rail, which is a through-hole implemented as a rail. The V2 rail follows the top view shape of the WL signal line in layer M2 or layer M3, although the V2 rail may not have the exact same dimensions as the WL signal line in layer M2 or layer M3.

[0050] Another result of implementing portions of the BL and BLB signal lines in layer M1 is a change in the orientation of the metal lines in layers M1 and M2. As discussed above, other types of SRAM devices implement metal lines extending in the Y direction in layer M1 and in the X direction in layer M2, but this Super SRAM scheme implements metal lines extending in the X direction in layer M1 (e.g., BL signal line segments 310B and 312C) and in the Y direction in layer M2 (e.g., WL signal line 320). The metal lines in layer M3 can be oriented in the same direction (i.e., the Y direction) as other types of SRAM devices. In some embodiments, the metal lines in layer M3 can also be used to implement WL signal lines. Additionally, electrical power signals (e.g., power supply voltage Vdd) can be implemented in layer M0, and electrical ground signals (e.g., ground voltage Vss) can be implemented in layer M4 (e.g., the interconnect layer immediately above layer M3), similar to other types of SRAM devices.

[0051] It should be understood that changes in the orientation of the metal lines in layers M1 and M2 may not apply to every region of the IC device 300. More specifically, a super SRAM device (and other types of SRAM devices) may include a memory cell region and a surrounding region. In some embodiments, the memory cell region is a space where multiple SRAM devices can be implemented (e.g., Figure 2 The area of ​​SRAM cells 299). As an SRAM cell array, the SRAM devices in the memory cell area may contain blocks (e.g., an array) that are substantially the same as the SRAM cells implemented as repeating circuit units. In some embodiments, the SRAM devices in the memory cell area are for use with reference to the above. Figures 1A to 1C The discussion focuses on FinFET and GAA transistors for implementation. However, it should be understood that other types of transistors (e.g., planar transistors) can also be used to implement SRAM devices in memory cell areas.

[0052] In contrast, the peripheral region may be located adjacent to the memory cell area and may include various areas surrounding the memory cell area. The peripheral region may include circuitry outside the memory cell array. As a non-limiting example, the peripheral region of IC device 300 includes an input / output (I / O) area, a WL driver area, a control circuitry area, a standard cell area, and / or an electronically programmable fuse (eFuse) area. In some embodiments, the I / O area includes electrical circuitry for processing I / O of the SRAM device for the SRAM cell array, the WL driver area includes electrical circuitry for driving the WL of the SRAM device for the SRAM cell array, the control circuitry area includes electrical circuitry for controlling the electrical operation of the SRAM device for the SRAM cell array, the standard cell includes logic circuitry for performing Boolean logic operations, and the electronically programmable fuse area includes miniature electronically programmable fuses configured to enable dynamic real-time reprogramming of the chip. The I / O area, WL driver area, control circuitry area, standard cell area, and / or electronically programmable fuse area may be collectively or individually referred to as the peripheral region. It should also be understood that in some embodiments, one or more of the regions discussed above (e.g., standard cell regions) may be considered as regions separate from SRAM cell regions and surrounding regions.

[0053] Regardless of the specific types of regions included in the surrounding area, it should be understood that, according to the various embodiments of this disclosure, changes in the orientation of metal lines in layers M1 and M2 may not apply to the surrounding area (or other types of non-SRAM regions). In other words, although metal lines in the memory cell region may extend in the X direction in layer M1 and in the Y direction in layer M2, metal lines in the surrounding area (or other types of non-SRAM regions) may extend in the Y direction in layer M1 and in the X direction in layer M2.

[0054] Figures 4A to 4BSRAM layout design 400 and its revised version, Super SRAM layout design 401, are explained separately. More specifically... Figure 4A and Figure 4B All are top views defined by the horizontal X and Y directions. However, it should be noted that... Figures 4A to 4B The X and Y directions relative to Figure 3A The X and Y directions are rotated by 90 degrees. In other words, Figure 3A In the middle, the Y direction is displayed as a horizontal extension and the X direction as a vertical extension, while Figure 4A and Figure 4B The X-direction is displayed as a horizontal extension and the Y-direction as a vertical extension.

[0055] SRAM layout design 400 and revised Super SRAM layout design 401 each illustrate specific segments of the IC device 300 (implemented herein as an SRAM device) corresponding to the edge portions of memory cell region 410 and peripheral region 411. In some embodiments, memory cell region 410 may include SRAM cells (e.g., cells of a bit cell array) discussed above, while peripheral region 411 may include peripheral regions (including I / O areas, WL driver areas, control circuit areas, standard cell areas, etc., but without SRAM cells). However, although SRAM layout design 400 can be referenced above... Figures 3A to 3B The described non-Super SRAM scheme can be implemented, but the revised Super SRAM layout design 401 can be implemented not only according to the Super SRAM scheme, but also according to the enhanced Super SRAM scheme that further improves the Super SRAM implementation method.

[0056] More specifically, the SRAM layout design 400 illustrates multiple interconnect elements (interconnect elements 420 to 428), each interconnect element being... Figure 4AThe memory cell region 410 extends along the X direction. In this example, interconnect elements 420, 424, and 428 are configured to carry an electrical ground signal (e.g., ground voltage Vss), interconnect elements 422 and 426 are configured to carry an electrical power signal (e.g., power supply voltage Vdd), interconnect elements 421 and 427 are configured to carry a BL signal, and interconnect elements 423 and 425 are configured to carry a BLB signal. Interconnect elements 420 to 428 are implemented in the bottommost interconnect layer (e.g., M0 layer) of the MLI structure. Meanwhile, the peripheral region 411 includes a plurality of interconnect elements 430 also implemented in the M0 layer. Interconnect elements 421, 423, 425 and 427 (corresponding to BL signal line and BLB signal line) in memory cell area 410 are electrically coupled to a subset of interconnect elements 430 through jumpers 440, 441, 442 and 443 in layer M1.

[0057] According to the SRAM layout design 400, one or more of interconnect elements 420 to 428 may extend continuously within the memory cell region 410. For example, interconnect elements 421, 423, 425, and 427 (corresponding to the BL signal line and the BLB signal line) may each extend continuously through multiple SRAM cells along the X direction. Conversely, as referenced above... Figures 3A to 3B The revised Super SRAM layout design discussed here will decompose these signal lines into multiple discrete segments and implement the segments in multiple interconnect layers (e.g., M0 layer and M1 layer) to reduce parasitic resistance.

[0058] For example, refer to Figure 4B The revised Super SRAM layout design 401 implements interconnect elements 461, 463, 465, and 467, which carry the BL signal, BLB signal, BLB signal, and BL signal, respectively. Compared to their corresponding interconnect elements 421, 423, 425, and 427 in the SRAM layout design 400, the interconnect elements 461, 463, 465, and 467 in the revised Super SRAM layout design 401 each correspond only to segments of the BL signal line, BLB signal line, BLB signal line, and BL signal line, respectively. In other words, interconnect element 461 (carrying the BL signal) can be a discrete (e.g., independent) interconnect element in the M0 layer because interconnect element 461 is not directly connected to any other interconnect element "to its left". Another section of the BL signal line is located "to the left" of interconnect element 461, but this section is separated from interconnect element 461 by a gap (filled with dielectric material in the actual IC device) (and not in... Figure 4B(See detailed illustration). This differs from the corresponding interconnect element 421, which extends continuously "to the left" through multiple SRAM cells. Interconnect element 461 and other interconnect elements 461 disposed "to the left" of interconnect element 461 are electrically coupled together through another interconnect element disposed in the upper M1 layer. Similarly, other interconnect elements 463, 465, and 467 are also discrete segments of BLB signal lines, BLB signal lines, and BL signal lines, and these interconnect elements are separated in the X direction from other segments of these signal lines located "to their left".

[0059] According to the revised Super SRAM layout design 401, the peripheral region 411 also includes multiple interconnect elements 470 in the M0 layer. Some of these interconnect elements 470 can also be configured to carry BL or BLB signals. For example, according to the revised Super SRAM layout design 401, interconnect elements 471, 473, 475, and 477 are implemented in the M0 layer of the peripheral region 411, serving as segments of BL, BLB, and BLB signal lines, respectively. Due to various layout-related reasons, the positions of interconnect elements 471, 473, 475, and 477 in the peripheral region 411 may not be aligned with the positions of interconnect elements 461, 463, 465, and 467 in the memory cell region 410 (e.g., in the Y direction). For example, even though interconnect elements 461 and 471 are both configured to carry BL signals and therefore should be electrically coupled together, interconnect element 461 is located "below" interconnect element 471 in the Y direction. As another example, even though interconnect elements 463 and 473 are both configured to carry BLB signals and therefore should be electrically coupled together, interconnect element 463 is located "above" interconnect element 473 in the Y direction.

[0060] According to the embodiment of the revised Super SRAM layout design, multiple additional interconnect elements 481, 483, 485, and 487 are implemented to connect interconnect elements 461, 463, 465, and 467 to interconnect elements 471, 473, 475, and 477, respectively. Interconnect elements 481, 483, 485, and 487 are also implemented in the M0 layer (the same layer as interconnect elements 461, 463, 465, 467, 471, 473, 475, and 477). The shapes or outlines of interconnect elements 481, 483, 485, and 487 can be flexibly configured to address misalignment between interconnect elements 461, 463, 465, and 467 and interconnect elements 471, 473, 475, and 477, respectively. For example, interconnect element 481 includes a segment 481A extending in the X direction within memory cell region 410, and a segment 481B extending in the X direction into (or across) memory cell region 410 and peripheral region 411. Segment 481A is connected to (e.g., incorporated into) interconnect element 461, while segment 481B is connected to (e.g., incorporated into) interconnect element 471. Because interconnect elements 461 and 471 are misaligned, segments 481A and 481B together define a jog, which can be represented by segment 481B being "above" segment 481A in the Y direction.

[0061] It should be noted that the width of segment 481A (e.g., the dimension measured in the Y direction) or the width of interconnect element 461 can be configured to be greater than the width of segment 481B to reduce the parasitic resistance of the BL signal line (since segment 481A and interconnect element 461 together constitute the majority of the parasitic resistance of the BL signal line). At the same time, the width of segment 481B (also the dimension measured in the Y direction) reduces the risk of electrical short circuits between segment 481B and another interconnect element disposed "above" or "below" interconnect element 471 in the Y direction.

[0062] As another example, interconnect element 483 includes a segment 483A extending in the X direction within memory cell region 410, a segment 483B extending in the X direction into (or across) memory cell region 410 and peripheral region 411, and a segment 483C extending in the Y direction within memory cell region 410. Segment 483A is connected to (e.g., incorporated into) interconnect element 463, segment 483B is connected to (e.g., incorporated into) interconnect element 473, and segment 483C is connected to (e.g., incorporated into) segments 483A and 483B. Figure 4BAs shown, the degree / amount of misalignment between interconnect elements 463 and 473 is greater than the degree / amount of misalignment between interconnect elements 461 and 471, and the implementation of interconnect element 483 helps to compensate for this greater degree / amount of misalignment. Accordingly, segments 483A and 483C jointly define a transition, while segments 483B and 483C jointly define another transition.

[0063] It should be noted that the width of segment 483A (e.g., the dimension measured in the Y direction) or the width of interconnect element 463 can be configured to be greater than the width of segment 483B to reduce the parasitic resistance of the BLB signal line (since segment 483A and interconnect element 463 together constitute the majority of the parasitic resistance of the BLB signal line). Simultaneously, the width of segment 483B (also the dimension measured in the Y direction) can be configured to be substantially equal to the width of interconnect element 473 to reduce the risk of electrical short circuits between segment 483B and another interconnect element disposed "above" or "below" interconnect element 473 in the Y direction. It should also be understood that interconnect elements 485 and 487 (comprising segments 485A / 485B and 487A / 487B respectively) can be implemented in a similar manner to interconnect element 481, and for the sake of simplicity, the details of this implementation will not be repeated here.

[0064] Regardless of the shape / profile configuration of interconnect elements 481, 483, 485, and 487, it should be understood that these interconnect elements act as bridging structures, electrically and physically connecting interconnect elements 461, 463, 465, and 467 to interconnect elements 471, 473, 475, and 477. In this manner, BL and BLB signal lines from memory cell region 410 can extend or be routed to peripheral region 411 within the same interconnect layer (e.g., M0 layer) without traversing another interconnect layer (e.g., M1 layer).

[0065] It is worth noting that in some embodiments, the ground voltage Vss and power supply voltage Vdd signal lines can both be implemented as multiple discrete segments in SRAM layout design 400 and the revised Super SRAM layout design 401. Because Figure 4A This only illustrates a small portion of the ground voltage Vss and power supply voltage Vdd signal lines, and this embodiment may not be immediately apparent in the SRAM layout design 400.

[0066] In some embodiments, the revised Super SRAM layout design 401 is generated based on an IC circuit design produced by an IC design company. For example, the IC design company may generate one or more IC circuit design files that capture the circuit design of an IC chip. These IC circuit design files may contain files in various formats, such as HDL files, netlist files, SPICE files, DEF files, LEF files, etc. The IC design company may send these files to an IC manufacturing facility (e.g., an IC foundry). Based on these files, the IC manufacturing facility may generate an IC layout design similar to the revised Super SRAM layout design 401. The IC layout design may be in Graphic Data System (GDS) format, which may have a binary format and may include solder masks, geometry, layers, component labels, and a general layout of the circuitry. In some other embodiments, the IC design company may have generated an IC layout design file (e.g., a GDS file) corresponding to the SRAM layout design 400. The IC design company can then send the IC layout design file to the IC manufacturing facility, which can then modify the IC layout design (received from the IC design company) into a revised IC layout design similar to the revised Super SRAM layout design 401. In any case, it should be understood that the revised Super SRAM layout design 401 (e.g., also in GDS file format) can be used by the IC manufacturing facility to manufacture IC chips, for example, to manufacture IC devices in the form of enhanced Super SRAM devices. Although based on Figure 4B The view may not be immediately obvious, but the actual manufactured interconnects (manufactured based on the revised Super SRAM layout design 401) corresponding to interconnect elements 461, 463, 465 and 467 and / or interconnect elements 471, 473, 475 and 477 may have curved or rounded end portions in the top view as a result of various manufacturing process effects.

[0067] Figures 4A to 4B A first embodiment relates to routing the BL and BLB signal lines from memory cell region 410 to peripheral region 411 according to an enhanced super SRAM scheme. In this embodiment, the BL and BLB signal lines are routed within the bottommost interconnect layer of the interconnect structure (i.e., the M0 layer). However, other embodiments are also possible. In this regard, Figures 5A to 5C This relates to a second embodiment of a super SRAM scheme that routes the BL and BLB signal lines from memory cell region 410 to peripheral region 411. In this second embodiment (discussed in more detail below), the routing of the BL and BLB signal lines is also performed using layers M1 and M2 (i.e., the layers above and two layers above layer M0, respectively). In this regard, Figure 5AThis describes the M0 layer of the revised Super SRAM layout design. Figure 5B It also explains the M0 and M1 layers of the revised Super SRAM layout design (e.g., M0 and M1 layers are stacked together), and Figure 5C The revised Super SRAM layout design also describes the M1 and M2 layers (e.g., M1 and M2 layers stacked together). For consistency and clarity, [further details are needed]. Figures 4A to 4B Similar components appearing in the first embodiment can be Figures 5A to 5C In the second embodiment, they are indicated by the same reference numerals. It should be noted that, because... Figure 4A The SRAM layout design 400 remains unchanged, so the relevant description will not be repeated in the second embodiment.

[0068] Now for reference Figure 5A The revised Super SRAM layout design 401 also illustrates the various interconnect elements in the memory cell region 410 and the surrounding region 411, and the positions of these interconnect elements are the same as those in the reference above. Figure 4B The locations discussed in the first embodiment are substantially the same. Sections 481A, 483A, 485A, and 487A are implemented to effectively extend interconnect elements 461, 463, 465, and 467 (corresponding to BL signal lines, BLB signal lines, and BL signal lines) in the X direction until the end portions of sections 481A, 483A, 485A, and 487A are aligned with the end portions of other interconnect elements in the memory cell region 410 (e.g., corresponding to ground voltage Vss and power supply voltage Vdd lines). However, no bridging structures (e.g., ...) are implemented in the M0 layer. Figure 4B Sections 481B, 483B, 485B, and 487B are used to connect interconnect elements 461, 463, 465, and 467 in memory cell area 410 to interconnect elements 471, 473, 475, and 477 in surrounding area 411 (which also correspond to BL signal lines, BLB signal lines, BLB signal lines, and BL signal lines). In other words, no bridging structure is implemented in layer M0.

[0069] Now for reference Figure 5BThe revised Super SRAM layout design 401 illustrates interconnect elements 501, 503, 505, and 507, and other components (components 511, 513, 515, 517, 520, 525, and 530) located in the M1 layer of memory cell region 410. More specifically, interconnect elements 501, 503, 505, and 507 extend along the X direction. Portions of interconnect elements 501, 503, 505, and 507 are located above interconnect elements 461, 463, 465, and 467, respectively. In some embodiments, interconnect elements 501, 503, 505, and 507 are wider in the Y direction than interconnect elements 461, 463, 465, and 467, respectively, because interconnect elements 501, 503, 505, and 507 are located in interconnect layers further away from the substrate of the transistors forming the SRAM (e.g., M1 layer is located above M0 layer). Additionally, although based on Figure 5B The view may not be immediately obvious, but the actual manufactured interconnects (manufactured based on the revised Super SRAM layout design 401) corresponding to interconnect elements 501, 503, 505 and 507 may have curved or rounded end portions as a result of various manufacturing process effects.

[0070] Conductive vias 551, 553, 555, and 557 are implemented between layers M0 and M1 to electrically connect interconnect elements 461, 463, 465, and 467 to interconnect elements 501, 503, 505, and 507, respectively. Therefore, interconnect elements 501, 503, 505, and 507 are also configured to transmit BL, BLB, and BL signals respectively in layer M1.

[0071] Meanwhile, although island connection structures 511, 513, 515, and 517 are implemented in layer M1, these island connection structures are oriented to extend along the Y direction (e.g., each has a larger dimension in the Y direction than in the X direction). Parts of island connection structures 511, 513, 515, and 517 are located above segments 481A, 483A, 485A, and 487A (implemented in layer M0) discussed above, and are electrically connected together through conductive vias 561, 563, 565, and 567, which are also implemented between layers M0 and M1. Since segments 481A, 483A, 485A, and 487A are incorporated into interconnect elements 461, 463, 465, and 467, they can be considered as physical extensions of interconnect elements 461, 463, 465, and 467. Therefore, island connection structures 511, 513, 515, and 517 are also configured to transmit or carry BL signals, BLB signals, BLB signals, and BL signals respectively in layer M1.

[0072] Still referencing Figure 5B The revised Super SRAM layout design 401 further implements island interconnect structures 520 to 525, which are configured to carry other signals, such as WL or ground voltage Vss. Additionally, the revised Super SRAM layout design 401 implements interconnect elements 530 extending along the Y direction in the M1 layer. Interconnect elements 530 have a larger size (in the Y direction) than island interconnect structures 511, 513, 515, and 517, and can be used to provide further routing flexibility for ground voltage Vss and / or power supply voltage Vdd lines. However, it should be understood that the implementation of interconnect elements 530 is optional and may be omitted in some embodiments. It should also be understood that, although based on… Figure 5B The view may not be immediately obvious, but the actual manufactured island connection structures (manufactured based on the revised Super SRAM layout design 401) corresponding to island connection structures 511, 513, 515, 517 and 520 to 525 may have curved or rounded end portions as a result of various manufacturing process effects.

[0073] Now for reference Figure 5CThe revised Super SRAM layout design 401 illustrates interconnect elements 571, 573, 575, and 577 located in the M2 layer of memory cell region 410 and peripheral region 411. More specifically, interconnect elements 571, 573, 575, and 577 each span the boundary between memory cell region 410 and peripheral region 411. Interconnect elements 571, 573, 575, and 577 can be connected to interconnect elements 461, 463, 465, and 467 respectively (see [link to documentation]). Figure 5B The island connection structures 511, 513, 515, and 517 are not aligned in the Y direction. However, the Y-direction orientation of the island connection structures 511, 513, 515, and 517 can still facilitate the electrical connection between interconnect elements 571, 573, 575, and 577 and interconnect elements 461, 463, 465, and 467.

[0074] In this regard, interconnect element 571 is electrically connected to island connection structure 511 (located in layer M1) via conductive via 581 between layers M1 and M2; interconnect element 573 is electrically connected to island connection structure 513 (located in layer M1) via conductive via 583 between layers M1 and M2; interconnect element 575 is electrically connected to island connection structure 515 (located in layer M1) via conductive via 585 between layers M1 and M2; and interconnect element 577 is electrically connected to island connection structure 517 (located in layer M1) via conductive via 587 between layers M1 and M2. To ensure the connection of interconnect elements 461, 463, 465, and 467 (see...) Figure 5B These interconnects are electrically connected to interconnects 571, 573, 575, and 577, even though each interconnect has its own misalignment. The dimensions of each island connection structure 511, 513, 515, and 517 are configured to exceed the misalignment between interconnects 461, 463, 465, and 467 and interconnects 571, 573, 575, and 577, respectively. For example, the dimension of island connection structure 511 is greater than the misalignment between interconnect 471 and segment 481A (an extension of interconnect 461).

[0075] As referenced above Figure 5BAs discussed, island connection structures 511, 513, 515, and 517 are configured to transmit / carry BL signals, BLB signals, BLB signals, and BL signals. Due to their electrical connection with island connection structures 511, 513, 515, and 517, interconnect elements 571, 573, 575, and 577 also transmit / carry BL signals, BLB signals, BLB signals, and BL signals. In this manner, BL signals, BLB signals, BLB signals, and BL signals are transmitted from the M0 layer (e.g., via...) Figures 5A to 5B Interconnect elements 461, 463, 465, and 467), via the M1 layer (e.g., via respectively). Figures 5B to 5C Island connection structures 511, 513, 515, and 517), routed to layer M2 (e.g., via respectively). Figure 5C (interconnect elements 571, 573, 575, and 577). Figure 5B Conductive vias 561, 563, 565, and 567 (located between layers M0 and M1) and Figure 5C The conductive vias 581, 583, 585 and 587 (located between layers M1 and M2) also facilitate the electrical routing of the BL signal, BLB signal, BLB signal and BL signal.

[0076] It should be understood that, although based on Figure 5C The view may not be immediately obvious, but the actual manufactured interconnects corresponding to interconnects 571, 573, 575 and 577 (manufactured based on the revised Super SRAM layout design 401) may have curved or rounded end portions as a result of various manufacturing process effects.

[0077] The above reference Figures 4A to 4B and Figures 5A to 5C The discussion relates to different embodiments of the present disclosure, in which BL signals or BLB signals are routed from memory cell area 410 to peripheral area 411 in a super SRAM scheme. Figure 6 This relates to routing the WL signal from memory cell area 410 to surrounding area 411 according to some embodiments of this disclosure. Similarly, for consistency and clarity, in Figures 4A to 4B and Figures 5A to 5C Similar components appearing in [the context] can be found in [the context]. Figure 6 They are indicated by the same number.

[0078] refer to Figure 6This describes a top view of the revised Super SRAM layout design 401. The top view is defined by the X and Y directions, similar to... Figures 4A to 4B and Figures 5A to 5C The revised Super SRAM layout design 401 also includes memory cell area 410 and peripheral area 411. However, Figures 4A to 4B and Figures 5A to 5C The peripheral region 411 is located adjacent to the memory cell region 410 in the X direction, while Figure 6 The peripheral region 411 is located adjacent to the memory cell region 410 in the Y direction. In other words, Figures 4A to 4B and Figures 5A to 5C The portion of the surrounding area 411 described herein may differ from the portion of the surrounding area described herein. Figure 6 The surrounding area 411 described in the text. For example, Figures 4A to 4B and Figures 5A to 5C The area around 411 described in the text can be considered an I / O area, while... Figure 6 The area 411 described in the text may be the WL drive area.

[0079] Figure 6 The revised Super SRAM layout design 401 illustrates three different interconnect layers stacked together: layer M1 (located above the bottom layer M0), layer M2 located above layer M1, and layer M3 located above layer M2. More specifically, layer M1 includes interconnect elements 610, 611, 612, island connection structure 620, and island connection structure 621. Interconnect element 610 extends along the X direction and is configured to transmit or carry the BL signal discussed above. Therefore, interconnect element 610 can be referred to as part of the BL signal line in layer M1. Interconnect elements 611 and 612 each extend along the Y direction and are each configured to transmit or carry the WL signal. Therefore, interconnect elements 611 and 612 can each be referred to as part of the WL signal line in layer M1. Island connection structures 620 and 621 are located in the Y direction between interconnect elements 610 and interconnect elements 611 to 612. Island connection structures 620 and 621 are also configured to route WL signals. It should be noted that interconnect elements 611 and 612 also span the boundary between memory cell region 410 and peripheral region 411, while interconnect elements 610, island connection structures 620 and 621 are each located within memory cell region 410.

[0080] Layer M2 includes interconnect elements 641 and 642. Each interconnect element 641 and 642 includes a non-primary portion extending along the X direction, but the primary portions of interconnect elements 641 and 642 extend along the Y direction. The primary portions of interconnect elements 641 to 642 extend through island connection structures 620 to 621 and partially extend into interconnect elements 611 to 612, but do not enter the peripheral region 411 in the top view. In other words, interconnect elements 641 to 642 overlap with island connection structures 620 to 621, and partially overlap with interconnect elements 611 to 612. Furthermore, it should be understood that interconnect elements 641 and 642 may each extend further "up" in the Y direction (e.g., away from interconnect element 610), but for simplicity, these extensions of interconnect elements 641 and 642 are not shown. Figure 6 The details are explained below. In any case, interconnect elements 641 and 642 are also configured to transmit or carry WL signals. Therefore, interconnect elements 641 and 642 can each be referred to as part of the WL signal line in the M2 layer.

[0081] The M3 layer includes interconnect elements 651 and 652. Interconnect elements 651 and 652, in a top view, have a shape or outline substantially similar to that of interconnect elements 641 and 642, but are slightly smaller in size in the X and Y directions. Therefore, each of interconnect elements 651 to 652 also includes a non-primary portion extending in the X direction and a primary portion extending in the Y direction, wherein the primary portions of interconnect elements 651 to 652, in a top view, overlap with island connection structures 620 to 621, and partially overlap with interconnect elements 611 to 612, respectively. In any case, interconnect elements 651 and 652 are also configured to transmit or carry WL signals. Therefore, interconnect elements 651 and 652 can each be referred to as part of the WL signal line in the M3 layer.

[0082] It should be noted that the orientation of the WL signal lines in this M2 layer (e.g., the Y-direction extension of interconnect elements 641 to 642) differs from the orientation of WL signal lines in other types of SRAM devices (generally the X-direction). Due to the Y-direction orientation of the WL signal lines in the M2 layer, portions of the WL signal lines in the M3 layer (e.g., interconnect elements 651 to 652) substantially follow the shape / profile of the WL signal lines in the M2 layer. These different portions of the WL signal lines in the M2 and M3 layers are guided by conductive vias located between the M2 and M3 layers (e.g., similar to...). Figure 3B The V2 rails described herein are electrically connected together. For simplicity, the conductive through-hole rails are not shown. Figure 6The details are explained below. In any case, the revised Super SRAM layout design effectively distributes the WL signal lines in layers M2 and M3 within memory cell region 410, which helps reduce the parasitic resistance of the WL signal lines.

[0083] The revised Super SRAM layout design 401 further implements multiple conductive vias 671, 672, 681, and 682 located between layers M1 and M2. Specifically, conductive via 671 electrically connects the island-like interconnect structure 620 of layer M1 to the interconnect element 641 of layer M2; conductive via 672 electrically connects the island-like interconnect structure 621 of layer M1 to the interconnect element 642 of layer M2; conductive via 681 electrically connects the interconnect element 611 of layer M1 to the interconnect element 641 of layer M2; and conductive via 682 electrically connects the interconnect element 612 of layer M1 to the interconnect element 642 of layer M2. In this manner, the WL signal is routed from layers M2 and M3 in memory cell region 410 to layer M1 in the surrounding region 411.

[0084] It should be noted that interconnect element 611 may be implemented as wider in the X direction than interconnect elements 641 and 651, and interconnect element 612 may be implemented as wider in the X direction than interconnect elements 642 and 652. The wider width of interconnect elements 611 and 612 not only helps reduce the parasitic resistance of the WL signal lines, but also provides greater tolerance for electrically connecting interconnect elements 611 to 612 and to interconnect elements 641 / 651 and 642 / 652. It should also be understood that the revised Super SRAM layout design 401 may include additional components in layers M1, M2, and M3, such as additional interconnect elements, additional island-like connection structures, and / or additional conductive vias. For example, some of these additional components may be implemented to transmit or carry other types of signals, such as ground voltage Vss. For simplicity, these additional components are not shown in the diagram. Figure 6 The details are explained in the text.

[0085] As discussed above, the various components of layers M0, M1, M2, and M3 are layers of the MLI structure. To further clarify the various embodiments of the components implemented in the interconnect structure, Figure 7 An example of this MLI structure is illustrated as a partial planar top view. For example... Figure 7As shown, interconnect elements 700 and 701 (e.g., in the form of mostly rectangular conductive strips, interchangeably referred to as metal lines) are formed directly above conductive vias 710 to 712. Interconnect elements 700 and 701 are formed as part of interconnect layer MX, which is an interconnect layer above interconnect layer MX-1 containing interconnect elements 720 to 722 (e.g., also in the form of metal lines). It should be noted that interconnect layers MX-1 and MX can be any two vertically adjacent interconnect layers. For example, interconnect layer MX-1 can be layer M0 (0th metal layer), while interconnect layer MX can be layer M1 (1st metal layer). Alternatively, interconnect layer MX-1 can be layer M3 (3rd metal layer), while interconnect layer MX can be layer M4 (4th metal layer).

[0086] Regardless of the exact interconnect layer to which interconnect elements 720 to 722 and / or interconnect elements 700 to 701 belong, it should be understood that interconnect layers MX-1 and MX can be interconnected via conductive vias 710 to 712. For example, since conductive via 710 is located in the overlapping area of ​​interconnect elements 720 and 700 in a planar top view, conductive via 710 is electrically interconnected with interconnect elements 720 and 700 such that the lower surface of conductive via 710 (in the vertical Z direction) is in direct contact with the upper surface of interconnect element 720, and the upper surface of conductive via 710 (in the vertical Z direction) is in direct contact with the lower surface of interconnect element 700.

[0087] In some embodiments, interconnect elements 700 to 701 and / or interconnect elements 720 to 722 can be used to implement and Figure 4B , Figures 5A to 5C or Figure 6 Any interconnect elements and / or island structures discussed herein, such as interconnect elements for implementing BL signal lines, BLB signal lines, or WL signal lines. Similarly, conductive vias 710 to 712 may be used to implement interconnects with… Figure 4B , Figures 5A to 5C or Figure 6 Any conductive vias discussed in connection with the discussion, such as conductive vias 551, 553, 555, 557, 561, 563, 565, 567, 581, 583, 585, 587, 671 to 672, or 681 to 682.

[0088] In some embodiments, interconnect elements 720 to 722 have widths different from those of interconnect elements 700 to 701. For example, interconnect elements 720 to 722 may each have a width 725 measured in the X direction, while interconnect elements 700 to 701 may each have a width 730 measured in the Y direction, wherein width 730 is greater than width 725. In some embodiments, width 725 may be in the range of about 0.01 micrometers to about 0.37 micrometers, and width 730 may be in the range of about 0.01 micrometers to about 0.37 micrometers, but the ratio between width 730 and width 725 is greater than about 1:1. In other embodiments, width 725 and width 730 may be substantially equal to each other, and the ratio between width 725 and width 730 may be about 1:1.

[0089] It should also be understood that interconnect elements 700 to 701 and interconnect elements 720 to 722 (e.g., metal lines in interconnect layers MX and MX-1) are disposed in one or more dielectric layers 740. The dielectric layers 740 may be part of the ILD structure and provide electrical and physical isolation for interconnect elements 700 to 701 and interconnect elements 720 to 722.

[0090] In some embodiments, the interconnect elements in interconnect layer MX may have a different spacing than the interconnect elements in interconnect layer MX-1, wherein the spacing may be the sum of the width of a given interconnect element and the distance between the given interconnect element and its adjacent interconnect elements. For example, interconnect layer MX may have a spacing of 750 (e.g., as the sum of the width 730 and the distance between interconnect elements 700 and 701), while interconnect layer MX-1 may have a spacing of 751 (e.g., as the sum of the width 725 and the distance between interconnect elements 721 and 722), wherein the values ​​of spacing 750 and spacing 751 are different.

[0091] Figure 8 This is a schematic partial cross-sectional side view of an embodiment of an IC device 300 that includes the enhanced super SRAM discussed above, for example, a super SRAM manufactured based on a revised super SRAM layout design 401. Figure 8 A cross-sectional side view is illustrated, defined by the X direction in the horizontal direction and the Z direction in the vertical direction. However, it should be understood that in other embodiments, the cross-sectional side view may also be defined by the Y direction in the horizontal direction.

[0092] like Figure 8As shown, the IC device 300 includes a substrate 810, which may be an embodiment of the substrate 110 discussed above. A plurality of transistors 820 (e.g., FinFET or GAA devices discussed above) may be formed in or on the substrate 810. Bit cells of a super SRAM device may be fabricated using the transistors 820. An interconnect structure 830 is formed over the transistors 820 and provides electrical connections to the transistors 820. The interconnect structure 830 may be an embodiment of the substrate 110 discussed above. Figure 7 One embodiment of the discussed interconnect structure may include multiple interconnect layers, such as interconnect layer M1, interconnect layer M2, and interconnect layer M3. For example, interconnect layer M2 and interconnect layer M1 may be embodiments of interconnect layer MX and interconnect layer MX-1, respectively, or interconnect layer M3 and interconnect layer M2 may be embodiments of interconnect layer MX and interconnect layer MX-1, respectively. Each of interconnect layer M1, interconnect layer M2, and interconnect layer M3 may include one or more metal lines (e.g., as embodiments of interconnect elements 700 to 701 and / or interconnect elements 720 to 722 discussed above).

[0093] These metal lines are disposed in multiple dielectric layers 840. The dielectric layers 840 electrically and physically separate the metal lines of interconnect layers M1, M2, and M3 from each other. In some embodiments, the dielectric layers 840 may have different dielectric constant values. In some embodiments, the dielectric constant value of the dielectric layer 840 is lower than the dielectric constant value of the gate dielectric layer discussed above, which has a dielectric constant value of approximately 3.9. In some embodiments, the dielectric layer 840 disposed at a location farther from the substrate 810 is thicker than another dielectric layer 840 disposed closer to the substrate 810 (e.g., in the vertical Z direction). For example, the dielectric layer 840 in which the M3 layer metal lines are disposed may be thicker than the dielectric layer 840 in which the M2 layer metal lines are disposed.

[0094] In some embodiments, at least one metal line disposed in an interconnect layer farther from the substrate 810 may be thicker (e.g., in the perpendicular Z direction) than at least one metal line disposed in an interconnect layer closer to the substrate 810. For example, a metal line in interconnect layer M3 may be thicker than a metal line in interconnect layer M2 (e.g., the thickness is measured in the Z direction), and a metal line in interconnect layer M2 may be thicker than a metal line in interconnect layer M1. In some embodiments, at least one metal line in one of interconnect layers M1 to M3 has a curved upper surface in a cross-sectional view. In other words, the uppermost surface of such a metal line is not flat, but may exhibit various degrees of curvature, for example, having a convex profile. In some embodiments, the curved upper surface of such a metal line is not coplanar with the upper surface of the dielectric layer 840 in which the metal line is located. For example, the curved upper surface of such a metal line may be located above the upper surface of the dielectric layer 840 in which it is located (e.g., perpendicular to the Z direction).

[0095] In some embodiments, at least one metal wire of one of interconnect layers M1, M2, or M3 includes a bent end portion. Figure 7 For example, at least one of interconnect elements 700 to 701 includes a bent end portion. In other words, the end portions of interconnect elements 700 and / or 701 in the X direction may be bent, and the end portions of interconnect elements 720 or 721 in the Y direction may be bent. Additionally, at least two metal lines in the interconnect layer extend in different directions. For example, the metal lines in layer M1 may extend horizontally, while the metal lines in layer M2 (e.g., disposed adjacent to and above layer M1) may extend in a different horizontal direction than (e.g., perpendicular to) the horizontal direction along which the metal lines in layer M1 extend. Again... Figure 7 For example, interconnect elements 720 to 722 in the MX-1 layer extend along the Y direction, while interconnect elements 700 to 701 in the MX layer extend along the X direction. Furthermore, although... Figure 8 The embodiments described herein only illustrate three interconnect layers M1 to M3, but this is for simplicity only. It should be understood that in other embodiments, the interconnect structure 830 may contain more (or fewer) interconnect layers, and selective enlargement of conductive vias may be applied to any conductive via in the interconnect structure 830 that interconnects any two vertically adjacent interconnect layers.

[0096] The interconnect structure 830 also includes a plurality of conductive vias to electrically couple the interconnect layers to each other. For example, conductive vias V1 and V2 extend through one or more dielectric layers 840. Conductive via V1 electrically couples the interconnect components of interconnect layers M1 and M2 together, and conductive via V2 electrically couples the metal lines of interconnect layers M2 and M3 together.

[0097] Figure 9 An IC manufacturing system 900 according to an embodiment of the present disclosure is described. For example, the IC manufacturing system 900 can be used to generate or modify IC layout designs, and manufacture IC devices based on the IC layout designs. The manufacturing system 900 includes multiple entities (entity 902, entity 904, entity 906, entity 908, entity 910, entity 912, entity 914, entity 916...entity N), which are connected via a communication network 918. The network 918 may be a single network or multiple different networks, such as an internal network and an interconnected network, and may include wired and wireless communication channels.

[0098] In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer monitoring products of interest; entity 906 represents an engineer, such as a process engineer controlling processes and related formulations, or an equipment engineer monitoring or adjusting the conditions and settings of processing tools; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor processing tool, such as an EUV tool for performing lithography processes to define active regions; entity 912 represents a virtual metrology module associated with processing tool 910; entity 914 represents an advanced process control module associated with processing tool 910 and other additional processing tools; and entity 916 represents a sampling module associated with processing tool 910.

[0099] Each entity can interact with other entities and can provide and / or receive IC manufacturing, processing control, and / or computing capabilities from other entities. Each entity may also include one or more computer systems for performing calculations and implementing automation. For example, the advanced process control module of entity 914 may include multiple computer hardware components with software instructions encoded therein. The computer hardware may include hard disks, flash memory, CD-ROMs, RAM, display devices (e.g., monitors), and I / O devices (e.g., mice and keyboards). The software instructions can be written in any suitable programming language and can be designed to perform specific tasks.

[0100] The IC manufacturing system 900 enables interaction between entities for IC manufacturing purposes and advanced process control in IC manufacturing. In one embodiment, advanced process control includes adjusting processing conditions, settings, and / or formulations of processing tools applicable to the relevant wafer based on metrological results.

[0101] In another embodiment, the metrological results are obtained from a subset of processed wafers based on an optimal sampling rate, which is determined based on process quality and / or product quality. In yet another embodiment, the metrological results are obtained from selected fields and points of a subset of processed wafers based on an optimal sampling field / point, which is determined based on various characteristics of process quality and / or product quality.

[0102] The IC manufacturing system 900 provides capabilities enabling collaboration and information access across design, engineering, processing, metrology, and advanced process control. Another capability of the IC manufacturing system 900 is the integration of systems between facilities, such as metrology tools and processing tools. This integration allows facilities to coordinate their activities. For example, integrating metrology tools and processing tools allows manufacturing information to be more effectively incorporated into manufacturing processes or advanced process control modules, and enables wafer data to be measured online or in the field using metrology tools integrated with related processing tools.

[0103] Figure 10 This is a flowchart illustrating a method 1000 for implementing a layout design of an electronic memory device. In some embodiments, the layout design is as follows: Figure 4B A revised super SRAM layout design 401. Method 1000 includes operation 1010, wherein a first segment of a BL signal line or a BLB signal line is identified in a memory cell region of the layout design of the SRAM device. The first segment extends along a first direction in the layout design. In some embodiments, the memory cell region is Figure 4B The memory cell area 410, and the first segment of the BL signal line or BLB signal line can be an interconnect element 461, an interconnect element 463, an interconnect element 465, or an interconnect element 467. In some embodiments, the first direction is Figure 4B The X direction.

[0104] Method 1000 includes operation 1020, wherein a second segment of a BL signal line or a BLB signal line is identified in a peripheral region of a layout design of an SRAM device. The second segment extends along a first direction in the layout design. The first segment and the second segment are offset from each other in a second direction different from the first direction in the layout design. In some embodiments, the peripheral region is... Figure 4B Part of the surrounding area 411, and the second section may be Figure 4B One of interconnect element 471, interconnect element 473, interconnect element 475, or interconnect element 477. In some embodiments, the second direction is... Figure 4B Y direction.

[0105] Method 1000 includes operation 1030, wherein a third segment of a BL signal line or a BLB signal line is implemented, the third segment extending into the memory cell area and surrounding area. The third segment extends along a first direction in the layout design. A first end of the third segment is incorporated into a first segment. A second end of the third segment is incorporated into a second segment. The first segment, the second segment, and the third segment are located in the same interconnect layer of the MLI structure and contain different lengths along the first direction. In some embodiments, the third segment may be... Figure 4B One of interconnecting elements 481, 483, 485 or 487.

[0106] In some embodiments, the third segment of the BL signal line or BLB signal line is implemented by including a jog in the layout design.

[0107] In some embodiments, the third segment of the BL signal line or BLB signal line has a width that is substantially equal to the width of the second segment in the second direction in the layout design.

[0108] In some embodiments, the same interconnect layer implementing the first segment, the second segment, and the third segment is the bottommost interconnect layer of the MLI structure (e.g., the M0 layer).

[0109] It should be understood that method 1000 may include additional operations performed before, during, or after operations 1010 to 1030. For example, method 1000 may include operations for manufacturing an SRAM device based on a layout design. As another example, method 1000 may include operations for implementing a portion of a BL signal line or a BLB signal line in a memory cell region of the layout design, in a layer above the bottommost interconnect layer in an MLI structure. For the sake of brevity, other additional operations are not discussed in detail here.

[0110] Figure 11 The flowchart illustrates method 1100. Method 1100 includes operation 1110, which implements a first segment of a signal line in the lowest first interconnect layer of an MLI structure in a memory cell region of an IC device. The first segment of the signal line extends along a first direction. In some embodiments, the memory cell region includes... Figure 5A The memory cell area 410, the first segment contains Figure 5A The interconnect element 461 and segment 481A, the first interconnect layer includes an M0 layer, and the first direction is... Figure 5A The X direction.

[0111] Method 1100 includes operation 1120, implementing a second segment of a signal line and an island-shaped connection structure in a second interconnect layer in a memory cell region. The second interconnect layer is located above the first interconnect layer. The second segment of the signal line extends along a first direction, but the island-shaped connection structure extends along a second direction different from the first direction. The second segment of the signal line and the island-shaped connection structure are electrically coupled to the first segment of the signal line through a first conductive via and a second conductive via located between the first interconnect layer and the second interconnect layer, respectively. In some embodiments, the second segment includes... Figure 5B The interconnecting element 501, the island-shaped connection structure includes Figure 5B The island-shaped interconnect structure 511, the second interconnect layer includes the M1 layer, and the first conductive via includes Figure 5B The conductive via 551, and the second conductive via includes Figure 5B Conductive via 561.

[0112] Method 1100 includes operation 1130, implementing a third segment of a signal line in a peripheral region of an IC device. The third segment of the signal line extends along a first direction and crosses the boundary between a memory cell region and the peripheral region. The third segment of the signal line is implemented in a third interconnect layer of an MLI structure, the third interconnect layer being one layer above the second interconnect layer. The third segment of the signal line is electrically coupled to an island-like interconnect structure via a third conductive via located between the second and third interconnect layers. In some embodiments, the peripheral region includes... Figure 5C The surrounding area 411, the third section includes Figure 5C The interconnect element 571 has a third interconnect layer of M2, and the third conductive via contains... Figure 5C Conductive via 581.

[0113] In some embodiments, the IC device includes an SRAM cell, the signal line is a BL signal line or a BLB signal line of the SRAM cell, and the BL signal line is discontinuous in the SRAM cell and includes a plurality of discrete segments containing a first segment of the signal line.

[0114] In some embodiments, the second segment of the signal line has a larger size in the second direction than the first segment of the signal line.

[0115] In some embodiments, the third segment is not aligned with the first segment of the signal line in the second direction.

[0116] In some embodiments, the size of the island-shaped connection structure is greater than the misalignment distance corresponding to the third segment and the first segment of the signal line.

[0117] It should be understood that method 1100 may include additional operations performed before, during, or after operations 1110 to 1130. For example, method 1100 may include the operation of implementing a metal line in a second interconnect layer, wherein the metal line extends along a second direction and is located between a second segment of the signal line and the island-like connection structure in a first direction. The metal line is implemented to have a larger dimension in the second direction than the island-like connection structure. For the sake of brevity, other additional operations are not discussed in detail here.

[0118] Figure 12 The flowchart illustrates method 1200. Method 1200 includes operation 1210, forming first segments BL and WL in an SRAM device. Both the first segments BL and WL are formed in a first interconnect layer of an MLI structure. BL extends along a first direction. The first segment of WL extends along a second direction different from the first direction. BL is formed in a memory cell region of the SRAM device. The first segment of WL is formed in the memory cell region and a peripheral region of the SRAM device. In some embodiments, the first segment includes... Figure 6The interconnect element 611 has an M1 layer as the first interconnect layer and an X direction as the first direction. The memory cell region contains... Figure 6 The memory cell area 410, and the surrounding area contains Figure 6 The surrounding area 411.

[0119] Method 1200 includes operation 1220, forming a second segment of WL in a second interconnect layer in a memory cell region. The second interconnect layer is located above the first interconnect layer. A major portion of the second segment of WL extends along a second direction and is electrically coupled to a first segment of WL through a first conductive via. In some embodiments, the second segment includes Figure 6 The interconnect element 641, the second interconnect layer is the M2 layer, and the first conductive via includes Figure 6 Conductive via 681.

[0120] Method 1200 includes operation 1230, forming a third segment of WL in a third interconnect layer in a memory cell region. The third interconnect layer is located on top of the second interconnect layer. A major portion of the third segment of WL extends along a second direction and is electrically coupled to a second segment of WL through a second conductive via. At least one of BL, the first segment of WL, the second segment of WL, or the third segment of WL includes a bent end portion. In some embodiments, the third segment includes Figure 6 The interconnect element 651, the third interconnect layer is an M3 layer, and the second conductive via may contain elements similar to... Figure 3B The V2 guide rail has a through hole.

[0121] In some embodiments, the first interconnect layer is formed on the layer above the bottom layer of the interconnect structure.

[0122] In some embodiments, the first segment of WL has a larger size in a first direction than the second segment of WL.

[0123] In some embodiments, the shape of the third segment of WL is substantially similar to the shape of the third segment of WL in the top view, but smaller in size.

[0124] In some embodiments, the second conductive via is a via guide located between the second interconnect layer and the third interconnect layer.

[0125] It should be understood that method 1200 may include further operations performed before, during, or after operations 1210 to 1230. For example, method 1200 may include the operation of forming an island-shaped interconnect structure in a first interconnect layer. The island-shaped interconnect structure is located between a first segment of BL and WL in a second direction. The island-shaped interconnect structure is electrically coupled to a second segment of WL via a third conductive via. For the sake of simplicity, other additional operations are not discussed in detail here.

[0126] The advanced lithography processes, methods, and materials described above can be used in many applications, including FinFETs. For example, fins can be patterned to create relatively close spacing between components, and the above disclosure applies to this. Additionally, the spacers (also called mandrels) used to form the fins of a FinFET can be processed according to the above disclosure. It should also be understood that the various embodiments of this disclosure discussed above are applicable to multi-channel devices, such as GAA devices. Whenever this disclosure refers to fin structures or FinFET devices, these discussions are equally applicable to GAA devices.

[0127] In summary, this disclosure enhances a super SRAM device by routing BL signals, BLB signals, and / or WL signals from the memory device area to a peripheral area (e.g., an area containing circuitry outside the memory cell array). This disclosure provides certain advantages. However, it should be understood that not all advantages are discussed herein, different embodiments may offer different advantages, and no particular advantage is required in any embodiment. One advantage is routing flexibility. For example, in a first embodiment, BL signal lines or BLB signal lines are routed from the memory cell area (e.g., the bit cell array area) to the corresponding BL signal line or BLB signal line in the peripheral area (e.g., the peripheral region) via a connection mechanism that may include bends. The bends can compensate for any misalignment that may exist between the BL signal lines or BLB signal lines in the memory device area and the peripheral region. In this embodiment, the BL signal lines, BLB signal lines, and connection mechanism can all be implemented as metal lines in the bottommost interconnect layer (e.g., the MO layer). In the second embodiment, the BL or BLB signal lines in the bottommost interconnect layer (e.g., layer M0) are routed from the memory cell region to the corresponding BL or BLB signal lines in the peripheral region, wherein the corresponding BL or BLB signal lines in the peripheral region are located in the interconnect layers two layers above the bottommost interconnect layer (e.g., layer M2). This can be achieved by additional segments of the BL or BLB signal lines and island-like connection structures implemented in layer M1 (e.g., located between layers M0 and M2). The size of the island-like connection structures is also configured to be large enough to compensate for any misalignment that may exist between the BL or BLB signal lines in the memory device region and the peripheral region. In the third embodiment, the WL signal lines are routed from the memory cell region to the peripheral region. Segments of the WL signal lines in the memory cell region are implemented in layers M2 and M3 and have substantially similar shapes. Segments of the WL signal lines in the peripheral region are implemented in layer M1 and span the boundary between the memory cell region and the peripheral region. Therefore, conductive vias can be used to electrically couple different segments of the WL signal together, thereby allowing the WL signal to be routed from the memory cell area to the surrounding area. Another advantage of this disclosure is improved device performance. The various routing schemes discussed above allow for the implementation of various signal lines in larger sizes, which helps reduce parasitic resistance, thereby translating into faster device speeds and / or lower power consumption. Other advantages may include compatibility with existing manufacturing processes, ease of implementation, and low cost.

[0128] It should be understood that although the concepts in this disclosure are discussed using electronic memory devices as examples, they are not intended to be limited to electronic memory devices unless otherwise stated. The concept of implementing additional signal lines in various interconnect layers to assist in routing electronic signals can also be applied to other suitable IC applications.

[0129] One embodiment of this disclosure relates to an IC device. The IC device includes a first interconnect element disposed in a dielectric material of a first interconnect layer of an interconnect structure. The first interconnect element is located in a first region of an integrated circuit device. The first interconnect element extends along a first horizontal direction in a top view. The dielectric constant of the dielectric material is less than 3.9. The IC device includes a second interconnect element disposed in the dielectric material of the first interconnect layer of the interconnect structure. The second interconnect element is located in a second region of the integrated circuit device adjacent to the first region. The second interconnect element extends along the first horizontal direction in the top view. The second interconnect element is not aligned with the first interconnect element in the top view in a second horizontal direction different from the first horizontal direction. The IC device includes a third interconnect element disposed in the dielectric material of the first interconnect layer of the interconnect structure. The third interconnect element spans the first region and the second region and is coupled to the first interconnect element and the second interconnect element. At least one of the first interconnect element, the second interconnect element, or the third interconnect element has a bent end portion in the top view.

[0130] In some embodiments, the first region includes a plurality of static random access memory (SRAM) cells; the second region includes circuitry other than the SRAM cells; and the first interconnect element, the second interconnect element, and the third interconnect element are multiple portions of a bit line signal line or an anti-phase line signal line of the SRAM cells. In some embodiments, the bit line signal line or the anti-phase line signal line located in the SRAM cells is discontinuous and includes multiple discrete segments, the discrete segments including the first interconnect element in the first interconnect layer. In some embodiments, a first portion of the third interconnect element is incorporated into the first interconnect element in the top view; a second portion of the third interconnect element is incorporated into the second interconnect element in the top view; and the first portion and the second portion together define a bend in the top view. In some embodiments, the IC device further includes a plurality of fourth interconnect elements disposed in the dielectric material of the first interconnect layer of the interconnect structure. The fourth interconnect elements are located in the first region. At least one of the fourth interconnect elements is an electrical power line of the integrated circuit device. At least another of the fourth interconnect elements is an electrical ground line of the integrated circuit device. In some embodiments, the interconnect structure includes a plurality of interconnect layers disposed vertically above each other in a cross-sectional side view; and the first interconnect layer is the bottommost interconnect layer of the interconnect layers. In some embodiments, the first interconnect element, the second interconnect element, and the third interconnect element each have a first dimension, a second dimension, and a third dimension measured along the second horizontal direction; the first dimension is different from the second dimension; and the second dimension is substantially equal to the third dimension.

[0131] One embodiment of this disclosure relates to a method. The method includes forming a first segment of a signal line in a first interconnect layer, wherein the first interconnect layer is the bottom layer of a multilayer interconnect structure in a first region of an integrated circuit device. The first segment of the signal line extends along a first direction. The method includes forming a second segment of the signal line and an island-shaped connection structure in a second interconnect layer of the multilayer interconnect structure in the first region. The second interconnect layer is located above the first interconnect layer. The second segment of the signal line extends along the first direction, while the island-shaped connection structure extends along a second direction different from the first direction. The second segment of the signal line and the island-shaped connection structure are electrically coupled to the first segment of the signal line through a first conductive via and a second conductive via located between the first interconnect layer and the second interconnect layer, respectively. The method includes forming a third segment of the signal line in a second region of the integrated circuit device. The third segment of the signal line extends along the first direction and crosses a boundary between the first region and the second region. The third segment of the signal line is formed in a third interconnect layer of the multilayer interconnect structure, the third interconnect layer being located on top of the second interconnect layer. The third segment of the signal line is electrically coupled to the island-shaped connection structure through a third conductive via located between the second interconnect layer and the third interconnect layer.

[0132] In some embodiments, the integrated circuit device includes a static random access memory (SRAM) cell; the signal line is a bit line signal line or an anti-phase line signal line of the SRAM cell; and the bit line signal line is discontinuous in the SRAM cell and includes a plurality of discrete segments, the discrete segments including the first segment of the signal line. In some embodiments, the method further includes forming a metal line in a second interconnect layer, wherein the metal line extends along a second direction and is located between the second segment of the signal line and the island-shaped connection structure in the first direction. In some embodiments, the metal line has a size larger than that of the island-shaped connection structure in the second direction. In some embodiments, the second segment of the signal line has a size larger than that of the first segment of the signal line in the second direction. In some embodiments, the third segment is not aligned with the first segment of the signal line in the second direction. In some embodiments, a size of the island-shaped connection structure is greater than a distance corresponding to the lack of alignment between the third segment and the first segment of the signal line.

[0133] Another embodiment of this disclosure relates to a method. The method includes forming a first segment of a first (BL) signal line and a second (WL) signal line in a memory (SRAM) device. Both the first signal line and the first segment of the second signal line are formed in a first interconnect layer of a multilayer interconnect structure. The first signal line extends along a first direction. The first segment of the second signal line extends along a second direction different from the first direction. The first signal line is formed in a first region of the memory device. The first segment of the second signal line is formed in the first region of the memory device and in a second region adjacent to the first region. The method includes forming a second segment of the second signal line in a second interconnect layer of the multilayer interconnect structure in the first region. The second interconnect layer is located above the first interconnect layer. A major portion of the second segment of the second signal line extends along the second direction and is electrically coupled to the first segment of the second signal line through a first conductive via. The method includes forming a third segment of the second signal line in a third interconnect layer of the multilayer interconnect structure in the first region. The third interconnect layer is located above the second interconnect layer. A major portion of the third segment of the second signal line extends along the second direction and is electrically coupled to the second segment of the second signal line through a second conductive via. The method includes forming an island-shaped connection structure in the first interconnect layer. The island-shaped connection structure is located between the first signal line and the first segment of the second signal line in the second direction. The island-shaped connection structure is electrically coupled to the second segment of the second signal line through a third conductive via. At least one of the first signal line, the first segment of the second signal line, the second segment of the second signal line, or the third segment of the second signal line includes a bent end portion.

[0134] In some embodiments, the first interconnect layer is formed on top of the bottom layer of the interconnect structure. In some embodiments, the first region includes a memory cell array, and the second region includes circuitry other than the memory cell array. In some embodiments, the first segment of the second signal line has a larger dimension in the first direction than the second segment of the second signal line. In some embodiments, the shape of the third segment of the second signal line is substantially similar to the shape of the third segment of the second signal line in a top view, but smaller in size. In some embodiments, the second conductive via is a via guide located between the second interconnect layer and the third interconnect layer.

[0135] The foregoing outlines components of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

Claims

1. An integrated circuit device, comprising: The first interconnect element is disposed in the dielectric material of the first interconnect layer of the interconnect structure, wherein: The first interconnect element is located in a first region of the integrated circuit device; The first interconnecting element extends along a first horizontal direction in the top view; and The dielectric constant of the dielectric material is less than 3.9; A second interconnect element is disposed in the dielectric material of the first interconnect layer of the interconnect structure, wherein: The second interconnect element is located in a second region of the integrated circuit device adjacent to the first region; The second interconnecting element extends along the first horizontal direction in the top view; and The second interconnecting element is not aligned with the first interconnecting element in the top view in a second horizontal direction different from the first horizontal direction; and A third interconnect element is disposed in the dielectric material of the first interconnect layer of the interconnect structure, wherein: The third interconnect element spans the first region and the second region, and is coupled to the first interconnect element and the second interconnect element; and At least one of the first interconnecting element, the second interconnecting element, or the third interconnecting element has a curved end portion in the top view.

2. The integrated circuit device according to claim 1, wherein: The first region contains multiple static random access memory units; The second region includes circuitry other than the static random access memory cell; and The first interconnect element, the second interconnect element, and the third interconnect element are multiple portions of the bit line signal line or anti-phase line signal line of the static random access memory cell.

3. The integrated circuit device of claim 2, wherein the bit line signal line or the anti-phase line signal line located in the static random access memory cell is discontinuous and comprises a plurality of discrete segments, the discrete segments comprising the first interconnect element in the first interconnect layer.

4. The integrated circuit device according to claim 1, wherein: The first portion of the third interconnecting element is incorporated into the first interconnecting element in the top view; The second portion of the third interconnecting element is incorporated into the second interconnecting element in the top view; as well as The first part and the second part together define the transition in the top view.

5. A method for manufacturing an integrated circuit, comprising: A first segment of a signal line is formed in the first interconnect layer, wherein: The first interconnect layer is the bottom layer of the multilayer interconnect structure in the first region of the integrated circuit device; and The first segment of the signal line extends along a first direction; A second segment of the signal line and an island-shaped connection structure are formed in the second interconnect layer of the multilayer interconnect structure in the first region, wherein: The second interconnect layer is located on top of the first interconnect layer; The second segment of the signal line extends along the first direction, while the island-shaped connection structure extends along a second direction different from the first direction; and The second segment of the signal line and the island-shaped connection structure are electrically coupled to the first segment of the signal line through a first conductive via and a second conductive via located between the first interconnect layer and the second interconnect layer, respectively; and A third segment of the signal line is formed in the second region of the integrated circuit device, wherein: The third segment of the signal line extends along the first direction and crosses the boundary between the first region and the second region; The third segment of the signal line is formed in the third interconnect layer of the multilayer interconnect structure, and the third interconnect layer is located on top of the second interconnect layer; and The third segment of the signal line is electrically coupled to the island-shaped connection structure through a third conductive via located between the second interconnect layer and the third interconnect layer.

6. The integrated circuit manufacturing method according to claim 5, wherein: The integrated circuit device includes a static random access memory unit; The signal line is either the bit line signal line or the anti-phase line signal line of the static random access memory cell; and The bit line signal line is discontinuous in the static random access memory cell and includes multiple discrete segments, the discrete segments including the first segment of the signal line.

7. An integrated circuit manufacturing method, comprising: A first segment of a first signal line and a second signal line is formed in the memory device, wherein: The first signal line and the first segment of the second signal line are both formed in the first interconnect layer of a multilayer interconnect structure; The first signal line extends along a first direction; The first segment of the second signal line extends along a second direction different from the first direction; The first signal line is formed in a first region of the memory device; as well as The first segment of the second signal line is formed in the first region of the memory device and in the second region adjacent to the first region; A second segment of the second signal line is formed in the second interconnect layer of the multilayer interconnect structure in the first region, wherein: The second interconnect layer is located on top of the first interconnect layer; and The main portion of the second segment of the second signal line extends along the second direction and is electrically coupled to the first segment of the second signal line through the first conductive via. A third segment of the second signal line is formed in the third interconnect layer of the multilayer interconnect structure in the first region, wherein: The third interconnect layer is located on top of the second interconnect layer; and The main portion of the third segment of the second signal line extends along the second direction and is electrically coupled to the second segment of the second signal line through a second conductive via; and An island-shaped interconnect structure is formed in the first interconnect layer, wherein: The island-shaped connection structure is located between the first segment of the first signal line and the second signal line in the second direction; and The island-shaped connection structure is electrically coupled to the second segment of the second signal line through a third conductive via. At least one of the first signal line, the first segment of the second signal line, the second segment of the second signal line, or the third segment of the second signal line includes a bent end portion.

8. The integrated circuit manufacturing method according to claim 7, wherein the first interconnect layer is formed on the layer above the bottom layer of the interconnect structure.

9. The integrated circuit manufacturing method according to claim 7, wherein the first region comprises a memory cell array, and the second region comprises circuitry other than the memory cell array.

10. The integrated circuit manufacturing method according to claim 7, wherein the first segment of the second signal line has a larger size in the first direction than the second segment of the second signal line.

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