An SRAM cell, a manufacturing method thereof, a memory and an electronic device

Abstract

The application relates to the technical field of semiconductor devices, in particular to an SRAM unit and a manufacturing method thereof, a memory and an electronic device, which comprise a substrate; a first active region, a second active region and a third active region located on the substrate and extending along a first direction, the second active region having a first active section and a second active section arranged at intervals along the first direction; six transistors formed by the first active region, the second active region and the third active region, a first pull-down transistor and a first gate transistor formed on the first active region and arranged in sequence along the first direction; a second gate transistor and a second pull-down transistor formed on the third active region and arranged in sequence along the first direction; a first pull-up transistor formed on the first active section, and a second pull-up transistor formed on the second active section; wherein the gate of the first gate transistor is aligned with the gate of the second gate transistor in a second direction. The application significantly reduces the area of the SRAM unit and improves the array integration density.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to an SRAM cell and its manufacturing method, memory and electronic device. Background Technology

[0002] As integrated circuit technology continues to evolve towards more advanced nodes, the size of SRAM memory cells is constantly shrinking, placing increasingly higher demands on layout design. In a traditional 6T SRAM layout, multiple active regions are arranged extending along a first direction and side-by-side along a second direction, with multiple gate structures extending along the second direction and spanning each active region. Specifically, the first pull-down transistor and the first transmission gate transistor are formed on the same active region and arranged sequentially along the first direction; the second pull-down transistor and the second transmission gate transistor are formed on the same active region and arranged sequentially along the first direction; and the first pull-up transistor and the second pull-up transistor are formed on different active regions. In this traditional layout, the gate structures of each transistor are typically aligned along the first direction, and the first and second pull-up transistors are each formed on independent active regions.

[0003] However, the aforementioned traditional SRAM cell layout has several shortcomings in practical applications. First, since PU1 and PU2 are each formed on independent active regions, two redundant gate structures are generated in the boundary region between two adjacent SRAM cells along the first direction, resulting in a significant waste of active region area and limiting further reduction in SRAM cell area. Second, the layout of aligning the gate structures along the first direction restricts the wiring space, leading to a large coupling capacitance between the bit line (BL) and the complementary bit line (BLB), which affects the read / write performance and operational stability of the SRAM.

[0004] In view of this, the present invention is proposed. Summary of the Invention

[0005] The purpose of this invention is to provide an SRAM cell that significantly reduces the SRAM cell area and improves the array integration density.

[0006] In a first aspect, the present invention provides an SRAM cell, including a substrate; A first active region, a second active region, and a third active region are located on the substrate and extend along a first direction. The first active region, the second active region, and the third active region are arranged side by side in sequence along a second direction. The second active region has a first active segment and a second active segment arranged at intervals along the first direction. The second direction is perpendicular to the first direction. Six transistors are formed by the first active region, the second active region, and the third active region. The six transistors include a first pull-down transistor, a second pull-down transistor, a first pull-up transistor, a second pull-up transistor, a first gate transistor, and a second gate transistor. The first pull-down transistor and the first gate transistor are formed on the first active region and arranged sequentially along the first direction; the second gate transistor and the second pull-down transistor are formed on the third active region and arranged sequentially along the first direction; the first pull-up transistor is formed on the first active segment, and the second pull-up transistor is formed on the second active segment; The gate of the first gate transistor and the gate of the second gate transistor are aligned in the second direction.

[0007] In a preferred embodiment of this technical solution, the gate of the first pull-down transistor is aligned with the gate of the first pull-up transistor in the second direction; The gate of the second pull-down transistor is aligned with the gate of the second pull-up transistor in the second direction.

[0008] As a preferred embodiment of this technical solution, the gate structures of the first pull-down transistor and the first pull-up transistor, the gate structures of the first gate transistor and the second gate transistor, and the gate structures of the second pull-down transistor and the second pull-up transistor are arranged sequentially at intervals in the first direction.

[0009] As a preferred embodiment of this technical solution, the offset between the gate of the first pull-down transistor and the gate of the second pull-down transistor in the first direction does not exceed one gate contact distance. And / or, the offset between the gate of the first pull-up transistor and the gate of the second pull-up transistor in the first direction does not exceed one gate contact pitch.

[0010] In a preferred embodiment of this technical solution, an isolation structure is formed between the first active segment and the second active segment, and the first pull-up transistor and the second pull-up transistor are isolated from each other through the isolation structure.

[0011] As a preferred embodiment of this technical solution, the first pull-down transistor and the first pull-up transistor form a first inverter, and the second pull-down transistor and the second pull-up transistor form a second inverter; The output terminal of the first inverter is electrically connected to the gate of the second pull-down transistor and the gate of the second pull-up transistor to form a first memory node; The output of the second inverter is electrically connected to the gate of the first pull-down transistor and the gate of the first pull-up transistor to form a second memory node.

[0012] As a preferred embodiment of this technical solution, it further includes a high-level connection part, a low-level connection part, and a word line connection part; The high-level connection and the low-level connection are located on one side of the SRAM cell; The word line connection is connected to the gate contacts of the first gate transistor and the second gate transistor, and is located on the side of the SRAM cell near the high-level connection and the low-level connection.

[0013] As a preferred embodiment of this technical solution, it further includes a first bit line connection portion and a second bit line connection portion, wherein the first bit line connection portion and the second bit line connection portion are located on the other side of the SRAM cell.

[0014] As a preferred embodiment of this technical solution, the first active region, the second active region, and the third active region are any one of a planar active region, a fin-type active region, or a nanowire / sheet stacked active region.

[0015] In a preferred embodiment of this technical solution, the first pull-down transistor, the second pull-down transistor, the first gate transistor, and the second gate transistor are all N-type transistors, and the first pull-up transistor and the second pull-up transistor are both P-type transistors.

[0016] Secondly, the present invention also discloses an SRAM memory comprising a plurality of the above-described SRAM cells.

[0017] Thirdly, the present invention also discloses a method for manufacturing an SRAM cell, comprising the following steps: Provide substrate; A first active region, a second active region, and a third active region are formed on the substrate, extending along a first direction and arranged side by side along a second direction, wherein the second direction is perpendicular to the first direction; A plurality of gate structures extending along the second direction are formed on the first active region, the second active region and the third active region; By using a cutting process, redundant gate structures and channel regions are removed, so that the second active region is cut along the first direction into a first active segment and a second active segment that are spaced apart. A first pull-down transistor and a first gate transistor are formed in the first active region and arranged sequentially along the first direction. A second gate transistor and a second pull-down transistor are formed in the third active region and arranged sequentially along the first direction. A first pull-up transistor is formed in the first active segment and a second pull-up transistor is formed in the second active segment. The gate of the first gate transistor and the gate of the second gate transistor are aligned in the second direction.

[0018] As a preferred embodiment of this technical solution, the cutting process includes: The region located between the first pull-up transistor and the second pull-up transistor in the second active region is cut to remove the gate structure and channel region of the region, and a dielectric isolation layer is filled in the cut region.

[0019] As a preferred embodiment of this technical solution, when forming the plurality of gate structures, the gate of the first pull-down transistor and the gate of the first pull-up transistor are aligned in the second direction; The gate of the second pull-down transistor is aligned with the gate of the second pull-up transistor in the second direction; The gate of the first gate transistor is aligned with the gate of the second gate transistor in the second direction.

[0020] As a preferred embodiment of this technical solution, after forming a plurality of gate structures extending along the second direction on the first active region, the second active region, and the third active region, the method further includes: Sidewalls are formed on the sidewalls of the gate structure; Using the gate structure and the sidewall as a mask, source and drain regions are formed on both sides of the gate structure.

[0021] As a preferred embodiment of this technical solution, it further includes: The output terminal of the first inverter, which is composed of the first pull-down transistor and the first pull-up transistor, is electrically connected to the gate of the second pull-down transistor and the gate of the second pull-up transistor to form a first memory node; The output terminal of the second inverter, which is composed of the second pull-down transistor and the second pull-up transistor, is electrically connected to the gate of the first pull-down transistor and the gate of the first pull-up transistor to form a second memory node.

[0022] Fourthly, the present invention also discloses an electronic device including the above-mentioned SRAM cell or SRAM memory, the electronic device including a smartphone, personal computer, tablet computer, artificial intelligence device, wearable device or power bank.

[0023] The SRAM cell of the present invention has at least the following beneficial effects: 1. The SRAM cells of this invention are arranged diagonally, wherein PG1 / PG2 share a common gate, PD1 / PU1 share a common gate, and PD2 / PU2 share a common gate. These three gate structures are arranged sequentially at intervals along a first direction. Furthermore, in the second active region, the first active segment forming PG1 and the second active segment forming PG2 are spaced apart along the first direction. Compared to the conventional SRAM layout where adjacent cell boundary regions have two redundant gate structures, this invention generates only one redundant gate structure. This layout optimization reduces the cell area of ​​the SRAM cell by 12.5% ​​compared to a symmetrical SRAM layout, significantly improving wafer area utilization, reducing chip costs, and facilitating higher storage density within a limited chip area.

[0024] 2. The diagonal layout of the SRAM cells in this invention provides ample opening space for contact holes and interconnect vias, resulting in simpler interconnect paths between PG transistors and reduced interconnect length and curvature. This not only reduces the difficulty of photolithography and etching processes and widens the process window, but also shortens interconnect lengths, reduces parasitic resistance and capacitance, thereby reducing signal transmission delay and optimizing SRAM read / write speed and operational stability. Attached Figure Description

[0025] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of a traditional SRAM cell; Figure 2 This is a schematic diagram of the SRAM cell structure of the present invention; Figure 3 This is a layout of the SRAM cell of the present invention; Figure 4 The parasitic effects and performance of the SRAM cells in this invention; Figure 5 This is a layout diagram of the SRAM memory of the present invention; Figure 6 This is a comparison of the number of array cells in the present invention and a conventional SRAM array under the same rectangular boundary.

[0027] Explanation of reference numerals in the attached figures: 100: First active region; 200: Second active region; 201: First active segment; 202: Second active segment; 300: Third active region. Detailed Implementation

[0028] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0029] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0030] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0031] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0032] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0033] like Figure 1 As shown, the device layout and interconnection methods of existing SRAM cells are fixed, resulting in strong design constraints. In complex circuit scenarios, existing solutions lack flexibility for adjustment, limiting device combination, wiring layout, and cell expansion. This leads to insufficient design flexibility and makes it difficult to adapt to diverse circuit functional requirements. Furthermore, the internal interconnection space of existing SRAM cells is narrow and heavily obstructed, making interconnection structure fabrication difficult, with narrow process windows and low yields. It also easily introduces parasitic effects, affecting the read / write performance and operational stability of SRAM.

[0034] To address the aforementioned problems, this invention proposes an SRAM cell employing a diagonal transistor layout. PG1 / PG2, PD1 / PU1, and PD2 / PU2 share a common gate structure, arranged sequentially at intervals along a first direction. Furthermore, in the second active region 200, the first active segment 201 forming PG1 and the second active segment 202 forming PG2 are spaced apart along the first direction. This ensures that the boundary region between two adjacent SRAM cells along the first direction has only one redundant gate structure, effectively reducing the SRAM cell area, lowering the inter-bit line coupling capacitance, and improving device performance. Figure 1 This is a schematic diagram of the SRAM cell of the present invention.

[0035] Firstly, such as Figure 2 As shown, an embodiment of the present invention provides an SRAM cell, including a substrate and a first active region 100, a second active region 200 and a third active region 300 located on the substrate and extending along a first direction. The first active region 100, the second active region 200 and the third active region 300 are arranged side by side in sequence along a second direction, which is perpendicular to the first direction. The second active region 200 has a first active segment 201 and a second active segment 202 that are spaced apart along the first direction.

[0036] Six transistors are formed by a first active region 100, a second active region 200, and a third active region 300. The six transistors include a first pull-down transistor, a second pull-down transistor, a first pull-up transistor, a second pull-up transistor, a first gate transistor, and a second gate transistor. The first pull-down transistor and the first gate transistor are formed on the first active region 100 and arranged sequentially along a first direction. The second gate transistor and the second pull-down transistor are formed on the third active region 300 and arranged sequentially along the first direction. The first pull-up transistor is formed on a first active segment 201, and the second pull-up transistor is formed on a second active segment 202. The gates of the first gate transistor and the second gate transistor are aligned in a second direction.

[0037] The following is in conjunction with the appendix Figure 2-3 The structure of the SRAM cell of the present invention will be described in detail.

[0038] In this embodiment of the invention, the substrate is used to provide a supporting foundation for the SRAM cell. The substrate can be any suitable semiconductor substrate material known in the art, such as single-crystal silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-on-insulator (SOI), or germanium-on-insulator (GOI), and is preferably a single-crystal silicon substrate.

[0039] A first active region 100, a second active region 200, and a third active region 300 are formed on a substrate, extending along a first direction and arranged side-by-side along a second direction. Here, the active region refers to the area in the substrate used to form the transistor channel region and the source / drain region. The three active regions are arranged side-by-side along the second direction, wherein the first active region 100 and the third active region 300 are used to form N-type transistors (pull-down transistors and gate transistors), and the second active region 200 is used to form P-type transistors (pull-up transistors).

[0040] The second active region 200 has a first active segment 201 and a second active segment 202 spaced apart along a first direction. That is, the second active region 200 is not a continuous active region, but is divided into two separate active segments along the first direction. The first active segment 201 is used to form a first pull-up transistor, and the second active segment 202 is used to form a second pull-up transistor. An isolation structure is formed between the first active segment 201 and the second active segment 202, thereby achieving electrical isolation between the first and second pull-up transistors. This differs from the traditional SRAM layout where PU1 and PU2 are each formed on independent active regions. By setting the second active region 200 as an intermittent structure and combining it with a diagonal gate arrangement, this invention effectively reduces the number of redundant gate structures in the boundary regions of adjacent cells.

[0041] In some embodiments of the present invention, the first active region 100, the second active region 200, and the third active region 300 can be any one of a planar active region, a fin active region, or a nanowire / sheet stacked active region. That is, the SRAM cell of the present invention can be applied to different device architectures such as planar transistors (MOSFETs), fin field-effect transistors (FinFETs), or gate-all-around transistors (GAA-FETs). For a planar active region, the active region is a flat area on the substrate surface; for a fin active region, the active region is a fin-like structure protruding from the substrate surface; for a nanowire / sheet stacked active region, the active region includes multiple vertically stacked nanowires or nanosheets. The present invention has good compatibility with different device architectures.

[0042] The SRAM cell in this embodiment of the invention includes six transistors: a first pull-down transistor (PD1), a second pull-down transistor (PD2), a first pull-up transistor (PU1), a second pull-up transistor (PU2), a first gate transistor (PG1), and a second gate transistor (PG2), wherein the pull-down transistor and the gate transistor are N-type transistors, and the pull-up transistor is a P-type transistor.

[0043] Specifically, the first pull-down transistor and the first gate transistor are formed on the first active region 100 and arranged sequentially along the first direction. That is, the first pull-down transistor and the first gate transistor are formed sequentially on the first active region 100 along the first direction. The first pull-down transistor and the first gate transistor share the first active region 100 as the basis for the channel region and the source / drain region.

[0044] The second gate transistor and the second pull-down transistor are formed on the third active region 300 and arranged sequentially along the first direction. That is, on the third active region 300, the second gate transistor and the second pull-down transistor are formed sequentially along the first direction, and the second pull-down transistor and the second gate transistor share the third active region 300 as the basis for the channel region and the source / drain region.

[0045] The first pull-up transistor is formed on the first active segment 201 of the second active region 200, and the second pull-up transistor is formed on the second active segment 202 of the second active region 200. Since the first active segment 201 and the second active segment 202 are spaced apart in the second active region 200, the first pull-up transistor and the second pull-up transistor are physically separated from each other, and electrical isolation between them is achieved through an isolation structure.

[0046] The above transistor distribution method allows the six transistors to form a three-row, three-column layout on the board: the first row (first active region 100) contains PD1 and PG1, the second row (second active region 200) contains PU1 and PU2 (located on two active segments respectively), and the third row (third active region 300) contains PG2 and PD2. When combined with the staggered arrangement of the gate structure, a diagonal transistor layout can be formed.

[0047] In this embodiment of the invention, each transistor includes a gate, a channel region, and source / drain regions located on both sides of the channel region along a first direction, wherein the gate of each transistor extends along a second direction, that is, the gate structure is arranged across each active region along the second direction.

[0048] Specifically, the gates of the first and second transistors are aligned in the second direction. That is, the gates of PG1 and PG2 are located on the same straight line extending along the second direction, and they belong to the same gate structure. Since PG1 is located on the first active region 100 and PG2 is located on the third active region 300, this gate structure spans the first active region 100 and the third active region 300. At the location of the second active region 200 (the area where PU1 and PU2 are located), it is cut off or does not extend through, thereby avoiding unnecessary coupling with the P-type active region.

[0049] In some embodiments of the present invention, the gate of the first pull-down transistor is aligned with the gate of the first pull-up transistor in a second direction. That is, the gate of PD1 and the gate of PU1 are located on the same straight line extending along the second direction, and they belong to the same gate structure. PD1 is located on the first active region 100, and PU1 is located on the first active segment 201 of the second active region 200. Therefore, this gate structure spans the first active region 100 and the first active segment 201 of the second active region 200, realizing the electrical connection between the gates of PD1 and PU1, and providing a physical basis for the common-gate node of the first inverter.

[0050] In some embodiments of the present invention, the gate of the second pull-down transistor is aligned with the gate of the second pull-up transistor in a second direction. That is, the gate of PD2 and the gate of PU2 are located on the same straight line extending along the second direction, and they belong to the same gate structure. PD2 is located on the third active region 300, and PU2 is located on the second active segment 202 of the second active region 200. Therefore, this gate structure spans the third active region 300 and the second active segment 202 of the second active region 200, realizing the electrical connection between the gates of PD2 and PU2, and providing a physical basis for the common-gate node of the second inverter.

[0051] Therefore, the SRAM cell of this invention contains three gate structures extending along the second direction: the first is the gate structure containing the first and second gate transistors (i.e., the PG1 / PG2 gate structure), the second is the gate structure containing the first pull-down transistor and the first pull-up transistor (i.e., the PD1 / PU1 gate structure), and the third is the gate structure containing the second pull-down transistor and the second pull-up transistor (i.e., the PD2 / PU2 gate structure). These three gate structures extend along the second direction and each spans a different combination of active regions. More importantly, these three gate structures are arranged sequentially and at intervals along the first direction; that is, in the first direction, the three gate structures are not aligned on the same straight line, but are staggered and arranged sequentially and at intervals.

[0052] The specific meaning of this "arranged in sequence" is that along the first direction (i.e., the channel length direction), the three gate structures are located in three different positions, with a certain spacing between adjacent gate structures. For example, taking the first direction from left to right as a reference, they are arranged as follows: PD1 / PU1 gate structure, PG1 / PG2 gate structure, and PD2 / PU2 gate structure. That is, the three gate structures are not aligned on the same straight line, but are arranged sequentially along the first direction. This layout makes the different gate structures appear "diagonally" in a top view.

[0053] The diagonal layout of this invention breaks the fixed layout constraint of the gate structure being aligned along the first direction in traditional SRAM, reserving sufficient opening space for contact holes and interconnect vias, effectively increasing wiring space and reducing the difficulty of interconnect structure fabrication.

[0054] In some embodiments of the present invention, the offset between the gate of the first pull-down transistor and the gate of the second pull-down transistor in a first direction does not exceed one gate contact pitch (CPP). The gate contact pitch refers to the minimum distance between the gates of adjacent transistors and is a core design parameter in semiconductor manufacturing. The specific value of CPP varies for different process nodes; for example, the CPP for a 5nm process is approximately 48 to 51 nm, and for a 2nm process, it is approximately 30 to 32 nm. Limiting the offset to no more than one CPP avoids excessive expansion of the lateral dimensions of the layout, which is beneficial for cell miniaturization and reduces the area occupied by the SRAM.

[0055] Similarly, the offset between the gate of the first pull-up transistor and the gate of the second pull-up transistor in the first direction does not exceed one gate contact pitch. Since the gate of PU1 is aligned with the gate of PD1 in the second direction, and the gate of PU2 is aligned with the gate of PD2 in the second direction, the offset between PU1 and PU2 is substantially the same as the offset between PD1 and PD2.

[0056] By properly controlling the offset, this invention can achieve the beneficial effects of a diagonal layout while avoiding an excessive increase in the lateral size of the cells due to excessive gate offset, thus ensuring a good balance between area reduction and layout flexibility.

[0057] In the SRAM cell of this embodiment of the invention, the first pull-down transistor and the first pull-up transistor constitute a first inverter, and the second pull-down transistor and the second pull-up transistor constitute a second inverter.

[0058] The output of the first inverter is electrically connected to the gates of the second pull-down transistor and the second pull-up transistor, forming a first memory node (QB). Specifically, the output of the first inverter refers to the common connection node between the drains of the first pull-down transistor and the first pull-up transistor. This node is electrically connected to the gates of the second pull-down transistor and the second pull-up transistor through an interconnect layer, forming a cross-coupled connection.

[0059] The output of the second inverter is electrically connected to the gates of the first pull-down transistor and the first pull-up transistor, forming a second memory node (Q). Specifically, the output of the second inverter refers to the common connection node between the drains of the second pull-down transistor and the second pull-up transistor. This node is electrically connected to the gates of the first pull-down transistor and the first pull-up transistor through an interconnect layer, forming a cross-coupled connection.

[0060] In some embodiments of the present invention, the SRAM cell further includes a high-level connection portion (VDD connection portion), a low-level connection portion (VSS connection portion), and a word line connection portion (WL connection portion). The high-level connection portion is used to connect to the power supply voltage VDD, and the low-level connection portion is used to connect to the ground terminal VSS. The high-level connection portion and the low-level connection portion are located on one side of the SRAM cell. The word line connection portion is connected to the gate contacts of the first gate transistor and the second gate transistor, and is located on the side of the SRAM cell closer to the high-level connection portion and the low-level connection portion. That is, the VDD, VSS, and WL connections are all arranged on the same side of the SRAM cell, which helps to simplify the interconnection structure and reduce the wiring length.

[0061] In some embodiments of the present invention, the SRAM cell further includes a first bit line connection (BL connection) and a second bit line connection (BLB connection). The first bit line connection and the second bit line connection are located on the other side of the SRAM cell, and the first memory node and the second memory node are also located on the other side of the SRAM cell, arranged on the same side as the first bit line connection (BL) and the second bit line connection (BLB). That is, by introducing a back-side process, the bit line connection and the power / word line connection can be placed on both sides of the SRAM cell. This layout significantly increases the physical spacing between the word line (WL) and the first bit line connection (BL) and the second bit line connection (BLB), effectively reducing the coupling interference of parasitic capacitance on the memory node potential and improving the stability of data retention.

[0062] Figure 4 This describes the parasitic effects and performance characteristics of the SRAM cells in this invention. Figure 4 As can be seen, the layout of the present invention significantly increases the physical spacing between the word line (WL) and the first bit line connection portion (BL) and the second bit line connection portion (BLB), reduces parasitic effects, and thus significantly improves the performance of SRAM.

[0063] Secondly, such as Figure 5 As shown, this embodiment of the invention provides an SRAM memory including multiple SRAM cells. The multiple SRAM cells can be arranged in an array along a first direction and / or a second direction to form an SRAM memory array. With PD:PG:PU = 1:1:1, the cell area of ​​the SRAM of this invention can be reduced by 12.5% ​​compared to a traditional symmetrical SRAM layout. For large-scale arrays, since the internal components of the array are closely adjacent, although there will be some wasted transistors in the diagonal SRAM at the boundaries, the proportion is very small. For example, as... Figure 6 As shown, given a 100*100 rectangle (in transistor units), the density can be increased by 10.5%. As the array size increases, the increase gets closer and closer to the ideal value. Therefore, SRAM memories using the SRAM cells of this invention can integrate more memory cells on the same chip area, increasing storage density.

[0064] Thirdly, embodiments of the present invention provide a method for manufacturing an SRAM cell. The structure of the SRAM cell formed by the manufacturing method provided in the third aspect of the present invention is the same as the structure of the SRAM cell provided in the first aspect. Therefore, the beneficial effects of the third aspect and its various implementations in the present invention can be referred to the analysis of the beneficial effects in the first aspect and its various implementations, and will not be repeated here.

[0065] Specifically, the manufacturing method of this SRAM cell includes the following steps: First, a substrate is provided. The substrate can be any suitable semiconductor substrate material known in the art, such as a single-crystal silicon substrate.

[0066] Next, a first active region 100, a second active region 200, and a third active region 300 are formed on the substrate, extending along a first direction and arranged side by side along a second direction.

[0067] Specifically, a hard mask layer is deposited on the substrate surface, and the active region is defined by photolithography. Furthermore, anisotropic dry etching is used, with a hard mask as a barrier layer, to etch the substrate and form the active region structure; Furthermore, the hard mask layer is removed, and the surface of the active region is planarized. Furthermore, an isolation medium is deposited between the active regions, and a shallow trench isolation structure (STI) is formed through a back-etching process to achieve electrical isolation between different active regions.

[0068] When forming a fin field-effect transistor, the active region is a fin-shaped structure protruding from the substrate surface.

[0069] When forming a gate-all-around transistor, the active region includes multiple vertically stacked nanowires or nanosheets, which can be formed by epitaxially growing alternately stacked channel layers and channel sacrificial layers, and then selectively etching to release the channel layers.

[0070] Next, a plurality of gate structures extending along the second direction are formed on the first active region 100, the second active region 200 and the third active region 300.

[0071] Specifically, the gate structure can be formed using either a front-gate process or a back-gate process, depending on the actual process requirements.

[0072] When using a front-gate process, a gate dielectric layer and a gate electrode layer can be deposited sequentially on the device surface, and then multiple gate structures extending along a second direction can be patterned by photolithography and anisotropic etching.

[0073] When using a post-gate process, a dummy gate dielectric layer and a dummy gate electrode layer (e.g., a polysilicon layer) can be deposited sequentially on the device surface. Multiple dummy gate structures are formed by photolithography and anisotropic etching. After the source / drain regions are formed and annealed for activation, the dummy gate structures are removed to form a gate trench, and a high-k gate dielectric layer and a metal gate electrode layer are deposited sequentially in the gate trench.

[0074] Next, source and drain regions are formed on both sides of the gate structure.

[0075] Specifically, doped ions of the corresponding conductivity type can be implanted into the active regions on both sides of the gate structure through ion implantation to form source and drain regions.

[0076] For N-type transistors (pull-down transistors and gate transistors), N-type ions (such as phosphorus or arsenic) can be implanted; for P-type transistors (pull-up transistors), P-type ions (such as boron) can be implanted.

[0077] Further, annealing is performed to activate the dopant ions.

[0078] In addition, selective epitaxy can be used to grow doped semiconductor materials (such as Si or SiGe) on both sides of the gate structure as source / drain regions.

[0079] Next, through a cutting process, redundant gate structures and channel regions are removed, so that the second active region 200 is cut along the first direction into a first active segment 201 and a second active segment 202 that are spaced apart.

[0080] Specifically, the region located between the first pull-up transistor and the second pull-up transistor in the second active region 200 is cut to remove the gate structure and channel region of the region, and a dielectric isolation layer is filled in the cut region.

[0081] The cutting process here can use photolithography to define the cutting area, then remove the gate structure and active area material of the area through anisotropic etching, finally deposit an insulating dielectric (such as silicon oxide) to fill the cutting area, and then planarize it through chemical mechanical polishing.

[0082] Thus, the core structure of the SRAM cell of this invention is formed: a first pull-down transistor and a first gate transistor (PD1→PG1) are sequentially arranged along the first direction on the first active region 100; a second gate transistor and a second pull-down transistor (PG2→PD2) are sequentially arranged along the first direction on the third active region 300; a first pull-up transistor is formed on the first active segment 201 of the second active region 200; and a second pull-up transistor is formed on the second active segment 202 of the second active region 200. The gates of the first gate transistor and the second gate transistor are aligned in the second direction; the gates of the first pull-down transistor and the first pull-up transistor are aligned in the second direction; and the gates of the second pull-down transistor and the second pull-up transistor are aligned in the second direction. The three gate structures are arranged at intervals in the first direction.

[0083] Next, an interconnect layer is formed to achieve electrical connections between the transistors.

[0084] Specifically, an interlayer dielectric layer is deposited on the device surface, contact holes are etched to form the contact holes, and then a metal layer (such as tungsten, copper, or cobalt) is deposited and patterned to form an interconnect layer. Through the interconnect layer, the output terminal of a first inverter composed of a first pull-down transistor and a first pull-up transistor is electrically connected to the gate of a second pull-down transistor and the gate of a second pull-up transistor, forming a first memory node (QB); the output terminal of a second inverter composed of a second pull-down transistor and a second pull-up transistor is electrically connected to the gate of the first pull-down transistor and the gate of the first pull-up transistor, forming a second memory node (Q).

[0085] Next, a back-side process is introduced to continue fabricating a multilayer metal interconnect structure and interlayer vias, sequentially forming a high-level connection (VDD connection), a low-level connection (VSS connection), a word line connection (WL connection), a first bit line connection (BL connection), and a second bit line connection (BLB connection). The high-level and low-level connections are located on one side of the SRAM cell, and the word line connection is also located on that side; the first bit line connection and the second bit line connection are located on the other side of the SRAM cell; and the first and second memory nodes are also located on the other side of the SRAM cell, arranged on the same side as the first bit line connection and the second bit line connection.

[0086] Finally, a passivation layer (such as silicon nitride) is deposited to complete the fabrication of the SRAM cell.

[0087] Fourthly, embodiments of the present invention provide an electronic device including the aforementioned SRAM cell or SRAM memory. The electronic device includes, but is not limited to, smartphones, personal computers, tablet computers, artificial intelligence devices, wearable devices, or power banks. Because the SRAM cell of the present invention has advantages such as small area, low power consumption, and good read / write performance, electronic devices using the SRAM cell of the present invention can achieve higher storage capacity and better performance within a limited space.

[0088] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that layers and regions of desired shapes can be formed using various technical means. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An SRAM cell, characterized in that, Including substrate; A first active region, a second active region, and a third active region are located on the substrate and extend along a first direction. The first active region, the second active region, and the third active region are arranged side by side in sequence along a second direction. The second active region has a first active segment and a second active segment arranged at intervals along the first direction. The second direction is perpendicular to the first direction. Six transistors are formed by the first active region, the second active region, and the third active region. The six transistors include a first pull-down transistor, a second pull-down transistor, a first pull-up transistor, a second pull-up transistor, a first gate transistor, and a second gate transistor. The first pull-down transistor and the first gate transistor are formed on the first active region and arranged sequentially along the first direction; the second gate transistor and the second pull-down transistor are formed on the third active region and arranged sequentially along the first direction; the first pull-up transistor is formed on the first active segment, and the second pull-up transistor is formed on the second active segment; The gate of the first gate transistor and the gate of the second gate transistor are aligned in the second direction.

2. The SRAM cell according to claim 1, characterized in that, The gate of the first pull-down transistor is aligned with the gate of the first pull-up transistor in the second direction; The gate of the second pull-down transistor is aligned with the gate of the second pull-up transistor in the second direction.

3. The SRAM cell according to claim 1, characterized in that, The gate structures containing the first pull-down transistor and the first pull-up transistor, the gate structures containing the first gate transistor and the second gate transistor, and the gate structures containing the second pull-down transistor and the second pull-up transistor are arranged sequentially at intervals in the first direction.

4. The SRAM cell according to claim 1, characterized in that, The offset between the gate of the first pull-down transistor and the gate of the second pull-down transistor in the first direction does not exceed one gate contact pitch; And / or, the offset between the gate of the first pull-up transistor and the gate of the second pull-up transistor in the first direction does not exceed one gate contact pitch.

5. The SRAM cell according to claim 1, characterized in that, An isolation structure is formed between the first active segment and the second active segment, and the first pull-up transistor and the second pull-up transistor are isolated from each other through the isolation structure.

6. The SRAM cell according to claim 1, characterized in that, The first pull-down transistor and the first pull-up transistor form a first inverter, and the second pull-down transistor and the second pull-up transistor form a second inverter; The output terminal of the first inverter is electrically connected to the gate of the second pull-down transistor and the gate of the second pull-up transistor to form a first memory node; The output of the second inverter is electrically connected to the gate of the first pull-down transistor and the gate of the first pull-up transistor to form a second memory node.

7. The SRAM cell according to claim 1, characterized in that, It also includes a high-level connection section, a low-level connection section, and a word line connection section; The high-level connection and the low-level connection are located on one side of the SRAM cell; The word line connection is connected to the gate contacts of the first gate transistor and the second gate transistor, and is located on the side of the SRAM cell near the high-level connection and the low-level connection.

8. The SRAM cell according to claim 7, characterized in that, It also includes a first bit line connection portion and a second bit line connection portion, which are located on the other side of the SRAM cell.

9. The SRAM cell according to claim 1, characterized in that, The first active region, the second active region, and the third active region are each any one of a planar active region, a fin-type active region, or a nanowire / sheet stacked active region.

10. The SRAM cell according to claim 1, characterized in that, The first pull-down transistor, the second pull-down transistor, the first gate transistor, and the second gate transistor are all N-type transistors, and the first pull-up transistor and the second pull-up transistor are both P-type transistors.

11. An SRAM memory, characterized in that, It includes the SRAM cells of any one of claims 1-10.

12. A method for manufacturing an SRAM cell, characterized in that, Includes the following steps: Provide substrate; A first active region, a second active region, and a third active region are formed on the substrate, extending along a first direction and arranged side by side along a second direction, wherein the second direction is perpendicular to the first direction; A plurality of gate structures extending along the second direction are formed on the first active region, the second active region and the third active region; By using a cutting process, redundant gate structures and channel regions are removed, so that the second active region is cut along the first direction into a first active segment and a second active segment that are spaced apart. A first pull-down transistor and a first gate transistor are formed in the first active region and arranged sequentially along the first direction. A second gate transistor and a second pull-down transistor are formed in the third active region and arranged sequentially along the first direction. A first pull-up transistor is formed in the first active segment and a second pull-up transistor is formed in the second active segment. The gate of the first gate transistor and the gate of the second gate transistor are aligned in the second direction.

13. The manufacturing method according to claim 12, characterized in that, The cutting process includes: The region located between the first pull-up transistor and the second pull-up transistor in the second active region is cut to remove the gate structure and channel region of the region, and a dielectric isolation layer is filled in the cut region.

14. The manufacturing method according to claim 12, characterized in that, When forming the plurality of gate structures, the gate of the first pull-down transistor is aligned with the gate of the first pull-up transistor in the second direction; The gate of the second pull-down transistor is aligned with the gate of the second pull-up transistor in the second direction; The gate of the first gate transistor is aligned with the gate of the second gate transistor in the second direction.

15. The manufacturing method according to claim 12, characterized in that, After forming a plurality of gate structures extending along the second direction on the first active region, the second active region, and the third active region, the method further includes: Sidewalls are formed on the sidewalls of the gate structure; Using the gate structure and the sidewall as a mask, source and drain regions are formed on both sides of the gate structure.

16. The manufacturing method according to claim 12, characterized in that, Also includes: The output terminal of the first inverter, which is composed of the first pull-down transistor and the first pull-up transistor, is electrically connected to the gate of the second pull-down transistor and the gate of the second pull-up transistor to form a first memory node; The output terminal of the second inverter, which is composed of the second pull-down transistor and the second pull-up transistor, is electrically connected to the gate of the first pull-down transistor and the gate of the first pull-up transistor to form a second memory node.

17. An electronic device, characterized in that, Includes the SRAM cell of any one of claims 1-10 or the SRAM memory of claim 11; The electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, or power banks.

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