Semiconductor device and method of manufacturing the same, memory system

Abstract

Embodiments of the present disclosure provide a semiconductor device, a method for manufacturing the semiconductor device, and a memory system. The semiconductor device includes a semiconductor body and a bit line structure. The semiconductor body extends along a first direction; the bit line structure is located at one side of the semiconductor body in the first direction and extends along a second direction, wherein the first direction intersects the second direction; wherein the semiconductor body includes a first end portion facing away from the bit line structure in the first direction, the first end portion having a doping element, the doping element including at least one of a noble gas element, a group III element, a group IV element, a group V element, and fluorine.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a method for fabricating a semiconductor device, and a memory system. Background Technology

[0002] Semiconductor devices can be used in memory, such as Dynamic Random Access Memory (DRAM). DRAM is widely used in the memory of electronic devices such as computers and mobile phones due to its simple structure, large capacity, high density, low power consumption, and high speed. Summary of the Invention

[0003] In a first aspect, some embodiments of this disclosure provide a semiconductor device. The semiconductor device includes a semiconductor body and a bit line structure. The semiconductor body extends along a first direction; the bit line structure is located on one side of the semiconductor body in the first direction and extends along a second direction, wherein the first direction intersects the second direction; wherein the semiconductor body includes a first end portion facing away from the bit line structure in the first direction, the first end portion having a doping element, the doping element including at least one of rare gas elements, group III elements, group IV elements, group V elements, and fluorine.

[0004] In an exemplary embodiment, the doping element includes at least one of argon, xenon, boron, indium, germanium, carbon, nitrogen, phosphorus, arsenic, and fluorine.

[0005] In an exemplary embodiment, in the first direction, the doping concentration of the portion of the first end facing away from the bit line structure is greater than the doping concentration of the portion of the first end facing the bit line structure.

[0006] In an exemplary embodiment, the material of the semiconductor body includes monocrystalline silicon.

[0007] In an exemplary embodiment, the semiconductor device further includes a connection structure. The connection structure is located on a side of the semiconductor body opposite to the bit line structure in a first direction and is connected to the semiconductor body.

[0008] In an exemplary embodiment, in the second direction, the dimensions of the connecting structure are equal to the dimensions of the first end.

[0009] In an exemplary embodiment, a plurality of semiconductor bodies and connection structures connected thereto are arranged at intervals in a second direction. The semiconductor device also includes an isolation body structure and an isolation pad layer. The isolation body structure is located between adjacent connection structures in the second direction. At least a portion of the isolation pad layer is located on opposite sides of the isolation body structure in the second direction and is in contact with the connection structure. The isolation body structure and the isolation pad layer are made of different materials.

[0010] In an exemplary embodiment, the material of the insulating body structure includes silicon nitride, and the material of the insulating liner layer includes silicon oxide.

[0011] In an exemplary embodiment, the connection structure includes a metal silicide portion and a conductive body portion in a first direction, with the metal silicide portion in contact with the semiconductor body. In a second direction, the size of the conductive body portion is larger than the size of the first end portion.

[0012] In an exemplary embodiment, a plurality of semiconductor bodies and connection structures connected thereto are arranged at intervals in a second direction. The semiconductor device also includes an isolation body structure. The isolation body structure is located between adjacent conductive body portions in the second direction and is in contact with the conductive body portions.

[0013] In an exemplary embodiment, the semiconductor device further includes a gate structure and a gate dielectric layer. The gate structure is located on at least one side of the semiconductor body in a direction intersecting the first direction and extends along a third direction. The gate dielectric layer is located between the gate structure and the semiconductor body. The first direction, the second direction, and the third direction intersect each other.

[0014] In an exemplary embodiment, the semiconductor device further includes a capacitor structure. The capacitor structure is located on a side of the semiconductor body opposite to the bit line structure in a first direction. A portion of the capacitor structure is used to form a capacitor, which is connected to the connection structure.

[0015] Secondly, some embodiments of this disclosure provide a memory system. The memory system includes a memory and a controller, the memory including semiconductor devices as mentioned in any of the embodiments described above. The controller is coupled to the memory and is used to control the memory to store data.

[0016] Thirdly, some embodiments of this disclosure provide a method for fabricating a semiconductor device. The method includes: forming an initial semiconductor body extending along a first direction, wherein the material of the initial semiconductor body includes a single-crystal material; converting a first portion of the initial semiconductor body in the first direction into an amorphous portion; and etching the amorphous portion to obtain the semiconductor body.

[0017] In an exemplary embodiment, converting a first portion of an initial semiconductor body in a first direction into an amorphous portion includes: incorporating a dopant element into the first portion through an ion implantation process to convert the single-crystal first portion into an amorphous portion.

[0018] In an exemplary embodiment, the doping element includes at least one of rare gas elements, group III elements, group IV elements, group V elements, and fluorine.

[0019] In an exemplary embodiment, the doping element includes at least one of argon, xenon, boron, indium, germanium, carbon, nitrogen, phosphorus, arsenic, and fluorine.

[0020] In an exemplary embodiment, the material of the initial semiconductor body includes monocrystalline silicon, wherein etching the amorphous portion includes etching the amorphous portion using chlorine gas, wherein the material of the amorphous portion includes amorphous silicon.

[0021] In an exemplary embodiment, a plurality of initial semiconductor bodies are spaced apart in a second direction, and the first direction intersects the second direction. The fabrication method further includes: forming an isolation pad layer and an isolation body structure between first portions of adjacent initial semiconductor bodies in the second direction, wherein the isolation pad layer is located on opposite sides of the isolation body structure in the second direction and on one side in the first direction; wherein, after forming the isolation pad layer and the isolation body structure, the first portions are transformed and the amorphous portion is etched.

[0022] In an exemplary embodiment, the material of the isolation liner layer includes silicon oxide, and the material of the isolation host structure includes silicon nitride.

[0023] In an exemplary embodiment, the fabrication method further includes forming a connection structure on one side of the semiconductor body in a first direction, wherein the connection structure is located between adjacent isolation body structures in a second direction.

[0024] In an exemplary embodiment, before forming a connection structure on one side of the semiconductor body in the first direction, the fabrication method further includes removing portions of the isolation liner layer located on opposite sides of the isolation body structure in the second direction.

[0025] In an exemplary embodiment, the fabrication method further includes: forming a gate structure on at least one side of the semiconductor body in a direction intersecting with the first direction, wherein the gate structure extends along a third direction, and the first direction, the second direction, and the third direction intersect each other; and forming a gate dielectric layer between the gate structure and the semiconductor body.

[0026] In an exemplary embodiment, the fabrication method further includes: forming a bit line structure on one side of the semiconductor body in a first direction, the bit line structure extending along a second direction, the first direction intersecting the second direction; and forming a capacitor structure on the side of the semiconductor body away from the bit line structure in the first direction, wherein a portion of the capacitor structure is used to constitute a capacitor, and the capacitor is connected to the semiconductor body. Attached Figure Description

[0027] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0028] Figure 1This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this disclosure;

[0029] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this disclosure;

[0030] Figure 3 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0031] Figures 4A to 4J This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this disclosure during the fabrication process;

[0032] Figures 5A to 5D This is a cross-sectional schematic diagram of a semiconductor device during its fabrication process, provided in another embodiment of this disclosure;

[0033] Figure 6 This is a schematic block diagram of a system with a memory system provided in the embodiments of this disclosure; and

[0034] Figure 7A and Figure 7B This is a schematic block diagram of a memory system provided in an embodiment of this disclosure. Detailed Implementation

[0035] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this disclosure, the first end discussed herein may also be referred to as the second end, and vice versa.

[0037] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0038] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0039] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0040] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0041] Furthermore, when the term “connection” or “linkage” is used in this disclosure, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0042] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0043] This disclosure provides a semiconductor device through some embodiments. Figure 1 A schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure is shown.

[0044] It should be noted that the D1 direction (corresponding to the first direction), D2 direction (corresponding to the second direction), and D3 direction (corresponding to the third direction) in the various figures illustrate the spatial relationships of the components in the semiconductor device. For example, the D1 direction may be the extension direction of the semiconductor body, and the D2 and D3 directions may be two directions that intersect (e.g., are perpendicular to each other) on planes that intersect (e.g., are perpendicular to) the aforementioned extension directions. For example, the D2 direction may be the extension direction of the bit line structure. The same concepts will be used throughout this disclosure to describe the spatial relationships of the components in the semiconductor device.

[0045] like Figure 1 As shown, the semiconductor device 100 may include a semiconductor body 110 and a bit line structure 121. The semiconductor body 110 extends along the D1 direction. The bit line structure 121 is located on one side of the semiconductor body 110 in the D1 direction and extends along the D2 direction. The semiconductor body 110 includes a first end 111 facing away from the bit line structure 121 in the D1 direction. The first end 111 has a doped element. The doped element includes at least one of rare gas elements, group III elements, group IV elements, group V elements, and fluorine.

[0046] According to some embodiments, the surface of the first end 111 facing away from the bit line structure 121 in the D1 direction can be obtained by etching a first portion of the initial semiconductor body. Before etching, the first portion is bombarded with dopant ions, causing the first portion to be converted from a single-crystal portion to an amorphous portion. During the etching process, the amorphous portion is etched at a faster rate than other unconverted single-crystal portions of the initial semiconductor body, thereby reducing the influence of the interface states of the first portion on etching inhomogeneity and ensuring the position of the surface of the first end 111 in the D1 direction. When the semiconductor device 100 includes a plurality of semiconductor bodies 110, this helps to improve the consistency of the position of the surface of each of the plurality of semiconductor bodies 110. After etching, the elements of these bombarding ions remain in the first end 111 of the semiconductor body 110.

[0047] In some embodiments, the semiconductor body 110 may be a columnar structure extending generally along the D1 direction. In addition to the first end 111, the semiconductor body 110 may also include a second end 112 in the D1 direction near the bit line structure 121, and a middle portion 113 located between the first end 111 and the second end 112. The first end 111, the second end 112, and the middle portion 113 may be a single integral structure. For example, the first end 111 may serve as one of the source or drain of a transistor (e.g., the source). Ensuring that the surface of the first end 111 is in a predetermined position in the D1 direction helps to ensure the performance of the transistor and the performance consistency of multiple transistors. For example, the second end 112 may serve as the other of the source or drain of a transistor (e.g., the drain). The middle portion 113 may serve as the channel of the transistor.

[0048] In some embodiments, multiple semiconductor bodies 110 may be arranged in the D2 direction, or in the D3 direction. For example, multiple semiconductor bodies 110 may be arranged in an array in both the D2 and D3 directions. For example, a row of semiconductor bodies 110 arranged in the D2 direction may be aligned with each other, and a row of semiconductor bodies 110 arranged in the D3 direction may also be aligned with each other. In some examples, the second ends 112 of each of the semiconductor bodies 110 in a row arranged in the D2 direction may be connected to each other, while two adjacent rows of semiconductor bodies 110 in the D3 direction may be spaced apart by an insulating material.

[0049] In some embodiments, the semiconductor body 110 may be made of a single-crystal material. The material of the semiconductor body 110 may include silicon, germanium, germanium-silicon, silicon carbide, gallium nitride, or any other suitable single-crystal semiconductor material. In one example, the semiconductor body 110 may be made of single-crystal silicon. For example, the first end 111, the second end 112, and the middle portion 113 are all made of single-crystal silicon.

[0050] In some embodiments, the dopant element can be incorporated via an ion implantation process. As a result, the concentration of the dopant element decreases with increasing doping depth. Therefore, in the D1 direction, the dopant element concentration of the portion of the first end 111 away from the bit line structure 121 is greater than the dopant element concentration of the portion of the first end 111 facing the bit line structure 121. As an example, the dopant element concentration of the first end 111 decreases along the D1 direction toward the bit line structure 121.

[0051] In some embodiments, the dopant element may be at least one of argon, xenon, boron, indium, germanium, carbon, nitrogen, phosphorus, arsenic, and fluorine. These dopant element ions may serve as bombardment ions. In some examples, boron and fluorine are used in the form of BF2. + The formation of [something] is incorporated.

[0052] In some embodiments, the bit line structure 121 may be connected to each of a row of semiconductor bodies 110. When the second ends 112 of each of the semiconductor bodies 110 in a row are connected to each other, the bit line structure 121 may contact the connected portion.

[0053] In some embodiments, the material of the bit line structure 121 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, metal silicides, or any other suitable conductive material. For example, the metal silicide may include a silicide of at least one of titanium, cobalt, nickel, and platinum.

[0054] In some embodiments, a plurality of bit line structures 121 may be arranged in the D3 direction. Each bit line structure 121 may be connected (e.g., contacted) to a second end 112 of each of a corresponding row of semiconductor bodies 110.

[0055] In some implementations, such as Figure 1 As shown, the semiconductor device 100 may further include a gate structure 151. The gate structure 151 may be located on at least one side of the semiconductor body 110 in a direction intersecting the D1 direction and extends along the D3 direction. In some examples, the gate structure 151 may be located on one side of the middle portion 113 of the semiconductor body 110 in the D2 direction and extends along the D3 direction. In other examples, the gate structure 151 may be located on opposite sides of the middle portion 113 of the semiconductor body 110 in the D3 direction and on one side in the D2 direction, and extends along the D3 direction (not shown). In still other examples, the gate structure 151 may be located on opposite sides of the middle portion 113 of each in a row of semiconductor bodies 110 in the D2 direction and on opposite sides in the D3 direction, and extends along the D3 direction (not shown). According to some embodiments, from the D1 direction, a portion of the gate structure 151 that partially or completely surrounds a single semiconductor body 110 may serve as the gate of a transistor. The extension of the gate structure 151 along the D3 direction may connect the gates of each in a row of transistors to each other.

[0056] In some embodiments, multiple gate structures 151 may be arranged in the D2 direction. When the gate structure 151 is located on one side of the center 113 of the semiconductor body 110 in the D2 direction, such as... Figure 1 As shown, two adjacent gate structures 151 may be located between two (e.g., two rows) adjacent semiconductor bodies 110 in the D2 direction.

[0057] In some embodiments, the material of the gate structure 151 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. For example, the gate structure 151 may include a titanium nitride layer and a tungsten layer bonded to each other. The titanium nitride layer may be closer to the semiconductor body 110. Alternatively, the gate structure 151 may be made of a single conductive material, and this disclosure does not specifically limit this.

[0058] In some implementations, such as Figure 1 As shown, the semiconductor device 100 may further include a gate dielectric layer 152. The gate dielectric layer 152 may be located between the semiconductor body 110 and the gate structure 151. For example, the gate dielectric layer 152 may be in contact with the gate structure 151 and the semiconductor body 110. The gate dielectric layer 152 may be used for the gate and channel of an electrically isolated transistor.

[0059] In some embodiments, the material of the gate dielectric layer 152 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating material. The high dielectric constant materials may include, but are not limited to, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide, etc. For example, the material of the gate dielectric layer 152 may be silicon oxide.

[0060] According to some embodiments, the semiconductor body 110, the partial gate structure 151, and the gate dielectric layer 152 can be used to form a transistor. Multiple transistors can be arrayed in the D2 and D3 directions. Integrating the transistor's channel, source, and drain in the vertical direction (e.g., the D1 direction) helps save on the transistor's planar area overhead.

[0061] When the gate structure 151 is located on one side of the semiconductor body 110 in the D2 direction, such as Figure 1 As shown, the semiconductor device 100 may further include a first isolation structure 153 and a second isolation structure 154. The first isolation structure 153 may be located between two adjacent gate structures 151 in the D2 direction. The second isolation structure 154 may be located between two adjacent semiconductor bodies 110 in the D2 direction and extend along the D3 direction. The first isolation structure 153 and the second isolation structure 154 may be arranged alternately in the D2 direction.

[0062] In some embodiments, the materials of the first isolation structure 153 and the second isolation structure 154 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material.

[0063] In some embodiments, the second isolation structure 154 may include a conductive structure 155 and a first dielectric layer 156. The conductive structure 155 may be located between the middle 113 of two adjacent semiconductor bodies 110 in the D2 direction and extend along the D3 direction. The first dielectric layer 156 may be located between and in contact with the conductive structure 155 and the semiconductor bodies 110. During operation of the semiconductor device 100, the conductive structure 155 may act as a shield, thereby helping to reduce mutual interference between adjacent gate structures 151 in the D2 direction. For example, during operation of the semiconductor device 100, the conductive structure 155 may be configured to apply a ground voltage or a negative voltage. The first dielectric layer 156 may electrically isolate the conductive structure 155 and the semiconductor bodies 110.

[0064] In other embodiments, the conductive structure 155 may be replaced by an air gap. The air gap has a lower dielectric constant, which can reduce mutual interference by decreasing the parasitic capacitance between adjacent gate structures 151.

[0065] In some implementations, such as Figure 1As shown, the semiconductor device 100 may further include a connection structure 130. The connection structure 130 may be located on the side of the semiconductor body 110 facing away from the bit line structure 121 in the D1 direction and connected (e.g., in contact) to a first end 111 of the semiconductor body 110. For example, the connection structure 130 may be generally a columnar structure. The opposing surfaces of the connection structure 130 in the D3 direction are generally parallel, and the opposing surfaces of the connection structure 130 in the D2 direction are arranged generally parallel.

[0066] In some embodiments, the connection structure 130 includes a metal silicide portion 131 and a conductive body portion 132 in the D1 direction. The metal silicide portion 131 may contact a first end portion 111 of the semiconductor body 110. In the D2 direction, the dimension d2 of the conductive body portion 132 may be larger than the dimension d1 of the first end portion 111. Optionally, in the D3 direction, the dimension of the conductive body portion 132 may be larger than the dimension of the first end portion 111. For example, in the D2 direction, the dimension of the metal silicide portion 131 may be equal to the dimension d1 of the first end portion 111. For example, in the D3 direction, the dimension of the metal silicide portion 131 may be equal to the dimension of the first end portion 111.

[0067] According to some embodiments, the conductive body portion 132 has a larger dimension in the D2 direction, which increases the contact area with the first electrode 161 in the capacitor structure 160, thereby improving the reliability of the electrical connection. The capacitor structure 160 and its included first electrode 161 will be described in detail below.

[0068] In some embodiments, the material of the metal silicide portion 131 may include a silicide of at least one of titanium, cobalt, nickel, and platinum. The material of the conductive body portion 132 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. In one example, the conductive body portion 132 may include an adhesive layer and a metal body. The adhesive layer may surround the metal body perpendicular to the D1 direction and be located between the metal body and the metal silicide portion 131.

[0069] In some implementations, such as Figure 1 As shown, the first end 111 of each semiconductor body 110 can be connected to a connection structure 130. For example, the semiconductor body 110 and the connection structure 130 connected thereto can be centrally aligned. When multiple semiconductor bodies 110 are spaced apart in the D2 direction, multiple connection structures 130 connected to each of the multiple semiconductor bodies 110 are also spaced apart in the D2 direction. When multiple semiconductor bodies 110 are spaced apart in the D3 direction, multiple connection structures 130 connected to each of the multiple semiconductor bodies 110 are also spaced apart in the D3 direction. In other words, multiple connection structures 130 can be spaced apart in both the D2 and D3 directions.

[0070] In some implementations, such as Figure 1 As shown, the semiconductor device 100 may include an isolation body structure 141. The isolation body structure 141 may be located between and in contact with adjacent conductive body portions 132 in the D2 direction. Optionally, the isolation body structure 141 may also be located between and in contact with adjacent conductive body portions 132 in the D3 direction. For example, the surface of the isolation body structure 141 facing away from the bit line structure 121 in the D1 direction is coplanar with the surface of the conductive body portion 132 facing away from the bit line structure 121 in the D1 direction. The dimension of the isolation body structure 141 in the D1 direction is smaller than the dimension of the conductive body portion 132 in the D1 direction.

[0071] In some embodiments, the material of the insulating body structure 141 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of the insulating body structure 141 may be different from the material of the first insulating structure 153. In one example, the material of the first insulating structure 153 may be silicon oxide, and the material of the insulating body structure 141 may be silicon nitride.

[0072] In some implementations, such as Figure 1 As shown, the semiconductor device 100 may further include a capacitor structure 160. The capacitor structure 160 may be located on the side of the semiconductor body 110 opposite to the bit line structure 121 in the D1 direction. Part of the capacitor structure 160 may be used to form a capacitor, which may be connected to the connection structure 130.

[0073] In some embodiments, the capacitor structure 160 may include a first electrode 161. The first electrode 161 may extend along the D1 direction and be connected to a first end 111 of the semiconductor body 110 via a connection structure 130. The first electrode 161 may be a solid columnar structure or a barrel-shaped structure extending along the D1 direction. For example, the outer contour of the first electrode 161 may be generally cylindrical. When the first electrode 161 is a barrel-shaped structure, a support pillar 164 may be provided inside it. The material of the first electrode 161 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, doped semiconductor, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. For example, the material of the first electrode 161 may be titanium nitride. When the support pillar 164 is provided, the material of the support pillar 164 may include polycrystalline silicon (e.g., doped polycrystalline silicon). For example, the number of first electrodes 161 may be multiple. Each of the multiple first electrodes 161 may be connected to each of the multiple semiconductor bodies 110 in the D1 direction.

[0074] In some embodiments, the capacitor structure 160 may further include a capacitor dielectric layer 162. The capacitor dielectric layer 162 may at least partially surround the first electrode 161 in a direction perpendicular to D1, and may be located on the side of the first electrode 161 facing away from the semiconductor body 110 in the D1 direction. For example, the capacitor dielectric layer 162 may be a layered structure. When the semiconductor device 100 is in its current placement position, the capacitor dielectric layer 162 may cover the upper surface and a portion of the side surface of each of the plurality of first electrodes 161. The material of the capacitor dielectric layer 162 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating material. The high dielectric constant materials may include, but are not limited to, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide, etc.

[0075] In some embodiments, the capacitor structure 160 may further include a second electrode 163. The second electrode 163 may be located on the side of the capacitor dielectric layer 162 opposite to the first electrode 161. For example, the second electrode 163 may be a layered structure. The second electrode 163 may cover the surface of the capacitor dielectric layer 162 opposite to the first electrode 161. The material of the second electrode 163 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, silicon, germanium, germanium-silicon, or any other suitable conductive material.

[0076] In some embodiments, the capacitor structure 160 may further include a filler layer 165. The filler layer 165 may be located on the side of the second electrode 163 opposite to the capacitor dielectric layer 162. When the semiconductor device 100 is in its current placement position, the filler layer 165 may have a flat upper surface perpendicular to the D1 direction.

[0077] In some embodiments, the capacitor structure 160 may further include insulating layers 166-1, 166-2, and 166-3. Insulating layers 166-1, 166-2, and 166-3 may be spaced apart in the D1 direction. Each of insulating layers 166-1, 166-2, and 166-3 may extend along the D2 and D3 directions and may be arranged substantially parallel to each other. Insulating layers 166-3 and 166-2 may respectively surround a portion of the end and middle of the first electrode 161 away from the semiconductor body 110, and insulating layer 166-1 may surround the end of the first electrode 161 near the semiconductor body 110. In other words, the first electrode 161 may penetrate through insulating layers 166-1, 166-2, and 166-3. The capacitor dielectric layer 162, the second electrode 163, and the filling layer 165 may pass through insulating layers 166-2 and 166-3 along the D1 direction.

[0078] In some embodiments, the materials of insulating layers 166-1, 166-2, and 166-3 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, insulating layers 166-1, 166-2, and 166-3 may all be made of silicon nitride.

[0079] It should be noted that this disclosure does not impose a specific limitation on the number of insulating layers. As an example, at least one of insulating layers 166-1, 166-2, and 166-3 may be omitted. As another example, a greater number (e.g., more than 3) of insulating layers (not shown) may be provided. These insulating layers can serve a supporting function during the fabrication of the capacitor structure 160.

[0080] According to some embodiments, in capacitor structure 160, a first electrode 161, a capacitor dielectric layer 162, and a second electrode 163 can be used to form a capacitor. Since the outer contour of the first electrode 161 is a columnar structure extending along the D1 direction, this capacitor can be called a columnar capacitor. The first electrode 161 of each of the plurality of capacitors can be connected to a corresponding connection structure 130. The second electrode 163 of each of the plurality of capacitors can be connected to each other.

[0081] It should be noted that the shapes of the first electrode 161, the capacitor dielectric layer 162, and the second electrode 163 in the capacitor structure 160 described above are merely examples. In other embodiments, the capacitor may also be implemented as a stacked capacitor, a cup-shaped capacitor, a barrel-shaped capacitor, etc. The shapes of the first electrode, the capacitor dielectric layer, and the second electrode differ in different types of capacitors. The first electrode of different types of capacitors can be connected to the semiconductor body 110 via the connection structure 130.

[0082] According to some embodiments, the connection structure 130 can serve to connect a capacitor and a transistor. Specifically, the first electrode 161 of the capacitor can be connected to, for example, the source of the transistor via the connection structure 130. The capacitor and the transistor can constitute a memory cell, such as a DRAM memory cell. The capacitor can be used to implement data storage, and the transistor can act as a switch to access the data in the capacitor.

[0083] In some embodiments, the semiconductor device 100 may further include peripheral circuitry (not shown). The peripheral circuitry may be located on the side of the capacitor structure 160 facing away from the semiconductor body 110 in the D1 direction, or on the side of the bit line structure 121 facing away from the semiconductor body 110 in the D1 direction. In this way, the transistors, capacitors, and peripheral circuitry can be stacked in the D1 direction, thereby helping to save planar area and improve integration density.

[0084] In some implementations, the peripheral circuitry may include any suitable digital, analog, and / or mixed-signal peripheral circuitry for controlling the operation of the memory cell array. For example, this peripheral circuitry may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0085] Figure 2 A cross-sectional schematic diagram of a semiconductor device according to another embodiment of this disclosure is shown. For the purpose of brevity, the same content as in the previous embodiment will not be repeated in this embodiment and the following embodiments.

[0086] In some implementations, such as Figure 2 As shown, in the semiconductor device 200, the connection structure 230 may include a metal silicide portion 231 and a conductive body portion 232 in the D1 direction. The metal silicide portion 231 may contact the first end portion 211 of the semiconductor body 210.

[0087] In some embodiments, in the D2 direction, the dimension d1 of the connecting structure 230 may be equal to the dimension d1 of the first end portion 211. For example, the conductive body portion 232 and the metal silicide portion 231 have equal dimensions in the D2 direction. Optionally, in the D3 direction, the dimension of the connecting structure 230 is equal to the dimension of the first end portion 211. For example, the conductive body portion 232 and the metal silicide portion 231 have equal dimensions in the D3 direction.

[0088] In some implementations, such as Figure 2 As shown, the semiconductor device 200 may include an isolation body structure 241 and an isolation pad layer 242. The isolation body structure 241 may be located between adjacent connection structures 230 in the D2 direction. At least a portion of the isolation pad layer 242 may be located on opposite sides of the isolation body structure 241 in the D2 direction and contact the adjacent connection structures 230 in the D2 direction. For example, the isolation pad layer 242 may also contact the isolation body structure 241. Optionally, the isolation body structure 241 may be located between adjacent connection structures 230 in the D3 direction. At least a portion of the isolation pad layer 242 may be located on opposite sides of the isolation body structure 241 in the D3 direction and contact the adjacent connection structures 230 in the D3 direction.

[0089] In some embodiments, the surface of the isolation body structure 241 facing away from the bit line structure 221 in the D1 direction, the surface of the isolation liner layer 242 facing away from the bit line structure 221 in the D1 direction, and the surface of the conductive body portion 232 facing away from the bit line structure 221 in the D1 direction are coplanar. The dimension of the isolation body structure 241 in the D1 direction is smaller than the dimension of the conductive body portion 232 in the D1 direction. For example, the isolation liner layer 242 may extend to the surface of the isolation body structure 241 facing the bit line structure 221 in the D1 direction.

[0090] In some embodiments, the materials of the insulating body structure 241 and the insulating pad layer 242 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. The material of the insulating body structure 241 is different from the material of the insulating pad layer 242. For example, the material of the insulating body structure 241 is silicon nitride, and the material of the insulating pad layer 242 is silicon oxide. When the material of the insulating pad layer 242 is the same as the material of the first insulating structure 253, there is no obvious interface between the portion of the insulating pad layer 242 extending to the surface of the insulating body structure 241 facing the bit line structure 221 in the D1 direction and the first insulating structure 253.

[0091] According to some embodiments, an isolation liner layer and an isolation body structure are formed before etching the initial semiconductor body. To reduce the influence of interface states on the etching rate of the portion of the initial semiconductor body to be etched, in an exemplary embodiment where an alkaline etching solution (e.g., ammonia) is used to etch the initial semiconductor body to obtain the semiconductor body, the isolation liner layer is simultaneously removed during the etching process. As a result, the removal of the portion of the isolation liner layer located on the surface of the first isolation structure may cause the isolation body structure to peel off from the first isolation structure, thereby affecting the isolation effect and product yield.

[0092] According to some embodiments of this disclosure, the isolation liner layer 242 and the isolation body structure 241 are formed before the amorphous portion is etched. During the etching of the amorphous portion, the etching material (e.g., chlorine gas) does not simultaneously remove the isolation liner layer 242, which reduces the risk of the isolation body structure 241 peeling off from the first isolation structure 253, thereby ensuring the isolation effect and product yield.

[0093] This disclosure also provides a method for fabricating a semiconductor device in some embodiments. Figure 3 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure. Figure 3 As shown, the semiconductor device fabrication method 300 (hereinafter referred to as fabrication method 300) may include the following steps.

[0094] S310, forming an initial semiconductor body extending along a first direction, wherein the material of the initial semiconductor body includes a single crystal material.

[0095] S320 transforms the first portion of the initial semiconductor body in the first direction into an amorphous portion.

[0096] S330, etching the amorphous portion to obtain the semiconductor body.

[0097] The preparation method 300 will be described below with reference to the accompanying drawings and various embodiments.

[0098] Figures 4A to 4J A cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this disclosure during its fabrication process is shown. Specifically, Figure 4A The intermediate structure after the initial semiconductor body is formed is shown. Figure 4B The intermediate structure after the formation of the exposed second extension trench is shown. Figure 4C The intermediate structure after the formation of the first and second insulating material layers is shown. Figure 4D The intermediate structure is shown after the formation of the insulating liner layer and the insulating main structure. Figure 4E The intermediate structure after the transformation of the amorphous portion is shown. Figure 4F The intermediate structure after removing the amorphous portion is shown. Figure 4G The intermediate structure is shown after part of the isolation liner layer has been removed. Figure 4H The intermediate structure after the connection structure is formed is shown. Figure 4I The intermediate structure after the capacitor structure is formed is shown. Figure 4J The semiconductor device after the bit line structure is formed is shown.

[0099] Preparation method 300 begins with step S310. For example... Figure 4A As shown, an initial semiconductor body 410' extending along the D1 direction can be formed. In some embodiments, the initial semiconductor body 410' can be obtained by etching the semiconductor layer 471. The unetched semiconductor layer 471 can extend along the D2 and D3 directions.

[0100] To obtain the initial semiconductor body 410', firstly, a plurality of first extension trenches extending along the D2 direction are etched on the first side of the semiconductor layer 471 in the D1 direction, resulting in semiconductor walls 472 extending along the D2 direction. These first extension trenches can be arranged in the D3 direction, and the semiconductor walls 472 can also be arranged in the D3 direction. For example, the depth of the first extension trenches can be less than the dimension of the semiconductor layer 471 in the D1 direction. Subsequently, an insulating material can be filled into the first extension trenches using a thin film deposition process. For example, the insulating material can be silicon oxide. Next, the semiconductor walls 472 and the insulating material can be etched again on the first side of the semiconductor layer 471 to obtain second extension trenches 473 and third extension trenches 474 extending along the D3 direction, simultaneously obtaining a plurality of initial semiconductor bodies 410' arranged in an array in the D2 and D3 directions. The second extension trenches 473 and third extension trenches 474 are arranged alternately in the D2 direction. For example, the depths of the second extending trench 473 and the third extending trench 474 may be the same and may be smaller than the dimension of the semiconductor wall 472 in the D1 direction. Thus, portions of the plurality of initial semiconductor bodies 410' arranged in the D2 direction near the semiconductor layer 471 can be connected to each other via the unetched semiconductor wall 472. For example, the trench widths of the second extending trench 473 and the third extending trench 474 may be different. As an example, the trench width of the second extending trench 473 may be greater than the trench width of the third extending trench 474.

[0101] In some embodiments, the semiconductor layer 471 may be made of a single-crystal material. The material of the semiconductor layer 471 may include silicon, germanium, germanium-silicon, silicon carbide, gallium nitride, or any other suitable single-crystal semiconductor material. Since the initial semiconductor body 410' is obtained by etching the semiconductor layer 471, the material of the initial semiconductor body 410' is the same as the material of the semiconductor layer 471. In one example, the material of the initial semiconductor body 410' may be single-crystal silicon.

[0102] In some embodiments, the fabrication method 300 may further include forming a gate structure 451 and a gate dielectric layer 452 (see reference). Figure 4J The steps of this process are as follows. Taking the formation of gate structure 451 on one side of semiconductor body 410 in the D2 direction as an example, some sub-steps in this process can be performed first. For example, an initial gate dielectric layer 452' and an initial gate layer 451' can be sequentially formed on the bottom inner wall of the second extended trench 473. Other sub-steps in this process will be performed later.

[0103] In some embodiments, the fabrication method 300 may further include forming a first isolation structure 453 inside the initial gate layer 451'. Thus, the first isolation structure 453 may extend along the D3 direction. For example, the first isolation structure 453 may fill the top space of the second extended trench 473.

[0104] In some embodiments, the fabrication method 300 may further include forming a second isolation structure 454 comprising a conductive structure 455 and a first dielectric layer 456 (see reference). Figure 4J The steps are as follows. Figure 4A As shown, some sub-steps in this step can be performed first. First, an initial first dielectric layer 456' can be formed on the bottom inner wall of the third extending trench 474. Subsequently, an initial conductive structure 455' can be formed inside the initial first dielectric layer 456'. Other sub-steps in this step will be performed subsequently.

[0105] In some embodiments, the fabrication method 300 may further include forming a third isolation structure 457 in the top space of the third extended trench 474. For example, the material of the third isolation structure 457 is the same as that of the first isolation structure 453, for example, both are made of silicon oxide.

[0106] In some embodiments, the preparation method 300 may further include forming an isolation body structure 441 and an isolation liner layer 442 (see reference). Figure 4D The steps are as follows. In some implementations, such as... Figure 4A and Figure 4B As shown, a portion of the first isolation structure 453 and a portion of the third isolation structure 457 can be removed by an etching process (e.g., wet etching), thereby exposing a portion of the second extension trench 473 and a portion of the third extension trench 474 again. The top surfaces of the first isolation structure 453 and the third isolation structure 457 after removal are substantially coplanar. Optionally, during the removal of a portion of the first isolation structure 453 and a portion of the third isolation structure 457, a portion of the insulating material between adjacent initial semiconductor bodies 410' in the D3 direction can also be removed. For example, the top surfaces of the removed insulating material, the first isolation structure 453, and the third isolation structure 457 are substantially coplanar. After the above process, the initial semiconductor body 410' can protrude from the coplanar surfaces of the first isolation structure 453 and the third isolation structure 457, and this protruding portion serves as at least a portion of the first portion 414 of the initial semiconductor body 410'.

[0107] It should be noted that the dimension of the first portion 414 defined in the D1 direction may depend on the process parameters (e.g., ion implantation depth) of the subsequent conversion (e.g., ion implantation) process, and this disclosure does not impose any specific limitations on it.

[0108] Furthermore, such as Figure 4B and Figure 4CAs shown, a first insulating material layer 475 can be formed on the inner walls of the second extension trench 473 and the third extension trench 474 using a thin film deposition process. Thus, the first insulating material layer 475 covers the opposing surfaces of the first portion 414 in the D2 direction. Optionally, if a portion of the insulating material is also removed, the first insulating material layer 475 may also cover the opposing surfaces of the first portion 414 in the D3 direction. Furthermore, the first insulating material layer 475 may also cover the top surface of the first portion 414.

[0109] Furthermore, such as Figure 4C As shown, a second insulating material layer 476 can be formed inside the first insulating material layer 475 by a thin film deposition process. For example, the second insulating material 476 can extend to the top of the first portion 414.

[0110] Furthermore, such as Figure 4C and Figure 4D As shown, the portions of the first insulating material layer 475 and the second insulating material 476 located at the top of the first portion 414 can be removed by a planarization process to obtain an insulating pad layer 442 and an insulating body structure 441. Thus, the insulating pad layer 442 and the insulating body structure 441 can be formed between adjacent first portions 414 in the D2 direction. The insulating pad layer 442 can be located on opposite sides of the insulating body structure 441 in the D2 direction and on one side in the D1 direction. For example, in the D2 direction, the insulating pad layer 442 is in contact with the first portion 414 and the insulating body structure 441. In the D1 direction, the insulating pad layer 442 is in contact with the first insulating structure 453 (or the third insulating structure 457).

[0111] In some embodiments, since the isolation liner layer 442 and the isolation body structure 441 are obtained by etching the first insulating material layer 475 and the second insulating material 476, respectively, the material of the isolation liner layer 442 is the same as the material of the first insulating material layer 475, and the material of the isolation body structure 441 is the same as the material of the second insulating layer 476. For example, the materials of the isolation liner layer 442 and the isolation body structure 441 are different. As an example, the material of the isolation liner layer 442 includes silicon oxide, and the material of the isolation body structure 441 includes silicon nitride.

[0112] Preparation method 300 proceeds to step S620. In some embodiments, such as Figure 4D and Figure 4EAs shown, after forming the isolation liner layer 442 and the isolation host structure 441, a dopant element can be incorporated into the first portion 414 via an ion implantation process to transform the first portion 414, which is composed of single-crystal material, into an amorphous portion 415. The dopant element bombards the first portion 414 in ionic form, causing the atoms of the first portion 414, which is composed of single-crystal material, to change from a regular arrangement to a disordered arrangement, thereby obtaining the amorphous portion 415. For example, the implantation depth of the dopant element, i.e., the size of the first portion 414 in the D1 direction, can be controlled by the parameters of the ion implantation process (e.g., energy and / or concentration).

[0113] In some embodiments, the doping element may include at least one of rare gas elements, Group III elements, Group IV elements, Group V elements, and fluorine. For example, the doping element may include at least one of argon, xenon, boron, indium, germanium, carbon, nitrogen, phosphorus, arsenic, and fluorine.

[0114] Preparation method 300 proceeds to step S630. In some embodiments, such as Figure 4E and Figure 4F As shown, the amorphous portion 415 can be removed by etching, leaving the initial semiconductor body 410' as the semiconductor body 410. During etching, the initial semiconductor body 410' remains a single-crystal portion except for the amorphous portion 415. During etching, the single-crystal portion has fewer lattice defects and limited surface reactive sites, resulting in a slower etching rate. The polycrystalline portion 415 has disordered atomic arrangement and numerous defects and dangling bonds on its surface, providing abundant reactive sites and a faster etching rate. Even when the amorphous portion 415 has interface state issues, the influence of interface states on the etching rate is less than the influence of the amorphous material itself on the etching rate during etching. Therefore, the amorphous portion 415 can be etched at a faster rate, which helps improve the process controllability of removing the first portion 414 and results in better surface uniformity of each semiconductor body 410.

[0115] It should be pointed out that, in cases such as Figure 4F As shown, after removing the amorphous portion 415, there are still some doped elements remaining at the first end 411 of the semiconductor body 410.

[0116] In some implementations, such as Figure 4E and Figure 4F As shown, when the amorphous portion 415 is amorphous silicon and the other portions of the initial semiconductor body 410' are monocrystalline silicon, chlorine gas can be used to etch the amorphous portion 415. For example, under high temperature conditions, silicon reacts with chlorine gas to generate silicon tetrachloride. For example, during the etching process, the etching rate of chlorine gas on the amorphous portion 415 can be 5 to 8 times that on the monocrystalline portion.

[0117] In some implementations, such as Figure 4F and Figure 4G As shown, the fabrication method 300 further includes a step of removing a portion of the isolation pad layer 442. Exemplarily, portions of the isolation pad layer 442 located on opposite sides of the isolation body structure 441 in the D2 direction can be removed by an etching process (e.g., dry etching). Thus, the dimension d2 of the top of the connection hole 477 defined by the isolation pad layer 442 and the isolation body structure 441 in the D2 direction can be greater than the dimension d1 of the bottom of the connection hole 477 defined by the first isolation structure 453 and the third isolation structure 457 in the D2 direction. Optionally, the isolation pad layer 442 and the isolation body structure 441 are also formed on an initial semiconductor body 410' adjacent in the D3 direction (see reference). Figure 4D In the case of the above removal process, the isolation liner 442 located on the opposite sides of the isolation main structure 441 in the D3 direction can also be removed. In this way, the top dimension of the connection hole 477 defined by the isolation liner 442 and the isolation main structure 441 in the D3 direction can be greater than the bottom dimension of the connection hole 477 defined by the first isolation structure 453, the third isolation structure 457 and the insulating material in the D3 direction.

[0118] In some exemplary embodiments, reference is made to Figure 4D After forming the isolation liner layer 442 and the isolation body structure 441, in order to reduce the influence of the interface states of the portion of the initial semiconductor body to be etched on the etching rate, an alkaline etching solution (e.g., ammonia) can be used to etch the initial semiconductor body to obtain the semiconductor body. However, during the etching process, the isolation liner layer is removed simultaneously. As a result, the removal of the portion of the isolation liner layer located on the surface of the first isolation structure may cause the isolation body structure to peel off from the first isolation structure, thereby affecting the isolation effect and product yield.

[0119] According to some embodiments of this disclosure, during the etching of the amorphous portion 415, the etching material (e.g., chlorine) does not simultaneously remove the isolation liner layer 442, which reduces the risk of delamination between the isolation body structure 441 and the first isolation structure 453, thereby ensuring the isolation effect and product yield. After removing the amorphous portion 415, removing the portions of the isolation liner layer 442 located on opposite sides of the isolation body structure 441 in the D2 direction (or D3 direction) using a dry etching process helps to increase the size of the top of the connection hole 477.

[0120] In some implementations, such as Figure 4G and Figure 4HAs shown, the fabrication method 300 may further include the step of forming a connection structure 430. Exemplarily, firstly, a metal layer may be formed on the surface of the first end 411 exposed at the bottom of the connection hole 477; subsequently, for example, the metal layer may react with the first end 411 under high temperature conditions to form a metal silicide portion 431; next, a conductive body portion 432 may be formed on the top of the connection hole 477 by a thin film deposition process. The metal silicide portion 431 and the conductive body portion 432 may constitute the connection structure 430. After the above process, the connection structure 430 may be formed on one side of the semiconductor body 410 in the D1 direction. In the D2 direction, the connection structure 430 may be located between adjacent isolation body structures 441. For example, the connection structure 430 is in contact with the isolation body structure 441.

[0121] It should be noted that the step of forming the metal silicide portion 431 can be omitted during the formation of the connection structure 430. In other words, the connection structure (not shown) can be formed by directly filling the connection hole 477 with one or more conductive materials.

[0122] In some implementations, such as Figure 4I As shown, the preparation method 300 may further include the step of forming a capacitor structure 460.

[0123] For example, firstly, an insulating layer 466-1, a sacrificial layer (not shown), an insulating layer 466-2, a sacrificial layer (not shown), and an insulating layer 466-3 may be sequentially formed on the side of the plurality of connection structures 430 facing away from the semiconductor body 410 in the D1 direction. Each of these layers may extend along both the D2 and D3 directions. Subsequently, a first electrode 461 may be formed, sequentially penetrating the insulating layer 466-3, the sacrificial layer, the insulating layer 466-2, the sacrificial layer, and the insulating layer 466-1 along the D1 direction to the connection structure 430. Optionally, the first electrode 461 may be generally barrel-shaped. A support pillar 464 may be formed inside the first electrode 461. Next, the sacrificial layer between the two insulating layers 466-1 and 466-2, and between the insulating layers 466-2 and 466-3, may be removed. The insulating layers 466-1 to 466-3 may provide support after the sacrificial layer is removed. Further, a capacitor dielectric layer 462 may be formed, for example, on the side surface of the first electrode 461, the surfaces of the insulating layers 466-1 to 466-3, and the upper end surface of the support pillar 464. Then, a second electrode 463 may be formed on the side of the capacitor dielectric layer 462 opposite to the first electrode 461 (e.g., the surface). Optionally, a filler layer 465 may also be formed on the side of the second electrode 463 opposite to the capacitor dielectric layer 462 (e.g., the surface). The filler layer 465 may be used to provide a flat surface perpendicular to the D1 direction.

[0124] According to some embodiments, in the capacitor structure 460, the first electrode 461, the capacitor dielectric layer 462, and the second electrode 463 can be used to form a capacitor. Since the outer contour of the first electrode 461 is a columnar structure extending along the D1 direction, this capacitor can be called a columnar capacitor.

[0125] It should be noted that the above description uses a cylindrical capacitor as an example to illustrate its formation process. In other embodiments, the capacitor can also be implemented as a stacked capacitor, a cup-shaped capacitor, a barrel-shaped capacitor, etc. These types of capacitors can be formed by any process method known in the art.

[0126] In some implementations, such as Figure 4I and Figure 4J As shown, the fabrication method 300 is performed up to several further sub-steps to form the gate structure 451 and the gate dielectric layer 452. Exemplarily, firstly, the semiconductor layer 471 can be removed from the side of the semiconductor body 410 away from the capacitor structure 460 in the D1 direction, for example, by a planarization process. Subsequently, a portion of the initial gate layer 451' located at the bottom of the second extended trench 473 can be removed, such that the initial gate layer 451' is broken into two gate structures 451 in the D2 direction. The portion of the initial gate dielectric layer 452' located between the semiconductor body 410 and the gate structure 451 can be the gate dielectric layer 452.

[0127] In some implementations, such as Figure 4I and Figure 4J As shown, the fabrication method 300 performs further sub-steps to form the conductive structure 455. Exemplarily, after removing the semiconductor layer 471, a portion of the initial conductive structure 455' located at the bottom of the third extended trench 474 may be removed to obtain the conductive structure 455. The portion of the initial first dielectric layer 456' located between the semiconductor body 410 and the conductive structure 455 may be the first dielectric layer 456. The first dielectric layer 456 and the conductive structure 455 may constitute a second isolation structure 454.

[0128] In some implementations, such as Figure 4I and Figure 4J As shown, the fabrication method 300 may further include the step of forming a bit line structure 421. Exemplarily, after removing the semiconductor layer 471, the ends of the capacitor structures 460 of a plurality of semiconductor bodies 410 arranged in the D2 direction may be connected to each other (i.e., semiconductor walls 472). In this case, the bit line structure 421 extending along the D2 direction can be formed by consuming the interconnected portions through a metal silicide process.

[0129] Figures 5A to 5DA cross-sectional schematic diagram of a semiconductor device according to another embodiment of this disclosure during its fabrication process is shown. For the purpose of brevity, the same content as in the previous embodiment will not be repeated here. For example, Figures 5A to 5D Available Figure 4E Based on the preparation method 300, some steps were performed to obtain the product.

[0130] In some implementations, such as Figure 5A and Figure 5B As shown, after forming the semiconductor body 510, the isolation pad layer 542, and the isolation body structure 541, the fabrication method 300 may further include the step of forming a connection structure 530. Exemplarily, firstly, a metal layer is formed on the surface of the first end 511 of the semiconductor body 510 exposed at the bottom of the connection hole 577; subsequently, a metal silicide portion 531 is formed by reacting the metal layer with the first end 511 under high temperature conditions, for example; next, a conductive body portion 532 is formed on the top of the connection hole 577 by a thin film deposition process. The metal silicide portion 531 and the conductive body portion 532 can constitute the connection structure 530. After the above process, the connection structure 530 can be formed on one side of the semiconductor body 510 in the D1 direction. In the D2 direction, the connection structure 530 can be located between adjacent isolation body structures 541. For example, the connection structure 530 is in contact with the isolation pad layer 542.

[0131] According to some embodiments, compared to etching the initial semiconductor substrate with an alkaline etching solution (e.g., ammonia) to obtain the semiconductor substrate, the amorphous portion 415 (see reference) is etched. Figure 4E During the etching process, the etching material (e.g., chlorine gas) does not simultaneously remove the isolation liner layer 542, reducing the risk of separation between the isolation host structure 541 and the first isolation structure 553, thereby ensuring isolation effect and product yield. During the removal of the amorphous portion 415 (see reference...) Figure 4E After that, without additionally removing the portion of the isolation liner 542 located on opposite sides of the isolation main structure 541 in the D2 direction, it helps to simplify the process and save manufacturing costs.

[0132] It should be noted that the step of forming the metal silicide portion 531 can be omitted during the formation of the connection structure 530. In other words, the connection structure (not shown) can be formed by directly filling the connection hole 577 with one or more conductive materials.

[0133] In some implementations, such as Figure 5B and Figure 5CAs shown, the fabrication method 300 may further include the step of forming a capacitor structure 560. Since the fabrication process of a capacitor structure comprising a columnar capacitor has been illustrated in the previous embodiment, it will not be repeated here. In other embodiments, the capacitor may also be implemented as a stacked capacitor, a cup-shaped capacitor, a barrel-shaped capacitor, etc. These types of capacitor structures can be formed by any process method known in the art.

[0134] In some implementations, such as Figure 5C and Figure 5D As shown, the fabrication method 300 is performed to some further sub-steps to form the gate structure 551 and the gate dielectric layer 552.

[0135] For example, firstly, the semiconductor layer 571 can be removed from the side of the semiconductor body 510 away from the capacitor structure 560 in the D1 direction, for example, by a planarization process. Subsequently, a portion of the initial gate layer 551' located at the bottom of the second extended trench 573 can be removed, such that the initial gate layer 551' is broken into two gate structures 551 in the D2 direction. The portion of the initial gate dielectric layer 552' located between the semiconductor body 510 and the gate structure 551 can be the gate dielectric layer 552.

[0136] In some implementations, such as Figure 5C and Figure 5D As shown, the fabrication method 300 performs further sub-steps to form the conductive structure 555. Exemplarily, after removing the semiconductor layer 571, a portion of the initial conductive structure 555' located at the bottom of the third extended trench 574 may be removed to obtain the conductive structure 555. The portion of the initial first dielectric layer 556' located between the semiconductor body 510 and the conductive structure 555 may be the first dielectric layer 556. The first dielectric layer 556 and the conductive structure 555 may constitute a second isolation structure 554.

[0137] In some implementations, such as Figure 5C and Figure 5D As shown, the fabrication method 300 may further include the step of forming a bit line structure 521. Exemplarily, after removing the semiconductor layer 571, the ends of the capacitor structures 560 of a plurality of semiconductor bodies 510 arranged in the D2 direction may be connected to each other (i.e., semiconductor walls 572). In this case, the bit line structure 521 extending along the D2 direction can be formed by consuming the interconnected portions through a metal silicide process.

[0138] This disclosure also provides a memory system. Figure 6 This is a schematic block diagram of a system with a memory system provided in an embodiment of this disclosure. Figure 7A and Figure 7B This is a schematic block diagram of a memory system provided in an embodiment of this disclosure.

[0139] like Figure 6 As shown, system 10 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 11 located therein). Figure 6 As shown, system 10 may include a host 14 and a memory system 11, the memory system 11 having one or more memories 12 and a controller 13. The host 14 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 14 may be configured to send or receive data to and from the memory 12.

[0140] Memory 12 may include, for example, the semiconductor devices described in any embodiment of this disclosure. According to some embodiments, controller 13 is coupled to memory 12 and host 14 and is configured to control memory 12. Controller 13 can manage data stored in memory 12 and communicate with host 14. In some embodiments, controller 13 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 13 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc. Controller 13 may be configured to control operations of memory 12, such as read, erase, and program operations. Controller 13 may also be configured to manage various functions related to data stored in or to be stored in memory 12, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 13 is further configured to process error correction codes (ECCs) related to data read from or written to memory 12. Controller 13 may also perform any other appropriate functions, such as formatting memory 12. Controller 13 may communicate with external devices (e.g., host 14) according to specific communication protocols. For example, controller 13 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0141] The controller 13 and one or more memories 12 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 11 can be implemented and packaged into different types of end electronic products. Figure 7AIn one example shown, controller 13 and a single memory 12 may be integrated into memory card 15. Memory card 15 may include PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 15 may further include a connector for connecting memory card 15 to a host computer (e.g., Figure 6 The host 14) is coupled to the memory card connector 16. In such a way... Figure 7B In another example shown, controller 13 and multiple storage units 12 may be integrated into SSD 17. SSD 17 may further include components for connecting SSD 17 to a host (e.g., Figure 6 The host 14) is coupled to the SSD connector 18. In some embodiments, the storage capacity and / or operating speed of the SSD 17 is higher than that of the memory card 15.

[0142] The above description is merely an illustration of the embodiments of this disclosure and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A semiconductor device, comprising: The semiconductor body extends along a first direction; Bit line structure, located on one side of the semiconductor body in the first direction and extending along the second direction, wherein the first direction intersects the second direction; The semiconductor body includes a first end facing away from the bit line structure in the first direction, and the first end has a doping element, which includes at least one of rare gas elements, group III elements, group IV elements, group V elements, and fluorine.

2. The semiconductor device according to claim 1, wherein, The doping element includes at least one of argon, xenon, boron, indium, germanium, carbon, nitrogen, phosphorus, arsenic, and fluorine.

3. The semiconductor device according to claim 2, wherein, In the first direction, the doping concentration of the portion of the first end facing away from the bit line structure is greater than the doping concentration of the portion of the first end facing the bit line structure.

4. The semiconductor device according to claim 1, wherein the material of the semiconductor body comprises monocrystalline silicon.

5. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: A connection structure is located on the side of the semiconductor body opposite to the bit line structure in the first direction and is connected to the semiconductor body.

6. The semiconductor device according to claim 5, wherein, In the second direction, the dimensions of the connecting structure are equal to the dimensions of the first end.

7. The semiconductor device according to claim 6, wherein, The plurality of said semiconductor bodies and the connection structures connected thereto are arranged at intervals in the second direction, wherein the semiconductor device further includes: An isolation main structure is located between adjacent connecting structures in the second direction; and An isolation liner layer is located at least partially on opposite sides of the isolation body structure in the second direction and is in contact with the connecting structure; The main isolation structure is made of a different material than the isolation liner layer.

8. The semiconductor device according to claim 7, wherein, The material of the main insulating structure includes silicon nitride, and the material of the insulating liner layer includes silicon oxide.

9. The semiconductor device according to claim 5, wherein, The connection structure includes a metal silicide portion and a conductive body portion in the first direction, wherein the metal silicide portion is in contact with the semiconductor body; In the second direction, the size of the conductive main body is larger than the size of the first end portion.

10. The semiconductor device according to claim 9, wherein, The plurality of said semiconductor bodies and the connection structures connected thereto are arranged at intervals in the second direction, wherein the semiconductor device further includes: An isolation main structure is located between adjacent conductive main portions in the second direction and is in contact with the conductive main portions.

11. The semiconductor device according to any one of claims 1 to 10, wherein, The semiconductor device further includes: A gate structure is located on at least one side of the semiconductor body in a direction intersecting the first direction and extends along a third direction; and A gate dielectric layer is located between the gate structure and the semiconductor body; The first direction, the second direction, and the third direction intersect each other.

12. The semiconductor device according to claim 5, wherein, The semiconductor device further includes: A capacitor structure is located on the side of the semiconductor body that is away from the bit line structure in the first direction; Some of the capacitor structures are used to form a capacitor, and the capacitor is connected to the connection structure.

13. A memory system, comprising: The memory includes the semiconductor device as described in any one of claims 1 to 12; as well as A controller, coupled to the memory, is used to control the memory to store data.

14. A method for fabricating a semiconductor device, comprising: An initial semiconductor body is formed extending along a first direction, wherein the material of the initial semiconductor body includes a single crystal material; Transforming the first portion of the initial semiconductor body in the first direction into an amorphous portion; and The amorphous portion is etched to obtain the semiconductor body.

15. The preparation method according to claim 14, wherein, Transforming the first portion of the initial semiconductor body in the first direction into an amorphous portion includes: The first portion is converted into the amorphous portion by incorporating doping elements into it through an ion implantation process.

16. The preparation method according to claim 15, wherein, The doping element includes at least one of the following: rare gas elements, group III elements, group IV elements, group V elements, and fluorine.

17. The preparation method according to claim 16, wherein, The doping element includes at least one of argon, xenon, boron, indium, germanium, carbon, nitrogen, phosphorus, arsenic, and fluorine.

18. The preparation method according to claim 14, wherein, The material of the initial semiconductor body includes monocrystalline silicon, wherein etching the amorphous portion includes: The amorphous portion is etched using chlorine gas, wherein the material of the amorphous portion includes amorphous silicon.

19. The preparation method according to any one of claims 14 to 18, wherein, The plurality of said initial semiconductor bodies are arranged at intervals in a second direction, the first direction intersecting the second direction, wherein the fabrication method further includes: An isolation liner layer and an isolation body structure are formed between the first portions of the adjacent initial semiconductor bodies in the second direction, wherein the isolation liner layer is located on opposite sides of the isolation body structure in the second direction and on one side in the first direction; After the isolation liner layer and the isolation main structure are formed, the first part is transformed and the amorphous part is etched.

20. The preparation method according to claim 19, wherein, The material of the isolation liner includes silicon oxide, and the material of the isolation body structure includes silicon nitride.

21. The preparation method according to claim 19, wherein, The preparation method further includes: A connection structure is formed on one side of the semiconductor body in the first direction, wherein the connection structure is located between adjacent isolation body structures in the second direction.

22. The preparation method according to claim 21, wherein, Before forming a connection structure on one side of the semiconductor body in the first direction, the fabrication method further includes: Remove the portions of the isolation liner layer located on opposite sides of the isolation main structure in the second direction.

23. The preparation method according to claim 14, wherein, The preparation method further includes: A gate structure is formed on at least one side of the semiconductor body in a direction intersecting the first direction, wherein the gate structure extends along a third direction, and the first direction, the second direction, and the third direction intersect each other; and A gate dielectric layer is formed between the gate structure and the semiconductor body.

24. The preparation method according to claim 14, wherein, The preparation method further includes: A bit line structure is formed on one side of the semiconductor body in the first direction, the bit line structure extending along a second direction, the first direction intersecting the second direction; and A capacitor structure is formed on the side of the semiconductor body opposite to the bit line structure in the first direction, wherein a portion of the capacitor structure is used to form a capacitor, and the capacitor is connected to the semiconductor body.

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