Semiconductor device and method of manufacturing the same, memory system

Abstract

The present disclosure provides a semiconductor device and a manufacturing method, a memory system. The semiconductor device includes a semiconductor body, a capacitor structure, and a connection structure. The semiconductor body extends along a first direction, and the capacitor structure is located at one side of the semiconductor body in the first direction. The connection structure extends along the first direction and connects the semiconductor body and the capacitor structure. The connection structure includes a first semiconductor portion and a second semiconductor portion which contact each other in the first direction, wherein a part of the first semiconductor portion is located between the second semiconductor portion and the semiconductor body in the first direction, and another part of the first semiconductor portion is located at least at one side of the semiconductor body in a second direction and contacts the semiconductor body, the first direction intersecting the second direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor design and fabrication, and more specifically, to semiconductor devices, methods for fabricating semiconductor devices, and memory systems. Background Technology

[0002] Memory is one of the most important semiconductor devices in electronic systems. Taking Dynamic Random Access Memory (DRAM) as an example, a semiconductor device can include memory cells composed of capacitors and transistors, where multiple memory cells can be arranged in a two-dimensional array.

[0003] With the rapid development of semiconductor technology, the shrinking size of semiconductor devices and the increase in integration, optimizing the electrical performance of semiconductor devices and improving their yield has become one of the important research directions in the industry. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor device, a semiconductor device, and a memory system that can at least partially solve the problems described above or other problems in the art.

[0005] This disclosure provides a semiconductor device comprising: a semiconductor body extending along a first direction; a capacitor structure located on one side of the semiconductor body in the first direction; and a connection structure extending along the first direction and connecting the semiconductor body and the capacitor structure, wherein the connection structure includes a first semiconductor portion and a second semiconductor portion that are in contact with each other in the first direction; and a portion of the first semiconductor portion is located between the second semiconductor portion and the semiconductor body in the first direction, and another portion of the first semiconductor portion is located at least on one side of the semiconductor body in the second direction and in contact with the semiconductor body, wherein the first direction intersects the second direction.

[0006] In some embodiments of this disclosure, the surface of the first semiconductor portion that contacts the semiconductor body includes a concave surface that is recessed toward the capacitor structure.

[0007] In some embodiments of this disclosure, in the second direction, the distance between adjacent first semiconductor portions is greater than or equal to 5 nm.

[0008] In some embodiments of this disclosure, the materials of the first semiconductor portion and the second semiconductor portion are different.

[0009] In some embodiments of this disclosure, the material of the first semiconductor portion is the same as the material of the semiconductor body.

[0010] In some embodiments of this disclosure, the dimension of the first semiconductor portion in the first direction is smaller than the dimension of the second semiconductor portion in the first direction.

[0011] In some embodiments of this disclosure, the second semiconductor portion includes a first end and a second end facing away from each other in a first direction, wherein the first end contacts the first semiconductor portion in the first direction; and in the second direction, the size of the first end is smaller than the size of the second end.

[0012] In some embodiments of this disclosure, the end of the semiconductor body that contacts the connection structure includes a first doped region; the second semiconductor portion includes a second doped region, wherein the conductive impurity doping concentration of the first doped region is less than the conductive impurity doping concentration of the second doped region.

[0013] In some embodiments of this disclosure, the contact area between the first semiconductor portion and the end of the semiconductor body is greater than the cross-sectional area of ​​the end of the semiconductor body in a plane perpendicular to the first direction.

[0014] In some embodiments of this disclosure, the connection structure further includes: a first connection portion located on the side of the second semiconductor portion away from the semiconductor body in a first direction; and a second connection portion located on the side of the first connection portion away from the second semiconductor portion in a first direction and in contact with the capacitor structure.

[0015] In some embodiments of this disclosure, the material of the second connecting portion includes a metallic material; and the material of the first connecting portion includes a metal silicide material.

[0016] In some embodiments of this disclosure, in the second direction, the size of the second connecting portion is larger than the size of the first connecting portion.

[0017] In some embodiments of this disclosure, in the second direction, the size of the first connecting portion is larger than the size of the second semiconductor portion.

[0018] In some embodiments of this disclosure, the second connection portion includes: a metal body portion; and an adhesive portion surrounding the metal body portion, wherein the material of the adhesive portion includes at least one of titanium, titanium nitride, tantalum, and tantalum nitride.

[0019] In some embodiments of this disclosure, the semiconductor device further includes: a gate structure located at least on one side of the semiconductor body in the second direction; and a bit line structure located on the side of the semiconductor body away from the capacitor structure in the first direction, extending along the second direction and connected to a plurality of semiconductor bodies.

[0020] In some embodiments of this disclosure, the semiconductor device further includes: an isolation structure extending along a third direction that intersects both the first direction and the second direction, wherein the isolation structure and the gate structure are located on opposite sides of the semiconductor body in the second direction.

[0021] This disclosure also provides a method for fabricating a semiconductor device, the method comprising: forming a semiconductor body extending along a first direction; forming a connection structure extending along the first direction; and forming a capacitor structure located on one side of the semiconductor body along the first direction, wherein the connection structure connects the semiconductor body and the capacitor structure, wherein the connection structure includes a first semiconductor portion and a second semiconductor portion that are in contact with each other in the first direction; and a portion of the first semiconductor portion is located between the second semiconductor portion and the semiconductor body in the first direction, and another portion of the first semiconductor portion is located at least on one side of the semiconductor body in the second direction and is in contact with the semiconductor body, wherein the first direction intersects the second direction.

[0022] In some embodiments of this disclosure, forming a connection structure extending along a first direction includes: forming an initial first semiconductor portion at an end of a semiconductor body in the first direction; forming a second dielectric layer on one side of a first dielectric layer in the first direction, wherein the first dielectric layer is located at least between adjacent semiconductor bodies in the second direction, and the initial first semiconductor portion is located in the second dielectric layer; removing a portion of the second dielectric layer and a portion of the initial first semiconductor portion to form an opening extending along the first direction, wherein the remaining initial first semiconductor portion is formed as a first semiconductor portion; and forming a second semiconductor portion in the opening that contacts the first semiconductor portion.

[0023] In some embodiments of this disclosure, a portion of the initial first semiconductor portion is located on one side of the semiconductor body in a first direction, and another portion of the initial first semiconductor portion is located at least on one side of the semiconductor body in a second direction.

[0024] In some embodiments of this disclosure, forming an initial first semiconductor portion at the end of a semiconductor body in a first direction includes: using an epitaxial growth process to form the initial first semiconductor portion at the end of a semiconductor body in a first direction.

[0025] In some embodiments of this disclosure, forming a second semiconductor portion in contact with the first semiconductor portion in the opening includes: forming the second semiconductor portion in contact with the first semiconductor portion in the opening using a deposition process.

[0026] In some embodiments of this disclosure, forming a connection structure extending along a first direction further includes: forming a first connection portion in the opening that contacts the second semiconductor portion, wherein the first connection portion is located on the side of the second semiconductor portion away from the first semiconductor portion in the first direction; and forming a second connection portion in the opening that contacts the first connection portion, wherein the second connection portion is located on the side of the first connection portion away from the second semiconductor portion in the first direction.

[0027] Another aspect of this disclosure provides a memory system including a controller and a semiconductor device provided in any embodiment of this disclosure, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0028] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0029] Some exemplary embodiments of this disclosure will now be described with reference to the accompanying drawings. These drawings are for illustrative purposes only and are not intended to limit the claimed technical solutions, wherein: Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to an exemplary embodiment of the present disclosure; Figure 2 yes Figure 1 The diagram shows a partially enlarged view of the semiconductor device at point A. Figure 3 This is a flowchart of a method for fabricating a semiconductor device according to an exemplary embodiment of the present disclosure; Figures 4 to 13 These are schematic diagrams illustrating a method for fabricating a semiconductor device according to one embodiment of this disclosure; and Figure 14 This is a block diagram of a system with a memory system provided by way of example in this disclosure. Detailed Implementation

[0030] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0031] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this disclosure, the first direction discussed herein may also be referred to as the second direction, and vice versa.

[0032] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0033] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0034] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0035] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0036] Furthermore, in this disclosure, the use of "connection" or "linkage" may indicate a direct or indirect connection between the corresponding components, and the use of "contact" may indicate a direct connection between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0037] This disclosure will now be described in detail with reference to the accompanying drawings and the gate structure of the embodiments.

[0038] Some embodiments of this disclosure provide a semiconductor device. Figure 1 This is a cross-sectional schematic diagram of a semiconductor device 1000 according to an exemplary embodiment of the present disclosure. Figure 2 yes Figure 1 The diagram shows a partially enlarged view of the semiconductor device 1000 at point A.

[0039] like Figures 1 to 2 As shown, the semiconductor device 1000 may include a semiconductor body 100, a connection structure 200, and a capacitor structure 300. The semiconductor body 100 extends along a first direction (z-direction), and the capacitor structure 300 is located on one side of the semiconductor body 100 in the z-direction. The connection structure 200 extends along the z-direction and connects the semiconductor body 100 and the capacitor structure 300. The connection structure 200 includes a first semiconductor portion 210 and a second semiconductor portion 220 that are in contact with each other in the z-direction. A portion of the first semiconductor portion 210 is located between the second semiconductor portion 220 and the semiconductor body 100 in the z-direction, and another portion of the first semiconductor portion 210 is located at least on one side of the semiconductor body 100 in a second direction (x-direction) and is in contact with the semiconductor body 100, wherein the z-direction intersects the x-direction.

[0040] In embodiments of this disclosure, a semiconductor device includes a transistor and a capacitor structure located on one side of the transistor in a first direction. The semiconductor device also includes a connection structure comprising a first semiconductor portion and a second semiconductor portion that are in contact with each other in the first direction. The second semiconductor portion is connected to the capacitor structure, and the first semiconductor portion is in contact with the semiconductor body of the transistor, thereby achieving a connection between the capacitor structure and the transistor through the connection structure. A portion of the first semiconductor portion is located between the second semiconductor portion and the semiconductor body in the first direction, and another portion of the first semiconductor portion is located at least on one side of the semiconductor body in the direction intersecting the first direction. This increases the size of the overlay process window between the ends of the connection structure and the semiconductor body, thereby optimizing the semiconductor device fabrication process and improving the semiconductor device yield. Furthermore, the fact that a portion of the first semiconductor portion of the connection structure is located at least on one side of the semiconductor body in the direction intersecting the first direction increases the contact area between the connection structure and the semiconductor body, increases the on-state current Ion of the transistor, and thus improves the electrical performance of the semiconductor device.

[0041] Specifically, in some embodiments of this disclosure, taking DRAM as an example, the semiconductor device 1000 may include a transistor layer 1001 and a capacitor structure layer 1002, wherein the transistor layer 1001 may include transistors, and the capacitor structure layer 1002 may include a capacitor structure 300. The capacitor structure layer 1002 is located on one side of the transistor layer 1001 in the z-direction, wherein the z-direction can be understood as the stacking direction of the transistor layer 1001 and the capacitor structure layer 1002.

[0042] The transistor layer 1001 may include multiple transistors, and the capacitor structure layer 1002 may include capacitor structures 300 connected to the transistors in the transistor layer 1001. Therefore, the transistors and the capacitor structures 300 connected to the transistors can constitute a memory cell of a semiconductor device. Multiple memory cells may be spaced apart in a direction intersecting the z-direction. It should be noted that the semiconductor device 1000 provided in this embodiment may be a memory or a part of a memory.

[0043] Optionally, the transistor layer 1001 and the capacitor structure layer 1002 can constitute the memory structure of the semiconductor device 1000. In addition, the semiconductor device 1000 may also include a peripheral circuit structure (not shown). Optionally, the peripheral circuit structure may be disposed on the side of the transistor layer 1001 away from the capacitor structure layer 1002 in the z-direction.

[0044] The peripheral circuitry of the peripheral circuitry structure may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of transistor layer 1001 and capacitor structure layer 1002. For example, the peripheral circuitry may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0045] Optionally, to further reduce the size of the two-dimensional array, the transistors may include a vertical gate transistor array. In this structure, the source 111 and drain 121 of the transistor can be formed at both ends of the extension direction of the transistor channel, respectively. The specific arrangement details of the transistors will be described in detail below with reference to the accompanying drawings.

[0046] Furthermore, in some embodiments of this disclosure, such as vertical metal-oxide-semiconductor field-effect transistors (Metal... Oxide Semiconductor Field Vertical transistors such as Effect Transistors (MOSFETs) can replace conventional planar transistors as transfer transistors for memory cells, thereby reducing the area occupied by transfer transistors, coupling capacitance, and interconnect wiring complexity.

[0047] In some embodiments of this disclosure, unlike planar transistors where an active region is formed in a substrate, a vertical transistor type transistor may include a semiconductor body 100 extending along the z-direction. The semiconductor body 100 extends along the z-direction, exposing not only its ends, such as a first end 110, but also its sidewalls.

[0048] For example, the semiconductor body 100 may have a cubic shape and four exposed sidewalls. However, those skilled in the art will understand that the semiconductor body 100 may also have any suitable 3D shape, such as a polyhedral or cylindrical shape. In other words, the cross-section of the semiconductor body 100 in a plane intersecting the z-direction may have a rectangular, trapezoidal, circular, elliptical, or any other suitable shape. It should be understood that, consistent with the scope of this disclosure, for a semiconductor body having a circular or elliptical cross-section in the aforementioned plane, the semiconductor body 100 may still be considered to have multiple sidewalls.

[0049] The material of the semiconductor body 100 may include any suitable semiconductor material. For example, the material of the semiconductor body 100 may include at least one of doped crystalline silicon or silicides. Alternatively, the material of the semiconductor body 100 may include a metal oxide, which may include at least one of indium gallium zinc oxide, indium tungsten oxide, indium tin oxide, and indium zinc oxide. It should be noted that this disclosure does not limit the material of the semiconductor body.

[0050] The semiconductor body 100 may include a first end 110 and a second end 120 facing away from each other in the z direction, wherein the first end 110 is closer to the capacitor structure 300 than the second end 120.

[0051] Optionally, the first end 110 of the semiconductor body 100 may form the source 111 of the transistor, and its second end 120 may form the drain 121 of the transistor. In other words, the vertical transistor may also include a source 111 and a drain 121 located at the first end 110 and the second end 120 of the semiconductor body 100 respectively in the z-direction, which can be understood as doped regions of the semiconductor body 100, and may also be referred to as source electrodes and drain electrodes. Alternatively, the source and drain may be doped with any suitable P-type dopant, which may include any one or a combination of boron (B) or gallium (Ga). Alternatively, the source and drain may be doped with any suitable N-type dopant, which may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb).

[0052] Optionally, the first end 110 of the semiconductor body 100 may be connected to the capacitor structure 300. Optionally, the second end 120 of the semiconductor body 100 may be connected to the bit line structure 400 of the semiconductor device 1000. The bit line structure 400 may extend in the x-direction and be connected to a plurality of semiconductor bodies 100. For example, the bit line structure 400 may extend in the x-direction and be connected to the second ends 120 of a plurality of semiconductor bodies 100.

[0053] Bit line structure 400 may include a semiconductor material layer (not shown). The material of the semiconductor material layer may include, but is not limited to, silicon (e.g., single-crystal silicon c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable semiconductor material. Furthermore, bit line structure 400 may also include a conductor material layer (not shown), wherein the material of the conductor material layer may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TIN), etc. Optionally, the semiconductor material layer of bit line structure 400 and the semiconductor body 100 may include different semiconductor materials. Alternatively, the semiconductor material layer of bit line structure 400 and the semiconductor body 100 may be fabricated from different semiconductor materials.

[0054] Furthermore, the semiconductor device 1000 may also include a bit line isolation structure (not shown), which may be alternately arranged with the bit line structure 400 in directions intersecting both the x and z directions. The bit line isolation structure may include a bit line isolation layer (not shown) and an air gap (not shown) surrounded by the bit line isolation layer. Optionally, the material of the bit line isolation layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.

[0055] In some embodiments of this disclosure, the vertical transistor may further include a gate structure 500, which may be located at least on one side of the semiconductor body 100 in the x-direction. For example, as an option, the gate structure 500 may be connected to one of the two sidewalls of the semiconductor body 100 facing away from each other in the x-direction; as another option, the gate structure 500 may be connected to one of the two sidewalls of the semiconductor body 100 facing away from each other in the x-direction, and also to the remaining sidewalls of the semiconductor body 100 other than the two sidewalls facing away from each other in the x-direction.

[0056] The gate structure 500 may include a gate conductive layer 510 and a gate dielectric layer 520, wherein the gate dielectric layer 520 is located between the semiconductor body 100 and the gate conductive layer 510. Optionally, the gate conductive layer 510 may include a plurality of conductive layers (not shown).

[0057] Optionally, the material of the gate dielectric layer 520 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the material of the gate dielectric layer 520 may include silicon oxide. Optionally, the material of the conductive layer may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicides, etc.

[0058] In some embodiments of this disclosure, the semiconductor device 1000 may further include a first dielectric layer 101, wherein the first dielectric layer 101 may be located at least on the side of the gate structure 500 away from the semiconductor body 100 in the x-direction. Optionally, the first dielectric layer 101 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. Exemplarily, the material of the first dielectric layer 101 may be the same as the material of the gate dielectric layer 520. It should be noted that when the material of the first dielectric layer 101 and the material of the gate dielectric layer 520 are the same, there is no clear boundary between them.

[0059] In some embodiments of this disclosure, the semiconductor device 1000 may further include an isolation structure 600, which may be located between adjacent gate structures 500 in the x-direction and extend along a direction intersecting both the z-direction and the x-direction. Optionally, the isolation structure 600 and the gate structure 500 may be located on opposite sides of the semiconductor body 100 in the x-direction. For example, the isolation structure 600 is connected to a first sidewall of the semiconductor body 100 in the x-direction, and the gate structure 500 is connected to a second sidewall of the semiconductor body 100 in the x-direction, wherein the first sidewall and the second sidewall are opposite to each other in the x-direction.

[0060] Alternatively, the isolation structure 600 may include an isolation dielectric layer and an isolation conductor layer or air gap surrounded by the isolation dielectric layer. Optionally, the material of the isolation dielectric layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. Optionally, the isolation conductor layer may include the same material as the gate conductive layer; for example, the isolation conductor layer may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. Furthermore, the isolation dielectric layer may also include the same material as the gate dielectric layer. This can simplify the fabrication steps and reduce fabrication costs during the fabrication of semiconductor devices.

[0061] During the operation of the semiconductor device 1000, the isolation structure 600 can act as a shield, thereby helping to reduce mutual interference between adjacent transistors. For example, during the operation of the semiconductor device 1000, a ground voltage or a negative voltage can be applied to the isolation conductor layer of the isolation structure 600 to reduce mutual interference between adjacent transistors, wherein the isolation dielectric layer can isolate the isolation conductor layer from the semiconductor body 100.

[0062] Optionally, refer again Figure 1 In some embodiments of this disclosure, the capacitor structure 300 may include a multilayer capacitor, a cup-shaped capacitor, a columnar capacitor, and a barrel-shaped capacitor, etc. It should be noted that this disclosure does not limit the internal structure of the capacitor structure.

[0063] Optionally, the capacitor structure 300 may include a first electrode portion 301, a second electrode portion 302, and a capacitor dielectric layer 303, wherein the first electrode portion 301 may extend along the z-direction, the capacitor dielectric layer 303 may be located at least on the sidewall of the first electrode portion 301 extending along the z-direction, and the second electrode portion 302 may be located on the side of the capacitor dielectric layer 303 opposite to the first electrode portion 301. The connection structure 200 may connect the semiconductor body 100 and the first electrode portion 301 in the z-direction, or connect the semiconductor body 100 and the second electrode portion 302 in the z-direction; this disclosure does not limit this.

[0064] As an example, the capacitor structure 300 may also include a support core (not shown) extending along the z-direction, a first electrode portion 301 located on the sidewall of the support core extending along the z-direction and the end face of the support core facing the semiconductor body 100, a capacitor dielectric layer 303 located at least on the side of the first electrode portion 301 away from the sidewall of the support core, and a second electrode portion 302 located on the side of the capacitor dielectric layer 303 away from the first electrode portion 301.

[0065] Optionally, the material of the support core may include elemental semiconductor materials such as silicon (Si) or composite semiconductor materials such as germanium-silicon (GeSi). In this case, the first electrode portion 301 may have a cylindrical structure extending along the z-direction. In other embodiments, the capacitor structure 300 may not include a support core, in which case the first electrode portion 301 may have a columnar structure extending along the z-direction. It should be noted that the capacitor structure 300 in the embodiments of this disclosure may adopt other structural forms suitable for this disclosure in addition to the above-described structural forms.

[0066] The materials of the first electrode portion 301 and the second electrode portion 302 mentioned above may be the same or different. The materials of the first electrode portion 301 and the second electrode portion 302 may include at least one of metal, metal compound and semiconductor material. For example, the materials of the first electrode portion 301 and the second electrode portion 302 may include at least one of titanium nitride, titanium silicide and nickel silicide.

[0067] Optionally, the material of the capacitor dielectric layer 303 may include at least one of aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, zirconium oxide, zirconium silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, hafnium zirconate, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, and praseodymium oxide.

[0068] Combination Figure 1 and Figure 2 In some embodiments of this disclosure, the surface of the first semiconductor portion 210 that contacts the semiconductor body 100 may include a concave surface 211 recessed toward the capacitor structure 300. It should be noted that, for ease of illustration, the concave surface 211 is... Figure 2 The lines along the edge of the concave surface 211 have been thickened. This concave shape increases the contact area between the interconnect structure and the semiconductor substrate, thereby increasing the size of the overlay process window between the interconnect structure and the semiconductor substrate, and improving the on-state current of the transistor.

[0069] Optionally, the contact area between the connection structure 200 and the first end 110 of the semiconductor body 100 may be greater than the cross-sectional area of ​​the first end 110 of the semiconductor body 100 in a plane perpendicular to the z-direction. In other words, the first end 110 may include an end face perpendicular to the z-direction and a side face connected to the end face. The surface of the first semiconductor portion 210 in contact with the semiconductor body 100 includes a concave surface 211 recessed toward the capacitor structure 300. This concave surface 211 contacts not only the end face of the first end 110 but also the side face of the first end 110 connected to the aforementioned end face. This increases the contact area between the connection structure and the semiconductor body, thereby increasing the size of the overlay process window between the connection structure and the semiconductor body and improving the on-state current of the transistor.

[0070] Optionally, the distance n between adjacent first semiconductor portions 210 in the x-direction can be greater than or equal to 5 nm. This can reduce the probability of leakage current occurring in the semiconductor device due to the distance between adjacent first semiconductor portions being too small.

[0071] In some embodiments of this disclosure, the dimension h1 of the first semiconductor portion 210 in the z-direction may be smaller than the dimension h2 of the second semiconductor portion 220 in the z-direction. A portion of the first semiconductor portion 210 is located between the second semiconductor portion 220 and the semiconductor body 100 in the z-direction, and another portion of the first semiconductor portion 210 is located at least on one side of the semiconductor body 100 in the x-direction and is in contact with the semiconductor body 100. Therefore, the first semiconductor portion 210 can increase the contact area between the connection structure 200 and the semiconductor body 100. Based on this, the dimension h1 of the first semiconductor portion 210 in the z-direction can be appropriately reduced to reduce the overall dimension of the connection structure 200 in the z-direction, which is beneficial for miniaturizing the semiconductor device.

[0072] Furthermore, the second semiconductor portion 220 may include a first end 221 and a second end 222 facing away from each other in the z-direction, wherein the first end 221 may contact the first semiconductor portion 210 in the z-direction. Optionally, the dimension d1 of the first end 221 in the x-direction may be smaller than the dimension d2 of the second end 222 in the x-direction. In some embodiments of this disclosure, an opening extending in the z-direction may be formed first by an etching process, and the second semiconductor portion 220 may be formed in the opening using a deposition process with semiconductor material. In this process, due to the limitations of the etching process, the opening has a top-to-bottom shape in a plane parallel to the z-direction (e.g., the xz plane). Therefore, the dimension d2 of the second end 222 of the second semiconductor portion 220 formed based on this opening in the x-direction may be larger than the dimension d1 of the first end 221 in the x-direction.

[0073] In some embodiments of this disclosure, the connection structure 200 may further include a first connection portion 230 and a second connection portion 240, wherein the first connection portion 230 may be located on the side of the second semiconductor portion 220 away from the semiconductor body 100 in the z-direction, and the second connection portion 240 may be located on the side of the first connection portion 230 away from the second semiconductor portion 220 in the z-direction, and is in contact with the capacitor structure 300. In other words, the first connection portion 230 is located between the second connection portion 240 and the second semiconductor portion 220 in the z-direction.

[0074] Optionally, the material of the second connection portion 240 may include a metallic material, and the material of the first connection portion 230 may include a metal silicide material. The resistivity of the first connection portion 230, which includes a silicide material, can affect the resistivity of the connection structure in which it is located, and thus affect parameters such as the transistor's on-state current and switching speed. For example, the relatively low resistivity of the silicide layer can reduce the resistivity of the connection structure, thereby increasing the transistor's on-state current and switching speed.

[0075] Optionally, the dimension d4 of the second connecting portion 240 in the x-direction may be greater than the dimension d3 of the first connecting portion 230 in the x-direction. Optionally, the dimension d3 of the first connecting portion 230 in the x-direction may be greater than the dimension of the second semiconductor portion 220 in the x-direction, for example, the dimension d2 of the second end 222 of the second semiconductor portion 220 in the x-direction.

[0076] As described above, the first connecting portion 230 and the second connecting portion 240 of the connecting structure 200 can also be formed by sequentially filling a metal silicide material, a metal material, etc., into an opening extending in the z-direction first formed by the etching process described above. In this process, due to limitations of the etching process, the opening has a shape that is larger at the top and smaller at the bottom in a plane parallel to the z-direction (e.g., the xz plane). Therefore, the first connecting portion 230 and the second connecting portion 240 formed based on this opening also have a shape that is larger at the top and smaller at the bottom in a plane parallel to the z-direction (e.g., the xz plane).

[0077] Optionally, in some embodiments of this disclosure, the second connection portion 240 may include a metal body portion 241 and an adhesive portion 242, wherein the adhesive portion 242 may be disposed around the metal body portion 241. The material of the adhesive portion 242 may include at least one of titanium, titanium nitride, tantalum, and tantalum nitride. The material of the metal body portion 241 may include at least one of tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al). The adhesive portion 242 may reduce the probability of diffusion of metal atoms or conductive impurities in the metal body portion 241 and improve the overall interfacial adhesion of the second connection portion 240, thereby optimizing the electrical performance of the connection structure and improving the yield of semiconductor devices.

[0078] Refer again Figure 1 In some embodiments of this disclosure, the first end 110 of the semiconductor body 100 may form the source 111 of a transistor, which can be understood as a first doped region. Furthermore, the second semiconductor portion 220 may include a second doped region 223. Alternatively, the second doped region 223 may be doped with any suitable P-type dopant, which may include any one or a combination of boron (B) or gallium (Ga). Alternatively, the second doped region 223 may be doped with any suitable N-type dopant, which may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb).

[0079] Optionally, the conductive impurity doping concentration of the first doped region 111 is lower than that of the second doped region 223. Alternatively, the connection structure 200 includes a heavily doped second semiconductor portion 220, which effectively reduces the contact resistance of the connection structure 200. The difference in conductive impurity concentration between the second doped region 223 of the connection structure 200 and the first doped region of the semiconductor body 100 generates a diffusion driving force, increasing current gain and consequently improving the transistor's on-state current and switching speed.

[0080] It should be noted that, Figure 1 The first doped region (source 111) and the second doped region 223 shown are for ease of observation only. This disclosure does not limit the specific shape of the first doped region and the second doped region 223.

[0081] Optionally, in some embodiments of this disclosure, the materials of the first semiconductor portion 210 and the second semiconductor portion 220 of the connection structure 200 may include any suitable semiconductor material. For example, the materials of the first semiconductor portion 210 and the second semiconductor portion 220 may include, but are not limited to, silicon (e.g., polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), or any other suitable semiconductor material.

[0082] Furthermore, the material of the first semiconductor portion 210 of the connection structure 200 and the material of its second semiconductor portion 220 may be different. In other words, the materials of the first semiconductor portion 210 and the second semiconductor portion 220 of the connection structure 200 may be formed using different fabrication processes and different semiconductor materials. For example, as described above, the second semiconductor portion 220 may be formed using a deposition process. Specifically, the second semiconductor portion 220 may be formed by adding a dopant precursor to a reaction gas and simultaneously incorporating impurity atoms during thin film deposition, such as in-situ doping deposition, to form a second semiconductor portion 220 having a second doped region 223. Optionally, the first semiconductor portion 210 may be formed at the first end 110 of the semiconductor body 100 using an epitaxial growth process.

[0083] Alternatively, the material of the first semiconductor section 210 may be the same as the material of the semiconductor body 100. Alternatively, the material of the first semiconductor section 210 may be different from the material of the semiconductor body 100.

[0084] In other words, in some embodiments of this disclosure, the first semiconductor portion 210 can be formed on the first end portion 110 of the semiconductor body 100 by an epitaxial growth process. Optionally, the material of the first semiconductor portion 210 may be different from the material of the semiconductor body 100. For example, a heteroepitaxial growth process can be used to form the first semiconductor portion 210 on the first end portion 110 of the semiconductor body 100. In this embodiment, the material of the first semiconductor portion 210 is different from the material of the semiconductor body 100. For example, the material of the semiconductor body 100 may include monocrystalline silicon, etc., and the material of the first semiconductor portion 210 may include gallium arsenide (GaAs), etc.

[0085] Furthermore, the material of the first semiconductor portion 210 can be the same as the material of the semiconductor body 100. For example, a homoepitaxial process can be used to form the first semiconductor portion 210 at the first end 110 of the semiconductor body 100. In this embodiment, the material of the first semiconductor portion 210 is the same as the material of the semiconductor body 100. It should be noted that although the material of the first semiconductor portion 210 is the same as the material of the semiconductor body 100, the two are still distinguishable. For example, the first end 110 of the semiconductor body 100 has doped conductive impurities, and the semiconductor body 100 and the first semiconductor portion 210 can be distinguished by observing the doping change at their interface. In addition, there is a difference in defect density between the semiconductor body 100 and the first semiconductor portion 210, which can be observed by observing dislocations or stacking faults at their interface. Figure 1 and Figure 2 The morphology of a first semiconductor portion 210 formed at the first end 110 of a single-crystal silicon semiconductor body 100 with a crystal phase of 111 using a homoepitaxial process is shown.

[0086] Therefore, according to at least one embodiment of this disclosure, a semiconductor device includes a transistor and a capacitor structure located on one side of the transistor in a first direction. The semiconductor device further includes a connection structure comprising a first semiconductor portion and a second semiconductor portion that are in contact with each other in the first direction. The second semiconductor portion is connected to the capacitor structure, and the first semiconductor portion is in contact with the semiconductor body of the transistor, thereby achieving a connection between the capacitor structure and the transistor through the connection structure. A portion of the first semiconductor portion is located between the second semiconductor portion and the semiconductor body in the first direction, and another portion of the first semiconductor portion is located at least on one side of the semiconductor body in the direction intersecting the first direction. This increases the size of the overlay process window between the ends of the connection structure and the semiconductor body, thereby optimizing the semiconductor device fabrication process and improving the semiconductor device yield. Furthermore, the fact that a portion of the first semiconductor portion of the connection structure is located at least on one side of the semiconductor body in the direction intersecting the first direction increases the contact area between the connection structure and the semiconductor body, increases the on-state current Ion of the transistor, and thus improves the electrical performance of the semiconductor device.

[0087] In addition, some embodiments of this disclosure also provide a method for manufacturing a semiconductor device 2000. Figure 3 This is a flowchart of a method 2000 for fabricating a semiconductor device according to an exemplary embodiment of the present disclosure. Figures 4 to 13 These are schematic diagrams of a method for fabricating a semiconductor device according to one embodiment of the present disclosure.

[0088] like Figure 3 As shown, this disclosure provides a method for fabricating a semiconductor device 2000, which may include: S1, forming a semiconductor body extending along the first direction.

[0089] S2, forming a connection structure extending along a first direction, wherein the connection structure includes a first semiconductor portion and a second semiconductor portion that are in contact with each other in the first direction, a portion of the first semiconductor portion being located between the second semiconductor portion and the semiconductor body in the first direction, and another portion of the first semiconductor portion being located at least on one side of the semiconductor body in the second direction and in contact with the semiconductor body, wherein the first direction intersects the second direction.

[0090] S3, forming a capacitor structure located on one side of the semiconductor body along a first direction, wherein the connection structure connects the semiconductor body and the capacitor structure.

[0091] The following will combine Figures 4 to 13 The specific processes for each step of the above preparation method 2000 are described in detail.

[0092] Step S1

[0093] Figure 4 This is a cross-sectional schematic diagram of the structure formed after forming the semiconductor body 100 according to a preparation method according to one embodiment of the present disclosure.

[0094] In some embodiments of this disclosure, taking DRAM as an example, the semiconductor device ultimately formed by the semiconductor device fabrication method 2000 may include a transistor layer and a capacitor structure layer, wherein the transistor layer may include transistors, and the capacitor structure layer may include capacitor structures. The capacitor structure layer may be located on one side of the transistor layer in the z-direction, wherein the z-direction can be understood as the stacking direction of the transistor layer and the capacitor structure layer.

[0095] Transistors and capacitor structures connected to transistors can constitute memory cells of a semiconductor device. Multiple memory cells can be spaced apart in a direction intersecting the z-direction. A transistor may include a semiconductor body and a gate structure, wherein the gate structure may be located at least on one side of the semiconductor body in the x-direction. Multiple semiconductor bodies in a transistor layer can also be spaced apart in a direction intersecting the z-direction.

[0096] It should be noted that the transistor layer can be formed using any suitable process, and this disclosure does not limit it. For example, combined with Figure 1 and Figure 4 Fabricating a transistor layer may include: forming a semiconductor body 100 extending along the z-direction; forming an initial gate structure 1200 located on one side of the semiconductor body 100 at least in the x-direction; and dividing the initial gate structure 1200 into two gate structures 500, wherein the two gate structures 500 may be arranged back-to-back along the x-direction.

[0097] In some embodiments of this disclosure, forming a semiconductor body 100 extending in the z-direction may include: forming a semiconductor substrate (not shown); forming a first trench (not shown) extending in the z-direction in the semiconductor substrate, wherein the first trench may also extend in the x-direction. A plurality of first trenches are spaced apart in a third direction intersecting both the x-direction and the z-direction, thereby forming at least a portion of the semiconductor substrate as a plurality of strip semiconductor layers (not shown) spaced apart in the third direction; and forming a second trench (not shown) extending in the z-direction, wherein the second trench may also extend in the third direction. A plurality of second trenches are spaced apart in the x-direction, thereby dividing the strip semiconductor layers into a plurality of semiconductor bodies 100.

[0098] Specifically, the material used to prepare the semiconductor substrate can be any suitable semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide and other group III-V compounds. Alternatively, single-crystal silicon can be selected as the semiconductor substrate.

[0099] In some embodiments of this disclosure, a semiconductor substrate can be formed by sequentially depositing multiple layers made of different materials using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0100] In some embodiments of this disclosure, the semiconductor substrate may include a substrate sacrificial layer (not shown). Optionally, the substrate sacrificial layer may include a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Alternatively, the substrate sacrificial layer may be a high-dielectric-constant dielectric layer. Another option is that the substrate sacrificial layer may include a dielectric layer, a sacrificial layer, and a dielectric layer sequentially disposed, wherein the dielectric layer may be a silicon nitride layer, and the sacrificial layer may be a silicon oxide layer. Yet another option is that the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer may be monocrystalline silicon or polycrystalline silicon. Specifically, in some embodiments of this disclosure, an exemplary material forming the sacrificial layer may be polycrystalline silicon.

[0101] Furthermore, certain regions of the semiconductor substrate may also form well regions doped with N-type or P-type dopants via ion implantation or diffusion processes. The dopants may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb); or any one or a combination of boron (B), gallium (Ga), or indium (In). In some embodiments of this disclosure, the well regions may be prepared using the same or different dopants; furthermore, the doping concentration of the well regions may be the same or different, and this disclosure does not limit this.

[0102] After the semiconductor substrate is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to remove part of the semiconductor substrate to form a first trench extending in the z-direction in the semiconductor substrate.

[0103] The first trench may also extend along the x-direction, wherein a plurality of first trenches are spaced apart in the third direction, thereby forming at least a portion of the semiconductor substrate as a plurality of strip semiconductor layers spaced apart in the third direction.

[0104] After forming the strip semiconductor layer, the first trench can be filled using one or more thin-film deposition processes to form a first intermediate (not shown). The thin-film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Optionally, the material filling the first trench may include any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, which is not limited herein.

[0105] After the first intermediate is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; alternatively, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to remove part of the first intermediate and form a second trench extending along the z-direction, wherein the second trench may also extend along a third direction. Multiple second trenches are spaced apart in the x-direction, thereby dividing the strip semiconductor layer into multiple semiconductor bodies 100. The semiconductor bodies 100 extend along the z-direction, exposing not only the first end 110 of the semiconductor body 100 but also the sidewalls of the semiconductor body 100.

[0106] For example, the semiconductor body 100 may have a cubic shape and four exposed sidewalls. However, those skilled in the art will understand that the semiconductor body 100 may also have any suitable 3D shape, such as a polyhedral or cylindrical shape. In other words, the cross-section of the semiconductor body 100 in a plane intersecting the z-direction may have a rectangular, trapezoidal, circular, elliptical, or any other suitable shape. It should be understood that, consistent with the scope of this disclosure, for a semiconductor body having a circular or elliptical cross-section in the aforementioned plane, the semiconductor body 100 may still be considered to have multiple sidewalls.

[0107] The semiconductor body 100 is made of the same material as the semiconductor substrate and may include any suitable semiconductor material. For example, the material of the semiconductor body 100 may include at least one of doped crystalline silicon or silicides.

[0108] Furthermore, the material of the semiconductor body 100 may also include a metal oxide, which may include at least one of indium gallium zinc oxide, indium tungsten oxide, indium tin oxide, and indium zinc oxide. It should be noted that this disclosure does not limit the material of the semiconductor body.

[0109] The semiconductor body 100 may include a first end 110 and a second end 120 facing away from each other in the z-direction, wherein the first end 110 is closer to the subsequently formed capacitor structure layer than the second end 120. Optionally, the first end 110 of the semiconductor body 100 may form the source of a transistor, and its second end 120 may form the drain of a transistor. Optionally, the first end 110 of the semiconductor body 100 may be connected to the subsequently formed capacitor structure. Optionally, the second ends 120 of a plurality of semiconductor bodies 100 may be connected to each other in the x-direction.

[0110] After forming the semiconductor body 100, a portion of the second trench can be filled by one or more thin film deposition processes to form an initial gate structure 1200. The thin film deposition process may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0111] The initial gate structure may include an initial gate dielectric layer 1201 and an initial gate conductive layer 1202 sequentially deposited in the second trench, wherein the initial gate conductive layer 1202 may be a composite structure, including a first conductive layer (not shown) and a second conductive layer (not shown) sequentially deposited in the second trench.

[0112] The initial gate dielectric layer 1201 may include any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. The first conductive layer may include, but is not limited to, titanium, titanium nitride, tantalum, or tantalum nitride. The second conductive layer may include any suitable conductive material, such as, but is not limited to, metallic materials such as tungsten (W), cobalt (Co), copper (Cu), or aluminum (Al), or any suitable semiconductor material such as silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), or germanium (Ge).

[0113] After forming the initial gate structure 1200, an initial dielectric layer 1011 can be formed by one or more thin-film deposition processes, wherein the thin-film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The initial first dielectric layer 1011 may be located at least on the side of the initial gate dielectric layer 1201 away from the semiconductor body 100 in the x-direction. Optionally, the initial dielectric layer 1011 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. Exemplarily, the material of the initial dielectric layer 1011 may be the same as the material of the initial gate dielectric layer 1201. It should be noted that when the material of the initial dielectric layer 1011 is the same as the material of the initial gate dielectric layer 1201, there is no clear boundary between the two.

[0114] Furthermore, in some embodiments of this disclosure, an initial isolation structure 1100 may be formed in a portion of the second trench before the initial gate structure 1200 is formed. The initial isolation structure 1100 may be located between adjacent initial gate structures 1200 in the x-direction and extend along a third direction. Optionally, the initial isolation structure 1100 and the initial gate structure 1200 may be located on opposite sides of the semiconductor body 100 in the x-direction.

[0115] Specifically, an initial isolation structure 1100 may be formed in a portion of a plurality of second trenches, and in subsequent steps, for example, a gate structure 500 may be formed (e.g., Figure 1 After (as shown), a portion of the initial isolation structure 1100 is removed to form the isolation structure 600 (as shown). Figure 1 (As shown).

[0116] For example, an initial isolation structure 1100 is formed in a portion of a plurality of second trenches by one or more thin film deposition processes, the thin film deposition processes including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0117] Alternatively, the initial isolation structure 1100 may be a composite structure. For example, the initial isolation structure 1100 may include an initial conductive portion 1101, an initial first dielectric isolation layer 1102, and an initial second dielectric isolation layer 1103. The initial first dielectric isolation layer 1102 may be located between the initial conductive portion 1101 and the semiconductor body 100, and the initial second dielectric isolation layer 1103 may be located at least on one side of the initial conductive portion 1101 in the z-direction. The materials of the initial first dielectric isolation layer 1102 and the initial second dielectric isolation layer 1103 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. Exemplarily, the material of the initial first dielectric isolation layer 1102 may include silicon oxide, and the material of the initial second dielectric isolation layer 1103 may include silicon nitride. Optionally, the material of the initial conductive portion 1101 may include, but is not limited to, conductive materials such as titanium, titanium nitride, tantalum, and tantalum nitride.

[0118] Furthermore, in some embodiments of this disclosure, before forming the initial isolation structure 1100 in a portion of the plurality of second trenches, a protective layer (not shown) may be formed in another portion of the plurality of second trenches (hereinafter referred to as the remaining second trenches), and after forming the initial isolation structure 1100, the protective layer is removed to expose the remaining second trenches, thereby facilitating the formation of the initial gate structure 1200 in the remaining second trenches.

[0119] Optionally, a protective layer is filled in the remaining second trenches before the initial isolation structure 1100 is formed by one or more thin film deposition processes. After the protective layer is formed, the initial isolation structure 1100 may be formed in a portion of the plurality of second trenches that are not filled with the protective layer. The thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0120] Alternatively, the protective layer can be formed of a material with a high deposition rate to facilitate rapid filling of the remaining second trenches, and the protective layer should be any material with high dry etching selectivity relative to the semiconductor body 100 to facilitate removal in subsequent steps. After the initial isolation structure 1100 is formed, the initial isolation structure 1100 and the remaining second trenches can be spaced apart in the x-direction.

[0121] Step S2

[0122] Figure 5 This is a cross-sectional schematic diagram of the structure formed after forming the initial first semiconductor portion 212 according to a preparation method according to an embodiment of the present disclosure. Figure 6 This is a cross-sectional schematic diagram of the structure formed after forming the second dielectric layer 102 according to a preparation method according to one embodiment of the present disclosure. Figure 7 This is a cross-sectional schematic diagram of the structure formed after forming the opening 1300 according to a preparation method according to one embodiment of the present disclosure. Figure 8 This is a cross-sectional schematic diagram of the structure formed after forming the initial second semiconductor portion 1400 according to a preparation method according to one embodiment of the present disclosure. Figure 9 This is a cross-sectional schematic diagram of the structure formed after forming the second semiconductor portion 220 according to a preparation method according to one embodiment of the present disclosure. Figure 10 This is a cross-sectional schematic diagram of the structure formed after forming the first connecting portion 230 according to a preparation method according to an embodiment of the present disclosure. Figure 11 This is a cross-sectional schematic diagram of the structure formed after forming the connecting structure 200 according to a preparation method according to one embodiment of the present disclosure.

[0123] like Figures 4 to 11As shown, in some embodiments of this disclosure, step S2, forming a connection structure extending along a first direction, may include: forming an initial first semiconductor portion 212 at the end of the semiconductor body 100 in the z-direction; forming a second dielectric layer 102 located on one side of the first dielectric layer 101 in the z-direction, wherein the first dielectric layer 101 is located at least between adjacent semiconductor bodies 100 in the x-direction, and the initial first semiconductor portion 212 is located in the second dielectric layer 102; removing a portion of the second dielectric layer 102 and a portion of the initial first semiconductor portion 212 to form an opening 1300 extending along the z-direction, wherein the remaining initial first semiconductor portion 212 is formed as a first semiconductor portion 210; and forming a second semiconductor portion 220 in the opening 1300 that contacts the first semiconductor portion 210.

[0124] Specifically, as an option, forming the initial first semiconductor portion 212 at the z-direction end of the semiconductor body 100 may include: using an epitaxial growth process to form the initial first semiconductor portion 212 at the z-direction end of the semiconductor body 100. The epitaxial growth process may include: vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MPE), or any combination thereof. The material of the initial first semiconductor portion 212 may include at least one of silicon, silicon-germanium, germanium, III-V compound materials, II-VI compound materials, organic semiconductor materials, and other suitable semiconductor materials.

[0125] Optionally, the initial first semiconductor portion 212 can be formed on the first end 110 of the semiconductor body 100 using a heteroepitaxial growth process. In this embodiment, the material of the initial first semiconductor portion 212 may be different from the material of the semiconductor body 100. For example, the material of the semiconductor body 100 may include single-crystal silicon, and the material of the initial first semiconductor portion 212 may include gallium arsenide (GaAs), etc. It should be noted that this disclosure does not limit the specific material and specific formation process of the initial first semiconductor portion 212.

[0126] Optionally, the initial first semiconductor portion 212 can be formed on the first end portion 110 of the semiconductor body 100 using a homoepitaxial process. In this embodiment, the material of the initial first semiconductor portion 212 is the same as the material of the semiconductor body 100. It should be noted that although the material of the initial first semiconductor portion 212 is the same as the material of the semiconductor body 100, the two are still distinguishable. For example, the first end portion 110 of the semiconductor body 100 has doped conductive impurities, and the semiconductor body 100 and the initial first semiconductor portion 212 can be distinguished by observing the doping change at their interface. Furthermore, there is a difference in defect density between the semiconductor body 100 and the initial first semiconductor portion 212, which can be observed by observing dislocations or stacking faults at their interface.

[0127] Figure 5 The morphology of an initial first semiconductor portion 212 formed at the first end 110 of a single-crystal silicon semiconductor body 100 with a crystal phase of 111 using a homoepitaxial process is shown. This initial first semiconductor portion 212 has a centrally symmetrical shape, for example, it is a square shape. Therefore, in a plane intersecting the z-direction, the initial first semiconductor portion 212 extends symmetrically by the same dimension in a direction away from the semiconductor body 100, centered on the semiconductor body 100.

[0128] Optionally, a portion of the initial first semiconductor portion 212 is located on one side of the semiconductor body 100 in the z direction, and another portion of the initial first semiconductor portion 212 is located at least on one side of the semiconductor body 100 in the x direction.

[0129] like Figures 5 to 6 As shown, after the initial first semiconductor portion 212 is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to remove part of the initial dielectric layer 1011 and form the first dielectric layer 101. This process can expose the first end portion 110 of the semiconductor body 100.

[0130] Subsequently, a second dielectric layer 102 located on one side of the first dielectric layer 101 in the z direction can be formed by one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0131] Optionally, the second dielectric layer 102 may include any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. This disclosure does not limit the material of the second dielectric layer 102.

[0132] Alternatively, the first dielectric layer 101 and the second dielectric layer 102 may comprise the same material. Alternatively, the first dielectric layer 101 and the second dielectric layer 102 may comprise different materials. For example, the material of the second dielectric layer 102 may be a material with a high etch selectivity relative to the material of the initial first semiconductor portion 212. This can improve the subsequent formation of the opening 1300 (e.g., Figure 7 The dry etching process (shown) increases the etching speed in the second dielectric layer 102 and improves the etching accuracy of the dry etching process in the initial first semiconductor section 212, thereby increasing the speed of the semiconductor device fabrication process and improving the consistency of the morphology of multiple interconnect structures.

[0133] like Figures 6 to 7 As shown, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to remove part of the second dielectric layer 102 and part of the initial first semiconductor portion 212, forming an opening 1300 extending along the z-direction, wherein the remaining initial first semiconductor portion 212 is formed as the first semiconductor portion 210. Optionally, the remaining second dielectric layer 102 is formed as the remaining second dielectric layer 103.

[0134] like Figures 7 to 9 As shown, in some embodiments of this disclosure, forming a second semiconductor portion in contact with the first semiconductor portion in the opening may include: forming a second semiconductor portion 220 in contact with the first semiconductor portion 210 in the opening 1300 using a deposition process. Optionally, the deposition process may include, but is not limited to, thin film deposition processes or any combination thereof, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. For example, the second semiconductor portion 220 may be formed by adding a dopant precursor to a reactive gas and simultaneously doping impurity atoms during thin film deposition using a process such as in-situ doping deposition, thereby forming a second semiconductor portion 220 having a doped region (not shown).

[0135] Optionally, the material of the second semiconductor section 220 may include, but is not limited to, silicon (e.g., polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), or any other suitable semiconductor material.

[0136] Specifically, such as Figures 7 to 8 As shown, an initial second semiconductor portion 1400 in contact with the first semiconductor portion 210 is formed in the opening 1300 using a deposition process. The deposition process may include, but is not limited to, thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Optionally, the initial second semiconductor portion 1400 at least fills the opening 1300.

[0137] like Figures 8 to 9 As shown, the second semiconductor portion 1400 is formed by, for example, a dry etching process or a combination of dry and wet etching processes; alternatively, other manufacturing processes may be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to remove a portion of the initial second semiconductor portion 1400 and form the second semiconductor portion 220. After the second semiconductor portion 220 is formed, the opening 1300 retains a first remaining space 1500 for forming the remaining portion of the connection structure.

[0138] like Figures 9 to 11 As shown, in some embodiments of this disclosure, forming a connection structure extending along the first direction may further include: in the opening 1300 (e.g. Figure 7 A first connecting portion 230 is formed in the opening 1300 to contact the second semiconductor portion 220, wherein the first connecting portion 230 is located in the z-direction on the side of the second semiconductor portion 220 away from the first semiconductor portion 210; and a second connecting portion 240 is formed in the opening 1300 to contact the first connecting portion 230, wherein the second connecting portion 240 is located in the z-direction on the side of the first connecting portion 230 away from the second semiconductor portion 220.

[0139] Optionally, such as Figures 9 to 10 As shown, after the second connection portion 240 is formed, a first connection portion 230 that contacts the second semiconductor portion 220 can be formed in the first remaining space 1500 of the opening through one or more thin film deposition processes. The thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The first connection portion 230 is located in the z-direction on the side of the second semiconductor portion 220 away from the first semiconductor portion 210. After the first connection portion 230 is formed, the opening 1300 (as shown) Figure 7 As shown, a second remaining space 1600 is also reserved for forming the rest of the connecting structure.

[0140] The material of the first connection portion 230 may include a metal silicide material. The resistivity of the first connection portion 230, which includes a silicide material, can affect the resistivity of the connection structure in which it is located, and thus affect parameters such as the transistor's on-state current and switching speed. For example, the relatively low resistivity of the silicide layer can reduce the resistivity of the connection structure, thereby increasing the transistor's on-state current and switching speed.

[0141] like Figures 10 to 11As shown, after the first connection portion 230 is formed, a second connection portion 240 that contacts the first connection portion 230 can be formed in the second remaining space 1600 of the opening by one or more thin film deposition processes. The thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0142] Optionally, the material of the second connection portion 240 may include a metallic material. Optionally, in some embodiments of this disclosure, the second connection portion 240 may include a metallic body portion 241 and an adhesive portion 242, wherein the adhesive portion 242 may be disposed around the metallic body portion 241. The material of the adhesive portion 242 may include at least one of titanium, titanium nitride, tantalum, and tantalum nitride. The material of the metallic body portion 241 may include at least one of tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al). The adhesive portion 242 may reduce the probability of diffusion of metal atoms or conductive impurities in the metallic body portion 241 and improve the overall interfacial adhesion of the second connection portion 240, thereby optimizing the electrical performance of the connection structure and improving the yield of the semiconductor device.

[0143] Step S3

[0144] Figure 12 This is a cross-sectional schematic diagram of the structure formed after forming the capacitor structure 300 according to an embodiment of the present disclosure.

[0145] refer to Figure 11 and Figure 12 In some embodiments of this disclosure, step S3, forming a capacitor structure located on one side of the semiconductor body along a first direction, may include: forming a stacked structure (not shown) on the side of the second dielectric layer 102 away from the first dielectric layer 101 in the z direction; forming a capacitor hole (not shown) in the stacked structure; forming a first electrode portion 301 in the capacitor hole; removing a portion of the stacked structure to expose a portion of the surface of the first electrode portion 301; and forming a capacitor dielectric layer 303 on a portion of the surface of the first electrode portion 301, and forming a second electrode portion 302 on the side of the capacitor dielectric layer 303 opposite to the first electrode portion 301.

[0146] Optionally, a stacked structure is formed by sequentially stacking a third dielectric layer (not shown) and a sacrificial layer (not shown) along the z-direction on the side of the second dielectric layer 102 away from the first dielectric layer 101 using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0147] Optionally, the material of the third dielectric layer may include at least one of silicon nitride (Si3N4), silicon oxynitride (SiON), and aluminum oxide (Al2O3). Furthermore, the material of the third dielectric layer may also be doped with dopants such as boron or carbon; for example, the material of the third dielectric layer may include at least one of silicon carbon nitride (SiCN) and silicon boron nitride (SiBN).

[0148] The sacrificial layer and the third dielectric layer may comprise different materials. For example, the sacrificial layer may be formed of a material with a high deposition rate to facilitate rapid formation, and the sacrificial layer should be any material with high dry etching selectivity relative to the third dielectric layer to facilitate removal in subsequent steps. Optionally, the dimension of the sacrificial layer in the z-direction may be larger than the dimension of the third dielectric layer in the z-direction.

[0149] After forming the stacked structure, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to form capacitor holes that pass through the stacked structure in the z-direction, wherein the capacitor holes pass through the third dielectric layer and the sacrificial layer in the z-direction. The capacitor holes can be used to form the first electrode portion 301 of the capacitor structure 300 in subsequent steps.

[0150] After the capacitor aperture is formed, a first electrode portion 301 can be formed in the capacitor aperture by one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, and this disclosure does not limit them.

[0151] The first electrode portion 301 can be a multi-layer structure or a single-layer structure, and this disclosure does not limit it in this way. For example, the first electrode portion 301 can be a conductive post extending along the z-direction. In the plane intersecting with z, the cross-section of the first electrode portion 301 can be rectangular, circular, elliptical, semi-circular, or other arbitrary shapes, and this disclosure does not limit it in this way. Optionally, the first electrode portion 301 may also include an electrode conductive layer (not shown) and a support core (not shown).

[0152] The material of the first electrode portion 301 may include at least one of a metallic material, a metallic compound material, and a semiconductor material. For example, the material of the first electrode portion 301 may include titanium nitride (TiN), titanium silicide (TiSi2), or nickel silicide (NiSi).

[0153] In some embodiments of this disclosure, after the first electrode portion 301 is formed, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to gradually remove the sacrificial layer to expose a portion of the surface of the first electrode portion 301.

[0154] A capacitor dielectric layer 303 and a second electrode portion 302 can be sequentially formed on a portion of the exposed first electrode portion 301 through one or more thin film deposition processes. The thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and this disclosure does not limit them.

[0155] Optionally, the capacitor dielectric layer 303 is located on at least a portion of the surface of the first electrode portion 301, and the second electrode portion 302 is located on the surface of the capacitor dielectric layer 303 away from the first electrode portion 301.

[0156] Alternatively, the material of the capacitor dielectric layer 303 may include a high dielectric constant material. For example, the material of the capacitor dielectric layer 303 may include aluminum oxide (Al₂O₃), tantalum oxide (Ta₂O₃), titanium oxide (TiO₂), yttrium oxide (Y₂O₃), zirconium oxide (ZrO₂), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), Hafnium silicon oxide (HfSi) x O y Hafnium silicon nitride oxide (HfSiON), hafnium zirconate (HfZrO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y At least one of the following: praseodymium oxide (Pr2O3).

[0157] Furthermore, the material of the second electrode portion 302 may include at least one of a metallic material, a metal compound material, and a semiconductor material. For example, the material of the second electrode portion 302 may include titanium nitride (TiN), titanium silicide (TiSi2), or nickel silicide (NiSi). Optionally, the materials of the first electrode portion 301 and the second electrode portion 302 may be the same or different, and this disclosure does not limit this.

[0158] Figure 13This is a cross-sectional schematic diagram of the structure formed after forming the gate structure 500 according to an embodiment of the present disclosure.

[0159] In addition, such as Figure 12 and Figure 13 As shown, in some embodiments of this disclosure, the semiconductor device fabrication method 2000 further includes: dividing the initial gate structure 1200 into two gate structures 500, wherein the two gate structures 500 can be arranged back-to-back along the x-direction; and removing a portion of the initial isolation structure 1100 to form an isolation structure 600.

[0160] Specifically, it can be Figure 12 The intermediate body of the capacitor structure 300 shown is flipped 180° and formed from the side where the second end 120 of the semiconductor body 100 is located by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to remove part of the initial gate structure 1200, thereby dividing the initial gate structure 1200 into two gate structures 500.

[0161] Furthermore, a first filling dielectric layer can be formed in the space created after removing a portion of the initial gate structure 1200 using one or more thin-film deposition processes. These thin-film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and are not limited thereto in this disclosure. Optionally, the material of the first filling dielectric layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, and is not limited thereto in this disclosure. For example, the material of the first filling dielectric layer may be the same as the material of the first dielectric layer 101. In this case, there is no clear boundary between the first filling dielectric layer and the first dielectric layer 101.

[0162] Alternatively, the isolation structure 600 can be formed from the side where the second end 120 of the semiconductor body 100 is located by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, can be performed to remove part of the initial isolation structure 1100 to form the isolation structure 600.

[0163] Furthermore, a second filling dielectric layer can be formed in the space created after removing a portion of the initial isolation structure 1100 using one or more thin-film deposition processes. These thin-film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and are not limited thereto in this disclosure. Optionally, the material of the second filling dielectric layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, and is not limited thereto in this disclosure. For example, the material of the second filling dielectric layer may be the same as the material of the first dielectric layer 101. In this case, there is no clear boundary between the second filling dielectric layer and the first dielectric layer 101. Additionally, the dimension of the first filling dielectric layer in the z-direction is smaller than the dimension of the second filling dielectric layer in the z-direction.

[0164] Therefore, according to at least one embodiment of this disclosure, a semiconductor device includes a transistor and a capacitor structure located on one side of the transistor in a first direction. The semiconductor device further includes a connection structure comprising a first semiconductor portion and a second semiconductor portion that are in contact with each other in the first direction. The second semiconductor portion is connected to the capacitor structure, and the first semiconductor portion is in contact with the semiconductor body of the transistor, thereby achieving a connection between the capacitor structure and the transistor through the connection structure. A portion of the first semiconductor portion is located between the second semiconductor portion and the semiconductor body in the first direction, and another portion of the first semiconductor portion is located at least on one side of the semiconductor body in the direction intersecting the first direction. This increases the size of the overlay process window between the ends of the connection structure and the semiconductor body, thereby optimizing the semiconductor device fabrication process and improving the semiconductor device yield. Furthermore, the fact that a portion of the first semiconductor portion of the connection structure is located at least on one side of the semiconductor body in the direction intersecting the first direction increases the contact area between the connection structure and the semiconductor body, increases the on-state current of the transistor, and thus improves the electrical performance of the semiconductor device. Some embodiments of this disclosure also provide a memory system.

[0165] Figure 14 This is a block diagram of a system with a memory system provided by way of example in this disclosure.

[0166] like Figure 14 As shown, system 3000 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 3100 located therein). Figure 14As shown, system 3000 may include host 3200 and memory system 3100. Memory system 3100 may have one or more memories 3110 and controller 3120. The memories 3110 may include semiconductor structures as described in the embodiments above (e.g., Figure 1 The semiconductor device 1000 is shown. The host 3200 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 3200 may be configured to send or receive data to and from the memory 3110.

[0167] In some embodiments, controller 3120 may be coupled to memory 3110 and host 3200 and configured to control memory 3110. For example, controller 3120 may be configured to control memory 3110 to perform operations such as read, erase, and program. Controller 3120 may also manage data stored in memory 3110 and communicate with host 3200. For example, controller 3120 may communicate with external devices (e.g., host 3200) according to a specific communication protocol. Although exemplary fabrication methods and structures of semiconductor devices have been described herein, it will be understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor device. Furthermore, the materials of the exemplified layers are merely exemplary.

[0168] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this disclosure.

Claims

1. A semiconductor device, comprising: The semiconductor body extends along a first direction; A capacitor structure is located on one side of the semiconductor body in the first direction; as well as A connection structure extends along the first direction and connects the semiconductor body and the capacitor structure. The connection structure includes a first semiconductor portion and a second semiconductor portion that are in contact with each other in the first direction; as well as A portion of the first semiconductor portion is located between the second semiconductor portion and the semiconductor body in the first direction, and another portion of the first semiconductor portion is located at least on one side of the semiconductor body in the second direction and is in contact with the semiconductor body, wherein the first direction intersects the second direction.

2. The semiconductor device according to claim 1, wherein, The surface of the first semiconductor portion that contacts the semiconductor body includes a concave surface recessed toward the capacitor structure.

3. The semiconductor device according to claim 1, wherein, In the second direction, the distance between adjacent first semiconductor portions is greater than or equal to 5 nm.

4. The semiconductor device according to claim 1, wherein, The materials of the first semiconductor part and the second semiconductor part are different.

5. The semiconductor device according to claim 1, wherein, The material of the first semiconductor part is the same as the material of the semiconductor body.

6. The semiconductor device according to claim 1, wherein, The dimension of the first semiconductor portion in the first direction is smaller than the dimension of the second semiconductor portion in the first direction.

7. The semiconductor device according to claim 1, wherein, The second semiconductor portion includes a first end and a second end facing away from each other in the first direction. Wherein, the first end is in contact with the first semiconductor portion in the first direction; and In the second direction, the size of the first end is smaller than the size of the second end.

8. The semiconductor device according to claim 1, wherein, The end of the semiconductor body that contacts the connection structure includes a first doped region; The second semiconductor portion includes a second doped region. The conductive impurity doping concentration in the first doped region is less than that in the second doped region.

9. The semiconductor device according to claim 1, wherein, The contact area between the first semiconductor portion and the end of the semiconductor body is greater than the cross-sectional area of ​​the end of the semiconductor body in a plane perpendicular to the first direction.

10. The semiconductor device according to claim 1, wherein, The connection structure also includes: A first connecting portion is located on the side of the second semiconductor portion away from the semiconductor body in the first direction; and The second connection portion is located on the side of the first connection portion away from the second semiconductor portion in the first direction, and is in contact with the capacitor structure.

11. The semiconductor device according to claim 10, wherein, The material of the second connecting part includes a metallic material; and The material of the first connecting part includes a metal silicide material.

12. The semiconductor device according to claim 10, wherein, In the second direction, the size of the second connecting portion is larger than the size of the first connecting portion.

13. The semiconductor device according to claim 10, wherein, In the second direction, the size of the first connecting portion is larger than the size of the second semiconductor portion.

14. The semiconductor device according to claim 10, wherein, The second connecting part includes: Metal body; and The adhesive portion surrounding the metal body. The adhesive material includes at least one of titanium, titanium nitride, tantalum, and tantalum nitride.

15. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: A gate structure, at least located on one side of the semiconductor body in the second direction; and Bit line structure, located on the side of the semiconductor body away from the capacitor structure in the first direction, extends along the second direction and is connected to a plurality of semiconductor bodies.

16. The semiconductor device according to claim 15, wherein, The semiconductor device further includes: The isolation structure extends along a third direction that intersects both the first and second directions. The isolation structure and the gate structure are located on opposite sides of the semiconductor body in the second direction.

17. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor body extending along the first direction is formed; A connection structure extending along the first direction is formed; as well as A capacitor structure is formed along the first direction on one side of the semiconductor body, wherein the connection structure connects the semiconductor body and the capacitor structure. The connection structure includes a first semiconductor portion and a second semiconductor portion that are in contact with each other in the first direction; as well as A portion of the first semiconductor portion is located between the second semiconductor portion and the semiconductor body in the first direction, and another portion of the first semiconductor portion is located at least on one side of the semiconductor body in the second direction and is in contact with the semiconductor body, wherein the first direction intersects the second direction.

18. The method according to claim 17, wherein, Forming a connection structure extending along the first direction includes: An initial first semiconductor portion is formed at the end of the semiconductor body in the first direction; A second dielectric layer is formed on one side of the first dielectric layer in the first direction, wherein the first dielectric layer is located at least between the semiconductor bodies adjacent in the second direction, and the initial first semiconductor portion is located in the second dielectric layer; A portion of the second dielectric layer and a portion of the initial first semiconductor portion are removed to form an opening extending along the first direction, wherein the remaining initial first semiconductor portion is formed as the first semiconductor portion; and A second semiconductor portion is formed in the opening, which contacts the first semiconductor portion.

19. The method according to claim 18, wherein, A portion of the initial first semiconductor portion is located on one side of the semiconductor body in the first direction, and another portion of the initial first semiconductor portion is located at least on one side of the semiconductor body in the second direction.

20. The method according to claim 18, wherein, Forming an initial first semiconductor portion at the end of the semiconductor body in the first direction includes: The initial first semiconductor portion is formed at the end of the semiconductor body in the first direction using an epitaxial growth process.

21. The method according to claim 18, wherein, The second semiconductor portion, which contacts the first semiconductor portion, is formed in the opening, including: A deposition process is used to form a second semiconductor portion that contacts the first semiconductor portion in the opening.

22. The method according to claim 18, wherein, The connection structure extending along the first direction further includes: A first connection portion is formed in the opening to contact the second semiconductor portion, wherein the first connection portion is located on the side of the second semiconductor portion away from the first semiconductor portion in the first direction; and A second connection portion is formed in the opening to contact the first connection portion, wherein the second connection portion is located on the side of the first connection portion away from the second semiconductor portion in the first direction.

23. A memory system, comprising: At least one semiconductor device as claimed in any one of claims 1 to 16; as well as A controller, coupled to the semiconductor device, is used to control the semiconductor device to store data.

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