A semiconductor structure, a method for fabricating the semiconductor structure, and a memory thereof.

Abstract

This disclosure relates to the semiconductor field, providing a semiconductor structure, a method for fabricating the semiconductor structure, and a memory thereof, which may include at least: a substrate; a transistor formed in the substrate; a capacitor structure electrically connected to the transistor, the capacitor structure including a filling layer; a first processing layer located on top of the filling layer; a first functional layer located within the first processing layer; a second functional layer, at least partially located within the first processing layer, the second functional layer located below the first functional layer; and a first metal layer in ohmic contact with the first functional layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure, a method for fabricating the semiconductor structure, and a memory thereof. Background Technology

[0002] In existing DRAM (Dynamic Random Access Memory), there are still problems such as high resistance of capacitor structures and transistor performance degradation due to the inability to obtain effective passivation. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, a method for fabricating the semiconductor structure, and a machine memory, which at least helps to solve the problems of high resistance in capacitor structures and transistor performance degradation due to the inability to obtain effective passivation.

[0004] According to some embodiments of this disclosure, one aspect of this disclosure provides a semiconductor structure, including:

[0005] Base;

[0006] Transistors are formed within a substrate;

[0007] A capacitor structure electrically connected to a transistor, the capacitor structure including a filling layer;

[0008] The first processing layer is located on top of the fill layer;

[0009] The first functional layer is located within the first processing layer;

[0010] The second functional layer is located at least partially within the first processing layer and is located below the first functional layer.

[0011] The first metal layer is in ohmic contact with the first functional layer.

[0012] In some embodiments, the capacitor structure has a first capacitor hole, and an initial filling layer fills the first capacitor hole and covers the capacitor structure.

[0013] In some embodiments, a first processed layer is obtained by pre-amorphizing a portion of the initial filler layer, and the remaining initial filler layer is used as a filler layer.

[0014] In some embodiments, the first functional layer contains a first ion, and the second functional layer contains a second ion, wherein the atomic mass of the second ion is less than the atomic mass of the first ion; the second ion can passivate the transistor.

[0015] In some embodiments, the ion concentration of the first ion gradually decreases from top to bottom in the direction perpendicular to the substrate, and the ion concentration of the second ion gradually decreases from top to bottom in the direction perpendicular to the substrate; the first ion includes boron ions, the second ion includes hydrogen ions, and the second ion is distributed to the transistor through the second functional layer.

[0016] In some embodiments, the capacitor structure comprises a support layer, a lower electrode, a dielectric layer, an upper electrode, and a filling layer; the support layer includes a bottom support layer, a middle support layer, and a top support layer, which are spaced apart along a direction perpendicular to the substrate; a portion of the sidewall of the lower electrode is connected to the support layer; the dielectric layer covers the lower electrode and the support layer, and the upper electrode covers the dielectric layer; the upper electrode forms a first capacitor hole, and the filling layer is located in the first capacitor hole.

[0017] In some embodiments, the substrate includes a first isolation structure and a second isolation structure, the second isolation structure being spaced apart along a direction parallel to the substrate; the transistor includes word lines; and a capacitor contact and a landing pad are further included between the transistor and the capacitor structure, the capacitor contact being electrically connected to the landing pad and the landing pad being electrically connected to the capacitor structure.

[0018] Another aspect of this disclosure provides a method for fabricating a semiconductor structure, including:

[0019] A substrate is provided, within which transistors are contained;

[0020] A capacitor structure is formed on a substrate, and the capacitor structure is electrically connected to a transistor. The capacitor structure includes a filler layer.

[0021] A first processing layer is formed, which is located on top of the filler layer;

[0022] A first functional layer is formed, and the first functional layer is located within the first processing layer;

[0023] A second functional layer is formed, which is at least partially located within the first processing layer and is located below the first functional layer.

[0024] A first metal layer is formed, and the first metal layer makes ohmic contact with the first functional layer.

[0025] In some embodiments, the capacitor structure has a first capacitor hole, and an initial filling layer fills the first capacitor hole and covers the capacitor structure.

[0026] In some embodiments, a first processed layer is obtained by pre-amorphizing a portion of the initial fill layer, and the remaining initial fill layer is used as the fill layer.

[0027] In some embodiments, forming the first functional layer and the second functional layer specifically includes: plasma implantation of the first processing layer and the filling layer, wet cleaning of the surface of the first processing layer, forming a first metal layer and then performing a rapid thermal annealing process to form the first functional layer and the second functional layer; the first functional layer contains a first ion, the second functional layer contains a second ion, the atomic mass of the second ion is less than the atomic mass of the first ion; the second ion can passivate the transistor.

[0028] In some embodiments, the ion concentration of the first ion gradually decreases from top to bottom in the direction perpendicular to the substrate, and the ion concentration of the second ion gradually decreases from top to bottom in the direction perpendicular to the substrate; the first ion includes boron ions, the second ion includes hydrogen ions, and the second ion is distributed to the transistor through the second functional layer.

[0029] In some embodiments, the capacitor structure comprises a support layer, a lower electrode, a dielectric layer, an upper electrode, and a filling layer; the support layer includes a bottom support layer, a middle support layer, and a top support layer, which are spaced apart along a direction perpendicular to the substrate; a portion of the sidewall of the lower electrode is connected to the support layer; the dielectric layer covers the lower electrode and the support layer, and the upper electrode covers the dielectric layer; the upper electrode forms a first capacitor hole, and the filling layer is located in the first capacitor hole.

[0030] In some embodiments, the substrate includes a first isolation structure and a second isolation structure, the second isolation structure being spaced apart along a direction parallel to the substrate; the transistor includes word lines; and a capacitor contact and a landing pad are further included between the transistor and the capacitor structure, the capacitor contact being electrically connected to the landing pad and the landing pad being electrically connected to the capacitor structure.

[0031] In another aspect, this disclosure provides a memory, including any of the aforementioned semiconductor structures or semiconductor structures prepared by any of the aforementioned methods.

[0032] The technical solution provided by the embodiments of this disclosure has at least the following advantages: by setting the first metal layer, the first functional layer and the second functional layer, the bulk resistance and contact resistance of the capacitor structure can be reduced, and the transistor can be effectively passivated to improve the performance of the transistor. Attached Figure Description

[0033] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a top view of a semiconductor structure;

[0035] Figure 2A This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0036] Figure 2B This is a schematic diagram of a semiconductor structure including a first capacitor hole according to an embodiment of the present disclosure;

[0037] Figure 2C This is a schematic diagram of a semiconductor structure including an initial filling layer according to an embodiment of the present disclosure;

[0038] Figure 2D This is a schematic diagram of a semiconductor structure comprising a first ion and a second ion according to an embodiment of the present disclosure;

[0039] Figure 3A This is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure;

[0040] Figure 3B This is a schematic diagram of a semiconductor structure including a first ion and a second ion according to another embodiment of the present disclosure;

[0041] Figure 4 A process flow diagram of a semiconductor structure formation method provided in an embodiment of this disclosure;

[0042] Figure 5 This is a schematic diagram of forming a first capacitor hole according to an embodiment of the present disclosure;

[0043] Figure 6 This is a schematic diagram of the formation of an initial fill layer according to an embodiment of the present disclosure;

[0044] Figure 7 This is a schematic diagram of a first processing layer formed according to an embodiment of the present disclosure;

[0045] Figure 8 This is a schematic diagram illustrating the formation of a first functional layer and an initial second functional layer according to an embodiment of the present disclosure;

[0046] Figure 9 This is a schematic diagram of the formation of a first metal layer according to an embodiment of the present disclosure;

[0047] Figure 10 This is a schematic diagram illustrating the formation of a first functional layer and a second functional layer according to an embodiment of the present disclosure;

[0048] Figure 11 This is a schematic diagram of an embodiment of the present disclosure including a first ion and a second ion;

[0049] Figure 12 This is a schematic diagram illustrating the formation of a first functional layer and a second functional layer according to another embodiment of the present disclosure;

[0050] Figure 13 This is a schematic diagram of another embodiment of the present disclosure including a first ion and a second ion; Detailed Implementation

[0051] As can be seen from the background technology, existing DRAM (Dynamic Random Access Memory) still has problems such as high resistance of capacitor structure and transistor performance degradation due to the inability to obtain effective passivation.

[0052] This disclosure provides a semiconductor structure, a method for fabricating the semiconductor structure, and a memory thereof. By setting a first metal layer, a first functional layer, and a second functional layer, the bulk resistance and contact resistance of the capacitor structure can be reduced, and the transistor can be effectively passivated, thereby improving the performance of the transistor.

[0053] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0054] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0055] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0056] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0057] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0058] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0059] Figure 1 This is a top view of a semiconductor structure; Figure 2A This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure; Figure 2B This is a schematic diagram of a semiconductor structure including a first capacitor hole according to an embodiment of the present disclosure; Figure 2C This is a schematic diagram of a semiconductor structure including an initial filling layer according to an embodiment of the present disclosure; Figure 2D This is a schematic diagram of a semiconductor structure comprising a first ion and a second ion according to an embodiment of the present disclosure; Figure 3A This is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure; Figure 3B This is a schematic diagram of a semiconductor structure including a first ion and a second ion according to another embodiment of the present disclosure; Figure 4 A process flow diagram of a semiconductor structure formation method provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of forming a first capacitor hole according to an embodiment of the present disclosure; Figure 6 This is a schematic diagram of the formation of an initial fill layer according to an embodiment of the present disclosure; Figure 7 This is a schematic diagram of a first processing layer formed according to an embodiment of the present disclosure; Figure 8 This is a schematic diagram illustrating the formation of a first functional layer and an initial second functional layer according to an embodiment of the present disclosure; Figure 9 This is a schematic diagram of the formation of a first metal layer according to an embodiment of the present disclosure;

[0060] Figure 10 This is a schematic diagram illustrating the formation of a first functional layer and a second functional layer according to an embodiment of the present disclosure; Figure 11 This is a schematic diagram of an embodiment of the present disclosure including a first ion and a second ion; Figure 12 This is a schematic diagram illustrating the formation of a first functional layer and a second functional layer according to another embodiment of the present disclosure; Figure 13 This is a schematic diagram of another embodiment of the present disclosure, including a first ion and a second ion.

[0061] Each DRAM (Dynamic Random Access Memory) cell consists of one access transistor and one storage capacitor (i.e., 1T1C); the transistor acts as a switch to control access to the capacitor, which stores charge (representing data 0 / 1). Reference Figure 1 For ease of subsequent description, a top view of the substrate is provided here, including an active region 104 extending along a certain inclined direction. Multiple active regions 104 are spaced apart along and perpendicular to the extension direction. The blank area between adjacent active regions 104 is a first isolation structure 102. Word lines 20 extend along a second direction Y and pass through multiple active regions 104, with adjacent word lines 20 spaced apart along a first direction X. Bit lines 21 extend along the first direction X, with multiple bit lines 21 spaced apart along the second direction Y. The active region 104 includes a source S and a drain D. The source S, drain D, and word lines 20 together constitute a transistor 30. A capacitor structure is also formed on the substrate, which will be discussed later. Figures 2A-3B and appendix Figure 5-13 All of them contain capacitor structures and along Figure 1 A cross-sectional view along the DD' direction.

[0062] Please refer to Figures 2A to 2C , Figure 2A This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. Figure 2B This is a schematic diagram of a semiconductor structure including a first capacitor hole according to an embodiment of the present disclosure. Figure 2C This is a schematic diagram of a semiconductor structure including an initial filling layer according to an embodiment of the present disclosure. A semiconductor structure 100 includes a substrate 10; a transistor 30 is formed within the substrate 10. It should be noted that because... Figure 2A for Figure 1 The figure shows a cross-sectional view along the DD' direction. In this cross-sectional view, only the word line 20 in transistor 30 can be seen, so word line 20 and transistor 30 are labeled in the figure. Capacitor structure 40 is electrically connected to transistor 30. Capacitor structure 40 includes a filling layer 701; a first processing layer 801 located on top of filling layer 701; a first functional layer 901 located within the first processing layer 801; a second functional layer 902 located at least partially within the first processing layer 801 and below the first functional layer 901; and a first metal layer 1001 in ohmic contact with the first functional layer 901.

[0063] Specific examples Figures 2A to 2DAs shown, the substrate 10 includes a substrate 101, a first isolation structure 102 and a second isolation structure 103, the second isolation structure 103 being spaced apart along a direction parallel to the substrate 10; the transistor 30 includes word lines 20; between the transistor 30 and the capacitor structure 40, there is also a capacitor contact 501 and a landing pad 502, the capacitor contact 501 and the landing pad 502 are electrically connected, and the landing pad 502 is electrically connected to the capacitor structure 40. The capacitor structure 40 is composed of a support layer 401, a lower electrode 402, a dielectric layer 403, an upper electrode 404, and a filling layer 701. The support layer 401 includes a bottom support layer 4011, a middle support layer 4012, and a top support layer 4013, which are spaced apart along a direction perpendicular to the substrate 10. Part of the sidewall of the lower electrode 402 is connected to the support layer 401. The dielectric layer 403 covers the lower electrode 402 and the support layer 401, and the upper electrode 404 covers the dielectric layer 403. The upper electrode 404 forms a first capacitor hole 601, and the filling layer 701 is located in the first capacitor hole 601.

[0064] Please refer to the details. Figure 2B and Figure 2C The capacitor structure 40 has a first capacitor hole 601, and an initial filling layer 701' fills the first capacitor hole 601 and covers the capacitor structure 40. For example... Figure 2C The result obtained after pre-amorphization of part of the initial filled layer 701' is shown in the figure. Figure 2A The first processed layer 801 is shown, with the remaining initial filling layer 701' serving as the filling layer 701. Pre-amorphization (PAI) is a technique for treating the surface of a material before ion implantation, aiming to reduce lattice defects and channel effects generated during ion implantation, thereby improving the uniformity and controllability of doping. In the embodiments of this application, the initial filling layer 701' can be made of germanium-silicon (SiGe), and the pre-amorphization treatment is performed after forming a layer such as... Figure 2D Before the ion implantation (first ion and second ion) doping shown, undoped ions (such as silicon or germanium) are implanted onto the surface of the initial filling layer 701' to disrupt its crystal structure, forming an amorphous silicon layer, namely the first processing layer 801. The first processing layer 801 refers to... Figure 2A The location of the dashed box is shown. The main purpose of this process is to suppress the "channeling effect," thereby improving the uniformity and controllability of ion implantation (first and second ions). In the pre-amorphization stage, low doses of undoped ions (such as Si+ or Ge+) are typically implanted into the initial filling layer 701' at medium energy; these ions disrupt the lattice structure of the material surface, forming a first processed layer 801 of amorphous silicon. After implantation, a rapid annealing process is performed to stabilize the structure of the amorphous layer and prevent its recrystallization.

[0065] Pre-amorphization offers several advantages. First, it suppresses channeling effects. During ion implantation, ions tend to diffuse along lattice defects (such as dislocations and grain boundaries), leading to uncontrolled doping. Pre-amorphization reduces this channeling effect by disrupting the lattice structure, resulting in a more uniform ion distribution within the material. Second, it improves doping control. Due to the looser structure of amorphous silicon, doping levels are easier to control during ion implantation, preventing overdoping or underdoping. Third, it reduces defects and leakage current. Pre-amorphization reduces lattice defects generated during implantation, thereby lowering device leakage current and improving device performance and reliability. Finally, it improves surface properties. The amorphous layer enhances the surface properties of semiconductor materials, improving compatibility with subsequent processes.

[0066] Then as Figure 2D The diagram shows doping implantation in the first processed layer 801 obtained after pre-amorphization treatment. After the pre-amorphization treatment, actual dopant ion implantation is performed. These ions are more easily and uniformly distributed in the first processed layer 801, thereby improving doping uniformity and dosage control. After doping implantation of the first ion A and the second ion B, a layer is formed as shown... Figure 2D The semiconductor structure 100 shown includes a first functional layer 901 and a second functional layer 902. The first functional layer 901 is located within a first processing layer 801, and the second functional layer 902 is at least partially located within the first processing layer 801, and is located below the first functional layer 901. In this embodiment, the second functional layer 902 is located within the first processing layer 801. The first functional layer 901 contains a first ion A, and the second functional layer 902 contains a second ion B. The atomic mass of the second ion B is less than the atomic mass of the first ion A, and the second ion B can passivate the transistor 30. In a specific embodiment, the ion concentration of the first ion A gradually decreases from top to bottom in the direction perpendicular to the substrate 10, and the ion concentration of the second ion B gradually decreases from top to bottom in the direction perpendicular to the substrate 10. The first ion A includes boron ions, and the second ion B includes hydrogen ions (H). The second ion B is distributed to the transistor 30 through the second functional layer 902. The semiconductor structure 100 also includes a first metal layer 1001. Since the first functional layer 901 is doped with a first ion A, which includes boron ions, the first metal layer 1001 and the first functional layer 901 can achieve ohmic contact, thereby reducing the contact resistance and the bulk resistance of the first functional layer 901 itself.

[0067] In this embodiment, the second ion B includes hydrogen ions. These hydrogen ions are distributed to the transistor 30 through the second functional layer 902 and passivate the transistor 30. It should be noted that thermal steps such as annealing are typically performed after the formation of the first metal layer 1001 and during back-end processing (BEOL) to activate doping or improve material properties. During thermal processing, the increased temperature promotes the diffusion of hydrogen (H). H diffuses downwards from the filler layer 701 (primarily made of SiGe), through the capacitor region, and finally reaches the transistor 30. When H diffuses to the gate oxide layer and silicon interface of the transistor 30, it can react with defects or dangling bonds at the interface. H ions or atoms can fill these defects, reducing the interface state density and thus improving interface quality. Furthermore, H passivation can repair interface defects. Defects at the gate oxide layer and silicon interface of the transistor 30 can lead to leakage and reliability issues. The passivation effect of H repairs these defects and improves the integrity of the interface. Reducing interface defects lowers leakage current and improves the electrical performance of the device; improved interface quality helps to increase carrier mobility and enhance the driving capability of the transistor; repairing defects improves the long-term reliability of the device and reduces the risk of failure due to interface problems.

[0068] Figure 3A This is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure; Figure 3B This is a schematic diagram of a semiconductor structure including a first ion and a second ion according to another embodiment of the present disclosure; Figure 3A and Figure 2A The difference is that, Figure 3A The second functional layer 902 can pass over the first processing layer 801 along a direction perpendicular to the substrate 10, but does not enter the upper electrode layer 404. The first processing layer 801 is shown by the dashed line in the figure. Figure 3A The height H2 of the second functional layer 902 in the middle is greater than Figure 2A The height H2 of the second functional layer 902 in the [layer name]. Please refer to [reference needed]. Figure 3BThe first functional layer 901 contains a first ion A, and the second functional layer 902 contains a second ion B. The atomic mass of the second ion B is smaller than that of the first ion A, and the second ion B can passivate the transistor 30. The first ion A includes boron ions, and the second ion B includes hydrogen ions (H). The second ion B is distributed to the transistor 30 through the second functional layer 902. The semiconductor structure 100 also includes a first metal layer 1001. Since the first functional layer 901 is doped with the first ion A, which includes boron ions, the first metal layer 1001 and the first functional layer 901 can achieve ohmic contact, reducing the contact resistance and the bulk resistance of the first functional layer 901 itself. This embodiment does not change the depth of the first functional layer 901, but the second functional layer 902 extends beyond the first processing layer 801, increasing its depth. That is, while ensuring ohmic contact between the first metal layer 1001 and the first functional layer 901, this embodiment brings the bottom of the second functional layer 902 closer to the transistor 30. The second functional layer 902 includes a second ion B, which can be a hydrogen ion. The hydrogen ions are distributed to the transistor 30 through the second functional layer 902 and passivate the transistor 30. Compared to the previous embodiment, the passivation effect of this embodiment is enhanced. It should be noted that thermal steps such as annealing are typically performed after the formation of the first metal layer 1001 and during the back-end process (BEOL) to activate doping or improve material properties. During thermal treatment, the increased temperature promotes the diffusion of hydrogen (H). H diffuses downwards from the filler layer 701 (mainly made of SiGe), through the capacitor structure region, and finally reaches the transistor 30. When hydrogen diffuses to the gate oxide-silicon interface of transistor 30, it can react with defects or dangling bonds at the interface. Hydrogen ions or atoms can fill these defects, reducing the interface state density and thus improving interface quality. Furthermore, hydrogen passivation can repair interface defects: defects at the gate oxide-silicon interface of transistor 30 can lead to leakage current and reliability issues. Hydrogen passivation repairs these defects, improving interface integrity. Reducing interface defects lowers leakage current and improves the electrical performance of the device; improved interface quality helps increase carrier mobility and enhances the transistor's driving capability; and defect repair improves the long-term reliability of the device and reduces the risk of failure due to interface problems.

[0069] Figure 4 This is a process flow diagram of a semiconductor structure formation method provided in an embodiment of the present disclosure. Figure 5 This is a schematic diagram of forming a first capacitor hole according to an embodiment of the present disclosure. Figure 6 This is a schematic diagram of the formation of an initial filling layer according to an embodiment of the present disclosure. Figure 7 This is a schematic diagram illustrating the formation of a first processing layer according to an embodiment of the present disclosure. Figure 8 This is a schematic diagram illustrating the formation of a first functional layer and an initial second functional layer according to an embodiment of the present disclosure. Figure 9This is a schematic diagram of the formation of a first metal layer according to an embodiment of the present disclosure. Figure 10 This is a schematic diagram illustrating the formation of a first functional layer and a second functional layer according to an embodiment of the present disclosure. Figure 11 This is a schematic diagram of an embodiment of the present disclosure including a first ion and a second ion. Figure 12 This is a schematic diagram illustrating the formation of a first functional layer and a second functional layer according to another embodiment of the present disclosure. Figure 13 This is a schematic diagram of another embodiment of the present disclosure, including a first ion and a second ion.

[0070] Please see Figure 4 A semiconductor structure formation method provided in an embodiment of this application includes: S10 providing a substrate having a transistor therein; S20 forming a capacitor structure on the substrate, the capacitor structure being electrically connected to the transistor, the capacitor structure including a filler layer; S30 forming a first processing layer, the first processing layer being located on top of the filler layer; S40 forming a first functional layer, the first functional layer being located within the first processing layer; S50 forming a second functional layer, the second functional layer being at least partially located within the first processing layer, the second functional layer being located below the first functional layer; and S60 forming a first metal layer, the first metal layer being in ohmic contact with the first functional layer.

[0071] Please refer to the details. Figure 4 and Figure 5 As shown, a substrate 10 is provided, and a transistor 30 is provided within the substrate 10; a capacitor structure 40 is formed on the substrate 10, and the capacitor structure 40 is electrically connected to the transistor 30; the substrate 10 includes a substrate 101, a first isolation structure 102 and a second isolation structure 103, the second isolation structure 103 being spaced apart along a direction parallel to the substrate 10; the transistor 30 includes word lines 20; a capacitor contact 501 and a landing pad 502 are also included between the transistor 30 and the capacitor structure 40, the capacitor contact 501 being electrically connected to the landing pad 502, and the landing pad 502 being electrically connected to the capacitor structure 40. The capacitor structure 40 includes a support layer 401, a lower electrode 402, a dielectric layer 403, and an upper electrode 404. The support layer 401 includes a bottom support layer 4011, a middle support layer 4012, and a top support layer 4013, which are spaced apart along a direction perpendicular to the substrate 10. A portion of the sidewall of the lower electrode 402 is connected to the support layer 401. The dielectric layer 403 covers the lower electrode 402 and the support layer 401, and the upper electrode 404 covers the dielectric layer 403. The upper electrode 404 forms a first capacitor hole 601.

[0072] Please refer to the following: Figure 6 The capacitor structure 40 has a first capacitor hole 601, and an initial filling layer 701' fills the first capacitor hole 601 and covers the upper electrode of the capacitor structure 40. Specifically, the initial filling layer 701' can be deposited by chemical vapor deposition (CVD).

[0073] Please refer to the following: Figure 7 After pre-amorphization treatment of a portion of the initial filling layer 701', a first processed layer 801 is obtained, and the remaining initial filling layer 701' serves as the filling layer 701. The first processed layer 801 is located on top of the filling layer 701. In a specific embodiment, the capacitor structure may further include a filling layer 701, which is pre-amorphized by Ar plasma bombardment or germanium ion implantation. The thickness of the surface amorphous layer is approximately 5-30 nm. Pre-amorphization (PAI) is a technique for treating the surface of a material before ion implantation, aiming to reduce lattice defects and channel effects generated during ion implantation, thereby improving the uniformity and controllability of doping. In the embodiments of this application, the initial filling layer 701' can be made of germanium silicon (SiGe), and the pre-amorphization treatment is performed after forming a... Figure 11 Before ion implantation (first and second ions) doping, undoped ions (such as silicon or germanium) are implanted into the surface of the initial fill layer 701' to disrupt its crystal structure, forming an amorphous silicon layer, i.e., the first processed layer 801. The main purpose of this process is to suppress the "channeling effect," thereby improving the uniformity and controllability of ion implantation (first and second ions). In the pre-amorphization stage, low doses of undoped ions (such as Si+ or Ge+) are typically implanted into the initial fill layer 701' at medium energy; these ions disrupt the crystal structure of the material surface, forming an amorphous silicon first processed layer 801. After implantation, rapid annealing can also be performed to stabilize the structure of the amorphous layer and prevent its recrystallization.

[0074] Pre-amorphization offers several advantages. First, it suppresses channeling effects. During ion implantation, ions tend to diffuse along lattice defects (such as dislocations and grain boundaries), leading to uncontrolled doping. Pre-amorphization reduces this channeling effect by disrupting the lattice structure, resulting in a more uniform ion distribution within the material. Second, it improves doping control. Due to the looser structure of amorphous silicon, doping levels are easier to control during ion implantation, preventing overdoping or underdoping. Third, it reduces defects and leakage current. Pre-amorphization reduces lattice defects generated during implantation, thereby lowering device leakage current and improving device performance and reliability. Finally, it improves surface properties. The amorphous layer enhances the surface properties of semiconductor materials, improving compatibility with subsequent processes.

[0075] Then as Figure 8-11As shown, after plasma injection into the first processing layer 801 and the filling layer 701, the surface of the first processing layer 801 is wet-cleaned, and then a first metal layer 1001 is formed. After the first metal layer 1001 is formed, a rapid thermal annealing process is performed to form a first functional layer 901 and a second functional layer 902. The first functional layer 901 contains a first ion A, and the second functional layer 902 contains a second ion B. The atomic mass of the second ion B is less than the atomic mass of the first ion A. The second ion B can passivate the transistor.

[0076] Specific examples Figure 8 As shown, plasma injection is performed on the first processing layer 801 to form an initial first functional layer 901' and an initial second functional layer 902'. Specifically, B and H elements can be doped into the surface of the first processing layer 801 through plasma doping (PLAD). The plasma gas is a gas containing B and H elements, such as BH3, B2H6, etc. The plasma injection energy can be 1~10KV, and the plasma injection dose can be 1e. 16 ~1e 18The process pressure is between 5 and 20 mTorr. Due to the presence of the first processing layer 801, the "channeling effect" can be suppressed during plasma implantation to form the initial first functional layer 901' and the initial second functional layer 902', thereby improving the uniformity and controllability of ion implantation. This allows the initial first functional layer 901' and the initial second functional layer 902' to be completely confined within the first processing layer 801. Specifically, when boron (B) and hydrogen (H) elements are simultaneously implanted into germanium-silicon materials, their implantation depths differ due to their different atomic masses; specifically, hydrogen is implanted deeper than boron. The specific principle is as follows: the relative atomic mass of boron is approximately 11, while the relative atomic mass of hydrogen is approximately 1. Due to this significant mass difference, at the same energy, the velocity of hydrogen ions is much higher than that of boron ions. Velocity is inversely proportional to energy and mass; therefore, the smaller hydrogen ions are faster. Furthermore, the ion implantation depth is directly proportional to its velocity; the faster the velocity, the longer the ion's path in the material, and the greater the implantation depth. Therefore, hydrogen ions, due to their faster velocity, are implanted deeper into the material. Therefore, in this embodiment, the initial first functional layer 901' contains a first ion, and the initial second functional layer 902' contains a second ion. The initial second functional layer 902' is located below the initial first functional layer 901'. The first ion can be boron, and the second ion can be hydrogen. Thus, after implantation, hydrogen is located at a deeper depth, while boron is located at a shallower depth. Specifically, the initial first functional layer 901' can be a boron-containing germanium-silicon layer, and the initial second functional layer 902' can be a hydrogen-containing germanium-silicon layer. After forming the initial first functional layer 901' and the initial second functional layer 902', the surface of the first processing layer 801 is further wet-cleaned to remove oxides formed on the surface of the first processing layer 801 due to plasma implantation.

[0077] Then as Figure 9 A first metal layer 1001 is formed above the initial first functional layer 901'. The first metal layer 1001 can be tungsten. Specifically, tungsten can be deposited on the surface of the initial first functional layer 901' by chemical vapor deposition (CVD). The tungsten confines boron and hydrogen within the germanium-silicon of the first processing layer 801.

[0078] Then as Figure 10-11 As shown, after forming the first metal layer 1001, a rapid thermal annealing process is performed to form a first functional layer 901 and a second functional layer 902; the first functional layer 901 contains a first ion A, and the second functional layer 902 contains a second ion B, the atomic mass of the second ion B being smaller than the atomic mass of the first ion A; the second ion B can passivate the transistor. For ease of description, Figure 11The diagram illustrates a first ion A and a second ion B, where white dots represent the first ion A and gray dots represent the second ion B. It should be noted that this is only to illustrate the presence of ions and does not represent their atomic mass. The ion concentration of the first ion A gradually decreases from top to bottom in the direction perpendicular to the substrate 10, and the ion concentration of the second ion B also gradually decreases from top to bottom in the same direction. The first ion A includes boron ions, and the second ion B includes hydrogen ions. The second ion B is distributed to the transistor 30 through the second functional layer 902 and the filling layer 701, and can passivate the transistor 30. In this embodiment, since a rapid thermal annealing process is performed after the formation of the first metal layer 1001, the initial first functional layer 901' and the initial second functional layer 902' will diffuse during the rapid thermal annealing process to form the first functional layer 901 and the second functional layer 902. It should be noted that because boron ions have a larger atomic mass than hydrogen ions, they diffuse more slowly during the rapid thermal annealing process. Therefore, the depth difference between the initial first functional layer 901' and the final first functional layer 901 is not significant. That is, the first functional layer 901 is close to the top of the first processing layer 801. Since the first functional layer 901 is heavily doped with boron ions, the Schottky barrier height at the interface between the first metal layer 1001 and the first functional layer 901 can be reduced, promoting the tunneling effect and achieving ohmic contact.

[0079] Because hydrogen atoms have a small mass, they diffuse rapidly during rapid thermal annealing. This results in a second functional layer 902 formed after the initial second energy layer 902 undergoes rapid thermal annealing. The initial second energy layer 902' has a thickness of H1, and the second energy layer 902 has a thickness of H2, where H2 is greater than H1. Figure 10 As shown, in this embodiment, the second energy layer 902 is confined within the first processing layer 801, meaning the second energy layer 902 does not extend beyond the first processing layer 801. In addition to the rapid thermal annealing process required after forming the first metal layer 1001, other additional rapid thermal annealing processes are performed in the back-end processes (such as forming metal interconnects in the back-end process), so that the second ion B can pass through the second functional layer 902 and through the fill layer 701, allowing the second ion B to be distributed to the transistor 30, and the second ion B can passivate the transistor 30.

[0080] It should be noted that thermal steps such as annealing are typically performed after the formation of the first metal layer 1001 and during the back-end process (BEOL) to activate doping or improve material properties. During thermal treatment, the increased temperature promotes the diffusion of hydrogen (H). H diffuses downwards from the filler layer 701 (primarily SiGe), through the capacitor structure 40 region, and finally reaches the transistor 30. When H diffuses to the gate oxide-silicon interface of the transistor 30, it can react with defects or dangling bonds at the interface. H ions or atoms can fill these defects, reducing the interface state density and thus improving interface quality. Furthermore, H passivation can repair interface defects: defects at the gate oxide-silicon interface of the transistor 30 can lead to leakage current and reliability issues. H passivation repairs these defects, improving interface integrity. The reduction of interface defects lowers leakage current and improves the electrical performance of the device; improved interface quality helps increase carrier mobility and enhances the transistor's driving capability; and defect repair improves the long-term reliability of the device and reduces the risk of failure due to interface problems.

[0081] Figure 12 This is a schematic diagram illustrating the formation of a first functional layer and a second functional layer according to another embodiment of the present disclosure; Figure 13 This is a schematic diagram illustrating another embodiment of the present disclosure, including a first ion and a second ion. Please refer to [link / reference]. Figure 12 and Figure 13 Embodiments of this application Figure 12 Compared with the previous embodiment Figure 10 The difference is that, Figure 10 The second energy layer 902 does not extend beyond the first processing layer 801, as described in this embodiment. Figure 12 The second functional layer 902 can pass over the first processing layer 801 along a direction perpendicular to the substrate 10, but does not enter the upper electrode layer 404. The first processing layer 801 is shown by the dashed line in the figure. Figure 12 The height H2 of the second functional layer 902 in the middle is greater than Figure 10 The height H2 of the second functional layer 902 in the [layer name]. Please refer to [reference needed]. Figure 13The first functional layer 901 contains a first ion A, and the second functional layer 902 contains a second ion B. The atomic mass of the second ion B is smaller than that of the first ion A, and the second ion B can passivate the transistor 30. The first ion A includes boron ions, and the second ion B includes hydrogen ions. The second ion B is distributed to the transistor 30 through the second functional layer 902. The semiconductor structure 100 also includes a first metal layer 1001. Since the first functional layer 901 is doped with the first ion A, which includes boron ions, the first metal layer 1001 and the first functional layer 901 can achieve ohmic contact, reducing the contact resistance and the bulk resistance of the first functional layer 901 itself. This embodiment does not change the depth of the first functional layer 901, but the second functional layer 902 extends beyond the first processing layer 801, increasing its depth. That is, while ensuring ohmic contact between the first metal layer 1001 and the first functional layer 901, this embodiment brings the bottom of the second functional layer 902 closer to the transistor 30. The second functional layer 902 includes second ions, which can be hydrogen ions. These hydrogen ions distribute through the second functional layer 902 to the transistor 30 and passivate it. Compared to the previous embodiment, the passivation effect is enhanced in this embodiment. It should be noted that thermal steps, such as annealing, are typically performed after the formation of the first metal layer 1001 and during the back-end process (BEOL) to activate doping or improve material properties. During thermal treatment, the increased temperature promotes the diffusion of hydrogen (H). H diffuses downwards from the filler layer 701 (mainly made of SiGe), through the capacitor structure region, and finally reaches the transistor 30. When hydrogen diffuses to the gate oxide-silicon interface of transistor 30, it can react with defects or dangling bonds at the interface. Hydrogen ions or atoms can fill these defects, reducing the interface state density and thus improving interface quality. Furthermore, hydrogen passivation can repair interface defects: defects at the gate oxide-silicon interface of transistor 30 can lead to leakage current and reliability issues. Hydrogen passivation repairs these defects, improving interface integrity. Reducing interface defects lowers leakage current and improves the electrical performance of the device; improved interface quality helps increase carrier mobility and enhances the transistor's driving capability; and defect repair improves the long-term reliability of the device and reduces the risk of failure due to interface problems.

[0082] Another embodiment of this disclosure also provides a memory, including any of the aforementioned semiconductor structures 100 or semiconductor structures 100 prepared by any of the aforementioned preparation methods.

[0083] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; Transistors are formed within the substrate; A capacitor structure electrically connected to the transistor, the capacitor structure including a filling layer; The first processing layer is located on top of the filling layer; The first functional layer is located within the first processing layer; The second functional layer is at least partially located within the first processing layer, and the second functional layer is located below the first functional layer. The first metal layer is in ohmic contact with the first functional layer.

2. The semiconductor structure according to claim 1, characterized in that, The capacitor structure has a first capacitor hole, and an initial filling layer fills the first capacitor hole and covers the capacitor structure.

3. The semiconductor structure according to claim 2, characterized in that, The first processed layer is obtained by pre-amorphizing a portion of the initial filling layer, and the remaining initial filling layer is used as the filling layer.

4. The semiconductor structure according to claim 1, characterized in that, The first functional layer contains a first ion, and the second functional layer contains a second ion, wherein the atomic mass of the second ion is less than the atomic mass of the first ion; the second ion can passivate the transistor.

5. The semiconductor structure according to claim 4, characterized in that, The concentration of the first ion gradually decreases from top to bottom in the direction perpendicular to the substrate, and the concentration of the second ion gradually decreases from top to bottom in the direction perpendicular to the substrate; the first ion includes boron ions, the second ion includes hydrogen ions, and the second ion is distributed to the transistor through the second functional layer.

6. The semiconductor structure according to any one of claims 1-5, characterized in that, The capacitor structure comprises a support layer, a lower electrode, a dielectric layer, an upper electrode, and a filling layer; the support layer includes a bottom support layer, a middle support layer, and a top support layer, which are spaced apart along a direction perpendicular to the substrate; a portion of the sidewall of the lower electrode is connected to the support layer; The dielectric layer covers the lower electrode and the support layer, and the upper electrode covers the dielectric layer; the upper electrode is configured to form a first capacitor hole, and the filling layer is located in the first capacitor hole.

7. The semiconductor structure according to any one of claims 1-5, characterized in that, The substrate includes a first isolation structure and a second isolation structure, the second isolation structures being spaced apart along a direction parallel to the substrate; the transistor includes word lines; between the transistor and the capacitor structure, there are also capacitor contacts and a landing pad, the capacitor contacts being electrically connected to the landing pad, and the landing pad being electrically connected to the capacitor structure.

8. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein a transistor is disposed therein; A capacitor structure is formed on the substrate, the capacitor structure is electrically connected to the transistor, and the capacitor structure includes a filler layer; A first processing layer is formed, which is located on top of the filler layer; A first functional layer is formed, which is located within the first processing layer; A second functional layer is formed, which is at least partially located within the first processing layer and is located below the first functional layer; A first metal layer is formed, and the first metal layer is in ohmic contact with the first functional layer.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The capacitor structure has a first capacitor hole, and an initial filling layer fills the first capacitor hole and covers the capacitor structure.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The first processed layer is obtained by pre-amorphizing a portion of the initial filling layer, and the remaining initial filling layer is used as the filling layer.

11. The method for preparing a semiconductor structure according to claim 8, characterized in that, The formation of the first functional layer and the second functional layer specifically includes: plasma implantation of the first processing layer and the filling layer, wet cleaning of the surface of the first processing layer, forming the first metal layer, and then performing a rapid thermal annealing process to form the first functional layer and the second functional layer; the first functional layer contains a first ion, the second functional layer contains a second ion, the atomic mass of the second ion is less than the atomic mass of the first ion; the second ion can passivate the transistor.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The concentration of the first ion gradually decreases from top to bottom in the direction perpendicular to the substrate, and the concentration of the second ion gradually decreases from top to bottom in the direction perpendicular to the substrate; the first ion includes boron ions, the second ion includes hydrogen ions, and the second ion is distributed to the transistor through the second functional layer.

13. The method for preparing a semiconductor structure according to any one of claims 9-12, characterized in that, The capacitor structure comprises a support layer, a lower electrode, a dielectric layer, an upper electrode, and a filling layer; the support layer includes a bottom support layer, a middle support layer, and a top support layer, which are spaced apart along a direction perpendicular to the substrate; a portion of the sidewall of the lower electrode is connected to the support layer; The dielectric layer covers the lower electrode and the support layer, and the upper electrode covers the dielectric layer; the upper electrode is configured to form a first capacitor hole, and the filling layer is located in the first capacitor hole.

14. The method for preparing a semiconductor structure according to any one of claims 9-12, characterized in that, The substrate includes a first isolation structure and a second isolation structure, the second isolation structures being spaced apart along a direction parallel to the substrate; the transistor includes word lines; between the transistor and the capacitor structure, there are also capacitor contacts and a landing pad, the capacitor contacts being electrically connected to the landing pad, and the landing pad being electrically connected to the capacitor structure.

15. A memory, characterized in that... It includes the semiconductor structure described in any one of claims 1-7 or the semiconductor structure prepared by any one of claims 8-14.

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