Memory device and method of manufacturing the same, electronic device

Abstract

The application provides a memory device and a manufacturing method thereof, and an electronic device. The manufacturing method of the memory device comprises the following steps: manufacturing a first stacked structure; the first stacked structure comprises a plurality of first semiconductor layers and a plurality of first dielectric layers which are alternately distributed along a first direction, the first semiconductor layer comprises a first part, a second part and a third part which are sequentially connected along a second direction, the first part extends along a third direction, and the plurality of second parts and the plurality of third parts are respectively distributed along the third direction and correspond to each other one by one; manufacturing a transistor based on the second part; replacing the first part with a bit line; removing the dielectric layer outside the third part; manufacturing a first electrode, a first capacitor dielectric layer and a second electrode which are sequentially arranged in a cylindrical shape outside the third part; replacing the third part with a second capacitor dielectric layer and a third electrode which are sequentially and conformally arranged on the inner wall of the first electrode, to obtain a capacitor. The application realizes the increase of the capacitance by effectively utilizing the interval between the capacitors.

Description

Technical Field

[0001] This application relates to the field of storage technology, and more specifically, to a storage device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development and progress of storage technology, storage devices are constantly moving towards miniaturization, high density, high integration, and low power consumption. At the same time, they are also facing problems and challenges from performance and process aspects. Summary of the Invention

[0003] This application proposes a storage device and a method for manufacturing the same, as well as an electronic device, for increasing capacitance by effectively utilizing the spacing between capacitors.

[0004] In a first aspect, embodiments of this application provide a method for manufacturing a storage device, comprising: A first stacked structure is fabricated on a substrate; the first stacked structure includes multiple first semiconductor layers and multiple first dielectric layers that are alternately distributed along a first direction perpendicular to the substrate. The first semiconductor layer includes a first part, a second part and a third part that are sequentially connected along a second direction. The first part extends along a third direction. Multiple second parts and multiple third parts are each distributed along a third direction and correspond one-to-one. The second direction and the third direction intersect and are both parallel to the substrate. Transistors are fabricated based on the second part; Replace the first part with a bit line; Remove the dielectric layer surrounding the third part; A first electrode, a first capacitor dielectric layer, and a second electrode are sequentially wound around the periphery of the third part in a cylindrical shape. The third part is replaced by a second capacitor dielectric layer and a third electrode that sequentially conformally cover the inner peripheral wall of the first electrode to obtain a capacitor.

[0005] In some optional embodiments of this application, a first stacked structure is fabricated on a substrate, including: An initial semiconductor layer and a first sacrificial layer are sequentially and alternately fabricated on one side of the substrate to obtain an initial stacked structure; Multiple rows of first trenches are formed that penetrate the initial stacked structure and are distributed along the second direction; each row of first trenches includes multiple first trenches distributed along the third direction; The first sacrificial layer is partially replaced with dielectric material through the first trench; Multiple second trenches are formed that penetrate the initial stacked structure to obtain a first semiconductor layer; the multiple second trenches and multiple rows of first trenches are alternately distributed along a second direction, and the second trenches extend along a third direction; The remaining first sacrificial layer is replaced with dielectric material through the second trench to form the first dielectric layer, thus obtaining the first stacked structure. And, after fabricating the first stacked structure on the substrate and before fabricating the transistor based on the second part, it also includes: Fabricate a second dielectric layer to fill the first trench; Create a third dielectric layer to fill the second trench.

[0006] In some optional embodiments of this application, the transistor is fabricated based on the second part, including: A third trench is formed that penetrates the first stacked structure and the second dielectric layer and is located on both sides of the second part along the third direction; the third trench exposes the multi-layered channel region; Insulation lines are made in the third trench, which are insulated from the trench area. The second portion located on both sides of the channel region along the second direction is respectively made into the first source-drain region and the second source-drain region to obtain the transistor.

[0007] In some optional embodiments of this application, word lines insulated from the channel region are fabricated within the third trench, including: The initial gate insulating layer, conductive layer, and fourth dielectric layer are sequentially fabricated to cover and fill the third trench; A fourth trench and a fifth trench are fabricated on both sides of the initial gate insulating layer along the second direction; the fourth trench and the fifth trench each expose a second portion located on both sides of the channel region along the second direction; Remove the initial gate insulating layer and the corresponding conductive layer exposed in the fourth and fifth trenches to obtain the gate insulating layer and word line; And, the second portion located on both sides of the channel region along the second direction is respectively made into a first source / drain region and a second source / drain region, including: By using the fourth and fifth trenches, the second portion located on both sides of the channel region along the second direction is doped to obtain the first source / drain region and the second source / drain region.

[0008] In some optional embodiments of this application, the first portion is replaced with a bit line, including: Remove the third dielectric layer to expose a first portion of the multilayer first semiconductor layer; Remove the first part of the multi-layer structure to form the first multi-layer channel; Create bit lines within the first channel.

[0009] In some optional embodiments of this application, the dielectric layer surrounding the third portion is removed, including: Along the third direction, the second dielectric layer located on both sides of the third part is removed to form the sixth trench; Along the first direction, the first dielectric layer located on both sides of the third part is removed to form the second channel; And, fabricating a first electrode, a first capacitor dielectric layer, and a second electrode that are sequentially arranged in a cylindrical shape around the periphery of the third part, including: An initial electrode layer, a first capacitor dielectric layer, and a second electrode are sequentially fabricated around the outer periphery of the third part and conformally cover the second channel and the sixth trench. Along the second direction, the initial electrode layer that conformally covers the side walls of the second channel and the sixth trench is removed to obtain the first electrode.

[0010] In some optional embodiments of this application, the third portion is replaced by a second capacitor dielectric layer and a third electrode that sequentially conformally cover the inner peripheral wall of the first electrode, including: Along the second direction, the dielectric layer on the side of the third part away from the transistor is removed, exposing the third part; Remove the third part to form a third channel; The second capacitor dielectric layer and the third electrode are fabricated sequentially to cover the third channel.

[0011] Secondly, embodiments of this application provide a memory device, including a multilayer device layer stacked on a substrate along a first direction; the device layer includes bit lines, a plurality of transistors, and a plurality of capacitors; Bit lines, transistors, and capacitors are electrically connected sequentially along the second direction; Bit lines extend along the third direction, and multiple transistors and multiple capacitors are distributed along the third direction and correspond one-to-one; The capacitor includes: a first electrode, which is cylindrical and extends along a second direction; The first capacitor dielectric layer and the second electrode are sequentially arranged around the periphery of the first electrode; The second capacitor dielectric layer and the third electrode sequentially conformally cover the inner peripheral wall of the first electrode.

[0012] In some optional embodiments of this application, the storage device includes at least one of the following: In a vertical section perpendicular to the second direction, the inner diameter of the first electrode is equal to or greater than the outer diameter of the source and drain regions of the transistor. Within a vertical section perpendicular to the second direction, the cross-sectional shape of the first electrode is rectangular; The memory device further includes word lines extending along a first direction, the word lines including a plurality of gates corresponding one-to-one with the channel regions of the multilayer transistors stacked along the first direction. Along the third direction, gates are provided on both sides of the channel region of the transistor.

[0013] Thirdly, embodiments of this application provide an electronic device, including: A storage device manufactured using the storage device manufacturing method described above; or, Such as the storage devices mentioned above.

[0014] The beneficial technical effects of the technical solutions provided in this application include: In this embodiment, a first electrode, a first capacitor dielectric layer, and a second electrode are sequentially fabricated around the periphery of the third part (the first electrode, the first capacitor dielectric layer, and the second electrode form an outer capacitor), such that the size of the inner peripheral wall of the first electrode is the same as the size of the outer peripheral wall of the third part, and the size of the outer peripheral wall of the first electrode is larger than the size of the outer peripheral wall of the third part. The second electrode is insulated and wound around the periphery of the first electrode. Then, the third part is removed and replaced with a second capacitor dielectric layer and a third electrode that sequentially conformally cover the inner peripheral wall of the first electrode (the first electrode, the second capacitor dielectric layer, and the third electrode form an inner capacitor), such that the size of the outer peripheral wall of the second capacitor dielectric layer is the same as the size of the inner peripheral wall of the first electrode (i.e., the size of the outer peripheral wall of the third part), and the third electrode is insulated and arranged inside the first electrode.

[0015] Compared to related technologies that form the inner capacitor first and then the outer capacitor, in this embodiment, the outer peripheral wall of the first electrode is larger than the outer peripheral wall of the third portion, increasing the relative area between the second and first electrodes, thereby increasing the capacitance of the outer capacitor. In this embodiment, the inner peripheral wall of the first electrode is the same as the outer peripheral wall of the third portion. Compared to related technologies where the outer peripheral wall of the first electrode is equal to the outer peripheral wall of the semiconductor portion, this embodiment increases the relative area between the third and first electrodes, thereby increasing the capacitance of the inner capacitor. This embodiment, by forming the outer capacitor first and then the inner capacitor, can increase the capacitance of the capacitor.

[0016] Furthermore, in this embodiment, the outer capacitor is first fabricated based on the third part (the size of the outer peripheral wall of the first electrode is larger than the size of the outer peripheral wall of the third part, and the sizes of the first capacitor dielectric layer and the second electrode extend outward in sequence). Compared with related technologies that first fabricate the semiconductor part as the inner capacitor (the size of the outer peripheral wall of the first electrode is equal to the size of the outer peripheral wall of the semiconductor part), when the thickness of each corresponding film layer of the capacitor is the same, the outer peripheral wall size of the capacitor manufactured in this embodiment is larger, which can reduce the gap between two adjacent capacitors and improve the effective utilization rate of the gap between capacitors.

[0017] This application provides a method for manufacturing a storage device that increases capacitance by effectively utilizing the spacing between capacitors.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic flowchart illustrating a method for manufacturing a storage device according to an embodiment of this application; Figures 2 to 52 A schematic diagram of the structure of a method for manufacturing a storage device according to an embodiment of this application at different processes; Figure 53 A schematic diagram of the cross-sectional structure of a capacitor of a storage device provided in this application, on a vertical section perpendicular to a third direction; Figure 54 This is a schematic diagram of the cross-sectional structure of a capacitor of a storage device provided in an embodiment of this application, in a vertical section perpendicular to the second direction.

[0020] Figure label: 100 - Storage devices; 10-Substrate; 20 - First stacked structure; 21-First semiconductor layer; 211-First portion; 212-Second portion; 213-Third portion; 22-First dielectric layer; 221-First sub-dielectric layer; 222-Second sub-dielectric layer; 30-transistor; 31-Channel region; 32-First source / drain region; 33-Second source / drain region; 34-Initial gate insulating layer; 35-Conductive layer; 36-Gate insulating layer; 37-Gate; 40-bit line; 62 - Second Channel; 63 - Third Channel; 70- Capacitor; 71-First electrode; 72-First capacitor dielectric layer; 73-Second electrode; 74-Initial electrode layer; 76-Second capacitor dielectric layer; 77-Third electrode; 80 - Initial stacked structure; 81 - Initial semiconductor layer; 82 - First sacrificial layer; 91 - First groove; 92 - Second groove; 93 - Third groove; 94 - Fourth groove; 95 - Fifth groove; 96 - Sixth groove; 97 - Seventh groove; 101 - Second dielectric layer; 1011 - Third sub-dielectric layer; 1012 - Fourth sub-dielectric layer; 102 - Third dielectric layer; 1021 - Fifth sub-dielectric layer; 1022 - Sixth sub-dielectric layer; 103 - Fourth dielectric layer; 1031 - Ninth sub-dielectric layer; 1032 - Tenth sub-dielectric layer; 104 - Fifth dielectric layer; 1041 - First sublayer; 1042 - Second sublayer; 105 - Sixth dielectric layer; 1051 - Third sublayer; 1052 - Fourth sublayer; 106 - Seventh dielectric layer; 1061 - Fifth sublayer; 1062 - Sixth sublayer; 107 - Ninth dielectric layer; 1071 - Seventh sub-dielectric layer; 1072 - Eighth sub-dielectric layer; 108 - Eighth dielectric layer; 110-line; 120 - First mask structure; 121 - First isolation layer; 122 - First mask layer; 130 - Second mask structure; 131 - Second isolation layer; 132 - Second mask layer; 141 - First connection structure; 142 - Second connection structure. Detailed Implementation

[0021] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0022] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in the specification of this application means the presence of the stated features, integers, steps, operations, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" can be implemented as "A," or as "B," or as "A and B."

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0024] 3D DRAM (3 Dimension Dynamic Random Access Memory) is considered a potential solution for increasing storage density. A 3D DRAM memory cell consists of one transistor (1T, 1 Transistor) and one capacitor (1C, 1 Capacitor).

[0025] Currently, the spacing between capacitors in 3D DRAM is too large and the arrangement is too sparse, resulting in wasted area and low effective utilization.

[0026] The storage devices, manufacturing methods, and electronic devices provided in this application are intended to solve the aforementioned technical problems in the related art.

[0027] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, learned from, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0028] This application provides a method for manufacturing a storage device, and a flowchart of the method is shown below. Figure 1 As shown, the structural schematic diagrams of the manufacturing method of this storage device at different processes are as follows. Figures 2 to 52 As shown. The manufacturing method of this storage device includes: S101. A first stacked structure 20 is fabricated on the substrate 10. The first stacked structure 20 includes multiple first semiconductor layers 21 and multiple first dielectric layers 22 that are alternately distributed along a first direction perpendicular to the substrate 10. The first semiconductor layer 21 includes a first portion 211, a second portion 212 and a third portion 213 that are sequentially connected along a second direction. The first portion 211 extends along a third direction. The multiple second portions 212 and multiple third portions 213 are each distributed along a third direction and correspond one-to-one. The second direction and the third direction intersect and are both parallel to the substrate 10.

[0029] S102, Based on the second part 212, transistor 30 is fabricated.

[0030] S103, Replace the first part 211 with bit line 40.

[0031] S104. Remove the dielectric layer surrounding the third part 213.

[0032] S105. Fabricate a first electrode 71, a first capacitor dielectric layer 72, and a second electrode 73 that are sequentially wound around the periphery of the third part 213 in a cylindrical shape.

[0033] S106. Replace the third part 213 with the second capacitor dielectric layer 76 and the third electrode 77 that sequentially cover the inner peripheral wall of the first electrode 71 to obtain the capacitor 70.

[0034] In the embodiments of this application, such as Figures 2 to 16As shown, a first stacked structure 20 is first fabricated on a substrate 10. The first stacked structure 20 includes multiple first semiconductor layers 21 and multiple first dielectric layers 22 that are alternately distributed along a first direction. Each first semiconductor layer 21 includes a first portion 211, a plurality of second portions 212 that are connected to one of the first portions 211, and a plurality of third portions 213 that are connected to one of the plurality of second portions 212. The first portions 211, the second portions 212 and the third portions 213 are distributed along a second direction. The first portions 211 extend along a third direction, the plurality of second portions 212 are distributed along a third direction, and the plurality of third portions 213 are distributed along a third direction.

[0035] Next, as Figures 18 to 24 As shown, transistor 30 is fabricated based on the second portion 212. The first stacked structure 20 includes multiple first semiconductor layers 21 stacked on the substrate 10. Each first semiconductor layer 21 includes multiple second portions 212. By fabricating transistor 30 based on the second portions 212, a multilayer transistor 30 stacked on the substrate 10 can be obtained, and each transistor layer includes multiple transistors 30.

[0036] Next, as Figures 26 to 33 As shown, the first portion 211 is replaced with a bit line (BL) 40. The first stacked structure 20 includes multiple first semiconductor layers 21 stacked on the substrate 10. Each first semiconductor layer 21 includes at least one first portion 211 extending in a third direction. Replacing the first portion 211 with a bit line 40 can obtain multiple bit lines 40 stacked on the substrate 10, with each bit line including at least one bit line 40 extending in a third direction.

[0037] Next, as Figures 34 to 52 As shown, capacitor 70 is fabricated. Fabricating capacitor 70 includes: like Figures 34 to 38 As shown, the dielectric layer surrounding the third part 213 is removed, exposing the outer peripheral wall of the third part 213.

[0038] Next, as Figures 39 to 46 As shown, a first electrode 71, a first capacitor dielectric layer 72, and a second electrode 73 are sequentially arranged in a cylindrical shape around the periphery of the third part 213. The first electrode 71 conformally covers the outer peripheral wall of the third part 213, the first capacitor dielectric layer 72 conformally covers the first electrode 71, and the second electrode 73 conformally covers the first capacitor dielectric layer 72 and is insulated from the first electrode 71 through the first capacitor dielectric layer 72.

[0039] Next, as Figures 47 to 52As shown, the third part 213 is replaced by a second capacitor dielectric layer 76 and a third electrode 77 that sequentially conformally cover the inner peripheral wall of the first electrode 71, resulting in a capacitor 70. The second capacitor dielectric layer 76 conformally covers the inner peripheral wall of the first electrode 71, and the third electrode 77 conformally covers the second capacitor dielectric layer 76 and is insulated from the first electrode 71 through the second capacitor dielectric layer 76. The first electrode 71, the first capacitor dielectric layer 72 and the second electrode 73 located around the first electrode 71, and the second capacitor dielectric layer 76 and the third electrode 77 located inside the first electrode 71 constitute the capacitor 70.

[0040] In this embodiment, a first electrode 71, a first capacitor dielectric layer 72, and a second electrode 73 are sequentially fabricated around the third part 213 (the first electrode 71, the first capacitor dielectric layer 72, and the second electrode 73 form an outer capacitor), such that the size of the inner peripheral wall of the first electrode 71 is the same as the size of the outer peripheral wall of the third part 213, and the size of the outer peripheral wall of the first electrode 71 is larger than the size of the outer peripheral wall of the third part 213. The second electrode 73 is insulated and wound around the periphery of the first electrode 71. Then, the third part 213 is removed and replaced with a second capacitor dielectric layer 76 and a third electrode 77 sequentially conformally covering the inner peripheral wall of the first electrode 71 (the first electrode 71, the second capacitor dielectric layer 76, and the third electrode 77 form an inner capacitor), such that the size of the outer peripheral wall of the second capacitor dielectric layer 76 is the same as the size of the inner peripheral wall of the first electrode 71 (i.e., the size of the outer peripheral wall of the third part 213), and the third electrode 77 is insulated and arranged inside the first electrode 71.

[0041] Compared to related technologies where the outer peripheral wall of the first electrode and the outer peripheral wall of the semiconductor portion are the same size, and the inner peripheral wall of the first electrode (i.e., the outer peripheral wall of the inner capacitor dielectric layer) is smaller than the outer peripheral wall of the semiconductor portion, and then the outer capacitor is formed, with the inner peripheral wall of the outer capacitor dielectric layer having the same size as the outer peripheral wall of the first electrode (i.e., the outer peripheral wall of the semiconductor portion), in this embodiment, the outer peripheral wall of the first electrode 71 is larger than the outer peripheral wall of the third portion 213, increasing the relative area between the second electrode 73 and the first electrode 71, thereby increasing the capacitance of the outer capacitor. In this embodiment, the inner peripheral wall of the first electrode 71 has the same size as the outer peripheral wall of the third portion 213. Compared to related technologies where the outer peripheral wall of the first electrode is equal to the outer peripheral wall of the semiconductor portion, this embodiment increases the relative area between the third electrode 77 and the first electrode 71, thereby increasing the capacitance of the inner capacitor. This embodiment, by forming the outer capacitor first and then the inner capacitor, can increase the capacitance of the capacitor 70.

[0042] Furthermore, in this embodiment, the outer capacitor is first fabricated based on the third part 213 (the size of the outer peripheral wall of the first electrode 71 is larger than the size of the outer peripheral wall of the third part 213, and the sizes of the first capacitor dielectric layer 72 and the second electrode 73 extend outward sequentially). Compared with related technologies that first fabricate the semiconductor part as the inner capacitor (the size of the outer peripheral wall of the first electrode is equal to the size of the outer peripheral wall of the semiconductor part), when the thickness of each corresponding film layer of the capacitor is the same, the outer peripheral wall size of the capacitor 70 manufactured in this embodiment is larger, which can reduce the gap between two adjacent capacitors 70 and improve the effective utilization rate of the gap between capacitors.

[0043] This application provides a method for manufacturing a storage device that increases capacitance by effectively utilizing the spacing between capacitors.

[0044] This application embodiment uses the following example to illustrate how the manufacturing method of the storage device provided in this application can improve the capacitance of the capacitor 70. Optionally, it is assumed that before the capacitor is manufactured, the third part 213 is a cuboid structure with length, width, and height dimensions a, b, and L, respectively. The thickness of each electrode plate of the manufactured capacitor is 5 nm (this is only an example and can be manufactured in other dimensions), and the thickness of each capacitor dielectric layer is 5.5 nm (this is only an example and can be manufactured in other dimensions).

[0045] Below, we will estimate the size of each capacitor under the two capacitor manufacturing methods of the relevant technologies and embodiments of this application.

[0046] In related technologies, the inner layer capacitor is formed first, and then the outer layer capacitor is formed.

[0047] The capacitor area S1 is: S1 = 4 × (a + b - 21) × L. In this embodiment, the outer capacitor is formed first, and then the inner capacitor is formed.

[0048] The area of ​​the capacitor S2 is: S2 = 4 × (a + b - 1) × L.

[0049] Compared to the capacitor area S1 in related technologies, the percentage increase in capacitor area S2 of the capacitor 70 manufactured using the storage device manufacturing method provided in this application is: (S2-S1) / S1=20 / (a+b-21).

[0050] Wherein, the smaller a and b are, the greater the percentage increase. Compared with related technologies, the manufacturing method of the memory device provided in this application has a greater advantage in making the capacitor 70. Assuming that the sum of a and b is 103 nanometers (nm), the capacitor 70 made by the manufacturing method of the memory device provided in this application has a 30% larger capacitance than the capacitor made by the preparation method of related technologies.

[0051] Therefore, the capacitor 70 can be manufactured using the storage device manufacturing method provided in the embodiments of this application, which can increase the capacitance.

[0052] Optionally, such as Figure 3 As shown in the embodiment of this application, the second direction is perpendicular to the third direction. The second direction is parallel to the aa and cc directions. The third direction is parallel to the dd and ff directions.

[0053] In some optional embodiments of this application, such as Figures 2 to 16 As shown, a first stacked structure 20 is fabricated on the substrate 10, including: like Figure 2 As shown, an initial semiconductor layer 81 and a first sacrificial layer 82 are sequentially and alternately fabricated on one side of the substrate 10 to obtain an initial stacked structure 80.

[0054] Optionally, in this embodiment, the material of the initial semiconductor layer 81 includes, but is not limited to, silicon (Si). The material of the first sacrificial layer 82 includes, but is not limited to, silicon germanium (SiGe).

[0055] Optionally, such as Figure 2 As shown in this embodiment, an initial semiconductor layer 81 and a first sacrificial layer 82 are sequentially and alternately fabricated on one side of the substrate 10, including: SOI (Silicon-On-Insulator, i.e., silicon on insulating substrate 10) is fabricated, and the top layer of SOI silicon is thinned to the required thickness to obtain the first initial semiconductor layer 81.

[0056] Specifically, such as Figure 2 As shown in the embodiment of this application, an eighth dielectric layer 108 is formed between the first initial semiconductor layer 81 and the substrate 10. The eighth dielectric layer 108 is used to electrically isolate the substrate 10 from the subsequently formed conductive components (such as bit lines 40, transistors 30, capacitors 70, etc.).

[0057] Optionally, the material of the eighth dielectric layer 108 includes an insulating medium, which includes, but is not limited to, silicon oxide (such as SiO2).

[0058] Next, SiGe and Si are alternately grown on SOI using epitaxial growth technology to form an alternating multilayer first sacrificial layer 82 and other initial semiconductor layers 81 (excluding the first initial semiconductor layer 81), resulting in an initial stacked structure 80.

[0059] Next, as Figures 3 to 8 As shown (where, Figure 3 for Figure 5 The cross-sectional view along the center line (G), that is, a schematic diagram of the cross-section of the initial semiconductor layer 81 located on the cross-section parallel to the substrate 10. Figure 4 for Figure 5 The cross-sectional view in the middle hh direction (i.e., the cross-sectional schematic diagram of the layer where the first sacrificial layer 82 is located on the cross-section parallel to the substrate 10) forms multiple rows of first trenches 91 that penetrate the initial stacked structure 80 and are distributed along the second direction; each row of first trenches 91 includes multiple first trenches 91 distributed along the third direction.

[0060] In this embodiment, the first trench 91 penetrates the initial stacked structure 80, with the bottom of the first trench 91 exposing the eighth dielectric layer 108 and the sides exposing multiple initial semiconductor layers 81 and multiple first sacrificial layers 82. Multiple first trenches 91 are arranged in an array along the second direction and the third direction, forming a row of first trenches 91, and multiple rows of first trenches 91 are distributed along the second direction.

[0061] Optionally, in this embodiment of the application, shallow trench isolation (STI) technology is used to pattern the initial stacked structure 80 through the first mask structure 120 to obtain a plurality of first trenches 91 distributed in an array.

[0062] Optionally, such as Figures 3 to 8 As shown in the embodiment of this application, the plurality of first trenches 91 forming an array distribution include: A first isolation layer 121 and a first mask layer 122 are sequentially grown on the initial stacked structure 80 to obtain a first mask structure 120.

[0063] Next, photolithography is performed on the first mask structure 120 to give the first mask structure 120 a first preset pattern, and the shape and position of a plurality of first trenches 91 are defined by the first preset pattern.

[0064] Next, based on the first mask structure 120 with the first preset pattern, the initial stacked structure 80 is etched to expose the eighth dielectric layer 108 and form a plurality of first trenches 91.

[0065] Optionally, the material of the first isolation layer 121 includes, but is not limited to, oxide. The material of the first mask layer 122 includes, but is not limited to, nitride (such as silicon nitride, SiN). The first mask structure 120 can be a hard mask (HM).

[0066] It should be noted that, in this embodiment, the fabrication method of the first mask structure 120 and the first preset pattern can be the same as or similar to the conventional mask and pattern fabrication method in the art, and will not be described in detail here. After forming the first groove 91 using the first mask structure 120, the first mask structure 120 can be removed.

[0067] Next, as Figures 4 to 8As shown, a portion of the first sacrificial layer 82 is replaced with dielectric material through the first trench 91.

[0068] Optionally, such as Figures 4 to 8 As shown in this embodiment, the portion of the first sacrificial layer 82 exposed by the first trench 91 is removed, and dielectric material is filled at the corresponding location to form a first sub-dielectric layer 221. The first sub-dielectric layer 221 is located between two adjacent initial semiconductor layers 81 along the first direction, and can electrically isolate the two adjacent initial semiconductor layers 81.

[0069] Optionally, in this embodiment, the material of the first sub-dielectric layer 221 includes, but is not limited to, silicon oxide (such as SiO2). A portion of SiGe can be released and replaced with SiO2 to form isolation between units.

[0070] Next, as Figures 9 to 16 As shown (where, Figure 9 for Figure 11 The cross-sectional view along the center line (G), that is, a schematic diagram of the cross-section of the layer containing the first semiconductor layer 21 parallel to the cross-section of the substrate 10. Figure 10 for Figure 11 A cross-sectional view along the middle hh direction, that is, a schematic diagram of the cross section of the layer where the first dielectric layer 22 is located on the cross section parallel to the substrate 10; Figures 11 to 16 They are respectively Figure 9 (The cross-sectional views in the directions of aa, bb, cc, dd, ee, and ff are shown. Other figures in this document are similarly described and will not be repeated here.) This forms a plurality of second trenches 92 that penetrate the initial stacked structure 80, resulting in a first semiconductor layer 21. The plurality of second trenches 92 and the plurality of columns of first trenches 91 are alternately distributed along the second direction, and the second trenches 92 extend along the third direction.

[0071] In this embodiment, the second trench 92 penetrates the initial stacked structure 80. The bottom of the second trench 92 exposes the eighth dielectric layer 108, and the sides expose multiple layers of first semiconductor layer 21, multiple layers of first sub-dielectric layer 221, and multiple layers of remaining first sacrificial layer 82. A plurality of second trenches 92 are distributed along a second direction and each extends along a third direction. The plurality of second trenches 92 and multiple rows of first trenches 91 are alternately distributed in the second direction.

[0072] In this embodiment of the application, the initial semiconductor layer 81 is divided into a plurality of first semiconductor layers 21 distributed along the second direction by a plurality of second trenches 92 and a plurality of columns of first trenches 91 alternately distributed along the second direction. Along the second direction, each first semiconductor layer 21 includes a first portion 211, a second portion 212 and a third portion 213.

[0073] Optionally, such as Figure 9As shown in the embodiment of this application, the first groove 91 extends along the second direction, the second groove 92 extends along the third direction, and the extension directions of the first groove 91 and the second groove 92 are perpendicular to each other.

[0074] Optionally, in this embodiment of the application, STI technology is used to pattern the initial stacked structure 80 through the second mask structure 130 (including the second isolation layer 131 and the second mask layer 132) to obtain a plurality of second trenches 92.

[0075] It should be noted that, in the embodiments of this application, the process steps of the second mask structure 130 can be the same as or similar to the process steps of the first mask structure 120 (such as hard mask growth, photolithography, and etching), as long as the shape and position of the multiple second trenches 92 defined by the second preset pattern of the second mask structure 130 conform to the distribution relationship between the second trenches 92 and the first trenches 91 (such as multiple second trenches 92 and multiple rows of first trenches 91 being alternately distributed in the second direction, and the extension directions of the first trenches 91 and the second trenches 92 being perpendicular).

[0076] Optionally, such as Figures 9 to 13 As shown in the embodiments of this application, the method for manufacturing the memory device further includes, simultaneously with or after forming the second trench 92: Multiple seventh trenches 97 are formed, penetrating the initial stacked structure 80. The bottom of the seventh trench 97 exposes the eighth dielectric layer 108, and the side exposes the end face of the third portion 213 of the multilayer first semiconductor layer 21 away from the second portion 212. The multiple seventh trenches 97 are distributed along the second direction and each extends along the third direction. The seventh trenches 97 are located on the side of the first trench 91 away from the second trench 92.

[0077] Next, as Figure 10 , Figure 12 , Figure 14 and Figure 16 As shown, the remaining first sacrificial layer 82 is replaced with dielectric material through the second trench 92 to form the first dielectric layer 22, resulting in the first stacked structure 20.

[0078] Optionally, such as Figure 10 As shown in this embodiment, the portion of the first sacrificial layer 82 exposed by the second trench 92 and the seventh trench 97 is removed (after removing part of the first sacrificial layer 82 through the first trench 91, all remaining portions of the first sacrificial layer 82 are removed), and dielectric material is filled at the corresponding locations to form a second sub-dielectric layer 222. The first sub-dielectric layer 221 and the second sub-dielectric layer 222 form the first dielectric layer 22. Two adjacent initial semiconductor layers 81 along the first direction are electrically isolated through the first dielectric layer 22.

[0079] Optionally, in this embodiment, the material of the second sub-dielectric layer 222 includes, but is not limited to, silicon oxide (such as SiO2). The remaining SiGe can be released and replaced with SiO2 to achieve complete release and replacement of SiGe in the memory array region.

[0080] It should be noted that in this embodiment, a portion of the first sacrificial layer 82 is replaced with the first sub-dielectric layer 221, and the remaining portion of the first sacrificial layer 82 is replaced with the second sub-dielectric layer 222 to obtain the first dielectric layer 22. Of course, in other optional embodiments of this application, the first sacrificial layer 82 can be completely replaced at once to obtain the first dielectric layer 22, depending on actual needs. Optionally, a support layer is fabricated to support the initial semiconductor layer 81 before replacing the first sacrificial layer 82.

[0081] In some optional embodiments of this application, after fabricating the first stacked structure 20 on the substrate 10 and before fabricating the transistor 30 based on the second portion 212, the method of manufacturing the memory device further includes: like Figure 17 As shown, a second dielectric layer 101 is fabricated to fill the first trench 91.

[0082] Next, as Figure 17 As shown, a third dielectric layer 102 is fabricated to fill the second trench 92.

[0083] Optionally, such as Figure 17 As shown in the embodiments of this application, silicon oxide and polysilicon are filled to obtain a third sub-dielectric layer 1011 and a fourth sub-dielectric layer 1012 that conformally cover and fill the first trench 91, a fifth sub-dielectric layer 1021 and a sixth sub-dielectric layer 1022 that conformally cover and fill the second trench 92, and a seventh sub-dielectric layer 1071 and an eighth sub-dielectric layer 1072 that conformally cover and fill the seventh trench 97. The third sub-dielectric layer 1011 and the fourth sub-dielectric layer 1012 serve as the second dielectric layer 101, the fifth sub-dielectric layer 1021 and the sixth sub-dielectric layer 1022 serve as the third dielectric layer 102, and the seventh sub-dielectric layer 1071 and the eighth sub-dielectric layer 1072 serve as the ninth dielectric layer 107.

[0084] In some optional embodiments of this application, such as Figures 18 to 24 As shown (where, Figure 18 This is a schematic cross-sectional view of the layer containing the first semiconductor layer 21, parallel to the cross-section of the substrate 10. Figure 19 for Figure 20 A cross-sectional view along the center line, that is, a schematic diagram of the cross section of the layer containing the first semiconductor layer 21 on a cross section parallel to the substrate 10. Figure 21 This is a schematic cross-sectional view of the layer containing the channel region 31, parallel to the cross-section of the substrate 10. Figure 22 for Figure 23 A cross-sectional view along the center line, i.e., a schematic diagram of the cross section of the layer containing the channel region 31 on a cross section parallel to the substrate 10. Figure 24 (A schematic cross-section of the layer containing the channel region 31 on a cross-section parallel to the substrate 10). Based on the second part 212, transistor 30 is fabricated, including: like Figure 18 As shown, a third trench 93 is formed that penetrates the first stacked structure 20 and the second dielectric layer 101 and is located on both sides of the second portion 212 along the third direction; the third trench 93 exposes the multi-layer channel region 31.

[0085] In this embodiment, the third trench 93 penetrates the first laminated structure 20 and the second dielectric layer 101, and is located on both sides of the second portion 212 along the third direction. During the formation of the third trench 93, the middle section of the second portion 212 (the middle section of the second portion 212 along the second direction) is removed on both sides along the third direction. The part of the middle section of the second portion 212 that is not removed is used as the trench region 31. Therefore, the third trench 93 is formed on both sides of the trench region 31 along the third direction, and both sides of the trench region 31 along the third direction are exposed by the third trench 93.

[0086] The bottom of the third trench 93 exposes the eighth dielectric layer 108, and the sides expose the multi-layer channel region 31, the multi-layer first dielectric layer 22, and the second dielectric layer 101.

[0087] In this embodiment, a third groove 93 is formed, which is then opened, trimmed, and a channel area 31 is formed.

[0088] Next, as Figures 19 to 23 As shown, a word line 110, which is insulated from the channel area 31, is fabricated in the third trench 93.

[0089] In this embodiment, the word line (WL) 110 extends along the third trench 93 in a first direction and is located at least on the side of the third trench 93 facing the channel region 31. The word line 110 corresponds to and is insulated from the multilayer channel region 31 exposed by the third trench 93. The word line 110 includes multilayer gates 37 (the gates 37 are insulated from the channel regions 31) that correspond one-to-one with the multilayer channel regions 31. The word line 110 is formed on both sides of the channel region 31 along the third direction, that is, each channel region 31 has gates 37 on both sides along the third direction, and one channel region 31 corresponds to two gates 37.

[0090] Next, as Figure 24 As shown, the second portion 212 located on both sides of the channel region 31 along the second direction is respectively made into a first source-drain region 32 and a second source-drain region 33 to obtain a transistor 30.

[0091] In this embodiment, the second portion 212 includes a first end segment, a middle segment, and a second end segment connected sequentially along a second direction. The middle segment is penetrated by a third groove 93 on both sides along a third direction, forming a channel region 31. The first end segment is located between the channel region 31 and the first portion 211, and the second end segment is located between the channel region 31 and the third portion 213. The second portion 212 located on both sides of the channel region 31 along the second direction is the first end segment and the second end segment.

[0092] In this embodiment, the first and second end segments located on both sides of the channel region 31 along the second direction are each made into a first source-drain region 32 and a second source-drain region 33. The channel region 31, the first source-drain regions 32 and the second source-drain regions 33 located on both sides of the channel region 31 along the second direction, and the two gates 37 located on both sides of the channel region 31 along the third direction form a transistor 30. The transistor 30 has dual gates.

[0093] In some optional embodiments of this application, such as Figures 19 to 23 As shown, a word line 110 insulated from phase 31 of the channel region is fabricated within the third trench 93, including: like Figure 19 and Figure 20 As shown, an initial gate insulating layer 34, a conductive layer 35, and a fourth dielectric layer 103 are sequentially fabricated to conformally cover and fill the third trench 93.

[0094] Optionally, such as Figure 19 and Figure 20 As shown in the embodiment of this application, the fourth dielectric layer 103 includes a ninth sub-dielectric layer 1031 and a tenth sub-dielectric layer 1032. The ninth sub-dielectric layer 1031 conformally covers the conductive layer 35, and the tenth sub-dielectric layer 1032 fills the third trench 93.

[0095] Optionally, the material of the initial gate insulating layer 34 includes, but is not limited to, low-dielectric-constant gate oxide materials and high-dielectric-constant gate oxide materials, such as oxides (e.g., SiO2, HfO2). The material of the conductive layer 35 includes, but is not limited to, metals and their alloys, such as TiN, Ru, etc. The material of the ninth sub-dielectric layer 1031 includes, but is not limited to, nitrides (e.g., SiN). The material of the tenth sub-dielectric layer 1032 includes, but is not limited to, oxides, such as SiO2.

[0096] Optionally, gate oxide and metal materials are deposited sequentially to form an initial gate insulating layer 34 and a conductive layer 35. Finally, SiN and Oxide are filled to form a ninth sub-dielectric layer 1031 and a tenth sub-dielectric layer 1032, resulting in a fourth dielectric layer 103.

[0097] Next, as Figure 21As shown, a fourth trench 94 and a fifth trench 95 are fabricated on both sides of the initial gate insulating layer 34 along the second direction; the fourth trench 94 and the fifth trench 95 respectively expose the second portion 212 located on both sides of the channel region 31 along the second direction.

[0098] In this embodiment, the fourth trench 94 penetrates the second dielectric layer 101 and is located on both sides of the first end segment of the second portion 212 along a third direction. The fourth trench 94 exposes the first end segment of the multilayer second portion 212. The fifth trench 95 penetrates the second dielectric layer 101 and is located on both sides of the second end segment of the second portion 212 along a third direction. The fifth trench 95 exposes the second end segment of the multilayer second portion 212. The fourth trench 94 and the fifth trench 95 are located on both sides of the initial gate insulating layer 34 along a second direction. The fourth trench 94 exposes one sidewall of the initial gate insulating layer 34 along the second direction, and the fifth trench 95 exposes the other sidewall of the initial gate insulating layer 34 along the second direction.

[0099] Optionally, the third sub-dielectric layer 1011 and the fourth sub-dielectric layer 1012 are etched to form a fourth trench 94 and a fifth trench 95, opening up the regions corresponding to the fourth trench 94 and the fifth trench 95 to expose the initial gate insulating layer 34.

[0100] Next, as Figure 22 and Figure 23 As shown, the initial gate insulating layer 34 and the corresponding conductive layer 35 exposed in the fourth trench 94 and the fifth trench 95 are removed to obtain the gate insulating layer 36 and the word line 110.

[0101] In this embodiment, by removing the sidewalls of the initial gate insulating layer 34 exposed by the fourth trench 94 and the fifth trench 95 along the second direction, the initial gate insulating layer 34 can be broken in the third direction, resulting in two gate insulating layers 36 distributed along the third direction. The gate insulating layers 36 extend along the first direction.

[0102] After removing the initial gate insulating layer 34 exposed by the fourth trench 94 and the fifth trench 95, the corresponding conductive layer 35 is exposed. Removing this exposed portion of the conductive layer 35 breaks it in the third direction, resulting in two word lines 110 distributed along the third direction. The word lines 110 extend along the first direction and are insulated from the multilayer channel region 31 by the gate insulating layer 36. The multilayer transistors 30 stacked along the first direction share the word lines 110. The two word lines 110 (including the gate 37) located in the same third trench 93 are insulated by the fourth dielectric layer 103.

[0103] Word lines 110 are formed on both sides of the channel region 31 along the third direction, so that there are two gates 37 on both sides of the channel region 31 along the third direction. By removing the initial gate insulating layer 34 and the corresponding conductive layer 35 exposed in the fourth trench 94 and the fifth trench 95, a dual gate structure can be formed and the isolation of adjacent gates 37 in the same layer can be achieved.

[0104] In some optional embodiments of this application, such as Figure 24 As shown, the second portion 212 located on both sides of the channel region 31 along the second direction is respectively made into a first source / drain region 32 and a second source / drain region 33, including: By using the fourth trench 94 and the fifth trench 95, the second portion 212 located on both sides of the channel region 31 along the second direction is doped to obtain the first source / drain region 32 and the second source / drain region 33.

[0105] In this embodiment, the first end segment of the second part 212 is doped by the fourth trench 94 to obtain the first source / drain region 32; the second end segment of the second part 212 is doped by the fifth trench 95 to obtain the second source / drain region 33.

[0106] Alternatively, PSG (Phosphosilicate Glass) can be deposited using an atomic layer deposition (ALD) process, annealed, and then the PSG can be removed to form the first source / drain region 32 and the second source / drain region 33.

[0107] In some optional embodiments of this application, such as Figure 25 As shown ( Figure 25 (A schematic cross-sectional view of the layer containing the channel region 31 on a cross-section parallel to the substrate 10). After fabricating the transistor 30 based on the second portion 212 and before replacing the first portion 211 with the bit line 40, the method for manufacturing the memory device further includes: A fifth dielectric layer 104 and a sixth dielectric layer 105 are fabricated to fill the fourth trench 94 and the fifth trench 95, respectively. Adjacent first source-drain regions 32 in the same layer are electrically isolated through the fifth dielectric layer 104, and adjacent second source-drain regions 33 in the same layer are electrically isolated through the sixth dielectric layer 105.

[0108] Optionally, dielectric materials such as SiN and Oxide are filled to form a first sublayer 1041 and a second sublayer 1042 that conformally covers and fills the fourth trench 94, and a third sublayer 1051 and a fourth sublayer 1052 that conformally covers and fills the fifth trench 95. The first sublayer 1041 and the second sublayer 1042 serve as the fifth dielectric layer 104, and the third sublayer 1051 and the fourth sublayer 1052 serve as the sixth dielectric layer 105.

[0109] In some optional embodiments of this application, such as Figures 26 to 33 As shown (where, Figure 26 for Figure 27 A cross-sectional view along the center line, i.e., a schematic diagram of the cross section of the layer containing the channel region 31 on a cross section parallel to the substrate 10. Figure 30 for Figure 31 The cross-sectional view along the center line (i.e., a schematic cross-section of the layer containing the channel region 31 on a cross-section parallel to the substrate 10) replaces the first part 211 with the bit line 40, including: like Figures 26 to 28 As shown, the third dielectric layer 102 is removed, exposing the first portion 211 of the multilayer first semiconductor layer 21.

[0110] In this embodiment, the third dielectric layer 102 filled in the second trench 92 (including the removal of the sixth sub-dielectric layer 1022 and the inner fifth sub-dielectric layer 1021) is removed, opening the second trench 92 and exposing the first portion 211 of the multilayer first semiconductor layer 21.

[0111] Next, as Figures 26 to 29 As shown, the first portion 211 of the multilayer is removed to form a third channel 63. The shape and position of the third channel 63 correspond to the removed first portion 211. The third channel 63 exposes the first source-drain region 32.

[0112] Optionally, the multilayer first semiconductor layer 21 is laterally etched through the second trench 92 to remove the multilayer first portion 211 and expose the multilayer first source and drain regions 32.

[0113] Next, as Figures 30 to 33 As shown, a bit line 40 is fabricated within the third channel 63. Multiple bit lines 40 are distributed along a first direction and each extends along a third direction. Multiple first source / drain regions 32 distributed along the third direction are electrically connected to the same bit line 40, i.e., they share the bit line 40.

[0114] Optionally, before fabricating bit line 40, the manufacturing method of the memory device may further include depositing a metal material (such as nickel Ni, cobalt Co, titanium Ti, TiN, etc.) and annealing it to form silicide on the surface of the first source-drain region 32 as a second source-drain contact.

[0115] Optionally, fabricating bit lines 40 includes: sequentially depositing a metal or its alloy material (such as TiN) and polysilicon, wherein the metal material fills the third channel 63 and at least conformally covers the second trench 92, and the polysilicon at least covers (or even fills) the second trench 92; then, removing the polysilicon and metal material located in the second trench 92, cutting off the metal material filling the plurality of third channels 63, wherein the metal material in the third channel 63 forms bit lines 40, thereby disconnecting adjacent layer bit lines 40.

[0116] Optionally, the resulting multi-level bit line 40 is a staircase BL.

[0117] In some optional embodiments of this application, such as Figures 30 to 32 As shown, after replacing the first part 211 with bit line 40, the method of manufacturing the memory device further includes: Fabricate the seventh dielectric layer 106 to fill the second trench 92.

[0118] Optionally, liner SiN and silicon oxide are sequentially filled in the second trench 92 to form a fifth sublayer 1061 that conformally covers the second trench 92 and a sixth sublayer 1062 that conformally covers the fifth sublayer 1061 and fills the second trench 92. The fifth sublayer 1061 and the sixth sublayer 1062 form a seventh dielectric layer 106 as an isolation between adjacent bit lines 40.

[0119] In some optional embodiments of this application, such as Figures 34 to 38 As shown (where, Figure 34 for Figure 36 The cross-sectional view along the center line (GG) is a schematic diagram of the cross-section of the layer containing the channel region 31, parallel to the substrate 10. Figure 35 for Figure 36 A cross-sectional view along the middle hh direction, that is, a schematic diagram of the cross section of the layer where the first dielectric layer 22 is located on the cross section parallel to the substrate 10; Figure 36 and Figure 37 They are respectively Figure 35 Sectional views of bb and cc directions. Figure 38 for Figure 34 (The cross-sectional view in section ii, and the descriptions of other figures in this document are similar and will not be repeated here), removes the dielectric layer surrounding the third part 213, including: like Figure 34 , Figure 35 and Figure 38 As shown, along the third direction, the second dielectric layer 101 located on both sides of the third part 213 is removed to form the sixth trench 96.

[0120] In this embodiment, the sixth trench 96 penetrates the second dielectric layer 101, exposes the eighth dielectric layer 108 at the bottom, and exposes the third portion 213 of the multilayer first semiconductor layer 21 and the multilayer first dielectric layer 22 on the side. The sixth trench 96 is formed on both sides of the third portion 213 along the third direction, and the third portion 213 is exposed by the sixth trench 96 on both sides along the third direction.

[0121] Optionally, a sixth trench 96 is formed by etching the third sub-dielectric layer 1011 and the fourth sub-dielectric layer 1012, opening up the region corresponding to the sixth trench 96 and exposing the semiconductor material, such as Si, on both sides of the third portion 213 along the third direction.

[0122] Next, as Figures 35 to 37 As shown, along the first direction, the first dielectric layer 22 located on both sides of the third part 213 is removed to form the second channel 62.

[0123] In this embodiment, the third portion 213 has second channels 62 formed on both sides along the first direction, and both sides of the third portion 213 along the first direction are exposed by the second channels 62. By forming the sixth groove 96 and the second channels 62, the sidewalls of the third portion 213 along both the third direction and the first direction are exposed, that is, the outer peripheral walls of the third portion 213 are exposed.

[0124] In some optional embodiments of this application, such as Figures 39 to 46 As shown (where, Figure 39 for Figure 40 A cross-sectional view along the center line, i.e., a schematic diagram of the cross section of the layer containing the channel region 31 on a cross section parallel to the substrate 10. Figure 43 for Figure 44 A cross-sectional view along the middle section (i.e., a schematic cross-section of the layer containing the channel region 31 on a cross section parallel to the substrate 10), comprising a first electrode 71, a first capacitor dielectric layer 72, and a second electrode 73 sequentially arranged in a cylindrical shape around the periphery of the third part 213, including: like Figures 39 to 46 As shown, an initial electrode layer 74, a first capacitor dielectric layer 72, and a second electrode 73 are sequentially fabricated around the outer periphery of the third part 213 and conformally cover the second channel 62 and the sixth trench 96.

[0125] In this embodiment, the initial electrode layer 74 conformally covers the outer peripheral wall of the third part 213, the inner wall of the second channel 62 and the sixth trench 96, the first capacitor dielectric layer 72 conformally covers the initial electrode layer 74, and the second electrode 73 conformally covers the first capacitor dielectric layer 72.

[0126] like Figures 43 to 46 As shown, along the second direction, the initial electrode layer 74 that conformally covers the side walls of the second channel 62 and the sixth trench 96 is removed to obtain the first electrode 71.

[0127] In this embodiment, after the initial electrode layer 74 that conformally covers the sidewalls of the second channel 62 and the sixth trench 96 is removed, the remaining initial electrode layer 74 that conformally covers the outer peripheral wall of the third portion 213 serves as the first electrode 71. The first electrode 71 is electrically connected to the second source-drain region 33 of the transistor 30, and the first capacitor dielectric layer 72 electrically isolates the second electrode 73 from the first electrode 71, thus insulating the second electrode 73 from the first electrode 71.

[0128] Optionally, in this embodiment, the step of removing the initial electrode layer 74 that conformally covers the side walls of the second channel 62 and the sixth trench 96 can be performed after fabricating the initial electrode layer 74, the first capacitor dielectric layer 72, and the second electrode 73. Optionally, a portion of the first dielectric layer 22 and the ninth dielectric layer 107 on both sides of the second channel 62 along the second direction are each removed, and a portion of the sixth dielectric layer 105 and the ninth dielectric layer 107 on both sides of the sixth trench 96 along the second direction are each removed, exposing the initial electrode layer 74 on both sides of the second channel 62 and the sixth trench 96 along the second direction; removing the exposed initial electrode layer 74 yields the first electrode 71.

[0129] Optionally, such as Figures 43 to 46 As shown in the embodiment of this application, after fabricating the first electrode 71, the first capacitor dielectric layer 72, and the second electrode 73, the method for manufacturing the memory device further includes: fabricating a first connection structure 141, which is electrically connected to the second electrode 73, and the first connection structure 141 is used to realize the electrical connection between the outer layer capacitor of the capacitor 70 and the external device.

[0130] Optionally, in this embodiment, TiN, a high-k material (i.e., a high-dielectric-constant material, including dielectrics with a dielectric constant k greater than or equal to 3.9), TiN, and W are deposited sequentially to form an initial electrode layer 74, a first capacitor dielectric layer 72, a second electrode 73, and a first connection structure 141 of a pillar structure. Next, the first dielectric layer 22 and the ninth dielectric layer 107 along both sides of the second channel 62 in the second direction, and the sixth dielectric layer 105 and the ninth dielectric layer 107 along both sides of the sixth trench 96 in the second direction are etched, opening up the regions along both sides of the second channel 62 and the sixth trench 96 in the second direction, exposing the initial electrode layer 74 along both sides of the second channel 62 and the sixth trench 96 in the second direction; then, the exposed initial electrode layer 74 is etched to cut off the first electrodes 71, thus disconnecting each first electrode 71.

[0131] Of course, in other optional embodiments of this application, the step of removing the initial electrode layer 74 that conformally covers the side walls of the second channel 62 and the sixth trench 96 can also be performed after the initial electrode layer 74 is fabricated and before the first capacitor dielectric layer 72 and the second electrode 73 are fabricated. Optionally, after fabricating the initial electrode layer 74, a second sacrificial layer is fabricated to cover the initial electrode layer 74 and fill the second channel 62 and the sixth trench 96; then, the second sacrificial layer and the initial electrode layer 74 in the second channel 62 and the sixth trench 96 are removed, and the remaining initial electrode layer 74 covering the outer peripheral wall of the third portion 213 serves as the first electrode 71. After obtaining the first electrode 71, the first capacitor dielectric layer 72, the second electrode 73, and the first connection structure 141 are fabricated.

[0132] In some optional embodiments of this application, such as Figures 47 to 52 As shown (where, Figure 47 This is a schematic diagram of a cross-section of the layer containing the channel region 31, parallel to the cross-section of the substrate 10. Figure 50 (This is a schematic cross-section of the layer containing the channel region 31 on a cross-section parallel to the substrate 10). The third part 213 is replaced by a second capacitor dielectric layer 76 and a third electrode 77 that sequentially conformally cover the inner peripheral wall of the first electrode 71, including: like Figures 47 to 49 As shown, along the second direction, the dielectric layer on the side of the third portion 213 away from the transistor 30 is removed, exposing the third portion 213.

[0133] Optionally, such as Figure 47 and Figure 48 As shown in the embodiment of this application, at least a portion of the ninth dielectric layer 107 along both sides of the second direction is removed (either a portion of the ninth dielectric layer 107 along both sides of the second direction or all of the ninth dielectric layer 107 can be removed), exposing the two side walls of the seventh trench 97 along the second direction, thereby exposing the third portion 213 located on both sides of the seventh trench 97 along the second direction, so as to facilitate the subsequent removal of the third portion 213.

[0134] Next, as Figures 47 to 49 As shown, the third portion 213 is removed to form the third channel 63. The third channel 63 exposes the second source-drain region 33 of the transistor 30 and the inner peripheral wall of the first electrode 71.

[0135] Next, as Figures 50 to 52 As shown, a second capacitor dielectric layer 76 and a third electrode 77 are sequentially fabricated to conformally cover the third channel 63. The second capacitor dielectric layer 76 conformally covers the inner peripheral walls of the second source / drain region 33 and the first electrode 71, and the third electrode 77 conformally covers the second capacitor dielectric layer 76. The third electrode 77 is electrically isolated from the second source / drain region 33 and the first electrode 71 through the second capacitor dielectric layer 76.

[0136] In some optional embodiments of this application, such as Figures 50 to 52 As shown, after fabricating the third electrode 77, the method for manufacturing the memory device further includes: fabricating a second connection structure 142, which is electrically connected to the third electrode 77, and the second connection structure 142 is used to realize the electrical connection between the inner layer capacitor of the capacitor 70 and the external device.

[0137] Optionally, in this embodiment, high-k material, Ti, and W are deposited sequentially, and planarization (stopping on SiN) is performed using chemical mechanical polishing (CMP) to obtain a second capacitor dielectric layer 76, a third electrode 77, and a second connection structure 142, thereby forming a cylinder structure capacitor 70. In this embodiment, a bottom electrode (i.e., a first electrode 71), a high-k material (as a first capacitor dielectric layer 72), and a top electrode (i.e., a second electrode 73) are deposited on a silicon pillar (i.e., the third part 213) to form an outer layer capacitor; then, the side is opened, and the horizontal silicon pillar is hollowed out (to obtain a third channel 63), and a high-k material (as a second capacitor dielectric layer 76) and a top electrode (i.e., a third electrode 77) are deposited to form an inner layer capacitor, thereby obtaining the capacitor 70.

[0138] This application provides a method for manufacturing a storage device in which an outer layer capacitor of a cylinder type capacitor is first fabricated, and then an inner layer capacitor of a cylinder type capacitor is fabricated. This method can effectively utilize the spacing between capacitors and increase the capacitance.

[0139] This application provides a method for manufacturing a Cylinder-type capacitor structure, which can be applied to the field of semiconductor device fabrication for fabricating memory cell structures; further, it can be applied to the field of 3D DRAM device fabrication to increase the cylinder capacitance of 3D DRAM.

[0140] Based on the same inventive concept, this application provides a storage device 100, the structural schematic diagram of which is shown below. Figures 50 to 52 As shown, the memory device 100 includes: a multilayer device layer stacked on the substrate 10 along a first direction; the device layer includes bit lines 40, a plurality of transistors 30, and a plurality of capacitors 70.

[0141] Bit line 40, transistor 30 and capacitor 70 are electrically connected sequentially along the second direction.

[0142] Bit line 40 extends along a third direction, and multiple transistors 30 and multiple capacitors 70 are distributed along the third direction and correspond one-to-one.

[0143] The capacitor 70 includes a first electrode 71, which is cylindrical and extends along a second direction.

[0144] The first capacitor dielectric layer 72 and the second electrode 73 are sequentially arranged around the periphery of the first electrode 71.

[0145] The second capacitor dielectric layer 76 and the third electrode 77 sequentially cover the inner peripheral wall of the first electrode 71 in a conformal manner.

[0146] In this embodiment, the multilayer device layers stacked on the substrate 10 form a second stacked structure. The substrate 10 is used to support the second stacked structure.

[0147] In this embodiment, multiple bit lines 40 are distributed along a first direction and each extends along a third direction. Multiple transistors 30 in the device layer are distributed along the third direction and electrically connected to the same bit line 40 (i.e., sharing the bit line 40). The transistors 30 are located on one side of the bit line 40 along a second direction, and the capacitors 70 are located on the side of the transistors 30 away from the bit line 40. Multiple capacitors 70 in the device layer are distributed along the third direction and connected one-to-one with each of the multiple transistors 30.

[0148] like Figure 53 and Figure 54 As shown, capacitor 70 includes a first electrode 71 extending along a second direction and in a cylindrical shape, a first dielectric layer 72 and a second electrode 73 sequentially surrounding the first electrode 71, and a second dielectric layer 76 and a third electrode 77 sequentially conformally covering the inner peripheral wall of the first electrode 71. The first electrode 71 is electrically connected to a source-drain region (such as a second source-drain region 33) of transistor 30. The first electrode 71, the first dielectric layer 72, and the second electrode 73 constitute the outer layer capacitor, and the first electrode 71, the second dielectric layer 76, and the third electrode 77 constitute the inner layer capacitor.

[0149] Compared to traditional capacitors (which include two insulated plates), in this embodiment of the application, the first electrode 71 is surrounded by a second electrode 73 that is insulated from the first electrode 71, and the first electrode 71 is surrounded by a third electrode 77 that is insulated from the first electrode 71. By setting the outer layer capacitor and the inner layer capacitor, the capacitance of the capacitor 70 can be increased.

[0150] It should be noted that the storage devices of this application embodiment can be manufactured using the manufacturing method of the storage device provided in the embodiments of this application. Since the storage devices of this application embodiment can be manufactured using the manufacturing method of the storage device provided in the embodiments of this application, the storage devices of this application embodiment also have the above-mentioned beneficial effects of the manufacturing method of the storage device provided in the embodiments of this application, which will not be repeated here.

[0151] In some optional embodiments of this application, in a vertical cross-section perpendicular to the second direction, the inner diameter of the first electrode 71 is equal to or greater than the outer diameter of the source-drain region of the transistor 30. This allows the outer peripheral wall of the first electrode 71 to have a larger dimension than the outer diameter of the source-drain region of the transistor 30.

[0152] Compared to related technologies where the outer peripheral wall size of the first electrode is equal to or smaller than the outer peripheral wall size of the source and drain regions of the transistor (the inner diameter of the first electrode is smaller), in the embodiments of this application, the relative area between the outer peripheral wall of the first electrode 71 and the second electrode 73 is larger, resulting in a larger capacitance of the outer layer capacitor. The relative area between the inner peripheral wall of the first electrode 71 and the third electrode 77 is also larger, resulting in a larger capacitance of the inner layer capacitor, thereby increasing the capacitance of the capacitor 70.

[0153] In some optional embodiments of this application, such as Figure 54 As shown, in a vertical section perpendicular to the second direction, the cross-sectional shape of the first electrode 71 is rectangular. This arrangement facilitates processing and manufacturing.

[0154] Of course, in other optional embodiments of this application, the cross-sectional shape of the first electrode 71 in the vertical section perpendicular to the second direction can be set to other regular or irregular shapes other than rectangles, such as square, circle, ellipse, etc., depending on the actual situation.

[0155] In some optional embodiments of this application, such as Figure 37 As shown, the memory device 100 also includes word lines 110 extending along a first direction, the word lines 110 including a plurality of gates 37 corresponding one-to-one with the channel regions 31 of the multilayer transistors 30 stacked along the first direction.

[0156] In this embodiment, the multilayer transistors 30 stacked along the first direction share a word line 110, which can reduce the number of traces and is beneficial for layout design, increasing device density and practicality.

[0157] In some optional embodiments of this application, such as Figure 50 As shown, along the third direction, gates 37 are provided on both sides of the channel region 31 of transistor 30. Transistor 30 has dual gates and strong gate control capability.

[0158] This application provides a cylinder capacitor structure that can be applied to the field of semiconductor devices, and further to the field of 3D DRAM devices.

[0159] Based on the same inventive concept, embodiments of this application provide an electronic device, which includes: a memory device manufactured using the memory device manufacturing method described above; or, a memory device 100 as described above.

[0160] It should be noted that since the electronic devices in the embodiments of this application include storage devices manufactured using the storage device manufacturing method provided in the embodiments of this application or storage devices in the embodiments of this application, the electronic devices in the embodiments of this application also have the above-mentioned beneficial effects of the storage device manufacturing method provided in the embodiments of this application or storage devices in the embodiments of this application, which will not be repeated here.

[0161] In some optional embodiments of this application, the electronic device includes a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include, for example, memory in a computer, and is not limited thereto.

[0162] By applying the embodiments of this application, at least the following beneficial effects can be achieved: In this embodiment, a first stacked structure is first fabricated on a substrate. The first stacked structure includes multiple first semiconductor layers and multiple first dielectric layers that are alternately distributed along a first direction. Each first semiconductor layer includes a first part, a plurality of second parts corresponding to and connected to one of the first parts, and a plurality of third parts corresponding to and connected to the plurality of second parts. The first part, the second part, and the third part are distributed along a second direction. The first part extends along a third direction, the plurality of second parts are distributed along a third direction, and the plurality of third parts are distributed along a third direction.

[0163] Next, transistors are fabricated based on the second part. The first stacked structure includes multiple first semiconductor layers stacked on a substrate, each first semiconductor layer including multiple second parts. By fabricating transistors based on the second parts, multilayer transistors stacked on the substrate can be obtained, and each transistor layer includes multiple transistors.

[0164] Next, the first portion is replaced with a bit line. The first stacked structure includes multiple first semiconductor layers stacked on a substrate, each first semiconductor layer including at least one first portion extending in a third direction. Replacing the first portion with a bit line yields multiple bit lines stacked on the substrate, each bit line including at least one bit line extending in a third direction.

[0165] Next, the capacitor is made. Making a capacitor includes: The dielectric layer surrounding the third part is removed, exposing the outer peripheral wall of the third part.

[0166] Next, a first electrode, a first capacitor dielectric layer, and a second electrode are sequentially fabricated and wound around the periphery of the third part in a cylindrical shape. The first electrode conformally covers the outer peripheral wall of the third part, the first capacitor dielectric layer conformally covers the first electrode, and the second electrode conformally covers the first capacitor dielectric layer and is insulated from the first electrode through the first capacitor dielectric layer.

[0167] Next, the third part is replaced by a second dielectric layer and a third electrode that conformally cover the inner peripheral wall of the first electrode, thus obtaining a capacitor. The second dielectric layer conformally covers the inner peripheral wall of the first electrode, and the third electrode conformally covers the second dielectric layer and is insulated from the first electrode through the second dielectric layer. The first electrode, the first dielectric layer and the second electrode located around the first electrode, and the second dielectric layer and the third electrode located inside the first electrode constitute the capacitor.

[0168] In this embodiment, a first electrode, a first capacitor dielectric layer, and a second electrode are sequentially fabricated around the periphery of the third part (the first electrode, the first capacitor dielectric layer, and the second electrode form an outer capacitor), such that the size of the inner peripheral wall of the first electrode is the same as the size of the outer peripheral wall of the third part, and the size of the outer peripheral wall of the first electrode is larger than the size of the outer peripheral wall of the third part. The second electrode is insulated and wound around the periphery of the first electrode. Then, the third part is removed and replaced with a second capacitor dielectric layer and a third electrode that sequentially conformally cover the inner peripheral wall of the first electrode (the first electrode, the second capacitor dielectric layer, and the third electrode form an inner capacitor), such that the size of the outer peripheral wall of the second capacitor dielectric layer is the same as the size of the inner peripheral wall of the first electrode (i.e., the size of the outer peripheral wall of the third part), and the third electrode is insulated and arranged inside the first electrode.

[0169] Compared to related technologies that form the inner capacitor first and then the outer capacitor, in this embodiment, the outer peripheral wall of the first electrode is larger than the outer peripheral wall of the third portion, increasing the relative area between the second and first electrodes, thereby increasing the capacitance of the outer capacitor. In this embodiment, the inner peripheral wall of the first electrode is the same as the outer peripheral wall of the third portion. Compared to related technologies where the outer peripheral wall of the first electrode is equal to the outer peripheral wall of the semiconductor portion, this embodiment increases the relative area between the third and first electrodes, thereby increasing the capacitance of the inner capacitor. This embodiment, by forming the outer capacitor first and then the inner capacitor, can increase the capacitance of the capacitor.

[0170] Furthermore, in this embodiment, the outer capacitor is first fabricated based on the third part (the size of the outer peripheral wall of the first electrode is larger than the size of the outer peripheral wall of the third part, and the sizes of the first capacitor dielectric layer and the second electrode extend outward in sequence). Compared with related technologies that first fabricate the semiconductor part as the inner capacitor (the size of the outer peripheral wall of the first electrode is equal to the size of the outer peripheral wall of the semiconductor part), when the thickness of each corresponding film layer of the capacitor is the same, the outer peripheral wall size of the capacitor manufactured in this embodiment is larger, which can reduce the gap between two adjacent capacitors and improve the effective utilization rate of the gap between capacitors.

[0171] This application provides a method for manufacturing a storage device that increases capacitance by effectively utilizing the spacing between capacitors.

[0172] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0173] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0174] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A method for manufacturing a storage device, characterized in that, include: A first stacked structure is fabricated on a substrate; the first stacked structure includes multiple first semiconductor layers and multiple first dielectric layers alternately distributed along a first direction perpendicular to the substrate, the first semiconductor layer includes a first part, a second part and a third part connected sequentially along a second direction, the first part extends along a third direction, a plurality of second parts and a plurality of third parts are each distributed along the third direction and correspond one-to-one, the second direction and the third direction intersect and are both parallel to the substrate. Based on the second part, transistors are fabricated; Replace the first part with a bit line; Remove the dielectric layer surrounding the third part; A first electrode, a first capacitor dielectric layer, and a second electrode are sequentially wound around the periphery of the third part in a cylindrical shape. The third part is replaced by a second capacitor dielectric layer and a third electrode that sequentially conformally cover the inner peripheral wall of the first electrode to obtain a capacitor.

2. The method for manufacturing a storage device according to claim 1, characterized in that, Fabricating a first stacked structure on a substrate includes: An initial semiconductor layer and a first sacrificial layer are sequentially and alternately fabricated on one side of the substrate to obtain an initial stacked structure; Multiple rows of first trenches are formed that penetrate the initial stacked structure and are distributed along the second direction; each row of first trenches includes multiple first trenches distributed along the third direction; The first sacrificial layer is partially replaced with dielectric material through the first trench; A plurality of second trenches are formed through the initial stacked structure to obtain the first semiconductor layer; the plurality of second trenches and the plurality of columns of first trenches are alternately distributed along the second direction, and the second trenches extend along the third direction; The remaining first sacrificial layer is replaced with dielectric material through the second trench to form the first dielectric layer, thus obtaining the first stacked structure. And, after fabricating the first stacked structure on the substrate and before fabricating the transistor based on the second portion, the method further includes: Fabricate a second dielectric layer to fill the first trench; A third dielectric layer is fabricated to fill the second trench.

3. The method for manufacturing a storage device according to claim 2, characterized in that, Based on the second part, transistors are fabricated, including: A third trench is formed, penetrating the first stacked structure and the second dielectric layer, and located on both sides of the second portion along the third direction; the third trench exposes a multi-layer channel region; Insulation lines are fabricated within the third trench to be insulated from the trench area; The transistor is obtained by fabricating the second portion located on both sides of the channel region along the second direction into a first source-drain region and a second source-drain region.

4. The method for manufacturing a storage device according to claim 3, characterized in that, Fabricating word lines insulated from the channel region within the third trench includes: An initial gate insulating layer, a conductive layer, and a fourth dielectric layer are sequentially fabricated to conformally cover and fill the third trench; A fourth trench and a fifth trench are fabricated on both sides of the initial gate insulating layer along the second direction; the fourth trench and the fifth trench each expose a second portion located on both sides of the channel region along the second direction; Remove the initial gate insulating layer and the corresponding conductive layer exposed in the fourth trench and the fifth trench to obtain the gate insulating layer and the word line; And, the second portion located on both sides of the channel region along the second direction is respectively formed into a first source / drain region and a second source / drain region, including: By using the fourth trench and the fifth trench, the second portion located on both sides of the channel region along the second direction is doped to obtain the first source / drain region and the second source / drain region.

5. The method for manufacturing a storage device according to claim 2, characterized in that, Replace the first part with bit lines, including: Remove the third dielectric layer to expose a first portion of the multilayer first semiconductor layer; Remove the first part of the multi-layer structure to form the first multi-layer channel; The bit line is fabricated within the first channel.

6. The method for manufacturing a storage device according to claim 2, characterized in that, Removing the dielectric layer surrounding the third part includes: Along the third direction, the second dielectric layer located on both sides of the third part is removed to form the sixth trench; Along the first direction, the first dielectric layer located on both sides of the third part is removed to form a second channel; And, fabricating a first electrode, a first capacitor dielectric layer, and a second electrode that are sequentially arranged in a cylindrical shape around the periphery of the third part, including: An initial electrode layer, a first capacitor dielectric layer, and a second electrode are sequentially fabricated, which are wound around the outer periphery of the third part and conformally cover the second channel and the sixth trench. Along the second direction, the initial electrode layer that conformally covers the side walls of the second channel and the sixth trench is removed to obtain the first electrode.

7. The method for manufacturing a storage device according to claim 2, characterized in that, The third part is replaced by a second capacitor dielectric layer and a third electrode that sequentially conformally cover the inner peripheral wall of the first electrode, including: Along the second direction, the dielectric layer located on the side of the third portion away from the transistor is removed, exposing the third portion; Remove the third part to form a third channel; The second capacitor dielectric layer and the third electrode, which conformally cover the third channel, are fabricated sequentially.

8. A storage device, characterized in that, The device includes a multilayer device layer stacked on a substrate along a first direction; the device layer includes bit lines, a plurality of transistors, and a plurality of capacitors. The bit line, the transistor, and the capacitor are electrically connected sequentially along the second direction; The bit line extends along a third direction, and the plurality of transistors and the plurality of capacitors are each distributed along the third direction and correspond one-to-one; The capacitor includes: a first electrode, which is cylindrical and extends along the second direction; The first capacitor dielectric layer and the second electrode are sequentially arranged around the periphery of the first electrode; The second capacitor dielectric layer and the third electrode sequentially conformally cover the inner peripheral wall of the first electrode.

9. The storage device according to claim 8, characterized in that, Includes at least one of the following: In a vertical section perpendicular to the second direction, the inner diameter of the first electrode is equal to or greater than the outer diameter of the source and drain regions of the transistor. In a vertical section perpendicular to the second direction, the cross-sectional shape of the first electrode is rectangular; The memory device further includes word lines extending along the first direction, the word lines including a plurality of gates corresponding one-to-one with the channel regions of the multilayer transistors stacked along the first direction. Along the third direction, gates are provided on both sides of the channel region of the transistor.

10. An electronic device, characterized in that, include: A memory device manufactured using the manufacturing method of any one of claims 1 to 7; or, The storage device as described in claim 8 or 9.

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