Semiconductor device and method of manufacturing the same, storage system

Abstract

The application discloses a semiconductor device, a preparation method thereof, and a storage system. The semiconductor device comprises a gate assembly, an isolation structure, a gate cut structure, and a plurality of semiconductor bodies. The gate assembly extends along a first direction and comprises two gate structures arranged opposite to each other in a second direction. The isolation structure is alternately distributed with the gate assembly in the second direction and extends along the first direction. The plurality of semiconductor bodies are located between adjacent gate assemblies and isolation structures in the second direction and extend along a third direction. The gate cut structure is located at two ends of the gate structure. In a direction intersecting the third direction, end portions of the two gate structures of the gate assembly respectively extend to the gate cut structure. One or more semiconductor bodies are located on a side of the gate assembly away from the gate cut structure in the second direction. The first direction, the second direction, and the third direction intersect with each other in pairs.

Description

Technical Field

[0001] The embodiments of this application relate to the field of semiconductor technology, and in particular to semiconductor devices and their fabrication methods and storage systems. Background Technology

[0002] Semiconductor devices are memory devices used to store information in modern information technology. Their main function is to store programs and various data, and to perform high-speed and automatic access to programs or data during computer operation. Taking DRAM (Dynamic Random Access Memory) as an example, DRAM typically includes multiple memory cells. Each memory cell includes a transistor and a capacitor structure. One end of the transistor is connected to the capacitor structure, and the other end of the transistor is connected to a bit line.

[0003] Currently, how to further improve the performance of semiconductor devices is one of the technical problems that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a semiconductor device, a method for fabricating the same, and a storage system.

[0005] The first aspect of this application provides a semiconductor device including a gate assembly, an isolation structure, a gate notch structure, and a plurality of semiconductor bodies. The gate assembly extends along a first direction and includes two gate structures disposed opposite each other in a second direction. The isolation structure and the gate assembly are alternately distributed in the second direction and extend along the first direction. The plurality of semiconductor bodies are located between adjacent gate assemblies and isolation structures in the second direction and extend along a third direction. The gate notch structure is located at both ends of the gate structure. In the direction intersecting with the third direction, the ends of the two gate structures of the gate assembly extend to the gate notch structure, respectively. One or more semiconductor bodies are located on the side of the gate assembly away from the gate notch structure in the second direction. The first direction, the second direction, and the third direction intersect each other.

[0006] In some implementations, the gate cutout structure extends along a second direction to an adjacent isolation structure on the side opposite to the gate assembly.

[0007] In some implementations, the semiconductor body and the gate cutout structure have the same dimensions at their adjacent ends in a third-direction orientation along a first direction.

[0008] In some embodiments, a portion of the semiconductor bodies and the gate cutout structure are spaced apart in a second direction, while another portion of the semiconductor bodies are located on one side of the gate cutout structure in a first direction.

[0009] In some embodiments, the gate cutout structure includes a first sub-part and a second sub-part, the first sub-part extending along a third direction, the second sub-part located on one side of the first sub-part in the third direction, at least a portion of the second sub-part located on the side of the first sub-part away from the adjacent isolation structure in a second direction, and the size of the first sub-part in the second direction being larger than the size of the second sub-part in the second direction.

[0010] In some implementations, the second sub-part bends in a direction away from the adjacent isolation structure in a second direction.

[0011] In some embodiments, one end of the gate cutout structure along a third direction has a first dimension in the first direction, and the other portions of the gate cutout structure have dimensions greater than or equal to the first dimension in the first direction.

[0012] In some implementations, the dimension of the gate notch structure in the third direction is larger than the dimension of the gate structure in the third direction.

[0013] In some embodiments, the gate notch structure includes a sub-notch structure and a first dielectric layer, the sub-notch structure penetrating the gate assembly along a first direction, and the first dielectric layer being located at least on a sidewall of the sub-notch structure extending along a third direction.

[0014] In some embodiments, the gate assembly further includes a gate isolation layer located between the two gate structures in a second direction, and a gate notch structure located on the side of the gate isolation layer opposite to the semiconductor body in the second direction.

[0015] In some embodiments, the gate structure includes a gate layer and a gate dielectric layer, wherein the gate layer is located in a second direction on the side of the semiconductor body away from the isolation structure and extends along a first direction, and the gate dielectric layer is located in the second direction on the side of the gate layer facing the semiconductor body.

[0016] In some embodiments, the gate dielectric layer includes a plurality of sub-dielectric layers spaced apart in a first direction, the sub-dielectric layers being located between the semiconductor body and the gate layer in a second direction.

[0017] A second aspect of this application provides a method for fabricating a semiconductor device, the method comprising: forming a plurality of initial semiconductor bodies and an initial isolation structure extending along a first direction; forming an initial gate structure extending along the first direction, wherein the initial isolation structure and the initial gate structure are alternately distributed in a second direction, and the initial semiconductor bodies are located between adjacent initial gate structures and initial isolation structures and extend along a third direction in the second direction; forming two gate cut structures spaced apart in the first direction on the initial gate structure, the gate cut structures penetrating a portion of the initial gate structure in the second direction along a third direction; wherein one or more initial semiconductor bodies are located on the side of the initial gate structure opposite to the gate cut structures in the second direction, and the first direction, the second direction and the third direction intersect each other.

[0018] In some embodiments, forming two gate cut-out structures spaced apart in a first direction on an initial gate structure includes: removing one or more initial semiconductor bodies to form a first sacrificial via to expose a portion of the surface of the initial gate structure facing an adjacent initial isolation structure in a second direction; removing at least a portion of the gate layer of the initial gate structure exposed within the first sacrificial via to form a gate cut-out; and forming a gate cut-out structure within the gate cut-out.

[0019] In some embodiments, forming an initial gate structure extending along a first direction includes: forming a plurality of gate trenches spaced apart in a second direction and extending along the first direction in a substrate, the gate trenches and an initial isolation structure being alternately distributed in the second direction, the initial semiconductor body being located between adjacent gate trenches and initial isolation structures in the second direction; and forming an initial gate structure within the gate trenches.

[0020] In some embodiments, removing one or more initial semiconductor bodies to form a first sacrificial via includes: replacing one or more initial semiconductor bodies with sacrificial bodies before forming an initial gate structure in the gate trench; and removing the sacrificial bodies to form a first sacrificial via after forming the initial gate structure in the gate trench.

[0021] In some embodiments, replacing a portion of the initial semiconductor body with a sacrificial body includes: forming a sacrificial layer within a gate trench; removing the initial semiconductor body between the sacrificial layer and an end of an adjacent initial isolation structure, and removing the initial semiconductor body between the sacrificial layer and an end of another adjacent initial isolation structure to form a second sacrificial via; forming a sacrificial body within the second sacrificial via; and removing the sacrificial layer to expose the gate trench.

[0022] In some embodiments, forming an initial gate structure within a gate trench includes: forming a gate dielectric layer on a portion of the inner wall of the gate trench; depositing an adhesive material in the remaining space of the gate trench to form a gate adhesive layer, the gate adhesive layer contacting the gate dielectric layer and the sacrificial body; forming a gate layer on the side of the gate adhesive layer opposite to the gate dielectric layer and the sacrificial body; and forming a gate isolation layer within a gap formed by the gate layer; wherein the initial gate structure includes a gate dielectric layer, a gate adhesive layer, a gate layer, and a gate isolation layer.

[0023] In some embodiments, forming a gate dielectric layer on a portion of the inner wall of the gate trench includes: forming the gate dielectric layer by oxidizing the surface of the initial semiconductor host exposed to the gate trench; wherein the material of the sacrificial host includes aluminum oxide.

[0024] In some embodiments, after forming the gate notch structure, the fabrication method further includes: removing the portion of the initial gate structure located at the bottom of the gate trench to form two gate structures disposed opposite each other in a second direction.

[0025] In some embodiments, forming a plurality of initial semiconductor bodies and an initial isolation structure extending along a first direction includes: forming a plurality of first trenches spaced apart in the first direction and extending along a second direction in a substrate; depositing a dielectric material in the first trenches to form a second dielectric layer; forming a plurality of second trenches and third trenches alternately distributed in the second direction and extending along the first direction in the substrate to divide the substrate into a plurality of initial semiconductor bodies with the first trenches; and forming an initial isolation structure in the second trenches.

[0026] In some embodiments, the fabrication method further includes: expanding the third trench to form a gate trench.

[0027] A third aspect of this application provides a storage system including a controller and a semiconductor device according to the first aspect of this application. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0028] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0029] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of the application. In the drawings: Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device according to one embodiment of this application; Figure 2 This is a schematic cross-sectional view of a semiconductor device according to one embodiment of this application in the xy plane; Figure 3A This is a schematic cross-sectional view of a semiconductor device according to another embodiment of this application in the xy plane; Figure 3B yes Figure 3A A cross-sectional view at point I-I; Figure 3C yes Figure 3A sectional view at point II-II; Figure 4 This is a schematic flowchart of a method for fabricating a semiconductor device according to another embodiment of this application; Figures 5A to 15B This is a schematic diagram of the fabrication method of a semiconductor device according to one embodiment of this application; and Figure 16 This is a block diagram of a system having semiconductor devices according to one embodiment of this application.

[0030] Figure label: 100, Gate assembly; 100', Initial gate structure; 110, Gate structure; 111. Gate dielectric layer; 112. Gate adhesive layer; 113. Gate layer; 114. Sub-dielectric layer; 120. Gate isolation layer; 200. Isolation structure; 200', Initial isolation structure; 210, Conductive structure; 220, Isolation dielectric layer; 221. First isolation layer; 222. Second isolation layer; 223. Third isolation layer; 230, conductive sacrificial structure; 300, semiconductor body; 300', initial semiconductor body; 310, Source; 320, Drain; 400, Gate notch structure; 401, Gate notch; 410. First sub-part; 420. Second sub-part; 430. Sub-cutting structure; 440, First dielectric layer; 500, Second dielectric layer; 510, Sacrificial layer; 511. Part One; 512. Part Two; 520. Sacrificial Subject; 600. Substrate; 601, First surface; 602, Second surface; 610, First groove; 620, Second trench; 630, Third trench; 640, Gate trench; 650, First sacrificial hole; 660, Second sacrificial hole; 670, Third sacrificial hole; 700, Capacitor structure; 800, Bit line; 900, System; 901, Memory system; 902. Semiconductor device; 903. Memory controller; 904. Host computer. Detailed Implementation

[0031] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0033] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale.

[0034] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0035] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0036] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0037] Furthermore, in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a range smaller than that of the structure below or above. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. Furthermore, in this application, the use of "connection" or "joint" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context.

[0038] With the rapid development of semiconductor technology, the size of DRAM memory cells is getting smaller and smaller, and their array architecture has expanded from 8F... 2 Developed to 6F 2 And from 6F 2 Developed to 4F 2 The architecture of memory has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried saddle fin array transistors, and finally from buried saddle fin array transistors to vertical gate transistors.

[0039] Figure 1 A schematic flowchart of a method for fabricating a semiconductor device according to one embodiment of this application is shown. Figure 2 A schematic cross-sectional view of a semiconductor device in one embodiment of this application is shown. (See attached diagram.) Figure 1 and Figure 2 As shown, this application provides a method 1000 for fabricating a semiconductor device, the method comprising: S101. Form multiple initial semiconductor bodies, which extend along a third direction, which can be the z-direction.

[0040] S102. An initial isolation structure and an initial gate structure are formed, extending along a first direction respectively. The initial gate structure is located on one side of the initial semiconductor body in a second direction, and the initial isolation structure is located on the side of the initial semiconductor body opposite to the initial gate structure in the second direction. The first direction can be the y-direction in the attached figure, and the second direction can be the x-direction in the attached figure.

[0041] S103. A patterned mask layer is formed on the third-direction side of the initial semiconductor body.

[0042] S104. The initial gate structure is etched at both ends in the first direction using a patterned mask layer to form a gate cut through the initial gate structure in a third direction. The first direction can be the y-direction in the attached figure, and the third direction can be the z-direction.

[0043] S105. A gate cut structure 400 is formed within the gate cut.

[0044] S106. A portion of the initial gate structure in the third direction is removed to form two gate structures 110 disposed opposite each other in the second direction. During this process, a portion of the initial isolation structure may also be removed to form an isolation structure 200.

[0045] S107. A semiconductor body 300 is formed based on the initial semiconductor body, and all of the semiconductor bodies 300 are located between the two gate cut-out structures 400 in a first direction. The first direction can be the y-direction in the attached figure.

[0046] This application also provides another method for fabricating a semiconductor device and another semiconductor device. Figure 3A This paper shows a schematic cross-sectional view of a semiconductor device in the xy plane according to another embodiment of this application. Figure 3B It shows Figure 3A Schematic diagram of cross-section at point I-I Figure 3C It shows Figure 3A Schematic diagram of cross-section at II-II.

[0047] like Figures 3A to 3C As shown, the semiconductor device includes a gate assembly 100, an isolation structure 200, a gate notch structure 400, and a plurality of semiconductor bodies 300. The isolation structure 200 and the gate assembly 100 are alternately distributed in a second direction and extend along a first direction. The gate assembly 100 includes two gate structures 110 disposed opposite each other in the second direction. The plurality of semiconductor bodies 300 are located between adjacent gate assemblies 100 and isolation structures 200 in the second direction and extend along a third direction. The gate notch structure 400 is located at both ends of the gate structure 110. In the direction intersecting with the third direction, the ends of the two gate structures 110 of the gate assembly 100 extend to the gate notch structure 400 respectively. One or more semiconductor bodies 300 are located on the side of the gate assembly 100 away from the gate notch structure 400 in the second direction. The first direction, the second direction, and the third direction intersect each other.

[0048] In this embodiment, one or more semiconductor bodies 300 are located on the side of the gate assembly 100 away from the gate cut structure 400 in the second direction. In other words, one or more semiconductor bodies 300 and the gate cut structure 400 are spaced apart in the second direction. Based on the above structural features and combined with the process characteristics of the semiconductor bodies 300, which are usually prepared by etching and doping processes, it can be seen that in this embodiment, the gate cut structure 400 replaces the original one or more semiconductor bodies 300.

[0049] It should be noted that the semiconductor device provided in the embodiments of this application can be a memory or a part of a memory. For example, the memory may include peripheral circuits and the aforementioned semiconductor device, with the peripheral circuits coupled to the semiconductor device. In this case, the aforementioned semiconductor device is a part of the memory. Alternatively, the memory may be a memory array, in which case the memory array is the aforementioned semiconductor device. Furthermore, in this application, the intersection of the first direction, the second direction, and the third direction can generally be understood as an angle between the first direction and the second direction, an angle between the second direction and the third direction, and an angle between the first direction and the third direction. For example, the first direction and the second direction are perpendicular or approximately perpendicular to each other, the second direction and the third direction are perpendicular or approximately perpendicular to each other, and the first direction and the third direction are perpendicular or approximately perpendicular to each other. As an example, in the embodiments of this application, the first direction can be the y-direction in the figures, the second direction can be the x-direction in the figures, and the third direction can be the z-direction in the figures.

[0050] In some implementations, such as Figure 3A and Figure 3B As shown, the gate cutout structure 400 extends along a second direction to an adjacent isolation structure 200 on the side opposite to the gate assembly 100. As an example, the gate assembly 100 may also include a gate isolation layer 120 located between two gate structures 110 in the second direction, with the gate cutout structure 400 contacting the gate isolation layer 120 on one side of the second direction and the adjacent isolation structure 200 on the other side.

[0051] In some implementations, such as Figure 3A As shown, a portion of the multiple semiconductor bodies 300 are spaced apart from the gate cutout structure 400 in the second direction, while another portion of the semiconductor bodies 300 are located on one side of the gate cutout structure 400 in the first direction. As an example, the first direction can be the y-direction in the figure, and the second direction can be the x-direction in the figure.

[0052] In some embodiments, the semiconductor body 300 and the gate cutout structure 400 have the same dimensions along a first direction at their adjacent ends in a third-direction orientation. The first direction can be the y-direction in the figures, and the third direction can be the z-direction in the figures. For example, the semiconductor body 300 includes a first end and a second end disposed opposite each other in a third-direction orientation. The dimension of the first end of the semiconductor body 300 in the first direction is smaller than the dimension of its second end in the first direction. The dimension of the first end of the semiconductor body 300 in the first direction is the same as the dimension of the end of the gate cutout structure 400 adjacent to the first end in the first direction, and the dimension of the second end of the semiconductor body 300 in the first direction is the same as the dimension of the end of the gate cutout structure 400 adjacent to the second end in the first direction. As an example, at least a portion of the second ends of a plurality of semiconductor bodies 300 distributed in a second direction are interconnected. The second direction can be the x-direction in the figures. Furthermore, those skilled in the art should understand that the same dimensions of the semiconductor body 300 and the gate cutout structure 400 at their adjacent ends in a third-direction orientation generally means that their dimensions are completely equal or have a slight deviation, for example, the difference in their dimensions does not exceed 15% of either of the two dimensions.

[0053] In some implementations, such as Figure 3A As shown, one end of the gate cutout structure 400 along the third direction has a first dimension D1 in the first direction, and the dimensions of other portions of the gate cutout structure 400 in the first direction are greater than or equal to the first dimension D1. Here, the first direction is the y-direction in the figures, and the third direction is the z-direction in the figures. For example, the semiconductor body 300 includes a first end and a second end disposed opposite to each other in the third direction. The dimension of the first end of the semiconductor body 300 in the first direction is smaller than the dimension of its second end in the first direction. The first dimension is the dimension of the end of the gate cutout structure 400 near the first end in the third direction in the first direction. As an example, the dimension of the gate cutout structure 400 in the first direction gradually decreases along the third direction.

[0054] In some implementations, such as Figure 3B As shown, the dimension h1 of the gate notch structure 400 in the third direction is greater than the dimension h2 of the gate structure 110 in the third direction. The third direction is the z-direction in the attached figure.

[0055] In the embodiments of this application, the gate notch structure 400 can be a single-layer structure or a multi-layer structure. For example, as Figure 3A and Figure 3BAs shown, the gate notch structure 400 may include a first dielectric layer 440 and a sub-notch structure 430. The sub-notch structure 430 extends through the gate assembly 100 in a third direction, and the first dielectric layer 440 is located at least on the sidewall of the sub-notch structure 430 extending in the third direction. As an example, a portion of the first dielectric layer 440 is located in a second direction between the gate isolation layer 120 and the sub-notch structure 430, and another portion of the first dielectric layer 440 is located in a second direction between the sub-notch structure 430 and the isolation structure 200. The material of the first dielectric layer 440 may include, but is not limited to, silicon nitride or silicon oxynitride, and the material of the sub-notch structure 430 may include, but is not limited to, silicon oxide.

[0056] In some implementations, such as Figure 3B As shown, the gate cutout structure 400 may include a first sub-part 410 and a second sub-part 420. The first sub-part 410 extends along a third direction, and the second sub-part 420 is located on one side of the first sub-part 410 in the third direction. At least a portion of the second sub-part 420 is located on the side of the first sub-part 410 away from the adjacent isolation structure 200 in a second direction. The dimension of the first sub-part 410 in the second direction is larger than the dimension of the second sub-part 420 in the second direction. The second direction can be the x-direction in the figures, and the third direction can be the z-direction in the figures. As an example, the second sub-part 420 is bent in the second direction away from the adjacent isolation structure 200. It should be noted that there may not be a clearly detectable interface between the first sub-part 410 and the second sub-part 420; they can be distinguished by comparing the dimensions of the first sub-part 410 and the second sub-part 420 in the second direction.

[0057] In some embodiments, the gate structure 110 may include a gate layer 113 and a gate dielectric layer 111. The gate layer 113 is located on the side of the semiconductor body 300 away from the isolation structure 200 in a second direction. The gate layer 113 extends along a first direction, and the gate dielectric layer 111 is located on the side of the gate layer 113 facing the semiconductor body 300 in the second direction. The first direction may be the y-direction in the figures, and the second direction may be the x-direction in the figures. As an example, the material of the gate layer 113 may include tungsten, aluminum, titanium, copper, cobalt, or tungsten nitride, and the material of the gate dielectric layer 111 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide.

[0058] like Figure 3A As shown, the gate dielectric layer 111 may include a plurality of sub-dielectric layers 114 spaced apart in a first direction, and the sub-dielectric layers 114 are located between the semiconductor body 300 and the gate layer 113 in a second direction. The first direction may be the y-direction in the figures, and the second direction may be the x-direction in the figures.

[0059] In some embodiments, the isolation structure 200 may have an air gap, and the material of the isolation structure 200 may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride. In other embodiments, such as Figure 3B As shown, the isolation structure 200 may include a conductive structure 210 and an isolation dielectric layer 220. The conductive structure 210 extends in a third direction, and the isolation dielectric layer 220 is located at least on the sidewall of the conductive structure 210 extending in the third direction. The material of the isolation dielectric layer 220 may include, but is not limited to, at least one of silicon oxide, silicon oxynitride, and silicon nitride, and the material of the conductive structure 210 may include, but is not limited to, at least one of tungsten, titanium nitride, copper, and silver. As an example, the isolation dielectric layer 220 may include a first isolation layer 221, a second isolation layer 222, and a third isolation layer 223. The third isolation layer 223 is located on one side of the conductive structure 210 in the third direction. The second isolation layer 222 is located at least on the sidewall of the conductive structure 210 extending in the third direction and on the surface of the conductive structure 210 facing away from the third isolation layer 223. The first isolation layer 221 is located on the side of the second isolation layer 222 facing away from the conductive structure 210. The material of the first isolation layer 221 can be silicon oxide, the material of the second isolation layer 222 can be silicon oxynitride, and the material of the third isolation layer 223 can be silicon nitride.

[0060] In some embodiments, the semiconductor device may further include a capacitor structure 700, which is located on one side of the semiconductor body 300 in a third direction and connected to the semiconductor body 300. As an example, the capacitor structure 700 may include a first electrode layer, a second electrode layer, and a capacitor dielectric layer (not shown). The first electrode layer extends in a third direction, the capacitor dielectric layer is located on the sidewall of the first electrode layer extending in the third direction and on the end face of the first electrode layer facing the semiconductor body 300, and the second electrode layer is located on the side of the capacitor dielectric layer away from the first electrode layer and connected to the semiconductor body 300. It should be noted that the capacitor structure 700 in the embodiments of this application may adopt other structural forms suitable for this application besides the above-described structural forms.

[0061] The materials of the first and second electrode layers mentioned above may include, but are not limited to, at least one of metals, metal compounds, semiconductor materials, and silicides; for example, the materials of the first and second electrode layers may include titanium nitride, titanium silicide, or nickel silicide. The material of the capacitor dielectric layer may include, but is not limited to, at least one of aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, zirconium oxide, zirconium silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, hafnium zirconate, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, and praseodymium oxide.

[0062] Furthermore, to reduce contact resistance, a contact structure can be provided between the capacitor structure 700 and the semiconductor body 300. This contact structure may include a semiconductor layer, a metal silicide layer, and a metal layer. The semiconductor layer contacts the semiconductor body 300, the metal silicide layer is located on the side of the semiconductor layer away from the semiconductor body 300 in a third-order orientation, and the metal layer is located on the side of the metal silicide layer away from the semiconductor layer. The semiconductor layer may be made of, but is not limited to, elemental semiconductor materials such as silicon (Si), composite semiconductor materials such as germanium silicon (GeSi), or polycrystalline silicon doped with dopants such as boron. The metal silicide layer may be made of, but is not limited to, at least one of titanium silicide, nickel silicide, and cobalt silicide. The metal layer may be made of, but is not limited to, at least one of tungsten, titanium nitride, copper, and silver.

[0063] In some embodiments, the semiconductor device may further include a bit line 800, which is located on one side of the semiconductor body 300 in a third direction and extends along a second direction. The second direction may be the x-direction in the figures, and the third direction may be the z-direction in the figures. As an example, the semiconductor body 300 may include a first end and a second end disposed opposite to each other in a third direction. The dimension of the first end of the semiconductor body 300 in the first direction is smaller than the dimension of its second end in the first direction. The capacitor structure 700 is located on the side of the first end of the semiconductor body 300 opposite to the second end in a third direction, and the bit line 800 is located on the side of the second end of the semiconductor body 300 opposite to the first end in a third direction.

[0064] In some implementations, such as Figure 3C As shown, the semiconductor body 300 may include a source 310 and a drain 320 spaced apart in a third-direction orientation. For example, the first end of the semiconductor body 300 has a source 310, and the second end of the semiconductor body 300 has a drain 320. The semiconductor body 300 and the gate structure 110 constitute a transistor. The source 310 is connected to the capacitor structure 700, and the drain 320 is connected to the bit line 800. At least a portion of the gate structure 110 can serve as a word line, which is used to apply voltage to control the transistor's on or off state. The bit line 800 is used to perform read or write operations on the capacitor structure 700 when the transistor is on. The amount of charge stored in the capacitor structure 700 represents whether a binary bit is 1 or 0. It should be noted that... Figure 3C The relative positions of the source 310 and the drain 320 are only shown. The source 310 and the drain 320 can also be interchanged.

[0065] Figure 4 A schematic flowchart of a method for fabricating a semiconductor device according to another embodiment of this application is shown. Figures 5A to 15B A schematic diagram of a process for fabricating a semiconductor device according to another embodiment of this application is shown. Figures 4 to 15B As shown, the preparation method 2000 includes: S201, forming a plurality of initial semiconductor bodies 300' and an initial isolation structure 200' extending along a first direction; S202, an initial gate structure 100' extending along a first direction is formed, the initial isolation structure 200' and the initial gate structure 100' are alternately distributed in a second direction, and the initial semiconductor body 300' is located between adjacent initial gate structures 100' and initial isolation structures 200' in the second direction and extends along a third direction. S203. Two gate cutout structures 400 spaced apart in a first direction are formed on the initial gate structure 100'. The gate cutout structures 400 penetrate a portion of the initial gate structure 100' in a second direction along a third direction. In this configuration, one or more initial semiconductor bodies 300' are located on the side of the initial gate structure 100' away from the gate cutout structure 400 in the second direction, and the first direction, the second direction, and the third direction intersect each other.

[0066] The following is a detailed description of each step in the semiconductor device fabrication method in the embodiments of this application.

[0067] Step S201

[0068] In step S201, a plurality of initial semiconductor bodies 300' and an initial isolation structure 200' extending along a first direction are formed, and the initial isolation structure 200' is located on one side of the initial semiconductor body 300' in a second direction.

[0069] Figure 5A This paper shows a schematic cross-sectional view in the xy plane of forming the initial semiconductor body 300' in another embodiment of this application. Figure 5B It shows Figure 5A Schematic diagram of cross-section at point III-III.

[0070] As an example, the initial semiconductor body 300' can be formed by etching the substrate 600. The substrate 600 can be a wafer or a bare die formed after the wafer has been diced. The material of the substrate 600 can be any suitable semiconductor material, such as a single-element semiconductor material like silicon (Si) or germanium (Ge), or a composite semiconductor material like silicon-on-insulator (SOI) or germanium-on-insulator (GeOI).

[0071] For example, such as Figure 5A and Figure 5BAs shown, the initial semiconductor body 300' can be formed as follows: A plurality of first trenches 610 are formed in the substrate 600, spaced apart in a first direction and extending along a second direction. The first direction can be the y-direction in the figure, and the second direction can be the x-direction in the figure. A second dielectric layer 500 is formed by depositing a dielectric material within the first trenches 610. The material of the second dielectric layer 500 can be, but is not limited to, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxide. A plurality of second trenches 620 and third trenches 630 are formed in the substrate 600, alternatingly distributed in the second direction and extending along the first direction. The first trenches 610, second trenches 620, and third trenches 630 together divide at least a portion of the substrate 600 in a third direction into a plurality of initial semiconductor bodies 300'. The third direction can be the z-direction in the figure.

[0072] The first trench 610, the second trench 620, and the third trench 630 can be formed in the substrate 600 using, but is not limited to, wet etching, dry etching (such as plasma etching or reactive ion etching), or combinations thereof. Furthermore, the dimensions of the first trench 610, the second trench 620, and the third trench 630 in the third direction can be the same or different. As an example, the substrate 600 may include a first surface 601 and a second surface 602 disposed opposite to each other in the third direction. The first trench 610, the second trench 620, and the third trench 630 can all be formed in the substrate 600 in the direction from the first surface 601 to the second surface 602. The dimension of the first trench 610 in the third direction can be smaller than the dimension of the substrate 600 in the third direction, and the dimension of the first trench 610 in the third direction is larger than the dimensions of the second trench 620 and the third trench 630 in the third direction, respectively. The third direction can be the z-direction in the figures. The dimensions of the second groove 620 and the third groove 630 in the third direction may be the same or different. As an example, the dimension of the second groove 620 in the first direction may be less than or equal to the dimension of the third groove 630 in the first direction.

[0073] It should be noted that the above steps can be performed in parallel, sequentially, or in different orders, as long as the initial semiconductor body 300' can be formed. This application does not limit this. For example, the second trench 620 and the third trench 630 can be formed in the same etching process, or the second trench 620 can be formed first and then the third trench 630 can be formed.

[0074] Figure 6A This paper shows a schematic cross-sectional view in the xy plane of another embodiment of the present application, showing the formation of the initial isolation structure 200'. Figure 6B It shows Figure 6ASchematic diagram of cross-section at point IV-IV.

[0075] As an example, such as Figure 6A and Figure 6B As shown, an initial isolation structure 200' can be formed within a second trench 620. For example, sacrificial materials can be filled in the second trench 620 and the third trench 630. These sacrificial materials may include materials with a high deposition rate, such as spin-coated carbon. The sacrificial material filling the second trench 620 is removed to expose the second trench 620. Isolation material is deposited within the second trench 620 to form an initial isolation structure 200' with air gaps. The sacrificial material filling the third trench 630 is removed to facilitate the subsequent formation of an initial gate structure 100' within the third trench 630. In some embodiments, two different deposition rates can be used to deposit the isolation material within the second trench 620 when forming the initial isolation structure 200'. For example, a portion of the initial isolation structure 200' can be formed on the inner wall of the second trench 620 using a first deposition rate, while another portion of the initial isolation structure 200' is formed at the opening of the second trench 620 using a second deposition rate greater than the first deposition rate. Because the second deposition rate is greater than the first deposition rate, when both parts are deposited simultaneously, the isolation material at the opening of the second trench 620 quickly seals the opening. However, due to the slower first deposition rate, some space within the second trench 620 remains unfilled after sealing, forming an air gap. Since the air gap has a low dielectric constant, close to that of a vacuum, its presence reduces the overall dielectric constant of the final isolation structure 200, thereby reducing parasitic capacitance and electrical interference between adjacent semiconductor bodies 300. The size and position of the air gap can be adjusted by controlling the first and second deposition rates during its formation. The larger the ratio between the second and first deposition rates, the larger the air gap formed within the initial isolation structure 200', and the better its effect on reducing parasitic capacitance. For example, the ratio α between the second and first deposition rates can range from 1 ≤ α ≤ 3. As an example, the ratio α can range from 1.5 ≤ α ≤ 2. Furthermore, those skilled in the art should understand that, without departing from the technical solutions claimed in this application, the structure, composition, and manufacturing process of the initial isolation structure 200' with air gaps can be modified to obtain the various results and advantages described in this specification.

[0076] It should be noted that, in addition to improving the isolation effect through air gaps, the isolation structure 200 can also improve the isolation effect by setting a conductive structure 210. Subsequently, grounding or connecting the conductive structure 210 to a negative voltage can improve the coupling effect between two adjacent semiconductor bodies 300. For example, ... Figure 6BAs shown, the initial isolation structure 200' may include a conductive structure 210, a conductive sacrificial structure 230, a first isolation layer 221, a second isolation layer 222, and a third isolation layer 223. In this case, the initial isolation structure 200' can be formed as follows: a first isolation layer 221 is formed on the inner wall of the second trench 620. The material of the first isolation layer 221 may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride. A conductive sacrificial structure 230 is formed within the gap formed by the first isolation layer 221. The material of the conductive sacrificial structure 230 may include, but is not limited to, at least one of tungsten, titanium nitride, copper, and silver. A portion of the conductive sacrificial structure 230 is removed to form a fourth trench (not shown) extending along a first direction. The first direction may be the y-direction shown in the figures. A second isolation layer 222 is formed on the inner wall of the fourth trench. The material of the second isolation layer 222 may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride. A conductive structure 210 is formed within the gap formed by the second insulating layer 222. The material of the conductive structure 210 may include, but is not limited to, at least one of tungsten, titanium nitride, copper, and silver. A portion of the conductive structure 210 is removed to form a fifth trench (not shown) extending along the first direction. An insulating material is filled into the fifth trench to form a third insulating layer 223. The material of the third insulating layer 223 may include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride.

[0077] Step S202

[0078] In step S202, an initial gate structure 100' extending along a first direction is formed, and the initial gate structure 100' is located on the side of the initial semiconductor body 300' away from the initial isolation structure 200' in a second direction.

[0079] Figure 10A This illustration shows a cross-sectional view in the xy plane of an initial gate structure 100' formed within a gate trench 640, according to another embodiment of this application. Figure 10B It shows Figure 10A Schematic diagram of cross section at VIII-VIII.

[0080] As an example, the initial gate structure 100' can be formed in the following manner: Figure 6A and Figure 6B As shown, a gate trench 640 extending along a first direction is formed in the substrate 600. The gate trench 640 is located on the side of the initial semiconductor body 300' opposite to the initial gate structure 100' in a second direction. The first direction can be the y-direction in the figures, and the second direction can be the x-direction in the figures. Figure 6AAs shown, the gate trench 640 and the initial isolation structure 200' can be alternately distributed in the second direction, and the initial semiconductor body 300' is located between adjacent gate trenches 640 and initial isolation structures 200' in the second direction. As an example, the gate trench 640 can be the third trench 630 mentioned above, or it can be a trench formed after expanding the third trench 630. Figure 10A and Figure 10B As shown, after forming the gate trench 640, an initial gate structure 100' can be formed within the gate trench 640. As an example, the initial gate structure 100' may include a gate dielectric layer 111, a gate layer 113, and a gate isolation layer 120. Specifically, the gate dielectric layer 111 can be formed on at least a portion of the inner wall of the gate trench 640. The material of the gate dielectric layer 111 may include, but is not limited to, silicon oxide, silicon oxynitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide. A conductive material is deposited within the gate trench 640 to form the gate layer 113, with at least a portion of the gate layer 113 located on the side of the gate dielectric layer 111 facing away from the inner wall of the gate trench 640. The material of the gate layer 113 may include, but is not limited to, polysilicon, metal, metal compound, silicide, or any combination thereof. For example, the material of the gate layer 113 may include tungsten, aluminum, titanium, copper, cobalt, or tungsten nitride. A gate isolation layer 120 is formed within the gap formed by the gate layer 113. The material of the gate isolation layer 120 may include, but is not limited to, silicon oxide, silicon oxynitride, silicon nitride, or high-k materials such as hafnium oxide, zirconium oxide, aluminum oxide, and tantalum oxide. To improve the adhesion between the gate layer 113 and the gate dielectric layer 111, an adhesive material may be deposited in the gate trench 640 before forming the gate layer 113 to form a gate adhesive layer 112. At least a portion of the gate adhesive layer 112 is located between the gate dielectric layer 111 and the gate layer 113. The material of the gate adhesive layer 112 may include, but is not limited to, at least one of titanium nitride, tantalum nitride, and tungsten carbide.

[0081] The gate dielectric layer 111, gate adhesive layer 112, gate layer 113, and gate isolation layer 120 mentioned above can all be formed by thin film deposition processes. These thin film deposition processes can be, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination of the above processes. In some other embodiments, the gate dielectric layer 111 can also be formed by in-situ oxidation.

[0082] Step S203

[0083] In step S203, two gate cutout structures 400 spaced apart in a first direction are formed on the initial gate structure 100'. The gate cutout structures 400 penetrate a portion of the initial gate structure 100' in a second direction along a third direction. The first direction can be the y-direction in the figures, the second direction can be the x-direction in the figures, and the third direction can be the z-direction in the figures.

[0084] Figure 12A This paper shows a schematic cross-sectional view of the xy plane forming the first sacrificial hole 650 in another embodiment of this application. Figure 12B It shows Figure 12A A cross-sectional view at X-X; Figure 13A This illustration shows a cross-sectional view in the xy plane of at least removing the gate layer 113 of the initial gate structure 100' to form a gate notch 401 in another embodiment of this application. Figure 13B It shows Figure 13A A cross-sectional view at XI-XI; Figure 14A This illustration shows a schematic cross-sectional view in the xy plane of a gate notch structure 400 formed within a gate notch 401, according to another embodiment of this application. Figure 14B It shows Figure 14A A cross-sectional view at XII-XII.

[0085] As an example, the gate notch structure 400 can be formed in the following manner: Figure 12A and Figure 12B As shown, one or more initial semiconductor bodies 300' are removed to form a first sacrificial via 650, exposing a portion of the surface of the initial gate structure 100' facing the adjacent initial isolation structure 200' in a second direction. The second direction can be the x-direction shown in the figures. Figure 13A and Figure 13B As shown, at least the portion of the gate layer 113 of the initial gate structure 100' exposed within the first sacrificial via 650 is removed to form a gate notch 401. Figure 14A and Figure 14B As shown, a gate notch structure 400 is formed within the gate notch 401. The gate notch structure 400 can be a single-layer structure or a multi-layer structure. For example, a first dielectric layer 440 can be formed on the inner wall of the gate notch 401. A sub-notch structure 430 is formed within the gap formed by the first dielectric layer 440. The material of the sub-notch structure 430 is different from the material of the first dielectric layer 440. For example, the material of the first dielectric layer 440 can be silicon nitride or silicon oxynitride, and the material of the second dielectric layer 500 can be silicon oxide.

[0086] The gate notch 401 in this embodiment is formed by removing at least a portion of the initial gate structure 100' exposed within the first sacrificial via 650. The first sacrificial via 650 is formed by removing one or more initial semiconductor bodies 300', thereby exposing a portion of the sidewalls of the initial gate structure 100' extending along a first direction within the first sacrificial via 650. Therefore, when forming the gate notch 401 using a process such as wet etching, i.e., removing at least a portion of the initial gate structure 100' exposed within the first sacrificial via 650, the contact area between the etchant and the initial gate structure 100' is larger, resulting in more uniform etching. This not only reduces the difficulty of the etching process and shortens the overall process time but also reduces the risk of simultaneous removal of a portion of the initial isolation structure 200' or excessive removal of the gate layer 113 due to over-etching. Consequently, it reduces the risk of a decrease in the breakdown voltage of the remaining gate layer 113 due to over-etching. In addition, it can reduce the risk of leakage between the gate layer 113 and the bit line 800 or the contact structure due to insufficient etching of the gate layer 113.

[0087] Figure 7A This illustration shows a cross-sectional view in the xy plane of a third sacrificial hole 670 formed in the sacrificial layer 510 according to another embodiment of this application. Figure 7B It shows Figure 7A A cross-sectional view at V-V; Figure 8A This illustration shows a cross-sectional view in the xy plane of another embodiment of the present application, showing the removal of the initial semiconductor body 300' to form the second sacrificial via 660. Figure 8B It shows Figure 8A A cross-sectional view at VI-VI; Figure 9A This illustration shows a cross-sectional view in the xy plane of a sacrificial body 520 formed within the second sacrificial hole 660, according to another embodiment of this application. Figure 9B It shows Figure 9A Schematic diagram of cross-section at VII-VII.

[0088] In some embodiments, the first sacrificial via 650 can be formed such that one or more initial semiconductor bodies 300' are replaced with sacrificial bodies 520 before the initial gate structure 100' is formed within the gate trench 640. Specifically, as Figure 8A and Figure 8B As shown, a sacrificial layer 510 can be formed within the gate trench 640. The material of the sacrificial layer 510 can be, but is not limited to, carbon, carbon-containing organic materials, or photoresist materials such as photoresist. Multiple initial semiconductor bodies 300' are removed to form two spaced-apart second sacrificial vias 660 in a first direction, the second sacrificial vias 660 being located on opposite sides of the gate trench 640 in a second direction. For example, as... Figure 8AAs shown, the initial semiconductor body 300' between the sacrificial layer 510 and the end of one of the adjacent initial isolation structures 200' can be removed to form one of the second sacrificial vias 660. Furthermore, the initial semiconductor body 300' between the sacrificial layer 510 and the end of another adjacent initial isolation structure 200' can also be removed to form another second sacrificial via 660. The first direction can be the y-direction in the figures, and the second direction can be the x-direction in the figures. It should be noted that during the formation of the sacrificial layer 510, the sacrificial material filling the gate trench 640 may also cover one end face of the initial semiconductor body 300' in a third direction. Figure 7A and Figure 7B As shown, the first portion 511 of the sacrificial layer 510 is located within the gate trench 640, and the second portion 512 of the sacrificial layer 510 is located on one side of the initial semiconductor body 300' in a third direction. Therefore, before forming the second sacrificial via 660, a third sacrificial via 670 can also be formed in the second portion 512 of the sacrificial layer 510. The third sacrificial via 670 is located at one end of the initial isolation structure 200' in a first direction to expose the initial semiconductor body 300' located on at least one side of the initial isolation structure 200' in a second direction. Subsequently, the second sacrificial via 660 can be formed by removing the exposed initial semiconductor body 300' through the third sacrificial via 670. Figure 9A and Figure 9B As shown, a sacrificial body 520 is formed within the second sacrificial via 660. The material of the sacrificial body 520 is different from that of the initial semiconductor body 300'. Under the same etching conditions, the sacrificial body 520 has a higher etch selectivity than the initial semiconductor body 300', so that the initial semiconductor body 300' is hardly removed during subsequent removal of the sacrificial body 520. As an example, the material of the sacrificial body 520 may include, but is not limited to, materials such as alumina. The sacrificial layer 510 is removed using a process such as ashing to expose the gate trench 640. Figure 12A and Figure 12B As shown, after the initial gate structure 100' is formed in the gate trench 640, the sacrificial body 520 is removed to form the first sacrificial hole 650.

[0089] Figure 11A This illustration shows a cross-sectional view in the xy plane of another embodiment of the present application, in which a portion of the initial gate structure 100' is removed to expose the sacrificial body 520. Figure 11B It shows Figure 11A A cross-sectional view at IX-IX.

[0090] like Figure 10BAs shown, when forming the initial gate structure 100', the initial gate structure 100' may also cover the sacrificial body 520. In other words, a portion of the initial gate structure 100' is located within the gate trench 640, and a portion may be located on one side of the sacrificial body 520 in a third-order orientation. Therefore, as... Figure 11A and Figure 11B As shown, a portion of the gate isolation layer 120 can be removed to expose the gate adhesive layer 112 on the surface facing away from the sacrificial body 520 in the third-party direction. The third-party direction can be the z-direction in the figures. At least the portions of the gate adhesive layer 112 and the gate layer 113 on the side of the sacrificial body 520 in the third-party direction are removed to expose the sacrificial body 520. Then, as... Figure 12A and Figure 12B As shown, the exposed sacrificial body 520 can be removed by a process such as wet etching to form the first sacrificial hole 650.

[0091] It should be noted that, as described above, the sacrificial body 520 is first formed within the second sacrificial via 660, and then the sacrificial layer 510 is removed. In other embodiments, the sacrificial layer 510 may be removed first to expose the gate trench 640, and then the sacrificial body 520 is formed within the second sacrificial via 660 and the gate trench 640, followed by the removal of the portion of the sacrificial body 520 located within the gate trench 640. Furthermore, as described above, the gate trench 640 can be exposed by removing either the sacrificial layer 510 or a portion of the sacrificial body 520, exposing the surface of the sacrificial body 520 facing away from the initial isolation structure 200' in the second direction within the gate trench 640. Thus, as... Figure 10A and Figure 10B As shown, when forming the gate dielectric layer 111 within the gate trench 640, the gate dielectric layer 111 can be formed by oxidizing the initial semiconductor body 300' exposed on the surface of the gate trench 640. The sidewalls of the sacrificial body 520 exposed on the gate trench 640 will not be oxidized. Thus, a portion of the subsequently formed gate adhesive layer 112 is located on the surface of the gate dielectric layer 111 away from the initial semiconductor body 300', and another portion of the gate adhesive layer 112 is located on the surface of the sacrificial body 520 exposed on the gate trench 640. The gate layer 113 is located on the side of the gate adhesive layer 112 away from the gate dielectric layer 111 and the sacrificial body 520. If the initial gate structure 100' does not include the gate adhesive layer 112, then a portion of the gate layer 113 is located on the surface of the sacrificial body 520 exposed on the gate trench 640.

[0092] Figure 15A This illustration shows a cross-sectional view in the xy plane of two gate structures 110 formed by removing a portion of the initial gate structure 100' in another embodiment of this application. Figure 15B It shows Figure 15ASchematic diagram of cross-section at XIII-XIII.

[0093] In some implementations, such as Figures 14A to 15B As shown, the fabrication method may further include: removing a portion of the initial gate structure 100' located at the bottom of the gate trench 640 to form two gate structures 110 disposed opposite each other in a second direction. The second direction may be the x-direction in the figures. For example, portions of the gate layer 113 and the gate adhesive layer 112 located at the bottom surface of the gate trench 640 may be removed to form a sixth trench (not shown) extending along a first direction. A dielectric material is deposited within the sixth trench, which may include at least one of silicon oxide, silicon oxynitride, and silicon nitride. As an example, the first direction may be the y-direction in the figures. The projected shape of the sixth trench on a plane perpendicular to the first direction may be semi-circular, U-shaped, or rectangular.

[0094] It should be noted that when the initial isolation structure 200' includes a conductive structure 210, a conductive sacrificial structure 230, a first isolation layer 221, a second isolation layer 222, and a third isolation layer 223, when a portion of the initial gate structure 100' located on the bottom surface of the gate trench 640 is removed, the portion of the second isolation layer 222 located between the conductive sacrificial structure 230 and the conductive structure 210 can serve as an etch stop layer. In other words, at least the conductive sacrificial structure 230 of the initial isolation structure 200' can be removed during this process to form the isolation structure 200.

[0095] In some embodiments, the fabrication method may further include forming a semiconductor body 300 based on an initial semiconductor body 300'. For example, the semiconductor body 300 may be formed by doping both ends of the initial semiconductor body 300'. One end of the initial semiconductor body 300' is doped to form a drain 320, and the other end of the initial semiconductor body 300' is doped to form a source 310. The source 310 and drain 320 may be both doped with P-type dopant or both doped with N-type dopant. The dopant of the source 310 and drain 320 may be the same or different. For example, the dopant may include, but is not limited to, boron (B), aluminum (Al), gallium (Ga), phosphorus (P), arsenic (As), or antimony (Sb).

[0096] In addition, this application also provides a storage system, which includes a controller and the aforementioned semiconductor device. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0097] Figure 16A block diagram of a system with semiconductor devices according to one embodiment of this application is shown. System 900 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device with storage located therein. Figure 16 As shown, system 900 may include host 904 and memory system 901, the memory system 901 having one or more semiconductor devices 902 and memory controller 903. Host 904 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-a-chip (SoC), such as an application processor (AP). Host 904 may be configured to send or receive data from semiconductor device 902.

[0098] Semiconductor device 902 can be any semiconductor device disclosed in this application, such as Figures 3A to 3C The semiconductor device is shown. According to some embodiments, a memory controller 903 is coupled to the semiconductor device 902 and the host 904, and is configured to control the semiconductor device 902. The memory controller 903 can manage data stored in the semiconductor device 902 and communicate with the host 904.

[0099] In some embodiments, the memory controller 903 is designed to operate in a low duty cycle environment, such as with Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In some embodiments, the memory controller 903 is designed to operate in a high duty cycle environment, such as with SSDs or embedded multimedia cards (eMMC), which are used as data storage devices in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays. The memory controller 903 can be configured to control the operation of the semiconductor device 902, such as read, erase, and program operations. The memory controller 903 can also be configured to manage various functions related to data stored in or to be stored in the semiconductor device 902, including but not limited to bad block management, garbage collection, logic-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 903 is further configured to process error correction codes (ECC) related to data read from or written to the semiconductor device 902. The memory controller 903 can also perform any other suitable functions, such as formatting the semiconductor device 902. The memory controller 903 can communicate with external devices (e.g., the host 904) according to a specific communication protocol. For example, the memory controller 903 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), and High Speed ​​PCI (PCI-8). E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, FireWire protocol, etc.

[0100] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. As an example, the steps described in this invention disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0101] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor device, comprising: A gate assembly extending along a first direction and including two gate structures disposed opposite each other in a second direction; An isolation structure, which is alternately distributed with the gate assembly in the second direction and extends along the first direction; Multiple semiconductor bodies are located between adjacent gate components and the isolation structure in the second direction and extend along a third direction; as well as A gate notch structure is located at both ends of the gate structure, and extends to the gate notch structure at the ends of the two gate structures of the gate assembly in a direction intersecting with the third direction. In this configuration, one or more of the semiconductor bodies are located on the side of the gate assembly away from the gate notch structure in the second direction, and the first direction, the second direction, and the third direction intersect each other.

2. The semiconductor device according to claim 1, wherein, The gate notch structure extends along the second direction to the adjacent isolation structure on the side opposite to the gate assembly.

3. The semiconductor device according to claim 1, wherein, The semiconductor body and the gate cutout structure have the same dimensions at their adjacent ends in the third direction along the first direction.

4. The semiconductor device according to claim 1, wherein, A portion of the semiconductor bodies and the gate cutout structure are spaced apart in the second direction, while another portion of the semiconductor bodies are located on one side of the gate cutout structure in the first direction.

5. The semiconductor device according to claim 1, wherein, The gate notch structure includes: The first sub-part extends along the third direction; The second sub-part is located on one side of the first sub-part in the third direction; Wherein, at least a portion of the second sub-part is located on the side of the first sub-part away from the adjacent isolation structure in the second direction, and the size of the first sub-part in the second direction is larger than the size of the second sub-part in the second direction.

6. The semiconductor device according to claim 5, wherein, The second sub-part bends in the second direction away from the adjacent isolation structure.

7. The semiconductor device according to claim 1, wherein, The gate cutout structure has a first dimension at one end along the third direction in the first direction, and the other portions of the gate cutout structure have dimensions in the first direction that are greater than or equal to the first dimension.

8. The semiconductor device according to claim 1, wherein, The dimension of the gate notch structure in the third direction is larger than the dimension of the gate structure in the third direction.

9. The semiconductor device according to claim 1, wherein, The gate notch structure includes: Sub-cut structure, extending through the gate assembly in the third direction; and The first dielectric layer is located at least on the sidewall of the sub-cut structure extending in the third direction.

10. The semiconductor device according to any one of claims 1 to 9, wherein, The gate assembly further includes: A gate isolation layer is located between the two gate structures in the second direction; The gate notch structure is located on the side of the gate isolation layer away from the semiconductor body in the second direction.

11. The semiconductor device according to any one of claims 1 to 9, wherein, The gate structure includes: A gate layer, located on the side of the semiconductor body opposite to the isolation structure in the second direction, and extending along the first direction; and A gate dielectric layer is located on the side of the gate layer facing the semiconductor body in the second direction.

12. The semiconductor device according to claim 11, wherein, The gate dielectric layer includes a plurality of sub-dielectric layers spaced apart in the first direction, and the sub-dielectric layers are located between the semiconductor body and the gate layer in the second direction.

13. A method for fabricating a semiconductor device, comprising: Multiple initial semiconductor bodies and an initial isolation structure extending along a first direction are formed; An initial gate structure is formed extending along the first direction, the initial isolation structure and the initial gate structure are alternately distributed in the second direction, and the initial semiconductor body is located between adjacent initial gate structures and initial isolation structures in the second direction and extends along the third direction; Two gate cutout structures spaced apart in the first direction are formed on the initial gate structure, and the gate cutout structures penetrate a portion of the initial gate structure in the second direction along a third direction; In this configuration, one or more of the initial semiconductor bodies are located on the side of the initial gate structure opposite to the gate notch structure in the second direction, and the first direction, the second direction, and the third direction intersect each other.

14. The method for fabricating a semiconductor device according to claim 13, wherein, Forming two gate notch structures spaced apart in the first direction on the initial gate structure includes: One or more of the initial semiconductor bodies are removed to form a first sacrificial via, thereby exposing a portion of the surface of the initial gate structure facing the adjacent initial isolation structure in the second direction; At least the portion of the gate layer of the initial gate structure exposed within the first sacrificial via is removed to form a gate notch; and A gate cut structure is formed within the gate cut.

15. The method for fabricating a semiconductor device according to claim 14, wherein, Forming an initial gate structure extending along the first direction includes: A plurality of gate trenches are formed in a substrate, spaced apart in the second direction and extending along the first direction. The gate trenches and the initial isolation structure are alternately distributed in the second direction. The initial semiconductor body is located in the second direction between adjacent gate trenches and the initial isolation structure. The initial gate structure is formed within the gate trench.

16. The method for fabricating a semiconductor device according to claim 15, wherein, Removing one or more of the initial semiconductor bodies to form a first sacrificial via includes: Before forming the initial gate structure within the gate trench, one or more of the initial semiconductor bodies are replaced with sacrificial bodies; and After the initial gate structure is formed in the gate trench, the sacrificial body is removed to form the first sacrificial via.

17. The method for fabricating a semiconductor device according to claim 16, wherein, Replacing a portion of the initial semiconductor host with a sacrificial host includes: A sacrificial layer is formed within the gate trench; The initial semiconductor body between the sacrificial layer and the end of an adjacent initial isolation structure is removed, and the initial semiconductor body between the sacrificial layer and the end of another adjacent initial isolation structure is removed to form a second sacrificial via; The sacrificial body is formed within the second sacrificial orifice; and Remove the sacrificial layer to expose the gate trench.

18. The method for fabricating a semiconductor device according to claim 16, wherein, Forming the initial gate structure within the gate trench includes: A gate dielectric layer is formed on a portion of the inner wall of the gate trench; An adhesive material is deposited in the remaining space of the gate trench to form a gate adhesive layer, the gate adhesive layer being in contact with the gate dielectric layer and the sacrificial body; A gate layer is formed on the side of the gate adhesive layer opposite to the gate dielectric layer and the sacrificial body; and A gate isolation layer is formed within the gap formed by the gate layer; The initial gate structure includes the gate dielectric layer, the gate adhesive layer, the gate layer, and the gate isolation layer.

19. The method for fabricating a semiconductor device according to claim 18, wherein, Forming a gate dielectric layer on a portion of the inner wall of the gate trench includes: The gate dielectric layer is formed by oxidizing the surface of the initial semiconductor body exposed to the gate trench; The material of the sacrificial body includes aluminum oxide.

20. The method for fabricating a semiconductor device according to any one of claims 15 to 19, wherein after forming the gate notch structure, the fabrication method further comprises: The portion of the initial gate structure located at the bottom of the gate trench is removed to form two gate structures disposed opposite each other in the second direction.

21. The method for fabricating a semiconductor device according to any one of claims 13 to 19, wherein, Forming multiple initial semiconductor bodies and an initial isolation structure extending along a first direction includes: A plurality of first trenches are formed in the substrate, which are spaced apart in the first direction and extend along the second direction; A second dielectric layer is formed by depositing a dielectric material within the first trench; A plurality of second and third trenches, alternately distributed in the second direction and extending along the first direction, are formed in the substrate to divide the substrate into a plurality of the initial semiconductor bodies with the first trenches; and The initial isolation structure is formed within the second trench.

22. The method for fabricating a semiconductor device according to claim 21, wherein, The preparation method further includes: The third trench is enlarged to form a gate trench.

23. A storage system, characterized in that, The storage system includes a controller and a semiconductor device according to any one of claims 1 to 12, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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