Semiconductor structure and forming method, semiconductor device and storage system

Abstract

The present disclosure provides a semiconductor structure and a forming method, a semiconductor device and a storage system, and relates to the technical field of memory. The semiconductor structure comprises a bonding layer extending along a second direction, the bonding layer comprising a contact structure and a connection structure connected with each other, wherein: the contact structure at least partially penetrates the bonding layer along a first direction, the first direction being perpendicular to the second direction; the connection structure at least partially penetrates the bonding layer along the first direction, and the ratio of the depth of the connection structure along the first direction to the width of the connection structure along the second direction is not less than 2.7. The semiconductor structure can increase the anti-complementary window of hybrid bonding.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and more specifically, to a semiconductor structure and its formation method, a semiconductor device, and a memory system. Background Technology

[0002] With the development of semiconductor technology, the feature size of semiconductor devices is shrinking and the integration density is increasing. The process and manufacturing technology of planar memory cells have become challenging and costly, leading to the emergence of three-dimensional semiconductor structures. Three-dimensional semiconductor structures improve storage density by arranging memory cells three-dimensionally on a substrate or other structure.

[0003] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a semiconductor structure and a method for forming it, a semiconductor device, and a memory system.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part by practice of this disclosure.

[0006] According to one aspect of this disclosure, a semiconductor structure is provided, comprising: a bonding layer extending along a second direction, the bonding layer including a contact structure and a connection structure connected together, wherein: the contact structure at least partially penetrates the bonding layer along a first direction, the first direction being perpendicular to the second direction; the connection structure at least partially penetrates the bonding layer along the first direction, and the ratio of the depth of the connection structure along the first direction to its width along the second direction is not less than 2.7.

[0007] According to one embodiment of this disclosure, the contact structure includes a first conductive material, and the connection structure includes a second conductive material, wherein the second conductive material is different from the first conductive material.

[0008] According to one embodiment of this disclosure, the first conductive material is copper, and the second conductive material is tungsten.

[0009] According to one embodiment of this disclosure, the ratio of the depth of the connecting structure along the first direction to its width along the second direction is between 10 and 50.

[0010] According to one embodiment of this disclosure, the connecting structure includes a first end and a second end disposed opposite to each other in the first direction, the first end of the connecting structure being connected to the contact structure, and the width of the contact structure along the second direction being greater than the width of the first end of the connecting structure along the second direction.

[0011] According to one embodiment of this disclosure, the width of the first end of the connection structure along the second direction is no greater than 120 nanometers.

[0012] According to one embodiment of this disclosure, the width of the first end of the connection structure along the second direction is no greater than 105 nanometers.

[0013] According to one embodiment of this disclosure, the difference between half the width of the contact structure along the second direction and half the width of the first end of the connection structure along the second direction is not less than 80 nanometers.

[0014] According to one embodiment of this disclosure, the width of the second end of the connection structure along the second direction is no greater than 100 nanometers.

[0015] According to one embodiment of this disclosure, the width of the second end of the connection structure along the second direction is no greater than 70 nanometers.

[0016] According to one embodiment of the present disclosure, the semiconductor structure further includes an interconnect layer and an interconnect structure, wherein the bonding layer and the interconnect layer are stacked along the first direction, the interconnect structure at least partially penetrates the interconnect layer along the first direction, and the interconnect structure is connected to a second end of the connection structure.

[0017] According to one embodiment of this disclosure, the width of the interconnect structure along the second direction is greater than the width of the second end of the connection structure along the second direction.

[0018] According to one embodiment of the present disclosure, the bonding layer includes a first dielectric layer and a second dielectric layer stacked along the first direction, the contact structure penetrates the first dielectric layer along the first direction, and the connection structure at least partially penetrates the second dielectric layer along the first direction.

[0019] According to one embodiment of the present disclosure, the first dielectric layer comprises a nitrogen-doped silicon carbide material, and the second dielectric layer comprises an oxide material.

[0020] According to one embodiment of the present disclosure, the connection structure includes a first conductive layer and a second conductive layer, wherein: in the second direction, the first conductive layer is disposed between the second conductive layer and the second dielectric layer.

[0021] According to one embodiment of the present disclosure, the semiconductor structure further includes an interconnect layer and an interconnect structure, the bonding layer and the interconnect layer are stacked along the first direction, the interconnect structure at least partially penetrates the interconnect layer along the first direction, and the interconnect structure is connected to the connection structure; in the first direction, the first conductive layer is disposed between the second conductive layer and the interconnect structure.

[0022] According to one embodiment of the present disclosure, the first conductive layer includes at least one of tantalum, tantalum nitride, titanium, and titanium nitride, and the second conductive layer includes tungsten.

[0023] According to one embodiment of this disclosure, the cross-section of the contact structure parallel to the first plane is trapezoidal, the cross-section of the connecting structure parallel to the first plane is trapezoidal, the first plane is parallel to both the first direction and the second direction, and the short side of the trapezoidal cross-section of the contact structure is connected to the long side of the trapezoidal cross-section of the connecting structure.

[0024] According to one embodiment of the present disclosure, the semiconductor structure includes a first semiconductor structure and a second semiconductor structure, and the bonding layer includes a first bonding layer and a second bonding layer. The first bonding layer is disposed on the first semiconductor structure, and the second bonding layer is disposed on the second semiconductor structure. The contact structure of the first bonding layer is connected to the contact structure of the second bonding layer.

[0025] According to another aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising: providing an interconnect layer and an interconnect structure, the interconnect structure at least partially penetrating the interconnect layer along a first direction, the interconnect layer extending along a second direction, the first direction being perpendicular to the second direction; forming a bonding layer on the interconnect layer, the bonding layer including a connection structure, wherein: the connection structure at least partially penetrating the bonding layer along the first direction, the connection structure being connected to the interconnect structure, and the ratio of the depth of the connection structure along the first direction to its width along the second direction being not less than 2.7.

[0026] According to one embodiment of this disclosure, the bonding layer further includes a second dielectric layer; forming the bonding layer on the interconnect layer includes: forming the second dielectric layer on the interconnect layer; forming a via through the second dielectric layer at a position corresponding to the interconnect structure, wherein the ratio of the depth of the via along the first direction to its width along the second direction is not less than 2.7; and forming the connection structure in the via.

[0027] According to one embodiment of this disclosure, the connection structure includes a first conductive layer and a second conductive layer; forming the connection structure in the through hole includes: forming the first conductive layer on the bottom surface and sidewall of the through hole; and forming the second conductive layer on the surface of the first conductive layer in the through hole.

[0028] According to one embodiment of this disclosure, the bonding layer further includes a first dielectric layer and a contact structure; forming the bonding layer on the interconnect layer further includes: forming the first dielectric layer on the second dielectric layer; forming the contact structure at a position on the first dielectric layer corresponding to the connection structure, wherein the width of the contact structure along the second direction is greater than the width of the connection structure along the second direction.

[0029] According to one embodiment of this disclosure, forming the contact structure at a position in the first dielectric layer corresponding to the connection structure includes: forming a groove in the first dielectric layer corresponding to the connection structure, wherein the width of the groove along the second direction is greater than the width of the connection structure along the second direction; and forming the contact structure in the groove.

[0030] According to another aspect of this disclosure, a semiconductor device is provided, comprising any of the semiconductor structures described above.

[0031] According to another aspect of this disclosure, a storage system is provided, including a semiconductor device as described above and a controller coupled to said semiconductor device.

[0032] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0033] The above and other objects, features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0034] Figure 1 A block diagram of an exemplary system with a memory is shown in an embodiment of this disclosure.

[0035] Figure 2A A block diagram of a memory system is shown as an example.

[0036] Figure 2B A block diagram of another memory system is shown as an example.

[0037] Figure 3A A schematic cross-sectional view of a semiconductor structure is shown according to an exemplary embodiment.

[0038] Figure 3B A cross-sectional schematic diagram of another semiconductor structure is shown according to an exemplary embodiment.

[0039] Figure 3C A cross-sectional schematic diagram of another semiconductor structure is shown according to an exemplary embodiment.

[0040] Figure 4 A schematic diagram of bonding backfilling of a semiconductor structure is shown according to an exemplary embodiment.

[0041] Figure 5 A cross-sectional schematic diagram of a bonding layer provided in an embodiment of this disclosure is shown.

[0042] Figure 6 A cross-sectional schematic diagram of another bonding layer provided in an embodiment of this disclosure is shown.

[0043] Figure 7 according to Figure 5 A cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this disclosure is shown.

[0044] Figure 8 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment.

[0045] Figure 9 It shows Figure 8 The step S804 shown is a schematic diagram of the processing procedure in one embodiment.

[0046] Figure 10 It shows Figure 9 The step S906 shown is a schematic diagram of the processing procedure in one embodiment.

[0047] Figure 11 It shows Figure 8 The step S804 shown is a schematic diagram of the processing procedure in another embodiment.

[0048] Figure 12 It shows Figure 11 The step S1104 shown is a schematic diagram of the processing procedure in another embodiment.

[0049] Figure 13 A cross-sectional schematic diagram of an interconnect layer and an interconnect structure is shown according to an exemplary embodiment.

[0050] Figure 14 A schematic cross-sectional view of a second dielectric layer formed on an interconnect layer is shown according to an exemplary embodiment.

[0051] Figure 15 A cross-sectional schematic diagram of a through-hole formed on a second dielectric layer is shown according to an exemplary embodiment.

[0052] Figure 16 A cross-sectional schematic diagram of a first conductive layer formed in a via is shown according to an exemplary embodiment.

[0053] Figure 17 A cross-sectional schematic diagram showing a second conductive layer formed on the surface of a first conductive layer is shown according to an exemplary embodiment.

[0054] Figure 18A schematic cross-sectional view of a first dielectric layer formed on a second dielectric layer is shown according to an exemplary embodiment.

[0055] Figure 19 A cross-sectional schematic diagram showing a contact structure formed in a first dielectric layer is shown according to an exemplary embodiment. Detailed Implementation

[0056] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0057] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0058] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. The symbol " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0059] It should be readily understood that the meanings of “on top of,” “above,” and “above” in this disclosure should be interpreted in the broadest possible sense, such that “on top of” means not only “directly on something,” but also includes being on something with an intermediate feature or layer between them, and that “on top of” or “above” means not only being on or above something, but also includes the meaning of having no intermediate feature or layer between them (i.e., being directly on something).

[0060] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "higher" may be used in this disclosure to describe the relationship of one component or feature to one or more other components or features, as illustrated in the accompanying drawings. In addition to the directions depicted in the drawings, these spatial relative terms are intended to cover different orientations or directions of the device in use or operation. The device may be oriented in other ways (e.g., by a 90-degree rotation or in other directions) and can be interpreted accordingly using the spatially related descriptions used in this disclosure.

[0061] In this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0062] In this disclosure, the term "layer" refers to a portion of material having a thickness in a region. A layer may extend over the entire lower or upper layer structure, or its extent may be less than that of the lower or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure, with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes between the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on and / or below it. A layer may contain multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0063] In this disclosure, unless otherwise expressly specified and limited, the term "connection" and similar terms should be interpreted broadly, for example, it can refer to an electrical connection or the ability to communicate with each other; it can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0064] Figure 1 A block diagram of an exemplary system with memory is shown according to an embodiment of this disclosure. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, or any other suitable electronic device having memory therein.

[0065] like Figure 1As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor) of an electronic device. The host 108 may be configured to send data to or receive data from the memory 104.

[0066] Memory 104 can be non-volatile memory, volatile memory, etc. Non-volatile memory can be NAND flash memory (e.g., 3D NAND flash memory). Volatile memory can be Dynamic Random Access Memory (DRAM).

[0067] In some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108.

[0068] In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0069] In some embodiments, the memory controller 106 is designed to operate in high duty cycle environments, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which can be used as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 106 can be configured to send commands to the memory 104 to cause the memory 104 to perform operations, such as read, erase, and program operations.

[0070] The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0071] In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0072] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0073] Figure 2A A block diagram of a memory system is shown as an example. Figure 2A As shown, the memory controller 106 and a single memory 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (also known as a PCMCIA card, Personal Computer Memory Card International Association card), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (e.g., MMC card, RS-MMC card, MMCmicro card, etc.), an SD card (e.g., SD card, miniSD card, microSD card, SDHC card, etc.), a UFS card, etc. The memory card 202 may also include a connector for connecting the memory card 202 to a host computer (e.g., ...). Figure 1 The memory card connector 204 is coupled to the host 108.

[0074] Figure 2B A block diagram of another memory system is shown as an example. Figure 2B As shown, the memory controller 106 and multiple memories 104 can be integrated into the SSD 206. The multiple memories 104 may include, for example, multiple NAND flash memories 1042 and one DRAM 1044. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., ...). Figure 1The SSD connector 208 is coupled to the host 108 in the host. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0075] Figure 3A A schematic cross-sectional view of a semiconductor structure is shown according to an exemplary embodiment. The semiconductor structure provided in this disclosure can be a semiconductor device, for example, it can be... Figures 1 to 2B DRAM memory in [the context]. For example... Figure 3A The semiconductor structure shown may include a first semiconductor structure 302 and a second semiconductor structure 304. A memory cell array 3022 is disposed in the first semiconductor structure 302, and a peripheral circuit structure 3042 is disposed in the second semiconductor structure. The first semiconductor structure 302 and the second semiconductor structure 304 can be arranged along... Figure 3A The memory is formed by stacking the components together in the Y direction.

[0076] Reference Figure 3A The first semiconductor structure 302 may include a memory cell array 3022 disposed on a substrate 3021. The memory cell array 3022 may include DRAM cells (not shown in FIG3) consisting of pairs of transistors and capacitors, which are formed in an array on a plane formed in the X and Z directions. Word lines (WL) and bit lines (BL) intersect on the plane formed in the X and Z directions, and the DRAM cells are formed at the intersection between WL and BL.

[0077] The second semiconductor structure 304 may include a peripheral circuit structure 3042 disposed on a substrate 3041, the peripheral circuit structure 3042 being connected to the memory cell array 3022. The peripheral circuit structure 3042 may include any suitable digital, analog, and / or mixed-signal peripheral circuitry for facilitating operation of the memory cell array 3022, and in some embodiments may include, for example, a row decoder / word line (WL) driver, a page buffer / sensor amplifier, a column decoder / bit line (BL) driver, an address register, a control logic unit, and input / output (I / O) circuitry, etc.

[0078] The first semiconductor structure 302 and the second semiconductor structure 304 can be bonded together through a bonding layer. For example... Figure 3AThe illustrated semiconductor structure may include a first bonding layer 3024 and a second bonding layer 3044. The first bonding layer 3024 is disposed on the first semiconductor structure 302, and the second bonding layer 3044 is disposed on the second semiconductor structure 304. The first bonding layer 3024 and the second bonding layer 3044 can be bonded together using any suitable bonding technology. This bonding technology may be one or more of the following: hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding. In this disclosure, the embodiments are illustrated using hybrid bonding technology as an example, but this is not a limitation.

[0079] The bonding layer may include interconnected contact structures and connection structures. The contact structures are used for electrical connection between the first and second bonding layers. The contact structures are connected to interconnect structures via connection structures, which are correspondingly connected to the memory cell array or peripheral circuitry. Figure 3A Taking the first semiconductor structure 302 as an example, the first bonding layer 3024 disposed therein may include a contact structure 310 and a connection structure 308.

[0080] The semiconductor structure may further include an interconnect layer stacked along the Y-direction with the bonding layer, wherein the interconnect structure at least partially penetrates the interconnect layer along the Y-direction, connecting corresponding components and interconnect structures. (See reference...) Figure 3A A first interconnect layer 3026 is disposed on the first semiconductor structure 302 and stacked with the first bonding layer 3024 along the Y direction. A second interconnect layer 3046 is disposed on the second semiconductor structure 304 and stacked with the second bonding layer 3044 along the Y direction. Taking the first semiconductor structure 302 as an example, it includes an interconnect structure 306 that at least partially penetrates the first interconnect layer 3026 along the Y direction. The contact structure 310 connects the interconnect structure 306 through the connection structure 308 to connect to the memory cell array 3022 (e.g., the interconnect structure 306 is connected to WL as shown in FIG3).

[0081] Figure 3B A schematic cross-sectional view of another semiconductor structure is shown according to an exemplary embodiment. The semiconductor structure provided in this disclosure can be a semiconductor device, for example, it can be... Figures 1 to 2B NAND flash memory in computers. For example... Figure 3B The semiconductor structure shown may include, for example: Figure 6 The semiconductor structure shown may include a first semiconductor structure 302 and a second semiconductor structure 304. A memory cell array 3022' is disposed in the first semiconductor structure 302, and peripheral circuitry 3042 is disposed in the second semiconductor structure 304. The memory cell array 3022' may be arranged in a vertical direction (e.g., Figure 3B The stacked structure (in the Y direction) provides the gate conductive layer of the transistor (including the select gate and WL), using a structure along the stacking direction (e.g., Figure 3BA channel structure (in the Y direction) penetrating the stacked structure provides the channel layer for transistors and also forms bit lines to connect the channel structure to the memory cells formed by the gate conductive layer. (See reference...) Figure 6 The gate conductive layer can extend on planes formed in the X and Z directions. The memory cell array 3022' can be formed in certain areas on the substrate 3021.

[0082] Figure 3B Zhongyu Figure 3A The same identifier can represent the same meaning. It will be understood by those skilled in the art that... Figure 3B Zhongyu Figure 3A The structures representing the same meaning can be adjusted in terms of connection, process, and number of elements according to the differences in actual operation between DRAM and NAND memory, and are not limited to being exactly the same.

[0083] Figure 3C A cross-sectional schematic diagram of another semiconductor structure is shown according to an exemplary embodiment. The semiconductor structure provided in this disclosure can be... Figures 1 to 2B The DRAM memory in the memory can be, for example, a high-performance DRAM memory based on 3D stacking technology, such as high-bandwidth memory (HBM). Figure 3C The semiconductor structure shown may include multiple first semiconductor structures 302' and second semiconductor structures 304', and each first semiconductor structure 302' may include a DRAM memory cell array. Figure 3C (Not shown, but could be a memory cell array 3022), the second semiconductor structure 304' may include a peripheral circuit structure ( Figure 3C (Not shown in the image), multiple first semiconductor structures 302' and second semiconductor structures 304' can be along... Figure 3A The memory is formed by stacking the components together in the Y direction.

[0084] Two adjacent first semiconductor structures 302' can be bonded together using a bonding layer, and adjacent first semiconductor structures 302' and second semiconductor structures 304' can also be bonded together using a bonding layer. The first semiconductor structure 302' may include a first bonding layer 3024', and the second semiconductor structure 304' may include a second bonding layer 3044'. Two adjacent first bonding layers 3024' and adjacent first bonding layers 3024' and second bonding layers 3044' can all be bonded together using bonding technology. An implementation of the first bonding layer 3024' can be found in [reference needed]. Figure 3A The implementation methods of the first bonding layer 3024 and the second bonding layer 3044' can be referred to Figure 3A The second bonding layer 3044 in the middle.

[0085] The first semiconductor structure 302' and the second semiconductor structure 304' may also include an interconnect layer stacked along the Y direction with the bonding layer. Figure 3C (Not shown in the diagram), the interconnect structure at least partially penetrates the interconnect layer along the Y direction, connecting the corresponding components and the connection structure. Implementation methods may also refer to... Figure 3A .

[0086] In the formation of such Figure 3A He Ru Figure 3B When forming the semiconductor structure shown, a first semiconductor structure 302 and a second semiconductor structure 304 are typically formed first, and then a first bonding layer 3024 and a second bonding layer 3044 are bonded together. In some embodiments, back-alignment may be required when aligning the first bonding layer 3024 and the second bonding layer 3044. Similarly, when forming such a semiconductor structure... Figure 3C In the semiconductor structure shown, when aligning the two first bonding layers 3024' to be bonded, and when aligning the first bonding layer 3024' and the second bonding layer 3044' to be bonded, reverse alignment may also be required. The following will all use... Figure 3A and Figure 3B The bonding of the first bonding layer 3024 and the second bonding layer 3044 in this embodiment is used as an example for illustration, but it is not limited thereto. The bonding layers and related bonding methods provided in this disclosure can be applied to any semiconductor structure that needs bonding, such as... Figure 3C The two adjacent first bonding layers 3024' and the adjacent first bonding layer 3024' and second bonding layer 3044' in the middle.

[0087] Figure 4 A schematic diagram of bonding back-complementation of a semiconductor structure is shown according to an exemplary embodiment. Figure 4 As shown, during the bonding process, when aligning the contact structure 310 in the first bonding layer 3024 and the contact structure 310' in the second bonding layer 3044, it may be necessary to move it along the X direction to increase the contact area of ​​the electrically connected contact structures 310 and 310'. This process can be called "reverse alignment". Ideally, the contact structures 310 and 310' should be moved until their contact surfaces completely overlap. In reality, the distance the contact structure moves is limited by the difference between its width along the X direction and the width of the connecting structure along the X direction. It is necessary to ensure that the end face of the connecting structure is completely connected to the contact structure. Refer to... Figure 4 The maximum distance that the contact structure 310 can move along the X direction is m (which allows the end face of the connecting structure 308 to be fully connected with the contact structure 310), which can be called its back-complementary window of m.

[0088] As the feature size of semiconductor devices shrinks, the center distance between transistors and / or interconnects also decreases, resulting in less and less space available for bonding process back-complementation. Furthermore, the requirements for bonding alignment become increasingly stringent. Therefore, it is particularly important to solve the technical problem of increasing bonding back-complementation space.

[0089] Figure 5 A cross-sectional schematic diagram of a bonding layer provided in an embodiment of this disclosure is shown. For example... Figure 5 As shown, the bonding layer 502 can be along the second direction (e.g., Figure 5 It extends in the X direction and can extend along a third direction (such as...). Figure 5 The bonding layer 502 can extend along the Z-direction, meaning it can extend in the XZ plane. The bonding layer 502 may include interconnected contact structures 504 and connection structures 506, with the contact structure 504 extending along the first direction (e.g., the Z-direction). Figure 5 The connection structure 506 penetrates at least partially through the bonding layer 502 in the Y direction, and the connection structure 506 penetrates at least partially through the bonding layer 502 in the first direction. The ratio of the depth h of the connection structure 506 in the first direction to its width d1 in the second direction is not less than 2.7.

[0090] According to the semiconductor structure provided in the embodiments of this disclosure, the semiconductor structure includes a bonding layer extending along a second direction, a contact structure and a connection structure connected together and both at least partially penetrating the bonding layer along a first direction. By setting the ratio of the depth of the connection structure along the first direction to its width along the second direction to be not less than 2.7, the width of the connection structure along the second direction can be shortened, and the width difference between the contact structure and the connection structure along the second direction can be increased, thereby increasing the bonding back-compensation window of the semiconductor structure. This avoids providing a back-compensation window through sacrifices in circuit design or winding layers, and meets the bonding back-compensation requirements of the reduced center distance between transistors and / or interconnects.

[0091] In some embodiments, the contact structure may include a first conductive material, and the connection structure may include a second conductive material, which is different from the first conductive material.

[0092] According to the semiconductor structure provided in the embodiments of this disclosure, by employing contact structures and connection structures including different conductive materials, the ratio of the depth of the connection structure along the first direction to its width along the second direction can be made not less than 2.7.

[0093] In some embodiments, the first conductive material may be copper, and the second conductive material may be tungsten.

[0094] In some embodiments, the ratio of the depth of the connection structure along the first direction to its width along the second direction is between 10 and 50.

[0095] In some embodiments, the cross-section of the contact structure parallel to the first plane is trapezoidal, and the cross-section of the connecting structure parallel to the first plane is also trapezoidal. The first plane is parallel to both the first and second directions, and the shorter side of the trapezoidal cross-section of the contact structure is connected to the longer side of the trapezoidal cross-section of the connecting structure. (Continue referring to...) Figure 5 The first direction corresponds to Figure 5 In the Y direction, the second direction corresponds to Figure 5 In the X direction, the first plane can correspond to Figure 5 In the XY plane, the cross section of the contact structure 504 parallel to the XY plane can be trapezoidal, and the cross section of the connecting structure 502 parallel to the XY plane is trapezoidal. The short side (side with length w1) of the trapezoidal cross section of the contact structure 504 is connected to the long side (side with length d1) of the trapezoidal cross section of the connecting structure 502.

[0096] In some embodiments, the connecting structure may include a first end and a second end disposed opposite to each other in a first direction, the first end of the connecting structure being connected to a contact structure, and the width of the contact structure along the second direction being greater than the width of the first end of the connecting structure along the second direction. (Continuing to refer to...) Figure 5 The connecting structure 506 may include a first end 50602 and a second end 50604 disposed opposite each other in the Y direction. The first end 50602 of the connecting structure 506 is connected to the contact structure 504. Taking the cross-section of the connecting structure 502 parallel to the XY plane as a trapezoid as an example, the first end 50602 can be one end of the long side of the trapezoidal cross-section, and the second end 50604 can be one end of the short side of the trapezoidal cross-section. The width of the contact structure 504 in the X direction (for example, it can be w1) is greater than the width d1 of the first end 50602 of the connecting structure 506 in the X direction. Taking the cross-section of the contact structure 504 parallel to the XY plane as a trapezoid as an example, the width w1 of the contact structure 504 in the X direction is greater than the width d1 of the first end 50602 of the connecting structure 502 in the X direction, and (w1-d1) / 2 is the back-complementary window in this case.

[0097] In some embodiments, the width of the first end of the connection structure along the second direction is no greater than 120 nanometers. For example, the width d1 of the first end 50602 of the connection structure 506 along the X direction can be 110 nanometers.

[0098] In some embodiments, the width of the first end of the connection structure along the second direction is no greater than 105 nanometers. For example, the width d1 of the first end 50602 of the connection structure 506 along the X direction can be 105 nanometers, 100 nanometers, etc.

[0099] In some embodiments, the difference between half the width of the contact structure along the second direction and half the width of the first end of the connecting structure along the second direction is not less than 80 nanometers. Taking the example that the width w1 of the contact structure 504 along the X direction is greater than the width d1 of the first end 50602 of the connecting structure 502 along the X direction, w1 / 2-d1 / 2 is not less than 80 nanometers, for example, it can be 80 nanometers, 90 nanometers, 100 nanometers, etc.

[0100] In some embodiments, the width of the second end of the connection structure along the second direction is no greater than 100 nanometers. For example, the width d2 of the second end 50604 of the connection structure 506 along the X direction (refer to...) Figure 7 It can be 90 nanometers, or 80 nanometers, etc.

[0101] In some embodiments, the width of the second end of the connection structure along the second direction is no greater than 70 nanometers. For example, the width d2 of the second end 50604 of the connection structure 506 along the X direction (refer to...) Figure 7 It can be 70 nanometers, or 65 nanometers, etc.

[0102] In some embodiments, the bonding layer may include a first dielectric layer and a second dielectric layer stacked along a first direction, a contact structure penetrating the first dielectric layer along the first direction, and a connection structure at least partially penetrating the second dielectric layer along the first direction. (Continuing to refer to...) Figure 5 The bonding layer 502 may include a first dielectric layer 5022 and a second dielectric layer 5024 stacked along the Y direction, the contact structure 504 penetrates the first dielectric layer 5022 along the Y direction, and the connection structure 506 penetrates at least partially through the second dielectric layer 5024 along the Y direction.

[0103] In some embodiments, the first dielectric layer comprises a nitrogen-doped silicon carbide material, and the second dielectric layer comprises an oxide material, which may be represented as OX and typically includes silicon dioxide (SiO2).

[0104] Figure 6 A cross-sectional schematic diagram of another bonding layer provided in an embodiment of this disclosure is shown. Figure 6 and Figure 5 The difference is that, Figure 6 The connection structure 506 may include a first conductive layer 5062 and a second conductive layer 5064. In the X direction, the first conductive layer 5062 is disposed between the second conductive layer 5064 and the second dielectric layer 5024.

[0105] In some embodiments, the first conductive layer may include at least one of tantalum, tantalum nitride, titanium, and titanium nitride, for example, a mixture of tantalum and tantalum nitride, or, more specifically, a mixture of titanium and titanium nitride. The second conductive layer may include tungsten.

[0106] Figure 7according to Figure 5 A cross-sectional schematic diagram of a semiconductor structure provided in an embodiment of this disclosure is shown. For example... Figure 7 As shown, in Figure 5 Based on this, the semiconductor structure may further include an interconnect layer 702 and an interconnect structure 704, with the bonding layer 502 and the interconnect layer 704 stacked along the Y direction, the interconnect structure 704 penetrating at least partially through the interconnect layer 702 along the Y direction, and the interconnect structure 704 connected to the second end 50604 of the connection structure.

[0107] In some embodiments, the width of the interconnect structure along the second direction is greater than the width of the second end of the connection structure along the second direction. (Continuing to refer to...) Figure 7 The width w2 of the interconnect structure 704 along the X direction is greater than the width d2 of the second end 50604 of the connection structure along the X direction.

[0108] In some embodiments, in a first direction, a first conductive layer is disposed between the second conductive layer and the interconnect structure. Continuing with reference to... Figure 7 ,exist Figure 6 Based on this, the connection structure 506 may further include a first conductive layer 5062 disposed between the second conductive layer 5064 and the interconnection structure 704.

[0109] In some embodiments, the interconnect layer may include silicon nitride material, and the interconnect structure may include copper material.

[0110] When performing bonding backcompensation on a semiconductor, the distance the contact structure can move along the second direction is limited by the difference between its width along the second direction and the width of the interconnect structure along the second direction. According to the semiconductor structure formation method provided in this disclosure, by forming the connection structure and the contact structure separately, the ratio of the depth of the connection structure along the first direction to its width along the second direction can be made not less than 2.7. This increases the width difference between the contact structure, the connection structure, and the interconnect structure along the second direction, thereby increasing the bonding backcompensation window of the semiconductor structure.

[0111] Figure 8 This is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment. Figure 8 The method shown may include, for example, forming using Figure 5 or Figure 6 The bonding layer shown Figure 3A or Figure 3B Partial steps of the semiconductor structure shown.

[0112] refer to Figure 8 The method 80 provided in this embodiment may include the following steps S802 to S804. Figures 13 to 19 It shows Figure 3A or Figure 3BThe diagram shows cross-sectional views of some process nodes during the formation of the semiconductor structure. Figure 8 (as well as Figures 9 to 12 The formation method described in this paper will be illustrated in conjunction with these cross-sectional diagrams.

[0113] In step S802, an interconnect layer and an interconnect structure are provided, wherein the interconnect structure at least partially penetrates the interconnect layer along a first direction, and the interconnect layer extends along a second direction, wherein the first direction is perpendicular to the second direction.

[0114] In some embodiments, corresponding components may be formed on a substrate, and then an interconnect layer may be formed thereon, with interconnect structures penetrating at least a portion of the interconnect layer and connected to the corresponding components. For example, to form Figure 3A Taking the first semiconductor structure 302 in the semiconductor structure shown as an example, transistors, bit line contact modules and bit lines, memory node contact modules, capacitors and other structures can be formed on the substrate 3021 extending in the XZ plane to form a DRAM memory cell array 3022. Then, the word lines, bit lines and other structures of the DRAM memory cell array 3022 are led out and an interconnect layer 3026 is formed. Then, an interconnect structure 306 is formed that at least partially penetrates the interconnect layer 3026 along the first direction. The interconnect structure 306 is connected to the corresponding structures in the word lines, bit lines and other structures.

[0115] For example, to form Figure 3A Taking the second semiconductor structure 304 in the semiconductor structure shown as an example, a peripheral circuit 3042 structure can first be formed on a substrate 3041 extending in the XZ plane, then the peripheral circuit 3042 structure can be led out and an interconnect layer 3046 can be formed, and then an interconnect structure that at least partially penetrates the interconnect layer 3046 along the first direction can be formed. Figure 3A The interconnect structure of the second semiconductor structure 304 is not shown in the figure.

[0116] Figure 13 A cross-sectional schematic diagram of an interconnect layer and an interconnect structure is shown according to an exemplary embodiment. Figure 13 As shown, the interconnect structure 704 partially penetrates the interconnect layer 702.

[0117] In step S804, a bonding layer is formed on the interconnect layer. The bonding layer includes a connection structure, wherein: the connection structure at least partially penetrates the bonding layer along a first direction, the connection structure is connected to the interconnect structure, and the ratio of the depth of the connection structure along the first direction to its width along the second direction is not less than 2.7.

[0118] In some embodiments, a second dielectric layer for bonding can be formed on the interconnect layer, and then a connection structure penetrating the second dielectric layer can be formed. Exemplary embodiments may refer to... Figure 9 .

[0119] According to the semiconductor structure formation method provided in the embodiments of this disclosure, by forming a connection structure and a contact structure respectively, the ratio of the depth of the connection structure along the first direction to its width along the second direction can be not less than 2.7, thereby increasing the width difference between the contact structure and the interconnect structure along the second direction and increasing the bonding back-complementary window of the semiconductor structure.

[0120] Figure 9 It shows Figure 8 The diagram shown illustrates step S804 in one embodiment. Figure 9 As shown in the present embodiment, step S804 may further include steps S902 to S906.

[0121] Step S902: A second dielectric layer is formed on the interconnect layer.

[0122] In some embodiments, an oxide material thin film may be deposited on the surface of the interconnect layer to form a second dielectric layer.

[0123] Figure 14 A schematic cross-sectional view of a second dielectric layer formed on an interconnect layer is shown according to an exemplary embodiment. Figure 14 As shown, a second dielectric layer 5024 is formed on the surface of the interconnect layer 702. Figure 14 Interconnect layer 702 in the middle can correspond to Figure 3A or Figure 3B The interconnect layer 3026 or 3046 in the substrate can form a second dielectric layer 5024 on its surface away from the substrate 3021 or 3041.

[0124] In step S904, a via is formed by penetrating the second dielectric layer at the position corresponding to the interconnect structure on the second dielectric layer. The ratio of the depth of the via along the first direction to its width along the second direction is not less than 2.7.

[0125] In some embodiments, a via can be formed on the second dielectric layer with the center position of the interconnect structure in the second direction (and a third direction perpendicular to the first and second directions) as the center, using an etching technique such as Chemical Mechanical Polishing (CMP), to penetrate the second dielectric layer along the first direction to expose the corresponding interconnect structure. The ratio of the depth of the via along the first direction to its width along the second direction can be set to be not less than 2.7.

[0126] Figure 15 A cross-sectional schematic diagram of a through-hole formed on a second dielectric layer is shown according to an exemplary embodiment. Figure 15 As shown, a via 1502 is formed in the second dielectric layer 5024, penetrating the second dielectric layer along the Y direction, and the via 1502 exposes the interconnect structure 704.

[0127] Step S906: Form a connection structure in the through hole.

[0128] In some embodiments, a first conductive layer and a second conductive layer may be sequentially formed in the through-hole to form a connection structure. Exemplary embodiments can be referred to [reference needed]. Figure 10 .

[0129] Figure 10 It shows Figure 9 The step S906 shown is a schematic diagram of the processing procedure in one embodiment. (See attached diagram.) Figure 10 As shown in the present embodiment, step S906 may further include steps S1002 to S1004.

[0130] Step S1002: A first conductive layer is formed on the bottom surface and sidewall of the through hole.

[0131] In some embodiments, at least one thin film of tantalum, tantalum nitride, titanium, or titanium nitride can be formed on the bottom surface and sidewalls of the via first, so that the second conductive layer (e.g., tungsten) for subsequent filling can better adhere to the bottom surface and sidewalls of the via and prevent the diffusion of the second conductive layer.

[0132] Figure 16 A cross-sectional schematic diagram of forming a first conductive layer in a via is shown according to an exemplary embodiment. Figure 16 As shown, a first conductive layer 5062 is deposited on the bottom surface and sidewalls of the via 1502. In some embodiments, the first conductive layer 5062 may be deposited simultaneously on the bottom surface and sidewalls of the via 1502 and on the surface of the second dielectric layer 5024. Figure 16 (Not shown in the image).

[0133] Step S1004: A second conductive layer is formed on the surface of the first conductive layer in the through hole.

[0134] In some embodiments, a second conductive layer may be deposited on the surface of the first conductive layer in the via.

[0135] Figure 17 A cross-sectional schematic diagram showing a second conductive layer formed on the surface of a first conductive layer is illustrated according to an exemplary embodiment. Figure 17 As shown, a second conductive layer 5064 is deposited on the surface of the first conductive layer 5062 in the via 1502. In some embodiments, the second conductive layer 5064 may be deposited simultaneously on the surface of the first conductive layer 5062 on the surface of the second dielectric layer 5024 and on the surface of the first conductive layer 5062 in the via 1502. Figure 17 (Not shown), and then the first conductive layer 5062 and the second conductive layer 5064 on the surface of the second dielectric layer 5024 are removed by etching (only the first conductive layer 5062 and the second conductive layer 5064 in the via 1502 are retained).

[0136] Figure 11 It shows Figure 8 The diagram illustrates step S804 in another embodiment. (See attached diagram.) Figure 11 As shown in the present embodiment, step S804 may further include steps S1102 to S1104.

[0137] Step S1102: Form the first dielectric layer on the second dielectric layer.

[0138] In some embodiments, a nitrogen-doped silicon carbide thin film may be deposited on the surface of the second dielectric layer to form the first dielectric layer.

[0139] Figure 18 A schematic cross-sectional view showing the formation of a first dielectric layer on a second dielectric layer is shown according to an exemplary embodiment. Figure 18 As shown, a first dielectric layer 5022 is formed on the surface of the second dielectric layer 5024.

[0140] In step S1104, a contact structure is formed at the position of the corresponding connection structure in the first dielectric layer, and the width of the contact structure along the second direction is greater than the width of the connection structure along the second direction.

[0141] In some embodiments, a groove may be formed at the location of the corresponding connection structure in the first dielectric layer, and then a conductive material may be filled into the groove to form a contact structure. An exemplary embodiment may be referred to. Figure 12 .

[0142] Figure 12 It shows Figure 11 The diagram illustrates step S1104 in another embodiment. (See attached diagram.) Figure 12 As shown in the present embodiment, step S1104 may further include steps S1202 to S1204.

[0143] In step S1202, a groove is formed at the position of the corresponding connection structure in the first dielectric layer, and the width of the groove along the second direction is greater than the width of the connection structure along the second direction.

[0144] In some embodiments, a groove can be formed on the first dielectric layer with the center position of the connection structure in the second direction (and a third direction perpendicular to the first and second directions) as the center, using an etching technique to penetrate the second dielectric layer along the first direction to expose the corresponding connection structure. The width of the groove along the second direction can be set to be greater than the width of the connection structure along the second direction.

[0145] Step S1204: Form a contact structure in the groove.

[0146] In some embodiments, copper material may be deposited in the groove to form a contact structure.

[0147] Figure 19 A cross-sectional schematic diagram showing a contact structure formed in a first dielectric layer is illustrated according to an exemplary embodiment. Figure 19 As shown, a contact structure 504 is formed at the position of the corresponding connection structure (5062, 5064) of the first dielectric layer 5022.

[0148] According to the semiconductor structure formation method provided in this disclosure, the connection structure and the contact structure are formed by a single damask process, which can achieve a ratio of the depth of the connection structure along the first direction to its width along the second direction of not less than 2.7, thereby increasing the width difference between the contact structure and the connection structure and the interconnect structure along the second direction, increasing the bonding back-complementary window of the semiconductor structure, and providing feasibility for the air gap process of the interconnect structure for the second semiconductor structure.

[0149] Exemplary embodiments of this disclosure have been specifically shown and described above. It should be understood that this disclosure is not limited to the detailed structures, arrangements, or implementations described herein; rather, this disclosure is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A semiconductor structure, characterized in that, The bonding layer includes a bonding layer extending along a second direction, the bonding layer comprising interconnected contact structures and connection structures, wherein: The contact structure at least partially penetrates the bonding layer along a first direction, the first direction being perpendicular to the second direction; The connection structure at least partially penetrates the bonding layer along the first direction, and the ratio of the depth of the connection structure along the first direction to its width along the second direction is not less than 2.

7.

2. The semiconductor structure according to claim 1, characterized in that, The contact structure includes a first conductive material, and the connection structure includes a second conductive material, which is different from the first conductive material.

3. The semiconductor structure according to claim 2, characterized in that, The first conductive material is copper, and the second conductive material is tungsten.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The ratio of the depth of the connection structure along the first direction to its width along the second direction is between 10 and 50.

5. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The connecting structure includes a first end and a second end disposed opposite to each other in the first direction. The first end of the connecting structure is connected to the contact structure, and the width of the contact structure along the second direction is greater than the width of the first end of the connecting structure along the second direction.

6. The semiconductor structure according to claim 5, characterized in that, The width of the first end of the connection structure along the second direction is no greater than 120 nanometers.

7. The semiconductor structure according to claim 6, characterized in that, The width of the first end of the connection structure along the second direction is no greater than 105 nanometers.

8. The semiconductor structure according to claim 5, characterized in that, The difference between half the width of the contact structure along the second direction and half the width of the first end of the connection structure along the second direction is not less than 80 nanometers.

9. The semiconductor structure according to claim 5, characterized in that, The width of the second end of the connection structure along the second direction is no greater than 100 nanometers.

10. The semiconductor structure according to claim 9, characterized in that, The width of the second end of the connection structure along the second direction is no greater than 70 nanometers.

11. The semiconductor structure according to claim 5, characterized in that, It also includes an interconnect layer and an interconnect structure, wherein the bonding layer and the interconnect layer are stacked along the first direction, the interconnect structure at least partially penetrates the interconnect layer along the first direction, and the interconnect structure is connected to a second end of the connection structure.

12. The semiconductor structure according to claim 11, characterized in that, The width of the interconnect structure along the second direction is greater than the width of the second end of the connection structure along the second direction.

13. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The bonding layer includes a first dielectric layer and a second dielectric layer stacked along the first direction, the contact structure penetrates the first dielectric layer along the first direction, and the connection structure at least partially penetrates the second dielectric layer along the first direction.

14. The semiconductor structure according to claim 13, characterized in that, The first dielectric layer comprises nitrogen-doped silicon carbide material, and the second dielectric layer comprises oxide material.

15. The semiconductor structure according to claim 14, characterized in that, The connection structure includes a first conductive layer and a second conductive layer, wherein: In the second direction, the first conductive layer is disposed between the second conductive layer and the second dielectric layer.

16. The semiconductor structure according to claim 15, characterized in that, It also includes an interconnect layer and an interconnect structure, wherein the bonding layer and the interconnect layer are stacked along the first direction, the interconnect structure at least partially penetrates the interconnect layer along the first direction, and the interconnect structure is connected to the connection structure; In the first direction, the first conductive layer is disposed between the second conductive layer and the interconnect structure.

17. The semiconductor structure according to claim 15, characterized in that, The first conductive layer includes at least one of tantalum, tantalum nitride, titanium, and titanium nitride, and the second conductive layer includes tungsten.

18. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The contact structure has a trapezoidal cross-section parallel to the first plane, and the connection structure has a trapezoidal cross-section parallel to the first plane. The first plane is parallel to both the first direction and the second direction. The short side of the trapezoidal cross-section of the contact structure is connected to the long side of the trapezoidal cross-section of the connection structure.

19. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The device includes a first semiconductor structure and a second semiconductor structure. The bonding layer includes a first bonding layer and a second bonding layer. The first bonding layer is disposed on the first semiconductor structure, and the second bonding layer is disposed on the second semiconductor structure. The contact structure of the first bonding layer is connected to the contact structure of the second bonding layer.

20. A method for forming a semiconductor structure, characterized in that, include: An interconnect layer and an interconnect structure are provided, the interconnect structure at least partially penetrating the interconnect layer along a first direction, the interconnect layer extending along a second direction, the first direction being perpendicular to the second direction; A bonding layer is formed on the interconnect layer, the bonding layer including a connection structure, wherein: The connection structure penetrates at least partially through the bonding layer along a first direction, the connection structure is connected to the interconnect structure, and the ratio of the depth of the connection structure along the first direction to its width along the second direction is not less than 2.

7.

21. The method according to claim 20, characterized in that, The bonding layer further includes a second dielectric layer; A bonding layer is formed on the interconnect layer, including: The second dielectric layer is formed on the interconnect layer; A via is formed by penetrating the second dielectric layer at a position corresponding to the interconnect structure, wherein the ratio of the depth of the via along the first direction to its width along the second direction is not less than 2.

7. The connection structure is formed in the through hole.

22. The method according to claim 21, characterized in that, The connection structure includes a first conductive layer and a second conductive layer; Forming the connection structure in the through hole includes: The first conductive layer is formed on the bottom surface and sidewall of the through hole; A second conductive layer is formed on the surface of the first conductive layer in the through hole.

23. The method according to claim 21 or 22, characterized in that, The bonding layer further includes a first dielectric layer and a contact structure; A bonding layer is formed on the interconnect layer, and the method further includes: The first dielectric layer is formed on the second dielectric layer; The contact structure is formed at the position corresponding to the connection structure in the first dielectric layer, and the width of the contact structure along the second direction is greater than the width of the connection structure along the second direction.

24. The method according to claim 23, characterized in that, The contact structure is formed at the position corresponding to the connection structure in the first dielectric layer, including: A groove is formed at the position of the first dielectric layer corresponding to the connection structure, and the width of the groove along the second direction is greater than the width of the connection structure along the second direction; The contact structure is formed in the groove.

25. A semiconductor device, characterized in that, Includes the semiconductor structure described in any one of claims 1 to 19.

26. A storage system, characterized in that, Includes the semiconductor device as described in claim 25 and a controller coupled to the semiconductor device.

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