Memory device, method of manufacturing memory device, and memory system

Abstract

The application discloses a memory device, a manufacturing method of the memory device, and a storage system. The memory device comprises a plurality of semiconductor bodies, a plurality of storage structures, and a plurality of word lines. The semiconductor body comprises a first body and a second body. The first body comprises a first end portion and a second end portion opposite to each other along a first direction. The second body comprises a third end portion and a fourth end portion opposite to each other along the first direction. The plurality of semiconductor bodies are arranged in a row along a second direction and in a column along a third direction. The first direction, the second direction, and the third direction intersect with each other in pairs. The plurality of storage structures are arranged correspondingly to the plurality of semiconductor bodies. One storage structure is coupled to the first end portion and the third end portion of the same semiconductor body. The plurality of word lines are arranged in sequence along the third direction of the array. The word line extends along the second direction of the array and is coupled to each semiconductor body in the same row. The word line is located between the first body and the second body of the same semiconductor body. The application can improve the comprehensive performance of the memory device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a storage device, a method for manufacturing the storage device, and a storage system. Background Technology

[0002] Memory devices are one of the most important components in electronic systems. With the rapid development of semiconductor technology, optimizing the overall performance of memory devices has become a key research direction in the industry. Summary of the Invention

[0003] This application provides a storage device, a method for manufacturing the storage device, and a storage system for optimizing the overall performance of the storage device.

[0004] According to one aspect of this application, a memory device is provided, comprising a plurality of semiconductor bodies arranged in an array, a plurality of memory structures, and a plurality of word lines. Each semiconductor body includes a first body and a second body. The first body includes a first end and a second end opposite each other along a first direction. The second body includes a third end and a fourth end opposite each other along the first direction. The first direction, the second direction, and the third direction intersect each other. The plurality of memory structures are correspondingly disposed with the plurality of semiconductor bodies, and one memory structure is coupled to the first end and the third end of the same semiconductor body. The plurality of word lines are arranged sequentially along the third direction, extending along a second direction and coupled to each of the semiconductor bodies in the same row. The word lines are located between the first body and the second body of the same semiconductor body.

[0005] In some embodiments, the word lines are coupled to the first body and the second body on opposite sides along the third direction, respectively.

[0006] In some embodiments, the memory device further includes a gate oxide structure located between the word line and the first body.

[0007] In some embodiments, the memory device further includes a gate oxide structure located between the word line and the second body.

[0008] In some embodiments, the end face of the first body facing one end of the storage structure, the end face of the second body facing one end of the storage structure, and the end face of the gate oxide structure facing one end of the storage structure are flush.

[0009] In some embodiments, the memory device further includes bit lines coupled to the second end and the fourth end of the semiconductor body.

[0010] In some embodiments, the memory device includes a plurality of bit lines, which are spaced apart along the second direction; the bit lines extend along the third direction and are coupled to the second end and the fourth end of the semiconductor body in the same column.

[0011] In some embodiments, the storage device further includes a shielding structure comprising a plurality of shielding portions spaced apart along the third direction; the shielding portions being located between two adjacent rows of the semiconductor bodies.

[0012] In some embodiments, along the third direction, the shielding portion and the word line are arranged alternately.

[0013] In some embodiments, the storage device further includes a plurality of storage node contacts disposed corresponding to a plurality of semiconductor bodies, wherein one end of the storage node contact is coupled to the storage structure along the first direction, and the other end is coupled to the first end and the third end of the same semiconductor body.

[0014] In some embodiments, the storage structure includes a capacitor coupled to the first end and the third end of the same semiconductor body.

[0015] According to another aspect of this application, a method for manufacturing a storage device is provided, comprising the following steps:

[0016] Multiple semiconductor bodies are arranged in an array. The semiconductor bodies include a first body and a second body. The first body includes a first end and a second end opposite to each other along a first direction. The second body includes a third end and a fourth end opposite to each other along the first direction. The first direction, the second direction, and the third direction intersect each other.

[0017] Multiple word lines are formed in sequence along a third direction. The word lines extend along a second direction and are coupled to each of the semiconductor bodies in the same row. The word lines are located between the first body and the second body of the same semiconductor body.

[0018] A plurality of memory structures are provided, and the plurality of memory structures are correspondingly disposed with a plurality of semiconductor bodies, wherein one memory structure is coupled to a first end and a third end of the same semiconductor body.

[0019] In some embodiments, it also includes:

[0020] Provides a semiconductor layer;

[0021] Multiple grooves are arranged at intervals on the semiconductor layer to form multiple arrayed semiconductor pillars. The multiple semiconductor pillars include multiple first bodies and multiple second bodies. Along the third direction, a first body and an adjacent second body constitute the semiconductor body.

[0022] A first conductive material is disposed between the first body and the second body of the same semiconductor body to form the word line.

[0023] In some embodiments, it also includes:

[0024] A second conductive material is disposed between two adjacent semiconductor bodies along the third direction to form a shielding portion located between two adjacent rows of semiconductor bodies.

[0025] In some embodiments, it also includes:

[0026] Multiple storage node contacts are formed, and one end of each storage node contact along the first direction is coupled to the first end and the third end of the same semiconductor body;

[0027] The storage structure is coupled to the other end of the storage node contact portion along the first direction.

[0028] According to another aspect of this application, a storage system is provided, comprising:

[0029] As described above, the storage device is configured to store data;

[0030] A controller, coupled to the storage device and configured to control the storage device.

[0031] The memory device of this application adjusts the relative positions of word lines, semiconductor body, and memory structure, coupling two parts of a semiconductor body to the same memory structure, i.e., the first body and the second body are coupled to the same memory structure, and the word lines are arranged between the first body and the second body of the same semiconductor body, so that adjacent word lines are separated, thereby improving the problem of short circuit between adjacent word lines and thus optimizing the overall performance of the memory device. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A schematic diagram of the structure of a storage device according to an embodiment of this application is shown.

[0034] Figure 2 A top view of a storage device according to an embodiment of this application is shown.

[0035] Figure 3 It shows along Figure 2 Cross-sectional view along the AA direction.

[0036] Figure 4 A schematic diagram illustrating the formation process of the basic structure of the storage device in one embodiment of this application is shown.

[0037] Figure 5 A schematic diagram of the formation process of the semiconductor body of the memory device in one embodiment of this application is shown.

[0038] Figure 6 It shows along Figure 5 Cross-sectional view in the BB direction.

[0039] Figure 7 A schematic diagram of the word line formation process of a memory device in one embodiment of this application is shown.

[0040] Figure 8 A schematic diagram of the formation process of the storage node contact portion of the storage device in one embodiment of this application is shown.

[0041] Figure 9 A schematic diagram illustrating the formation process of the storage structure of a storage device in one embodiment of this application is shown.

[0042] Figure 10 A schematic diagram showing the storage structure and coupling of the storage device with the peripheral circuitry in one embodiment of this application is shown.

[0043] Figure 11 and Figure 12 A schematic diagram of the bit line formation process of a memory device in one embodiment of this application is shown.

[0044] Figure 13 A schematic diagram of a storage system according to an embodiment of this application is shown.

[0045] Explanation of reference numerals in the attached figures:

[0046] 10000, Electronic devices;

[0047] 1000, Storage system; 100, Storage device; 200, Controller; 2000, Host;

[0048] 100a, Storage array; 100b, Storage cell; 100c, Peripheral circuitry;

[0049] 10. Semiconductor body; 10a. Basic structure; 10b. Initial isolation layer; 10c. Intermediate semiconductor layer; 10a1. Groove; 10a2. Semiconductor pillar; 11. First body; 111. First end; 112. Second end; 12. Second body; 121. Third end; 122. Fourth end;

[0050] 20. Storage structure;

[0051] 30. Word line; 31. Gate oxide structure; 32. Gate metal layer;

[0052] 40. Bit line;

[0053] 50. Shielding structure; 51. Shielding part;

[0054] 60. Storage node contact section;

[0055] X, first direction; Y, second direction; Z, third direction. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0057] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0058] See Figure 1 Some embodiments of this application provide a memory device 100, including peripheral circuitry 100c and a memory array 100a. The peripheral circuitry 100c and the memory array 100a are formed, for example, on different wafers and bonded face-to-face. Compared to side-by-side arrangements, stacked peripheral circuitry 100c and memory array 100a can reduce chip size and improve array efficiency. Optionally, more than one memory array 100a may be stacked together using bonding technology to further improve array efficiency.

[0059] Peripheral circuitry 100c includes, for example, digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory array 100a. Exemplarily, peripheral circuitry 100c includes one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line 30 drivers), input / output (I / O) circuitry, charge pumps, voltage sources or voltage generators, current or voltage references, portions (e.g., sub-circuits) of the aforementioned functional circuitry, or active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). Exemplarily, peripheral circuitry 100c is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

[0060] Storage array 100a includes, for example, a dynamic random access memory (DRAM) array. Storage array 100a includes multiple storage cells 100b arranged in an array.

[0061] Combined Figure 2 and Figure 3 Specifically, the memory array 100a includes multiple semiconductor bodies 10, multiple memory structures 20 corresponding to the multiple semiconductor bodies 10, and multiple word lines 30. The multiple semiconductor bodies 10 are arranged in rows along the second direction Y and in columns along the third direction Z.

[0062] The semiconductor body 10 includes a first body 11 and a second body 12. The first body 11 and the second body 12 may be made of the same or different materials. The material of the first body 11 includes, for example, at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The material of the second body 12 includes, for example, at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0063] The cross-sectional shape of the first main body 11 in the plane parallel to the second direction Y and the third direction Z is the same as or different from the cross-sectional shape of the second main body 12 in the same plane. The cross-sectional shape of the first main body 11 in the plane parallel to the second direction Y and the third direction Z is, for example, one or a combination of a square, rectangle, trapezoid, circle, and ellipse. The cross-sectional shape of the second main body 12 in the plane parallel to the second direction Y and the third direction Z is, for example, one or a combination of a square, rectangle, trapezoid, circle, and ellipse.

[0064] Continue reading Figure 2 and Figure 3 The first body 11 includes a first end 111 and a second end 112 opposite to each other along a first direction X. The first direction X, the second direction Y, and the third direction Z intersect each other, for example, they are perpendicular to each other or the included angle is greater than zero. The first end 111 forms, for example, the source of a vertical gate transistor (VGT), and the second end 112 forms, for example, the drain of a vertical gate transistor.

[0065] Optionally, the first end 111 and the second end 112 are doped with an N-type dopant, which includes any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb).

[0066] Optionally, the first end 111 and the second end 112 are doped with a P-type dopant, which includes any one or a combination of boron (B), gallium (Ga), and indium (In).

[0067] The second body 12 includes a third end 121 and a fourth end 122 opposite to each other along the first direction X, and the first direction X, the second direction Y, and the third direction Z intersect each other. The third end 121 forms, for example, the source of a vertical gate transistor (VGT), and the fourth end 122 forms, for example, the drain of a vertical gate transistor.

[0068] Optionally, the third end 121 and the fourth end 122 are doped with an N-type dopant, which includes any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb).

[0069] Optionally, the third end 121 and the fourth end 122 are doped with a P-type dopant, which includes any one or a combination of boron (B), gallium (Ga), and indium (In).

[0070] Continue reading Figure 2 and Figure 3 The storage structure 20 is, for example, a capacitor. A storage structure 20 is coupled to a first end 111 and a third end 121 of the same semiconductor body 10, meaning the same storage structure 20 is coupled to two parts of the same semiconductor body 10. Exemplarily, the storage structure 20 is coupled to the first end 111 and the third end 121 by contacting storage node contacts (SNCs) located at the first end 111 and the third end 121.

[0071] Multiple word lines 30 are arranged sequentially along the third direction Z, and extend along the second direction Y, coupled to each semiconductor body 10 in the same row. Exemplarily, the memory device 100 also includes multiple gate structures, each corresponding to a semiconductor body 10. One gate structure is located on one side of a corresponding semiconductor body 10 along the third direction Z and coupled to that semiconductor body 10. The semiconductor body 10, the corresponding memory structure 20, and the corresponding gate structure constitute a memory cell 100b, and the multiple memory cells 100b are arranged in an array to form a memory array 100a. Each gate structure in the same row extends continuously along the second direction Y, forming a word line 30 extending along the second direction Y. Multiple rows of gate structures form multiple word lines 30.

[0072] It should be noted that in some embodiments, the word lines of two adjacent memory cells along a third direction are arranged opposite each other, that is, the word lines are located between the semiconductor bodies of two face-to-face memory cells. To improve the array density, conductive material is first deposited in the trench between two adjacent semiconductor bodies. On the front side (FS), i.e., the side where the trench opening is located, a punch etch process is used to break the conductive material in the same trench into two mutually spaced parts along a third direction, forming two mutually spaced word lines along a third direction; or, on the back side (BS), i.e., the side where the trench bottom is located, a recess etch process is used to break the conductive material in the same trench into two mutually spaced parts along a third direction, forming two mutually spaced word lines along a third direction.

[0073] In the case of front-side punching etching, the small process window makes it difficult to completely disconnect the conductive material at the bottom of the trench, resulting in electrical connection between the two word lines and affecting the electrical performance of the final product. In the case of back-side groove etching, since the drain terminal already has a doped region, the groove etching process can easily cause dopants such as phosphorus (P) to precipitate, leading to leakage. Furthermore, the groove etching process can easily damage the semiconductor substrate, such as silicon (Si), which also affects the electrical performance of the final product.

[0074] Furthermore, as the size of memory devices decreases, the dimensions of word lines along the third direction also decrease, leading to excessive word line resistance. Additionally, as the size of memory devices decreases, the space between two face-to-face word lines becomes smaller, which can easily lead to increased coupling between word lines.

[0075] Continue reading Figure 2 and Figure 3Based on this, in this embodiment, the word line 30 is disposed between the first body 11 and the second body 12 of the same semiconductor body 10, so that two adjacent word lines 30 are separated by the first body 11 or the second body 12, which can more effectively prevent short circuits between two adjacent word lines 30, thereby optimizing the overall performance of the memory device 100; and, it simplifies the word line 30 forming process; furthermore, it reduces the resistance of the word line 30.

[0076] In some embodiments, the word line 30 is coupled to the first body 11 and the second body 12 on opposite sides along the third direction Z, respectively; or, the word line 30 is coupled to either the first body 11 or the second body 12 of the semiconductor body 10 on opposite sides along the third direction Z. In other words, both the first body 11 and the second body 12 are coupled to the word line 30 located between them, or one of the first body 11 and the second body 12 is coupled to the word line 30 located between them. In this way, specific portions of the semiconductor body 10 can be flexibly coupled to the word line 30 according to design requirements.

[0077] In some embodiments, the storage device 100 further includes a gate oxide structure 31 located between the word line 30 and the first body 11, or the gate oxide structure 31 located between the word line 30 and the second body 12.

[0078] Optionally, the gate structure includes a gate oxide structure 31 and a gate metal layer 32 sequentially disposed on the sidewall of the first body 11.

[0079] Optionally, the gate structure includes a gate oxide structure 31 and a gate metal layer 32 sequentially disposed on the sidewall of the second body 12.

[0080] Optionally, the gate structure includes a gate oxide structure 31, a gate adhesive layer, and a gate metal layer 32 sequentially disposed on the sidewall of the first body 11.

[0081] Optionally, the gate structure includes a gate oxide structure 31, a gate adhesive layer, and a gate metal layer 32 sequentially disposed on the sidewall of the second body 12.

[0082] Optionally, the gate oxide structure 31 disposed on the side wall of the first body 11 is connected to the gate oxide structure 31 disposed on the side wall of the second body 12.

[0083] In this configuration, the gate metal layers 32 of each gate structure located in the same row extend continuously along the second direction Y, forming word lines 30 extending along the second direction Y. The material of the gate oxide structure 31 includes, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the gate adhesive layer includes, for example, at least one of titanium, titanium nitride, tantalum, and tantalum nitride. The material of the gate metal layer 32 includes, for example, at least one of tungsten, cobalt, copper, aluminum, crystalline silicon, and silicides. The gate adhesive layer can prevent the diffusion of metal material in the gate metal layer 32 and can also improve the adhesion between the gate metal layer 32 and the gate oxide structure 31.

[0084] In some embodiments, the end face of the first body 11 facing one end of the storage structure 20, the end face of the second body 12 facing one end of the storage structure 20, and the end face of the gate oxide structure 31 facing one end of the storage structure 20 are flush. This improves the structural consistency of the storage cells 100b in the storage device 100, which helps to mitigate the impact of structural differences on the performance of the storage device 100.

[0085] Continue reading Figure 2 and Figure 3 In some embodiments, the memory device 100 further includes bit lines 40 coupled to the second end 112 and the fourth end 122 of the semiconductor body 10. Optionally, the memory device 100 includes a plurality of bit lines 40, which are spaced apart along a second direction Y and extend along a third direction Z, and are coupled to the second end 112 and the fourth end 122 of the semiconductor body 10 in the same column. The material of the bit lines 40 includes, for example, at least one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, and silicides.

[0086] Continue reading Figure 2 and Figure 3 In some embodiments, the memory device 100 further includes a shielding structure 50, which includes a plurality of shielding portions 51 arranged at Z intervals along a third direction, the shielding portions 51 being located between two adjacent rows of semiconductor bodies 10. The shielding structure 50 reduces interference between the gate structures of adjacent memory cells 100b, for example, by applying an external fixed voltage.

[0087] Optionally, the shielding structure 50 includes a dielectric layer disposed on the sidewall of the semiconductor body 10 and a conductive layer disposed on the side of the dielectric layer opposite to the semiconductor layer. The material of the dielectric layer includes, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the conductive layer includes, for example, at least one of titanium, titanium nitride, tantalum, and tantalum nitride.

[0088] Furthermore, the shielding structure 51 and the word line 30 are arranged alternately, that is, the shielding structure 50 and the word line 30 are located on opposite sides of the first body 11 along the third direction Z, or the shielding structure 50 and the word line 30 are located on opposite sides of the second body 12 along the third direction Z. In other words, the shielding structure 50 is located between two adjacent semiconductor bodies 10 along the third direction Z. Based on this, the shielding structure 50 can be formed simultaneously during the formation of the word line 30, thereby simplifying the manufacturing process and saving production costs.

[0089] Continue reading Figure 2 and Figure 3 In some embodiments, the storage device 100 further includes a plurality of storage node contacts 60 corresponding to a plurality of semiconductor bodies 10. One end of each storage node contact 60 along a first direction X is coupled to the storage structure 20, and the other end is coupled to a first end 111 and a third end 121 of the same semiconductor body 10. In other words, the storage structure 20 is coupled to the first end 111 and the third end 121 through the storage node contacts 60 located at the ends of the semiconductor bodies 10. This makes the coupling between the storage structure 20 and the semiconductor bodies 10 more convenient, faster, and more accurate.

[0090] In some embodiments, the storage structure 20 includes a capacitor coupled to a first end 111 and a third end 121 of the same semiconductor body 10. Thus, the semiconductor body 10, the corresponding storage structure 20, and the corresponding gate structure constitute a dynamic random access memory cell 100b.

[0091] Based on the same inventive concept, this application also provides a method for manufacturing a storage device, the method comprising the following steps:

[0092] Step S1: Form a plurality of semiconductor bodies arranged in an array. The semiconductor bodies include a first body and a second body. The first body includes a first end and a second end opposite to each other along a first direction. The second body includes a third end and a fourth end opposite to each other along the first direction. The first direction, the second direction, and the third direction intersect each other.

[0093] Step S2: Form multiple word lines arranged sequentially along a third direction. The word lines extend along a second direction and are coupled to each semiconductor body in the same row. The word lines are located between the first and second bodies of the same semiconductor body.

[0094] Step S3: Provide multiple memory structures and set multiple memory structures to correspond with multiple semiconductor bodies, wherein one memory structure is coupled to the first end and the third end of the same semiconductor body.

[0095] The following will combine Figures 3-8The specific process of some steps of the above preparation method in one embodiment is described in detail.

[0096] See Figure 3 and Figure 4 Step S1, the formation process of the array of multiple semiconductor bodies 10 includes, for example:

[0097] A semiconductor layer is provided. The material of the semiconductor layer includes, for example, at least one of single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The semiconductor layer is doped at both ends along a first direction X using an N-type dopant or a P-type dopant through, for example, ion implantation or diffusion processes to form well regions. The dopant includes, for example, any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb); or, the dopant includes, for example, any one or a combination of boron (B), gallium (Ga), or indium (In).

[0098] A portion of the semiconductor layer is removed by, for example, a dry etching process or a combination of dry and wet etching processes, or by a patterning process of photolithography, cleaning and chemical mechanical polishing, to form a plurality of openings spaced apart along the second direction Y, wherein the remaining portion of the initial semiconductor layer forms a plurality of intermediate semiconductor layers 10c spaced apart along the second direction Y.

[0099] Multiple openings are filled using a thin film deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, to form an initial isolation layer 10b. The initial isolation layer 10b and the intermediate semiconductor layer 10c are alternately arranged along the second direction Y to form a base structure 10a. The material of the initial isolation layer 10b includes, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0100] Combined Figure 5 and Figure 6By means of, for example, dry etching or a combination of dry and wet etching, or by patterning processes of photolithography, cleaning and chemical mechanical polishing, a portion of the base structure 10a is removed to form a plurality of grooves 10a1 spaced apart along the third direction Z, and a plurality of intermediate semiconductor layers 10c are divided into a plurality of arrayed semiconductor pillars 10a2. The plurality of arrayed semiconductor pillars 10a2 include a plurality of arrayed first bodies 11 and a plurality of arrayed second bodies 12. Along the third direction Z, the first bodies 11 and the second bodies 12 are arranged alternately. A first body 11 and an adjacent second body 12 constitute a semiconductor body 10, thereby forming a plurality of arrayed semiconductor bodies 10 composed of first bodies 11 and second bodies 12.

[0101] Combined Figure 7 Step S2, forming multiple character lines 30 arranged sequentially along the third direction Z, for example including:

[0102] A first conductive material is deposited in a trench 10a1 between a first body 11 and a second body 12 of the same semiconductor body 10 using a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof, to form multiple word lines 30 arranged sequentially along the third direction Z. Compared to first depositing conductive material in the trench and then using a front-side punching etching process or a back-side trench 10a1 etching process to break the conductive material in the same trench into two word lines 30, the word line 30 formation method of this embodiment can more effectively separate adjacent word lines 30 and is less likely to damage the semiconductor body 10, thereby improving the electrical performance of the final product.

[0103] Combined Figure 8 Step S3, which involves correspondingly configuring the multiple memory structures 20 with the multiple semiconductor bodies 10, includes, for example:

[0104] Multiple memory node contacts 60 are formed at the ends of the semiconductor bodies 10 arranged in multiple arrays along the first direction X. One end of a memory node contact 60 along the first direction X contacts the first end 111 and the third end 121 of the same semiconductor body 10. The material of the memory node contact 60 includes, for example, at least one of tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, and nitride.

[0105] Combined Figure 9The system provides multiple storage structures 20, each corresponding to a multiple storage node contact portion 60, such that the storage structure 20 contacts the storage node contact portion 60 at the other end along a first direction X. The storage structure 20 includes, for example, a capacitor, with one electrode of the capacitor in contact with the storage node contact portion 60.

[0106] Based on this, a memory structure 20 is coupled to a first body 11 and a second body 12 of the same semiconductor body 10. The word line 30 is located between the first body 11 and the second body 12 of the same semiconductor body 10, that is, the word line 30 is located inside the semiconductor body 10. When the word line 30 is coupled to the first body 11 and the second body 12 on opposite sides along the third direction Z, the word line 30 can control the first body 11 and the second body 12 of the same semiconductor body 10, which can realize total inversion and avoid the floating body effect.

[0107] Combined Figure 10 After the memory structure 20 is coupled to the semiconductor body 10, a peripheral circuit 10c is provided. The peripheral circuit 10c is implemented, for example, using complementary metal oxide semiconductor (CMOS) technology. The peripheral circuit 10c is coupled, for example, to the end of the memory structure 20 that is away from the semiconductor body 10.

[0108] Combined Figure 4 , Figure 6 and Figure 11 Remove Figure 4 In the semiconductor body 10 formed after a portion of the basic structure 10a, multiple arrays are arranged. Figure 6 Multiple semiconductor bodies 10 located in the same column along the third direction Z are connected at one end, that is... Figure 11 Multiple semiconductor bodies 10 located in the same column along the third direction Z are connected at the ends furthest from the peripheral circuit 10c. Based on this, the structure after coupling the peripheral circuit 10c to the memory structure 20 is inverted, and the material of the connected portion is thinned.

[0109] Combined Figure 3 and Figure 12 Conductive materials, such as at least one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, and silicides, are deposited through one or more thin film deposition processes to form an initial bit line structure covering the second end 112 and the fourth end 122 of the semiconductor body 10.

[0110] Then, a portion of the initial bit line structure is removed to form multiple openings spaced apart along the second direction Y. The remaining portion of the initial bit line structure forms multiple bit lines 40 spaced apart along the second direction Y. The multiple bit lines 40 and multiple openings are arranged alternately along the second direction Y.

[0111] Optionally, after forming bit lines 40, a dielectric material, such as at least one of silicon (Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), and silicon-on-insulator (SOI), is deposited through one or more thin film deposition processes to form a plurality of bit line isolation structures that fill a plurality of openings.

[0112] The following will combine Figures 3-8 The specific process of some steps of the above preparation method in one embodiment is described in detail.

[0113] See Figure 3 and Figure 4 Step S1, the formation process of the array of multiple semiconductor bodies 10 includes, for example:

[0114] A semiconductor layer is provided. The material of the semiconductor layer includes, for example, at least one of single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The semiconductor layer is doped at both ends along a first direction X using an N-type dopant or a P-type dopant through, for example, ion implantation or diffusion processes to form well regions. The dopant includes, for example, any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb); or, the dopant includes, for example, any one or a combination of boron (B), gallium (Ga), or indium (In).

[0115] A portion of the semiconductor layer is removed by, for example, a dry etching process or a combination of dry and wet etching processes, or by a patterning process of photolithography, cleaning and chemical mechanical polishing, to form a plurality of openings spaced apart along the second direction Y, wherein the remaining portion of the initial semiconductor layer forms a plurality of intermediate semiconductor layers 10c spaced apart along the second direction Y.

[0116] Multiple openings are filled using a thin film deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, to form an initial isolation layer 10b. The initial isolation layer 10b and the intermediate semiconductor layer 10c are alternately arranged along the second direction Y to form a base structure 10a. The material of the initial isolation layer 10b includes, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0117] Combined Figure 5 and Figure 6 By means of, for example, dry etching or a combination of dry and wet etching, or by patterning processes of photolithography, cleaning and chemical mechanical polishing, a portion of the base structure 10a is removed to form a plurality of grooves 10a1 spaced apart along the third direction Z, and a plurality of intermediate semiconductor layers 10c are divided into a plurality of arrayed semiconductor pillars 10a2. The plurality of arrayed semiconductor pillars 10a2 include a plurality of arrayed first bodies 11 and a plurality of arrayed second bodies 12. Along the third direction Z, the first bodies 11 and the second bodies 12 are arranged alternately. A first body 11 and an adjacent second body 12 constitute a semiconductor body 10, thereby forming a plurality of arrayed semiconductor bodies 10 composed of first bodies 11 and second bodies 12.

[0118] Combined Figure 7 Step S2, forming multiple character lines 30 arranged sequentially along the third direction Z, for example including:

[0119] A first conductive material is deposited in a trench 10a1 between a first body 11 and a second body 12 of the same semiconductor body 10 using a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof, to form multiple word lines 30 arranged sequentially along the third direction Z. Compared to first depositing conductive material in the trench and then using a front-side punching etching process or a back-side trench 10a1 etching process to break the conductive material in the same trench into two word lines 30, the word line 30 formation method of this embodiment can more effectively separate adjacent word lines 30 and is less likely to damage the semiconductor body 10, thereby improving the electrical performance of the final product.

[0120] Continue reading Figure 7 The main difference between this embodiment and other embodiments is that a shielding portion 51 is also formed between two adjacent rows of semiconductor bodies 10. The formation process of the shielding portion 51 in this embodiment will be described in detail below.

[0121] After forming an array of semiconductor bodies 10, a second conductive material is deposited in a groove 10a1 between two adjacent semiconductor bodies 10 along the third direction Z using, for example, one or more thin film deposition processes, to form a shielding portion 51 located between two adjacent rows of semiconductor bodies 10. To simplify the process and save production costs, the shielding portion 51 can be formed simultaneously using the same material as the word line 30 during the word line 30 formation process.

[0122] Combined Figure 8 Step S3, which involves correspondingly configuring the multiple memory structures 20 with the multiple semiconductor bodies 10, includes, for example:

[0123] Multiple memory node contacts 60 are formed at the ends of the semiconductor bodies 10 arranged in multiple arrays along the first direction X. One end of a memory node contact 60 along the first direction X contacts the first end 111 and the third end 121 of the same semiconductor body 10. The material of the memory node contact 60 includes, for example, at least one of tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide, and nitride.

[0124] Combined Figure 9 The system provides multiple storage structures 20, each corresponding to a multiple storage node contact portion 60, such that the storage structure 20 contacts the storage node contact portion 60 at the other end along a first direction X. The storage structure 20 includes, for example, a capacitor, with one electrode of the capacitor in contact with the storage node contact portion 60.

[0125] Based on this, a memory structure 20 is coupled to a first body 11 and a second body 12 of the same semiconductor body 10. The word line 30 is located between the first body 11 and the second body 12 of the same semiconductor body 10, that is, the word line 30 is located inside the semiconductor body 10. When the word line 30 is coupled to the first body 11 and the second body 12 on opposite sides along the third direction Z, the word line 30 can control the first body 11 and the second body 12 of the same semiconductor body 10, which can realize total inversion and avoid the floating body effect.

[0126] Combined Figure 10 After the memory structure 20 is coupled to the semiconductor body 10, a peripheral circuit 10c is provided. The peripheral circuit 10c is implemented, for example, using complementary metal oxide semiconductor (CMOS) technology. The peripheral circuit 10c is coupled, for example, to the end of the memory structure 20 that is away from the semiconductor body 10.

[0127] Combined Figure 4 , Figure 6 and Figure 11 Remove Figure 4 In the semiconductor body 10 formed after a portion of the basic structure 10a, multiple arrays are arranged. Figure 6 Multiple semiconductor bodies 10 located in the same column along the third direction Z are connected at one end, that is... Figure 11Multiple semiconductor bodies 10 located in the same column along the third direction Z are connected at the ends furthest from the peripheral circuit 10c. Based on this, the structure after coupling the peripheral circuit 10c to the memory structure 20 is inverted, and the material of the connected portion is thinned.

[0128] Combined Figure 3 and Figure 12 Conductive materials, such as at least one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, and silicides, are deposited through one or more thin film deposition processes to form an initial bit line structure covering the second end 112 and the fourth end 122 of the semiconductor body 10.

[0129] Then, a portion of the initial bit line structure is removed to form multiple openings spaced apart along the second direction Y. The remaining portion of the initial bit line structure forms multiple bit lines 40 spaced apart along the second direction Y. The multiple bit lines 40 and multiple openings are arranged alternately along the second direction Y.

[0130] Optionally, after forming bit lines 40, a dielectric material, such as at least one of silicon (Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), and silicon-on-insulator (SOI), is deposited through one or more thin film deposition processes to form a plurality of bit line isolation structures that fill a plurality of openings.

[0131] See Figure 13 Based on the same inventive concept, this application also provides a storage system 1000. The storage system 1000 includes a controller 200 and at least one storage device 100 of the above embodiments. The controller 200 is coupled to the storage device 100 and is used to control the storage device 100 to store data.

[0132] Optionally, the controller 200 and the individual storage device 100 are integrated into the memory card. Memory cards include Personal Computer Memory Card International Association (PCMCIA or PC), Compact Flash (CF), Smart Media (SM), Memory Stick, Multimedia Card (MMC), Secure Digital Memory Card (SD), Universal Flash Storage (UFS), etc.

[0133] Optionally, the controller 200 and multiple storage devices 100 are integrated into a solid state drive (SSD).

[0134] In some embodiments, the storage system 1000 is used for mobile phones, desktop computers, laptops, tablets, in-vehicle computers, game consoles, printers, positioning devices, wearable electronic devices 10000, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or other electronic devices 10000 having storage components located therein.

[0135] Optionally, the electronic device 10000 includes a host 2000 and a storage system 1000 having one or more storage devices 100 and a controller 200. The host 2000 may be a processor of the electronic device 10000, such as a central processing unit (CPU) or a system-on-chip (SoC). The host 2000 is configured to send data to or receive data from the storage device 100.

[0136] Optionally, the controller 200 is coupled to the storage device 100 and the processor, and the controller 200 is configured to manage data stored in the storage device 100 and communicate with the processor.

[0137] Optionally, the controller 200 is configured to control the operation of the storage device 100, such as read, erase, and program operations.

[0138] Optionally, the controller 200 is configured to manage various functions related to data stored in or to be stored in the storage device 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0139] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. Furthermore, in the description of this application, unless otherwise stated, "multiple" means at least two, for example, two, three, four, etc. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0140] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A storage device, characterized in that, include: A plurality of semiconductor bodies, the semiconductor bodies including a first body and a second body, the first body including a first end and a second end opposite to each other along a first direction, the second body including a third end and a fourth end opposite to each other along the first direction, the plurality of semiconductor bodies being arranged in a row along a second direction and in a column along a third direction, the first direction, the second direction and the third direction intersecting each other; Multiple memory structures are disposed corresponding to multiple semiconductor bodies, and one memory structure is coupled to the first end and the third end of the same semiconductor body; Multiple word lines are arranged sequentially along the third direction. The word lines extend along the second direction and are coupled to each of the semiconductor bodies in the same row. The word lines are located between the first body and the second body of the same semiconductor body.

2. The storage device according to claim 1, characterized in that, The character lines are coupled to the first body and the second body on opposite sides along the third direction, respectively.

3. The storage device according to claim 1, characterized in that, The storage device further includes a gate oxide structure located between the word line and the first body.

4. The storage device according to claim 1, characterized in that, The storage device further includes a gate oxide structure located between the word line and the second body.

5. The storage device according to claim 3 or 4, characterized in that, The end face of the first main body facing one end of the storage structure, the end face of the second main body facing one end of the storage structure, and the end face of the gate oxide structure facing one end of the storage structure are flush.

6. The storage device according to claim 1, characterized in that, The memory device further includes bit lines coupled to the second end and the fourth end of the semiconductor body.

7. The storage device according to claim 6, characterized in that, The storage device includes a plurality of bit lines, which are spaced apart along the second direction; The bit line extends along the third direction and is coupled to the second end and the fourth end of the semiconductor body in the same column.

8. The storage device according to claim 1, characterized in that, The storage device further includes a shielding structure, which includes a plurality of shielding portions spaced apart along the third direction; The shielding portion is located between two adjacent rows of the semiconductor bodies.

9. The storage device according to claim 8, characterized in that, Along the third direction, the shielding portion and the word line are arranged alternately.

10. The storage device according to claim 1, characterized in that, The storage device further includes a plurality of storage node contacts corresponding to the plurality of semiconductor bodies. One end of each storage node contact is coupled to the storage structure along the first direction, and the other end is coupled to the first end and the third end of the same semiconductor body.

11. The storage device according to claim 1, characterized in that, The storage structure includes a capacitor coupled to the first end and the third end of the same semiconductor body.

12. A method for manufacturing a storage device, characterized in that, Includes the following steps: Multiple semiconductor bodies are arranged in an array. The semiconductor bodies include a first body and a second body. The first body includes a first end and a second end opposite to each other along a first direction. The second body includes a third end and a fourth end opposite to each other along the first direction. The first direction, the second direction, and the third direction intersect each other. Multiple word lines are formed and arranged sequentially along a third direction of the array. The word lines extend along a second direction of the array and are coupled to each of the semiconductor bodies in the same row. The word lines are located between the first body and the second body of the same semiconductor body. A plurality of memory structures are provided, and the plurality of memory structures are correspondingly disposed with a plurality of semiconductor bodies, wherein one memory structure is coupled to a first end and a third end of the same semiconductor body.

13. The method for manufacturing a storage device according to claim 12, characterized in that, Also includes: Provides a semiconductor layer; Multiple grooves are arranged at intervals on the semiconductor layer to form multiple arrayed semiconductor pillars. The multiple semiconductor pillars include multiple first bodies and multiple second bodies. Along the third direction, a first body and an adjacent second body constitute the semiconductor body. A first conductive material is disposed between the first body and the second body of the same semiconductor body to form the word line.

14. The method for manufacturing a storage device according to claim 13, characterized in that, Also includes: A second conductive material is disposed between two adjacent semiconductor bodies along the third direction to form a shielding portion located between two adjacent rows of semiconductor bodies.

15. The method for manufacturing a storage device according to claim 12, characterized in that, Also includes: Multiple storage node contacts are formed, and one end of each storage node contact along the first direction is coupled to the first end and the third end of the same semiconductor body; The storage structure is coupled to the other end of the storage node contact portion along the first direction.

16. A storage system, characterized in that, include: The storage device according to any one of claims 1-11, wherein the storage device is configured to store data; A controller, coupled to the storage device and configured to control the storage device.

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