Semiconductor device and method of manufacturing the same, memory system

Abstract

The present disclosure provides a semiconductor device and a manufacturing method, a memory system. The semiconductor device includes a semiconductor body, a capacitor structure, and an isolation structure. The semiconductor body is located at one side of the capacitor structure in a first direction and extends along the first direction, wherein the semiconductor body includes a first portion and a second portion, and the second portion is located between the first portion and the capacitor structure in the first direction. The isolation structure is located at one side of the semiconductor body in a second direction intersecting the first direction, wherein a size of the second portion in the second direction is greater than a size of the first portion in the second direction.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor design and fabrication, and more specifically, to semiconductor devices, methods for fabricating semiconductor devices, and memory systems. Background Technology

[0002] Memory is one of the most important semiconductor devices in electronic systems. Taking Dynamic Random Access Memory (DRAM) as an example, a semiconductor device can include memory cells composed of capacitors and transistors, where multiple memory cells can be arranged in a two-dimensional array.

[0003] With the rapid development of semiconductor technology, the shrinking size of semiconductor devices and the increase in integration, optimizing the electrical performance of semiconductor devices and improving their yield has become one of the important research directions in the industry. Summary of the Invention

[0004] This disclosure provides a method for fabricating a semiconductor device, a semiconductor device, and a memory system that can at least partially solve the problems described above or other problems in the art.

[0005] This disclosure provides a semiconductor device comprising: a capacitor structure; a semiconductor body located on one side of the capacitor structure in a first direction and extending along the first direction, wherein the semiconductor body includes a first portion and a second portion, the second portion being located between the first portion and the capacitor structure in the first direction; and an isolation structure located on one side of the semiconductor body in a second direction, the second direction intersecting the first direction, wherein, in the second direction, the size of the second portion is larger than the size of the first portion. In some embodiments of this disclosure, the surface of the first semiconductor portion in contact with the semiconductor body includes a concave surface recessed toward the capacitor structure.

[0006] In some embodiments of this disclosure, the second part protrudes from the first part in a second direction toward the isolation structure.

[0007] In some embodiments of this disclosure, the material of the first part is the same as the material of the second part.

[0008] In some embodiments of this disclosure, in the second direction, the ratio between the size of the first part and the size of the second part is greater than or equal to 1 / 4 and less than or equal to 1 / 2.

[0009] In some embodiments of this disclosure, in a first direction, the ratio between the size of the second part and the size of the first part is greater than or equal to 1 / 5 and less than or equal to 1 / 3.

[0010] In some embodiments of this disclosure, the semiconductor device further includes: a gate structure, which is located on both sides of the semiconductor body in the second direction, at least as opposed to the isolation structure.

[0011] In some embodiments of this disclosure, a semiconductor body includes a first sidewall and a second sidewall facing away from each other in a second direction, wherein the first sidewall faces the gate structure in the second direction; and a plurality of semiconductor bodies include a first semiconductor body and a second semiconductor body adjacent to each other in a second direction, wherein a first distance between the first semiconductor body and the second semiconductor body is greater than or equal to a second distance between them, the first distance being the distance between a portion of the first sidewall of the first semiconductor body near the capacitor structure and a portion of the first sidewall of the second semiconductor body near the capacitor structure; and the second distance being the distance between the remaining portion of the first sidewall of the first semiconductor body and the remaining portion of the first sidewall of the second semiconductor body.

[0012] In some embodiments of this disclosure, the semiconductor device further includes: a bit line structure located on the side of the first portion away from the second portion in a first direction and extending along the second direction.

[0013] In some embodiments of this disclosure, the isolation structure includes: an isolation conductor portion; and an isolation dielectric portion surrounding the isolation conductor portion.

[0014] In some embodiments of this disclosure, the isolation conductor portion includes a first protrusion facing the bit line structure in a first direction.

[0015] In some embodiments of this disclosure, the isolation medium portion includes: a first isolation medium portion located on the side of the isolation conductor portion away from the bit line structure in a first direction.

[0016] In some embodiments of this disclosure, the first isolation medium portion includes a second protrusion extending toward the bit line structure in a first direction and contacting the isolation conductor portion.

[0017] In some embodiments of this disclosure, the isolation medium portion further includes: a second isolation medium portion located in a first direction between the isolation conductor portion and the bit line structure; and a first isolation medium portion 320 located in at least a first direction between the isolation conductor portion and the second isolation medium portion.

[0018] In some embodiments of this disclosure, the first isolation medium portion is also located between the isolation conductor portion and the semiconductor body, and between the first isolation medium portion and the semiconductor body.

[0019] In some embodiments of this disclosure, the isolation medium portion further includes: a second isolation medium portion located between the bit line structure and the second isolation medium portion, and also located between the semiconductor body and the first isolation medium portion.

[0020] This disclosure also provides a method for fabricating a semiconductor device, the method comprising: forming a semiconductor body extending along a first direction; forming an isolation structure located on one side of the semiconductor body in a second direction, wherein the second direction intersects the first direction; and forming a capacitor structure located on one side of the semiconductor body in the first direction, wherein the semiconductor body includes a first part and a second part, the second part being located between the first part and the capacitor structure in the first direction; and in the second direction, the size of the second part is larger than the size of the first part.

[0021] In some embodiments of this disclosure, forming a semiconductor body extending along a first direction includes: forming a first trench extending along the first direction in a semiconductor substrate, wherein a plurality of first trenches are spaced apart in a third direction, dividing at least a portion of the semiconductor substrate into a plurality of strip semiconductor layers spaced apart in the third direction, wherein the first direction, the second direction, and the third direction intersect each other; forming a second trench and a third trench extending along the first direction, wherein the second trench and the third trench are alternately distributed in the second direction, dividing the strip semiconductor layers into a plurality of initial semiconductor bodies, the initial semiconductor bodies including sidewalls extending along the first direction; and filling the first trench and the second trench, and removing a portion of the sidewalls of the initial semiconductor bodies via the third trench, thereby forming the semiconductor body.

[0022] In some embodiments of this disclosure, an isolation structure formed on one side of a semiconductor body in a second direction intersecting the first direction includes: forming a sacrificial layer in a third trench from the first side of the semiconductor body in the first direction; forming an isolation conductor portion in the third trench, wherein the isolation conductor portion is located on one side of the sacrificial layer in the first direction; filling the remaining space of the third trench with a first isolation dielectric portion; and removing the sacrificial layer from the second side opposite to the first side in the first direction, thereby forming the isolation structure.

[0023] In some embodiments of this disclosure, the isolation structure formed on one side of the semiconductor body in a second direction intersecting the first direction further includes: forming a first isolation dielectric portion at least in the first direction between the sacrificial layer and the isolation conductor portion, wherein the process of removing the sacrificial layer from the second side stops at the first isolation dielectric portion.

[0024] In some embodiments of this disclosure, the material of the sacrificial layer is the same as the material of the insulating conductor portion.

[0025] In some embodiments of this disclosure, forming a sacrificial layer in a third trench from a semiconductor body on a first side in a first direction includes: forming an initial sacrificial layer that at least fills the third trench, wherein a first air gap is formed in the initial sacrificial layer; and removing a portion of the initial sacrificial layer to form a sacrificial layer, wherein the surface of the sacrificial layer facing the first side includes a first concave surface formed based on the first air gap, the first concave surface being recessed toward the second side along the first direction.

[0026] In some embodiments of this disclosure, forming an isolation conductor portion in a third trench, wherein the isolation conductor portion is located on one side of the sacrificial layer in a first direction, includes: forming an initial isolation conductor portion that at least fills the third trench, wherein a second air gap is formed in the initial isolation conductor portion; and removing a portion of the initial isolation conductor portion to form an isolation conductor portion, wherein the surface of the initial isolation conductor portion facing the first side includes a second concave surface formed based on the second air gap, the second concave surface being recessed toward the second side in the first direction.

[0027] In some embodiments of this disclosure, the initial isolation conductor portion includes a first convex portion facing the first concave surface along a first direction.

[0028] In some embodiments of this disclosure, filling the remaining space of the third trench with a first insulating medium portion includes: forming an initial first insulating medium portion that is at least filled in the third trench, wherein the first insulating medium portion includes a second protrusion that contacts the second concave surface; and removing a portion of the initial first insulating medium portion to form the first insulating medium portion.

[0029] Another aspect of this disclosure provides a memory system including a controller and a semiconductor device provided in any embodiment of this disclosure, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0030] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0031] Some exemplary embodiments of this disclosure will now be described with reference to the accompanying drawings. These drawings are for illustrative purposes only and are not intended to limit the claimed technical solutions, wherein: Figures 1 to 5 These are cross-sectional schematic diagrams of semiconductor devices according to exemplary embodiments of the present disclosure; Figure 6 This is a flowchart of a method for fabricating a semiconductor device according to an exemplary embodiment of the present disclosure; Figures 4 to 27 These are schematic diagrams illustrating a method for fabricating a semiconductor device according to one embodiment of this disclosure; and Figure 28 This is a block diagram of a system with a memory system provided by way of example in this disclosure. Detailed Implementation

[0032] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this disclosure, the first direction discussed herein may also be referred to as the second direction, and vice versa.

[0034] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0035] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0036] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0038] Furthermore, in this disclosure, the use of "connection" or "linkage" may indicate a direct or indirect connection between the corresponding components, and the use of "contact" may indicate a direct connection between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0039] This disclosure will now be described in detail with reference to the accompanying drawings and the gate structure of the embodiments.

[0040] Some embodiments of this disclosure provide a semiconductor device. Figure 1 This is a partial cross-sectional schematic diagram of a semiconductor device 1000 according to an exemplary embodiment of the present disclosure.

[0041] like Figure 1 As shown, the semiconductor device 1000 may include a semiconductor body 100, a capacitor structure 200, and an isolation structure 300. The semiconductor body 100 is located on one side of the capacitor structure 200 in a first direction (z-direction) and extends along the z-direction. The isolation structure 300 is located on one side of the semiconductor body 100 in a second direction (x-direction), wherein the x-direction intersects the z-direction. The semiconductor body 100 includes a first portion 101 and a second portion 102, wherein the second portion 102 is located between the first portion 101 and the capacitor structure 200 in the z-direction. The dimension d2 of the second portion 102 of the semiconductor body 100 in the x-direction is larger than the dimension d1 of its first portion 101 in the x-direction.

[0042] In embodiments of this disclosure, a semiconductor device includes a capacitor structure and a transistor located on one side of the capacitor structure in a first direction. The semiconductor body of the transistor extends along the first direction and includes a first portion and a second portion connected to each other in the first direction. The first portion is located on the side of the second portion away from the capacitor structure and has a relatively small size in a second direction intersecting the first direction. This allows the transistor to have a narrower transport path (understood as a narrow channel region) for charge carriers (e.g., electrons or holes) in its operating state, thus relatively increasing the carrier concentration per unit volume. Under the action of the transistor gate voltage, the electric field intensity in the narrow channel region is more concentrated, which can accelerate carrier migration, effectively reduce channel resistance, improve the transistor's drive current capability, and improve the transistor's switching speed, thereby optimizing the electrical performance of the semiconductor device and improving its yield.

[0043] Specifically, in some embodiments of this disclosure, taking DRAM as an example, the semiconductor device 1000 may include a capacitor structure layer 1001 and a transistor layer 1002, wherein the transistor layer 1002 may include transistors, and the capacitor structure layer 1001 may include a capacitor structure 200. The capacitor structure layer 1001 is located on one side of the transistor layer 1002 in the z-direction, wherein the z-direction can be understood as the stacking direction of the transistor layer 1002 and the capacitor structure layer 1001.

[0044] The transistor layer 1002 may include a plurality of transistors, and the capacitor structure layer 1001 may include a capacitor structure 200 connected to the transistors in the transistor layer 1002. Therefore, the transistors and the capacitor structure 200 connected to the transistors can constitute a memory cell of a semiconductor device. The plurality of memory cells may be spaced apart in a direction intersecting the z-direction. It should be noted that the semiconductor device 1000 provided in this embodiment may be a memory or a part of a memory.

[0045] Optionally, the transistor layer 1002 and the capacitor structure layer 1001 can constitute the memory structure of the semiconductor device 1000. In addition, the semiconductor device 1000 may also include a peripheral circuit structure (not shown). Optionally, the peripheral circuit structure may be disposed on the side of the transistor layer 1002 away from the capacitor structure layer 1001 in the z-direction.

[0046] The peripheral circuitry of the peripheral circuitry structure may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the transistor layer 1002 and the capacitor structure layer 1001. For example, the peripheral circuitry may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0047] Optionally, to further reduce the size of the two-dimensional array, the transistors may include a vertical gate transistor array. In this structure, the two ends of the channel of the transistor can be respectively formed as the source (not shown) and drain (not shown) of the transistor. The specific arrangement details of the transistors will be described in detail below with reference to the accompanying drawings.

[0048] Furthermore, in some embodiments of this disclosure, such as vertical metal-oxide-semiconductor field-effect transistors (Metal... Oxide Semiconductor Field Vertical transistors such as Effect Transistors (MOSFETs) can replace conventional planar transistors as transfer transistors for memory cells, thereby reducing the area occupied by transfer transistors, coupling capacitance, and interconnect wiring complexity.

[0049] In some embodiments of this disclosure, unlike planar transistors where an active region is formed in a substrate, a vertical transistor type transistor may include a semiconductor body 100 extending along the z-direction. The semiconductor body 100 extends along the z-direction, exposing not only the ends of the semiconductor body 100 but also the sidewalls to which the semiconductor body 100 connects.

[0050] Optionally, the materials of the first portion 101 and the second portion 102 of the semiconductor body 100 may be the same. In other words, the first portion 101 and the second portion 102 of the semiconductor body 100 may be made of the same material, which may include any suitable semiconductor material. For example, the material of the semiconductor body 100 may include at least one of doped crystalline silicon or silicides. Alternatively, the material of the semiconductor body 100 may include a metal oxide, which may include at least one of indium gallium zinc oxide, indium tungsten oxide, indium tin oxide, and indium zinc oxide.

[0051] Furthermore, the materials of the first portion 101 and the second portion 102 of the semiconductor body 100 may also be different. For example, the first portion 101 and the second portion 102 of the semiconductor body 100 may be formed from different semiconductor materials in different process steps. Optionally, the materials of the first portion 101 and the second portion 102 may include any suitable semiconductor material.

[0052] In some embodiments of this disclosure, the first portion 101 of the semiconductor body 100 may have a cubic shape and four exposed sidewalls. However, those skilled in the art will understand that the first portion 101 may also have any suitable 3D shape, such as a polyhedral or cylindrical shape. In other words, the cross-section of the first portion 101 in a plane intersecting the z-direction may have a rectangular, trapezoidal, circular, elliptical, or any other suitable shape. It should be understood that, consistent with the scope of this disclosure, a first portion 101 having a circular or elliptical cross-section in the aforementioned plane may still be considered to have multiple sidewalls.

[0053] Similarly, the second portion 102 of the semiconductor body 100 may also have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. The cross-section of the second portion 102 in a plane intersecting the z-direction may have a rectangular shape, a trapezoidal shape, a circular shape, an elliptical shape, or any other suitable shape.

[0054] Optionally, in a plane intersecting the z-direction, the cross-sectional shape of the first part 101 may be the same as that of the second part 102, and the cross-sectional shape may include a rectangular shape, a trapezoidal shape, a circular shape, an elliptical shape, or any other suitable shape.

[0055] The second portion 102 of the semiconductor body 100 is located between the first portion 101 and the capacitor structure 200 in the z-direction. Alternatively, the first portion 101 of the semiconductor body 100 is located on the side of the second portion 102 away from the capacitor structure 200 in the z-direction. Optionally, the end of the second portion 102 of the semiconductor body 100 closer to the capacitor structure 200 in the z-direction can form the source of a transistor. The end of the first portion 101 of the semiconductor body 100 away from the second portion 102 in the z-direction can form the drain of a transistor.

[0056] In other words, the vertical transistor may also include a source and a drain located at opposite ends of the semiconductor body 100 in the z-direction, which can be understood as doped regions of the semiconductor body 100, and may also be referred to as source electrodes and drain electrodes. Alternatively, the source and drain may be doped with any suitable P-type dopant, which may include any one or a combination of boron (B) or gallium (Ga). Alternatively, the source and drain may be doped with any suitable N-type dopant, which may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb).

[0057] The semiconductor device provided in this disclosure has a first portion of the semiconductor body located on the side of the second portion away from the capacitor structure, and a relatively small size in the second direction intersecting the first direction. This allows the transistor to have a narrower transport path for charge carriers (e.g., electrons or holes) in the operating state (which can be understood as a narrow channel region), thus relatively increasing the carrier concentration per unit volume. Under the action of the gate voltage, the electric field intensity in the narrow channel region is more concentrated, which can accelerate carrier migration, effectively reduce channel resistance, improve the driving current capability of the transistor, and improve the switching speed of the transistor and the electrical performance of the semiconductor device.

[0058] Furthermore, in some embodiments of this disclosure, the conductor device 1000 may also include a connection structure 1003, which extends along the z-direction and is located between the second portion 102 of the semiconductor body 100 and the capacitor structure 200. Compared to the first portion 101 of the semiconductor body 100, the second portion 102 of the semiconductor body 100 is closer to the capacitor structure 200 in the z-direction and can be connected to the capacitor structure 200 through the connection structure 1003. In addition, the dimension d2 of the second portion 102 in the x-direction may be larger than the dimension d1 of the first portion 101 in the x-direction.

[0059] In other words, the second part of the semiconductor body is connected to the capacitor structure via a connection structure and has a relatively large size in the second direction intersecting the first direction. This allows the contact area between the second part and the connection structure to also have a relatively large size, enabling the semiconductor body as a whole, with its "narrow channel region," to achieve a stable and effective connection with the capacitor structure.

[0060] Figure 2 This is a partial cross-sectional schematic diagram of a semiconductor device 1000 according to an exemplary embodiment of the present disclosure.

[0061] Optionally, such as Figure 2 As shown, in order to enhance the above effect, the ratio between the dimension d1 of the first part 101 in the x direction and the dimension d2 of the second part 102 in the x direction can be greater than or equal to 1 / 4 and less than or equal to 1 / 2.

[0062] Figure 3 and Figure 4 These are partial cross-sectional schematic diagrams of a semiconductor device 1000 according to exemplary embodiments of the present disclosure.

[0063] In addition, such as Figure 3 As shown, the ratio between the dimension h2 of the second part 102 in the z-direction and the dimension h1 of the first part 101 in the z-direction can be greater than or equal to 1 / 5 and less than or equal to 1 / 3. This allows the semiconductor body with a "narrow channel region" to have a relatively long "narrow channel region" while still being able to achieve a stable and effective connection with the capacitor structure, thereby accelerating carrier migration, effectively reducing channel resistance, and improving the driving current capability of the transistor.

[0064] Refer again Figures 1 to 4 In some embodiments of this disclosure, the vertical transistor may further include a gate structure 400, which is located on both sides of the semiconductor body 100 in the x-direction, at least as opposed to the isolation structure 300. Optionally, the isolation structure 300 may extend along a third direction intersecting both the x-direction and the z-direction, and be located between adjacent gate structures 400 in the x-direction.

[0065] Alternatively, the semiconductor body 100 includes a first side and a second side facing away from each other in the x-direction, wherein the gate structure 400 may be located on the first side of the semiconductor body 100 and the isolation structure 300 may be located on the second side of the semiconductor body 100. Alternatively, the gate structure 400 may be located on one of the two sides of the semiconductor body 100 facing away from each other in the x-direction, and also on the remaining sides of the semiconductor body 100 other than the two sides facing away from each other in the x-direction.

[0066] The gate structure 400 may include a gate conductive layer 410 and a gate dielectric layer 420, wherein the gate dielectric layer 420 is located between the semiconductor body 100 and the gate conductive layer 410. Optionally, the gate conductive layer 410 may include a plurality of conductive layers (not shown).

[0067] Optionally, the material of the gate dielectric layer 420 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the material of the gate dielectric layer 420 may include silicon oxide. Optionally, the material of the conductive layer may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicides, etc.

[0068] Figure 5 This is a partial cross-sectional schematic diagram of a semiconductor device 1000 according to an exemplary embodiment of the present disclosure.

[0069] refer to Figure 5 In some embodiments of this disclosure, the second portion 102 of the semiconductor body 100 may protrude from its first portion 101 toward the isolation structure 300 in the x-direction. In other words, Figure 5 The portion of the isolation structure 300 shown between adjacent first parts 101 may have a dimension d3 in the x-direction that is larger than the portion of the isolation structure 300 between adjacent second parts 102 in the x-direction that is larger than the dimension d4 in the x-direction that is larger than the portion of the isolation structure 300 between adjacent second parts 102.

[0070] Furthermore, in some embodiments of this disclosure, the semiconductor body 100 may include a first sidewall and a second sidewall facing away from each other in the x-direction, wherein the first sidewall may face the gate structure 400 in the x-direction. For example, a plurality of semiconductor bodies 100 may include a first semiconductor body 110 and a second semiconductor body 120 adjacent in the x-direction. The first semiconductor body 110 may include a first sidewall 111 and a second sidewall 112 facing away from each other in the x-direction. The second semiconductor body 120 may include a first sidewall 121 and a second sidewall 122 facing away from each other in the x-direction. The first sidewall 111 of the first semiconductor body 110 and the first sidewall 121 of the second semiconductor body 120 may face the same gate structure 400 in the x-direction.

[0071] The first distance d5 between the first semiconductor body 110 and the second semiconductor body 120 can be greater than or equal to the second distance d6 between them, wherein the first distance d5 is the distance between the portion of the first sidewall 111 of the first semiconductor body 110 near the capacitor structure 200 and the portion of the first sidewall 121 of the second semiconductor body 120 near the capacitor structure 200; and the second distance d6 is the distance between the remaining portion of the first sidewall 111 of the first semiconductor body 110 and the remaining portion of the first sidewall 121 of the second semiconductor body 120. For example, Figure 5The case where the first distance d5 is equal to the second distance d6 is shown. Therefore, in this embodiment, the second part 102 may protrude from the first part 101 in the x-direction toward the isolation structure 300; while on the side in the x-direction toward the gate structure 400, the second part 102 does not protrude from the first part 101.

[0072] In some embodiments of this disclosure, an etching process can be used to form a plurality of trenches spaced apart in the x-direction and a plurality of trenches spaced apart in a third direction intersecting both the x and z directions in a semiconductor substrate, thereby dividing at least a portion of the semiconductor substrate into a plurality of initial semiconductor bodies. The initial semiconductor bodies may have relatively straight sidewalls. Furthermore, due to limitations of the etching process, the initial semiconductor bodies may have a top-smaller, bottom-larger shape in a plane parallel to the z-direction (e.g., the xz plane), or in other words, the initial semiconductor bodies may have sidewalls extending straight along a direction intersecting the z-direction at an acute angle. To form a second semiconductor body with a dimension in the x-direction larger than that of the first semiconductor body, a portion of the sidewalls of the initial semiconductor body can be removed via the aforementioned trenches to form the semiconductor body, and an isolation structure can be formed in the expanded trench space resulting from the removal of the partial sidewalls. This causes the second part of the semiconductor body to protrude from its first part in the x-direction toward the isolation structure. Furthermore, the sidewalls of the first and second parts in the x-direction toward the gate structure remain the original sidewalls of the initial semiconductor body. These sidewalls can extend straight along the z-direction or in a direction that intersects the z-direction at an acute angle.

[0073] Optionally, the semiconductor body 100 has a sidewall extending straight along the z-direction or in a direction intersecting the z-direction at an acute angle, and the gate structure 400 may be located on this sidewall. Therefore, forming the gate structure 400 at a relatively straight sidewall can reduce the probability of electrical performance degradation due to poor filling of the gate structure 400 or reduced electrical performance consistency among multiple gate structures 400, where poor filling may include insufficient or uneven filling. The formation process of the gate structure 400 will be described in detail below with reference to the accompanying drawings.

[0074] Refer again Figure 1 In some embodiments of this disclosure, the capacitor structure 200 may include multilayer capacitors, cup-shaped capacitors, columnar capacitors, and barrel-shaped capacitors, etc. It should be noted that this disclosure does not limit the internal structure of the capacitor structure.

[0075] Optionally, the capacitor structure 200 may include a first electrode portion 201, a second electrode portion 202, and a capacitor dielectric layer 203, wherein the first electrode portion 201 may extend along the z-direction, the capacitor dielectric layer 203 may be located at least on the sidewall of the first electrode portion 201 extending along the z-direction, and the second electrode portion 202 may be located on the side of the capacitor dielectric layer 203 opposite to the first electrode portion 201. The connection structure 1003 may connect the semiconductor body 100 and the first electrode portion 201 in the z-direction, or connect the semiconductor body 100 and the second electrode portion 202 in the z-direction; this disclosure does not limit this.

[0076] As an example, the capacitor structure 200 may also include a support core (not shown) extending in the z-direction, a first electrode portion 201 located on the sidewall of the support core extending in the z-direction and the end face of the support core facing the semiconductor body 100, a capacitor dielectric layer 203 located at least on the side of the first electrode portion 201 away from the sidewall of the support core, and a second electrode portion 202 located on the side of the capacitor dielectric layer 203 away from the first electrode portion 201.

[0077] Optionally, the material of the support core may include elemental semiconductor materials such as silicon (Si) or composite semiconductor materials such as germanium-silicon (GeSi). In this case, the first electrode portion 201 may have a cylindrical structure extending along the z-direction. In other embodiments, the capacitor structure 200 may not include a support core, in which case the first electrode portion 201 may have a columnar structure extending along the z-direction. It should be noted that, in addition to the above-described structural forms, the capacitor structure 200 in the embodiments of this disclosure may also adopt other structural forms suitable for this disclosure.

[0078] The materials of the first electrode portion 201 and the second electrode portion 202 mentioned above may be the same or different. The materials of the first electrode portion 201 and the second electrode portion 202 may include at least one of metal, metal compound and semiconductor material. For example, the materials of the first electrode portion 201 and the second electrode portion 202 may include at least one of titanium nitride, titanium silicide and nickel silicide.

[0079] Optionally, the material of the capacitor dielectric layer 203 may include at least one of aluminum oxide, tantalum oxide, titanium oxide, yttrium oxide, zirconium oxide, zirconium silicon oxide, hafnium oxide, hafnium silicon oxide, hafnium silicon nitride, hafnium zirconate, lanthanum oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, and praseodymium oxide.

[0080] Refer again Figure 1 and Figure 2 In some embodiments of this disclosure, the isolation structure 300 may include an isolation conductor portion 310 and an isolation medium portion 320 surrounding the isolation conductor portion 310.

[0081] Alternatively, the material of the isolation dielectric portion 320 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. Optionally, the isolation conductor portion 310 may be made of the same material as the gate conductive layer 410; for example, the isolation conductor portion 310 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. Furthermore, the isolation dielectric portion 320 may also be made of the same material as the gate dielectric layer 420. This simplifies the fabrication steps and reduces fabrication costs during the fabrication of semiconductor devices.

[0082] During the operation of the semiconductor device 1000, the isolation structure 300 can act as a shield, thereby helping to reduce mutual interference between adjacent transistors. For example, during the operation of the semiconductor device 1000, a ground voltage or a negative voltage can be applied to the isolation conductor portion 310 of the isolation structure 300 to reduce mutual interference between adjacent transistors, wherein the isolation dielectric portion 320 can isolate the isolation conductor portion 310 from the semiconductor body 100.

[0083] Optionally, the semiconductor device 1000 further includes a bit line structure 500, which may be located on the side of the first portion 101 of the semiconductor body 100 away from the second portion 102 in the z-direction and extend along the x-direction. Alternatively, the capacitor structure 200 may be located on the side of the second portion 102 of the semiconductor body 100 away from the first portion 101 in the z-direction and connected to the second portion 102 of the semiconductor body 100; the bit line structure 500 may be located on the side of the first portion 101 of the semiconductor body 100 away from the second portion 102 in the z-direction and connected to the first portion 101 of the semiconductor body 100.

[0084] Bit line structure 500 may include a semiconductor material layer (not shown). The material of the semiconductor material layer may include, but is not limited to, silicon (e.g., single-crystal silicon c-Si), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable semiconductor material. Furthermore, bit line structure 500 may also include a conductor material layer (not shown), wherein the material of the conductor material layer may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TIN), etc. Optionally, the semiconductor material layer of bit line structure 500 and the semiconductor body 100 may include different semiconductor materials. Alternatively, the semiconductor material layer of bit line structure 500 and the semiconductor body 100 may be fabricated from different semiconductor materials.

[0085] Furthermore, the semiconductor device 1000 may also include a bit line isolation structure (not shown), which may be alternately arranged with the bit line structure 500 in directions intersecting both the x and z directions. The bit line isolation structure may include a bit line isolation layer (not shown) and an air gap (not shown) surrounded by the bit line isolation layer. Optionally, the material of the bit line isolation layer may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.

[0086] Optionally, the isolation conductor portion 310 may include a first protrusion 331 facing the bit line structure 500 in the z direction.

[0087] Optionally, the isolation medium portion 320 may include a first isolation medium portion 321, which may be located on the side of the isolation conductor portion 310 away from the bit line structure 500 in the z direction. In addition, the first isolation medium portion 321 may include a second protrusion 332, which may extend toward the bit line structure 500 in the z direction and contact the isolation conductor portion 310.

[0088] In addition, the isolation medium portion 320 may also include a second isolation medium portion 323 and a first isolation medium layer 322, wherein the second isolation medium portion 323 is located between the isolation conductor portion 310 and the bit line structure 500 in the z direction, and the first isolation medium layer 322 is located between the isolation conductor portion 310 and the second isolation medium portion 323 at least in the z direction.

[0089] Optionally, the first isolation dielectric layer 322 may also be located between the isolation conductor portion 310 and the semiconductor body 100, and between the first isolation dielectric portion 321 and the semiconductor body 100. Alternatively, the first isolation dielectric layer 322 may surround the first isolation dielectric portion 321 and the isolation conductor portion 310.

[0090] Optionally, the isolation dielectric portion 320 may further include a second isolation dielectric layer 324, which may be located between the bit line structure 500 and the second isolation dielectric portion 323, and may also be located between the semiconductor body 100 and the first isolation dielectric layer 322. In other words, the second isolation dielectric layer 324 may surround the first isolation dielectric layer 322 and the second isolation dielectric portion 323.

[0091] The insulating medium portion 320 includes multiple different parts, such as at least two of the first insulating medium portion 321, the second insulating medium portion 323, the first insulating medium layer 322, and the second insulating medium layer 324. This can improve the situation of insufficient or uneven filling during the formation of the insulating medium portion using a filling process. The formation process of the insulating structure 300 will be described in detail below with reference to the accompanying drawings.

[0092] Optionally, multiple portions of the isolation dielectric portion 320 may employ different dielectric materials to improve the density and uniformity of the filling. These different dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the material of the first isolation dielectric portion 321 may include silicon nitride, the material of the second isolation dielectric portion 323 may include silicon oxide, the material of the first isolation dielectric layer 322 may include silicon oxynitride, and the material of the second isolation dielectric layer 324 may include a high-k dielectric material. Optionally, the etching selectivity ratio of the material of the first isolation dielectric layer 322 to the material of the isolation conductor portion 310 may be greater than 10:1, thereby using the first isolation dielectric layer 322 as an etching stop layer in the step of forming the isolation conductor portion 310.

[0093] refer to Figure 2 and Figure 3 , Figure 2 The shown isolation conductor portion 310 may include a first protrusion 331 facing the bit line structure 500 in the z-direction. Furthermore, Figure 2 The first isolation medium portion 321 shown may include a second protrusion 332 extending in the z-direction toward the bit line structure 500 and contacting the isolation conductor portion 310. Figure 2 Compared to the semiconductor device 1000 shown, Figure 3 The semiconductor device 1000 shown has no protrusions in its isolation conductor portion 310 and its first isolation dielectric portion 321.

[0094] This is because, during the fabrication of the semiconductor device 1000, after the semiconductor body 100 is formed, its second part 102 protrudes from its first part 101 in the x-direction toward the space where the isolation conductor part 310 and the isolation dielectric part 320 are to be formed. This causes the top dimension of the space in the x-direction to be smaller than the bottom dimension of the space in the x-direction, creating a "bottleneck" at the top of the entire space. Consequently, during the formation of the isolation conductor part 310 and the isolation dielectric part 320 using deposition processes, voids appear in the filler material layer. To solve this problem, a portion of the already formed filler material layer can be removed using etching processes to open the voids. Then, the remaining filler material layer is formed again using multiple deposition processes, filling the previously opened void spaces with the subsequently formed filler material layer. This creates a "protrusion" filling the void spaces, improving the situation of insufficient or uneven filling during the formation of the isolation dielectric part and the isolation conductor part using filling processes, and increasing the density and uniformity of the filling.

[0095] Therefore, in embodiments of this disclosure, the semiconductor device includes a capacitor structure and a transistor located on one side of the capacitor structure in a first direction. The semiconductor body of the transistor extends along the first direction and includes a first portion and a second portion connected to each other in the first direction. The first portion is located on the side of the second portion away from the capacitor structure and has a relatively small size in a second direction intersecting the first direction. This allows the transistor to have a narrower transport path (understood as a narrow channel region) for charge carriers (e.g., electrons or holes) in the operating state, thus relatively increasing the carrier concentration per unit volume. Under the action of the transistor gate voltage, the electric field intensity in the narrow channel region is more concentrated, which can accelerate carrier migration, effectively reduce channel resistance, improve the transistor's drive current capability, and improve the transistor's switching speed, thereby optimizing the electrical performance of the semiconductor device and improving the yield of the semiconductor device.

[0096] In addition, some embodiments of this disclosure also provide a method for manufacturing a semiconductor device 2000. Figure 6 This is a flowchart of a method 2000 for fabricating a semiconductor device according to an exemplary embodiment of the present disclosure. Figures 7 to 27 These are schematic diagrams of a method for fabricating a semiconductor device according to one embodiment of the present disclosure.

[0097] like Figure 6 As shown, this disclosure provides a method for fabricating a semiconductor device 2000, which may include: S1, forming a semiconductor body extending along a first direction, wherein the semiconductor body includes a first part and a second part.

[0098] S2, forming an isolation structure on one side of the semiconductor body in a second direction, wherein the second direction intersects with the first direction.

[0099] S3, forming a capacitor structure located on one side of the semiconductor body along a first direction, wherein a second part of the semiconductor body is located between the first part and the capacitor structure in the first direction, and in a second direction, the size of the second part is larger than the size of the first part.

[0100] The following will combine Figures 7 to 27 The specific processes for each step of the above preparation method 2000 are described in detail.

[0101] Step S1

[0102] Figure 7 This is a cross-sectional schematic diagram of the structure formed after forming a semiconductor substrate 1111 according to a preparation method according to one embodiment of the present disclosure. Figure 8 This is a top view schematic diagram of the structure formed after forming the first groove 1112 according to a preparation method according to an embodiment of the present disclosure. Figure 9This is a top view schematic diagram of the structure formed after forming an initial semiconductor 2100 according to a preparation method according to one embodiment of the present disclosure. Figure 10 This is a cross-sectional schematic diagram of the structure formed after forming an initial semiconductor 2100 according to a preparation method according to one embodiment of the present disclosure. Figure 11 This is a cross-sectional schematic diagram of the structure formed after forming the first process layer 2101 according to a preparation method according to one embodiment of the present disclosure. Figure 12 This is a cross-sectional schematic diagram of the structure formed after forming the fourth process layer 2105 according to a preparation method according to one embodiment of the present disclosure. Figure 13 This is a cross-sectional schematic diagram of the structure formed after removing part of the fourth process layer 2105 according to an embodiment of the present disclosure. Figure 14 This is a cross-sectional schematic diagram of the structure formed after forming the semiconductor body 100 according to a preparation method according to one embodiment of the present disclosure.

[0103] In some embodiments of this disclosure, taking DRAM as an example, the semiconductor device ultimately formed by the semiconductor device fabrication method 2000 may include a transistor layer and a capacitor structure layer, wherein the transistor layer may include transistors, and the capacitor structure layer may include capacitor structures. The capacitor structure layer may be located on one side of the transistor layer in the z-direction, wherein the z-direction can be understood as the stacking direction of the transistor layer and the capacitor structure layer.

[0104] Transistors and capacitor structures connected to transistors can constitute memory cells of a semiconductor device. Multiple memory cells can be spaced apart in a direction intersecting the z-direction. A transistor may include a semiconductor body and a gate structure, wherein the gate structure may be located at least on one side of the semiconductor body in the x-direction. Multiple semiconductor bodies of a transistor layer can also be spaced apart in a direction intersecting the z-direction. It should be noted that the transistor layer and capacitor structure layer can be formed using any suitable process, and this disclosure does not limit this process.

[0105] For example, combining Figure 1 and Figure 6 The fabrication of the transistor layer may include: forming a semiconductor body 100 extending along the z-direction; forming an isolation structure 300 on one side of the semiconductor body 100 in the x-direction; and forming a gate structure 400 at least on the other side of the semiconductor body 100 in the x-direction.

[0106] like Figures 7 to 14As shown, in some embodiments of this disclosure, forming a semiconductor body 100 extending along the z-direction may include: forming a first trench 1112 extending along the z-direction in a semiconductor substrate 1111, wherein a plurality of first trenches 1112 are spaced apart in a third direction (y-direction), dividing at least a portion of the semiconductor substrate 1111 into a plurality of strip semiconductor layers 1113 spaced apart in the y-direction, wherein the x-direction, y-direction, and z-direction intersect each other; forming a second trench 1114 and a third trench 1115 extending along the z-direction, wherein the second trench 1114 and the third trench 1115 are alternately distributed in the x-direction, dividing the strip semiconductor layers 1113 into a plurality of initial semiconductor bodies 2100, the initial semiconductor bodies 2100 may include sidewalls 2111 extending along the z-direction; and filling the first trenches 1112 and the second trenches 1114, and removing a portion of the sidewalls 2111 of the initial semiconductor bodies 2100 via the third trench 1115, thereby forming the semiconductor body 100.

[0107] Specifically, such as Figure 7 As shown, the material used to fabricate the semiconductor substrate 1111 can be any suitable semiconductor material, such as single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide and other group III-V compounds. Alternatively, the semiconductor substrate 1111 can be single-crystal silicon.

[0108] In some embodiments of this disclosure, a semiconductor substrate 1111 can be formed by sequentially depositing multiple layers made of different materials using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0109] In some embodiments of this disclosure, the semiconductor substrate 1111 may include a substrate sacrificial layer (not shown). Optionally, the substrate sacrificial layer may include a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Alternatively, the substrate sacrificial layer may be a high-dielectric-constant dielectric layer. Alternatively, the substrate sacrificial layer may include a dielectric sublayer, a sacrificial sublayer, and a dielectric sublayer disposed sequentially, wherein the dielectric sublayer may be a silicon nitride layer, and the sacrificial sublayer may be a silicon oxide layer. As yet another option, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial sublayer may be monocrystalline silicon or polycrystalline silicon. Specifically, in some embodiments of this disclosure, an exemplary material for forming the sacrificial sublayer may be polycrystalline silicon.

[0110] Furthermore, a portion of the semiconductor substrate 1111 may also form a well region doped with an N-type or P-type dopant via ion implantation or diffusion processes. The dopant may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb); or any one or a combination of boron (B), gallium (Ga), or indium (In). In some embodiments of this disclosure, the well regions may be prepared using the same or different dopants; furthermore, the doping concentration of the well regions may be the same or different, and this disclosure does not limit this.

[0111] like Figure 7 and Figure 8 As shown, after forming the semiconductor substrate 1111, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to remove part of the semiconductor substrate 1111 in order to form a first trench 1112 extending in the z-direction in the semiconductor substrate 1111.

[0112] The first trench 1112 may also extend along the x direction, wherein a plurality of first trenches 1112 are spaced apart in the y direction, thereby forming at least a portion of the semiconductor substrate 1111 as a plurality of strip semiconductor layers 1113 spaced apart in the y direction.

[0113] After forming the strip semiconductor layer 1113, the first trench 1112 can be filled by one or more thin film deposition processes to form a first intermediate (not shown), wherein the thin film deposition process may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Optionally, the material filling the first trench 1112 may include any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, which is not limited herein.

[0114] like Figures 8 to 10 As shown, after forming the strip semiconductor layer 1113, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; alternatively, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to remove a portion of the intermediate including the strip semiconductor layer 1113, forming a second trench 1114 and a third trench 1115 extending along the z-direction, wherein the second trench 1114 and the third trench 1115 can also extend along the y-direction. The second trench 1114 and the third trench 1115 are alternately distributed in the x-direction, thereby dividing the strip semiconductor layer 1113 into a plurality of initial semiconductor bodies 2100.

[0115] like Figure 10 As shown, the initial semiconductor body 2100 can extend along the z direction, exposing not only one end of the initial semiconductor body 2100, but also the sidewall 2111 of the initial semiconductor body 2100.

[0116] For example, the initial semiconductor body 2100 may have a cubic shape and four exposed sidewalls 2111. However, those skilled in the art will understand that the initial semiconductor body 2100 may also have any suitable 3D shape, such as a polyhedral or cylindrical shape. In other words, the cross-section of the initial semiconductor body 2100 in a plane intersecting the z-direction may have a rectangular, trapezoidal, circular, elliptical, or any other suitable shape. It should be understood that, consistent with the scope of this disclosure, for an initial semiconductor body 2100 having a circular or elliptical cross-section in the aforementioned plane, the initial semiconductor body 2100 may still be considered to have multiple sidewalls 2111.

[0117] The material of the initial semiconductor body 2100 is the same as that of the semiconductor substrate and may include any suitable semiconductor material. For example, the material of the initial semiconductor body 2100 may include at least one of doped crystalline silicon or silicides.

[0118] Furthermore, the material of the initial semiconductor body 2100 may also include a metal oxide, which may include at least one of indium gallium zinc oxide, indium tungsten oxide, indium tin oxide, and indium zinc oxide. It should be noted that this disclosure does not limit the material of the semiconductor body.

[0119] The initial semiconductor body 2100 may include a first end and a second end facing away from each other in the z-direction, wherein the first end is closer to the subsequently formed capacitor structure layer than the second end. Optionally, the second ends of the initial semiconductor body 2100 may be connected to each other in the x-direction.

[0120] like Figures 10 to 14As shown, after the initial semiconductor body 2100 is formed, the first trench 1112 and the second trench 1114 can be filled, and a portion of the sidewalls 2111 of the initial semiconductor body 2100 can be removed via the third trench 1115, thereby forming the semiconductor body 100.

[0121] Specifically, such as Figures 10 to 11 As shown, a first process layer 2101 can be formed by one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The first process layer 2101 may be located on the sidewall 2111 of the initial semiconductor body 2100 and on the surface of the first end.

[0122] Optionally, the material of the first process layer 2101 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the material of the first process layer 2101 may include silicon oxide.

[0123] After the first process layer 2101 is formed, a second process layer 2102 can be filled in the first trench 1112 and the second trench 1114 by one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The second process layer 2102 can fill the space of the first trench 1112 and the second trench 1114.

[0124] Optionally, the second process layer 2102 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. Exemplarily, the second process layer 2102 may be formed of a material with a high deposition rate to facilitate rapid filling of the first trench 1112 and the second trench 1114, and the second process layer 2102 should be any material with high dry etching selectivity relative to the first process layer 2101 to facilitate removal in subsequent steps. For example, the material of the second process layer 2102 may include a carbon-containing material.

[0125] like Figures 11 to 13 As shown, before removing a portion of the sidewalls 2111 of the initial semiconductor body 2100 via the third trench 1115 to form the semiconductor body 100, it is also necessary to define the position of the portion of the sidewalls 2111 to be removed.

[0126] Specifically, such as Figures 11 to 12As shown, a third process layer 2103 can be formed in the third trench 1115 by one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0127] The portion of sidewall 2111 covered by the third process layer 2103 is the portion of sidewall 2111 to be subsequently removed. Optionally, the third process layer 2103 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. Exemplarily, the material of the third process layer 2103 may be the same as the material of the second process layer 2102 to facilitate rapid filling of the third trench 1115 and convenient removal in subsequent steps. For example, the material of the third process layer 2103 may comprise a carbon-containing material.

[0128] Furthermore, to protect the portion of the sidewall 2111 that does not need to be removed during subsequent removal of the remaining sidewall 2111, a fourth process layer 2105 may be formed. At least a portion of the fourth process layer 2105 may be located within the third trench 1115 and cover a portion of the first process layer 2101 and a portion of the third process layer 2103. The fourth process layer 2105 may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0129] Optionally, the etching selectivity ratio of the material of the fourth process layer 2105 to the material of the third process layer 2103 or the initial semiconductor body 2100 can be greater than 10:1, thereby protecting the portion of the sidewall 2111 that does not need to be removed during the removal of a portion of the third process layer 2103 and a portion of the sidewall 2111 of the initial semiconductor body 2100.

[0130] like Figures 12 to 13 As shown, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, can be performed to remove the portion of the fourth process layer 2105 covering the third process layer 2103, thereby exposing the third process layer 2103.

[0131] like Figure 13 and Figure 14As shown, the semiconductor body 100 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; alternatively, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can be performed to remove the third process layer 2103 and the portion of the sidewalls 2111 covered by the third process layer 2103, thereby forming the semiconductor body 100. The semiconductor body 100 may include a first portion 101 and a second portion 102, wherein the sidewalls of the second portion 102 are a portion of the sidewalls 2111 of the initial semiconductor body 2100, and the dimension of the second portion 102 in the x-direction is larger than the dimension of the first portion 101 in the x-direction.

[0132] Step S2

[0133] Figure 15 This is a cross-sectional schematic diagram of the structure formed after forming the fifth process layer 2107 according to a preparation method according to one embodiment of the present disclosure. Figure 16 This is a cross-sectional schematic diagram of the structure formed after forming the initial sacrificial layer 2108 according to a preparation method according to one embodiment of the present disclosure. Figure 17 This is a cross-sectional schematic diagram of the structure formed after forming the sacrificial layer 2200 according to a preparation method according to one embodiment of the present disclosure. Figure 18 This is a cross-sectional schematic diagram of the structure formed after forming the first isolation medium layer 322 according to a preparation method according to one embodiment of the present disclosure. Figure 19 This is a cross-sectional schematic diagram of the structure formed after forming the initial isolation conductor portion 2203 according to a preparation method according to one embodiment of the present disclosure. Figure 20 This is a cross-sectional schematic diagram of the structure formed after forming the isolation conductor portion 310 according to a preparation method according to one embodiment of the present disclosure. Figure 21 This is a cross-sectional schematic diagram of the structure formed after forming the initial first isolation medium portion 2206 according to a preparation method according to an embodiment of the present disclosure. Figure 22 This is a cross-sectional schematic diagram of the structure formed after exposing the second process layer 2102 according to a preparation method according to one embodiment of the present disclosure. Figure 23 This is a cross-sectional schematic diagram of the structure formed after exposing the second trench 1114 according to a preparation method according to one embodiment of the present disclosure. Figure 24 This is a cross-sectional schematic diagram of the structure formed after forming an initial gate structure 2209 according to a preparation method according to one embodiment of the present disclosure. Figure 25 This is a cross-sectional schematic diagram of the structure formed after forming the filling medium layer 2300 according to a preparation method according to one embodiment of the present disclosure. Figure 26 This is a cross-sectional schematic diagram of the structure formed after forming the isolation structure 300 according to a preparation method according to one embodiment of the present disclosure.

[0134] like Figures 14 to 26As shown, in some embodiments of this disclosure, the isolation structure formed on one side of the semiconductor body in the second direction may include: forming a sacrificial layer 2200 in a third trench 1115 from a first side 01 in the z direction of the semiconductor body 100; forming an isolation conductor portion 310 in the third trench 1115, wherein the isolation conductor portion 310 is located on one side of the sacrificial layer 2200 in the z direction; filling the remaining space of the third trench 1115 with a first isolation dielectric portion 321; and removing the sacrificial layer 2200 from a second side 02 opposite to the first side 01 in the z direction, thereby forming the isolation structure 300.

[0135] like Figure 13 and Figure 14 As shown, after removing part of the sidewall 2111, the original third groove 1115 (as shown) Figure 11 (As shown) and the space formed after removing a portion of the sidewall 2111 of the initial semiconductor body 2100, can be formed as an expanded third trench 2016. Since the second portion 102 of the semiconductor body 100 protrudes from its first portion 101 in the x-direction toward the expanded third trench 2016, the dimension n2 of the top of the expanded third trench 2016 in the x-direction is smaller than the dimension n3 of the bottom of the expanded third trench 2016 in the x-direction.

[0136] A bottleneck appeared at the top of the expanded third trench 2016, increasing the difficulty of forming the isolation structure in the trench and potentially reducing the filling density and uniformity of the isolation structure formed subsequently in the expanded third trench 2016. To improve the situation of insufficient or uneven filling during the formation of the isolation structure using the filling process, a multi-layer deposition process can be used to form an isolation structure comprising multiple layers in the expanded third trench 2016. Specifically, voids may be generated in the initially formed layer structure due to insufficient filling. Etching processes can be used to remove part of the initially formed layer structure to open these voids. Then, the remaining layer structures are formed through multiple deposition processes, and the voids are filled with the subsequently formed layer structures, thus forming "protrusions" filling the void spaces. This improves the situation of insufficient or uneven filling during the formation of the isolation structure using the filling process and enhances the filling density and uniformity of the isolation structure.

[0137] Optionally, such as Figures 14 to 17As shown, forming a sacrificial layer 2200 from a first side 01 in the z-direction of a semiconductor body 100 in a third trench 1115 (which can be understood as an expanded third trench 2016) may include: forming an initial sacrificial layer 2108 that at least fills the expanded third trench 2016, wherein a first air gap 2109 is formed in the initial sacrificial layer 2108; and removing a portion of the initial sacrificial layer 2108 to form the sacrificial layer 2200, wherein the surface of the sacrificial layer 2200 facing the first side 01 may include a first concave surface 2201 formed based on the first air gap 2109, the first concave surface 2201 being recessed toward the second side 02 in the z-direction.

[0138] Specifically, such as Figures 14 to 15 As shown, after the semiconductor body 100 is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to remove the remaining fourth process layer 2105 and expose the remaining first process layer 2101 covered thereunder.

[0139] After exposing the remaining first process layer 2101, a fifth process layer 2107 may be formed through one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The fifth process layer 2107 may be located in the portion of the sidewall of the semiconductor body 100 not covered by the remaining first process layer 2101. The fifth process layer 2107 and the remaining first process layer 2101 surround the semiconductor body 100, thereby protecting it from damage during the subsequent formation of the isolation structure.

[0140] Optionally, the material of the fifth process layer 2107 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. Exemplarily, the material of the fifth process layer 2107 may be the same as the material of the first process layer 2101.

[0141] like Figures 15 to 16 As shown, an initial sacrificial layer 2108 can be formed, at least filling the expanded third trench 2016, through one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Exemplarily, the material of the initial sacrificial layer 2108 may be the same as the material of the subsequently formed insulating conductor portion.

[0142] Because the top dimension of the expanded third trench 2016 in the x direction is smaller than the bottom dimension n3 in the x direction, the initial sacrificial layer 2108 is not fully filled at the bottom of the trench, thus forming a first air gap 2109.

[0143] like Figures 16 to 17 As shown, the sacrificial layer 2200 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; alternatively, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can be performed to remove a portion of the initial sacrificial layer 2108 to form the sacrificial layer 2200. Exemplarily, the material of the sacrificial layer 2200 is the same as the material of the initial sacrificial layer 2108, and may be the same as the material of the subsequently formed insulating conductor portion.

[0144] During the formation of the sacrificial layer 2200, the first air gap 2109 can be opened to form a fillable space, wherein the inner wall of the opened first air gap 2109 can be formed as a portion of the surface of the sacrificial layer 2200. For example, the surface of the sacrificial layer 2200 facing the first side 01 may include a first concave surface 2201 formed based on the first air gap 2109, and the first concave surface 2201 may be recessed towards the second side 02 along the z-direction.

[0145] like Figures 17 to 20 As shown, in some embodiments of this disclosure, forming the insulating conductor portion 310 may include: forming at least filling the expanded third trench 2016 (e.g. Figure 15 The initial isolation conductor portion 2203 (shown) has a second air gap 2204 formed therein; and a portion of the initial isolation conductor portion 2203 is removed to form an isolation conductor portion 310, wherein the surface of the isolation conductor portion 310 facing the first side 01 may include a second concave surface 2205 formed based on the second air gap 2204, and the second concave surface 2205 may be recessed toward the second side 02 along the z direction.

[0146] like Figure 17 and Figure 19 As shown, at least the expanded third trench 2016 can be formed by one or more thin film deposition processes (e.g., Figure 15 The initial isolation conductor portion 2203 shown in the figure may include, but is not limited to, thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0147] Optionally, if the sacrificial layer 2200 includes a first concave surface 2201, the initial isolation conductor portion 2203 may include a first protrusion 331 facing the first concave surface 2201 in the z-direction. Optionally, the material of the initial isolation conductor portion 2203 may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0148] like Figure 19 and Figure 20 As shown, after the initial isolation conductor portion 2203 is formed, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to remove part of the initial isolation conductor portion 2203 and form the isolation conductor portion 310.

[0149] Optionally, the dimension of the isolation conductor portion 310 in the z-direction may be smaller than the dimension of the first portion 101 of the semiconductor body 100 in the z-direction. Furthermore, in the intermediate body including the isolation conductor portion 310... Figure 20 In the illustrated placement, the isolation conductor portion 310 can be located diagonally below the second portion 102 of the semiconductor body 100. Alternatively, the isolation conductor portion 310 can be located on one side of the first portion 101 of the semiconductor body 100 in the x-direction. The isolation structure including the isolation conductor portion 310 can act as a shield during the operation of the semiconductor device, thereby helping to improve mutual interference between adjacent transistors. Placing the isolation conductor portion 310 on one side of the first portion 101 of the semiconductor body 100 in the x-direction enhances its shielding effect on narrow channel regions in the transistor.

[0150] In addition, such as Figure 17 , Figure 18 and Figure 20 As shown, in some embodiments of this disclosure, forming the isolation structure 300 may further include forming a first isolation dielectric layer 322 located at least in the z direction between the sacrificial layer 2200 and the isolation conductor portion 310, wherein subsequent processing of removing the sacrificial layer 2200 from the second side O2 may stop at the first isolation dielectric layer 322.

[0151] Specifically, such as Figure 17 and Figure 18 As shown, a first isolation dielectric layer 322 at least located on the surface of the sacrificial layer 2200 can be formed by one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Optionally, the first isolation dielectric layer 322 may also cover the remaining first process layer 2101 and fifth process layer 2107.

[0152] The material of the first isolation dielectric layer 322 may include a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. Optionally, the etching selectivity ratio of the material of the first isolation dielectric layer 322 to the material of the sacrificial layer 2200 may be greater than 10:1, so that the subsequent removal of the sacrificial layer 2200 from the second side O2 may stop at the first isolation dielectric layer 322. Exemplarily, the material of the first isolation dielectric layer 322 may include silicon oxynitride.

[0153] like Figures 20 to 26 As shown, in some embodiments of this disclosure, forming the first isolation medium portion 321 may further include: forming an initial first isolation medium portion 2206 that is at least filled in the expanded third trench 2016, wherein the initial first isolation medium portion 2206 includes a second protrusion 332 that contacts the second concave surface 2205; and removing a portion of the initial first isolation medium portion 2206 to form the first isolation medium portion 321.

[0154] Specifically, such as Figure 20 and Figure 21 As shown, an initial first isolation dielectric portion 2206 filling at least the expanded third trench 2016 can be formed by one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Optionally, the material of the initial first isolation dielectric portion 2206 may include any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, which is not limited herein. Exemplarily, the material of the initial first isolation dielectric portion 2206 may include silicon nitride.

[0155] like Figures 21 to 26 As shown, in some embodiments of this disclosure, before removing part of the initial first isolation medium portion 2206 to form the first isolation medium portion 321, or before forming the isolation structure 300, the gate structure 400 of the semiconductor device may be formed first.

[0156] Specifically, forming the gate structure 400 may include: removing the second process layer 2102; forming an initial gate structure 2209 in the space exposed by the second trench 1114; and removing a portion of the initial gate structure 2209 from the second side 02 to form the gate structure 400.

[0157] Combination Figure 10 , Figure 11 as well as Figures 21 to 26Before forming the initial isolation structure, a second process layer 2102 is used to fill the second trench 1114 for forming the gate structure 400. Furthermore, before forming the second process layer 2102, a first process layer 2101 is also formed on the sidewalls 2111 and the surface of the first end of the initial semiconductor body 2100; after forming the second process layer 2102, a cover process layer 2207 is formed at least on the portion of the first process layer 2101 located at the first end. Therefore, before forming the gate structure 400, the cover process layer 2207 can be removed to expose the second process layer 2102 filled in the second trench 1114; and the second process layer 2102 in the second trench 1114 can be removed to expose the second trench 1114, wherein the first process layer 2101 is still formed in the second trench 1114.

[0158] like Figures 21 to 22 As shown, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes can be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to remove the overlay process layer 2207. It should be noted that in this process, a portion of the initial first isolation dielectric portion 2206 is also removed, thereby forming the remaining initial first isolation dielectric portion 2208.

[0159] like Figures 22 to 23 As shown, it can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, can also be performed to remove the second process layer 2102 filled in the second trench 1114 to expose the second trench 1114, wherein the first process layer 2101 is still formed in the second trench 1114.

[0160] like Figure 23 and Figure 24 As shown, an initial gate structure 2209 can be formed on the surface of the portion of the first process layer 2101 located in the second trench 1114 by one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0161] The initial gate structure 2209 may include multiple conductive layers (not shown), wherein the materials of the multiple conductive layers may include, but are not limited to, titanium, titanium nitride, tantalum, tantalum nitride, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, silicides, etc. Optionally, the portion of the first process layer 2101 located in the second trench 1114 may serve as a gate dielectric layer between the multiple conductive layers and the semiconductor body 100.

[0162] In addition, such as Figure 24 and Figure 25 As shown, after forming the initial gate structure 2209, a filling dielectric layer 2300 can be formed through one or more thin film deposition processes to fill the second trench 1114 (e.g., ...). Figure 23 The remaining space (as shown in the figure).

[0163] Optionally, the material of the filling dielectric layer 2300 may include any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, which is not limited herein. Exemplarily, the material of the filling dielectric layer 2300 may be the same as the material of the first process layer 2101.

[0164] like Figure 25 and Figure 26 As shown, after forming the initial gate structure 2209, the gate structure can be... Figure 25 The intermediate shown includes the initial gate structure 2209, which is flipped 180° to remove a portion of the initial gate structure 2209 from the second side 02, forming the gate structure 400.

[0165] Specifically, refer to Figure 9 , Figure 11 , Figure 25 and Figure 26 The initial gate structure 2209 is formed by, for example, a dry etching process or a combination of dry and wet etching processes; alternatively, other manufacturing processes may be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to remove a portion of the second process layer 2102 filled in the first trench 1112, thereby exposing a portion of the initial gate structure 2209 from the second side 02. Subsequently, the initial gate structure 400 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; alternatively, other manufacturing processes may be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to remove a portion of the initial gate structure 2209.

[0166] Subsequently, the space formed after removing part of the initial gate structure 2209 can be filled with a dielectric material through one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0167] Furthermore, during this process, the sacrificial layer 2200 located in the third trench 1115 can be exposed by removing a portion of the second process layer 2102 filled in the first trench 1112. This is formed by, for example, a dry etching process or a combination of dry and wet etching processes; alternatively, other manufacturing processes, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, can be performed to remove the sacrificial layer 2200. One or more thin-film deposition processes are then used to fill the space formed after removing the sacrificial layer 2200 with a dielectric material to form the second isolation dielectric portion 323 of the isolation structure. The thin-film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. It should be noted that the portion of the first process layer 2101 located in the third trench 1115 can serve as the second isolation dielectric layer 324 of the isolation structure.

[0168] Refer again Figure 25 and Figure 26 After the gate structure 400 is formed, the intermediate body on which the gate structure 400 is formed can be flipped 180° to remove part of the remaining initial first isolation medium portion 2208 from the first side 01, forming the first isolation medium portion 321. After the first isolation medium portion 321 is formed, the initial isolation structure is formed as the isolation structure 300.

[0169] Step S3

[0170] Figure 27 This is a cross-sectional schematic diagram of the structure formed after forming the capacitor structure 200 according to a preparation method according to one embodiment of the present disclosure.

[0171] like Figure 26 and Figure 27 As shown, in some embodiments of this disclosure, the semiconductor device fabrication method 2000 may further include: forming a connection structure 1003; and forming a capacitor structure 200 located on one side of the semiconductor body 100 along the z-direction.

[0172] Specifically, the semiconductor body 100 may include a first portion 101 and a second portion 102, wherein the dimension of the second portion 102 in the x-direction may be larger than the dimension of the first portion 101 in the x-direction. Alternatively, a connection structure 1003 may be formed on the side of the second portion 102 away from the first portion 101 in the z-direction.

[0173] A first dielectric layer 1013 is formed on one side of the second part 102 in the z-direction through one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Optionally, the first dielectric layer 1013 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. This disclosure does not limit the material of the first dielectric layer 1013.

[0174] The first dielectric layer 1013 is formed by, for example, a dry etching process or a combination of dry and wet etching processes; alternatively, other manufacturing processes may be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, to remove a portion of the first dielectric layer 1013, forming an opening (not shown) extending in the z-direction, wherein the opening exposes a portion of the second portion 102. Subsequently, a thin film deposition process may be used to form a connection structure 1003 in contact with the second portion 102 within the opening. Optionally, the deposition process may include, but is not limited to, thin film deposition processes or any combination thereof, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0175] Optionally, the connection structure 1003 may include multiple layer structures, such as semiconductor material layer structures, metal silicide layer structures, and metal material layer structures.

[0176] Alternatively, the material of the semiconductor material layer structure may include, but is not limited to, silicon (e.g., polycrystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), or any other suitable semiconductor material. Furthermore, the material of the metal material layer structure may include, but is not limited to, at least one of tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al).

[0177] In some embodiments of this disclosure, forming a capacitor structure 200 located on one side of the semiconductor body 100 along the z-direction may include: forming a stacked structure (not shown) on the side of the first dielectric layer 1013 away from the transistor layer 1002 in the z-direction; forming a capacitor hole (not shown) in the stacked structure; forming a first electrode portion 201 in the capacitor hole; removing a portion of the stacked structure to expose a portion of the surface of the first electrode portion 201; and forming a capacitor dielectric layer 203 on a portion of the surface of the first electrode portion 201, and forming a second electrode portion 202 on the side of the capacitor dielectric layer 203 opposite to the first electrode portion 201.

[0178] Optionally, a stacked structure is formed by sequentially stacking a second dielectric layer (not shown) and a third dielectric layer (not shown) along the z-direction on the side of the first dielectric layer 1013 away from the transistor layer 1002 using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0179] Optionally, the material of the second dielectric layer may include at least one of silicon nitride (Si3N4), silicon oxynitride (SiON), and aluminum oxide (Al2O3). Furthermore, the material of the second dielectric layer may also be doped with dopants such as boron or carbon; for example, the material of the second dielectric layer may include at least one of silicon carbon nitride (SiCN) and silicon boron nitride (SiBN).

[0180] The third dielectric layer and the second dielectric layer may comprise different materials. For example, the third dielectric layer may be formed of a material with a high deposition rate to facilitate rapid formation, and the third dielectric layer should be any material with high dry etching selectivity relative to the second dielectric layer to facilitate removal in subsequent steps. Optionally, the dimension of the third dielectric layer in the z-direction may be larger than the dimension of the second dielectric layer in the z-direction.

[0181] After forming the stacked structure, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to form capacitor holes that pass through the stacked structure in the z-direction, wherein the capacitor holes pass through the second dielectric layer and the third dielectric layer in the z-direction. The capacitor holes can be used to form the first electrode portion 201 of the capacitor structure 200 in subsequent steps.

[0182] After the capacitor aperture is formed, a first electrode portion 201 can be formed in the capacitor aperture by one or more thin film deposition processes, wherein the thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, and this disclosure does not limit them.

[0183] The first electrode portion 201 can be a multi-layer structure or a single-layer structure, and this disclosure does not limit it in this way. For example, the first electrode portion 201 can be a conductive post extending along the z-direction. In the plane intersecting with z, the cross-section of the first electrode portion 201 can be rectangular, circular, elliptical, semi-circular, or other arbitrary shapes, and this disclosure does not limit it in this way. Optionally, the first electrode portion 201 may also include an electrode conductive layer (not shown) and a support core (not shown).

[0184] The material of the first electrode portion 201 may include at least one of a metallic material, a metallic compound material, and a semiconductor material. For example, the material of the first electrode portion 201 may include titanium nitride (TiN), titanium silicide (TiSi2), or nickel silicide (NiSi).

[0185] In some embodiments of this disclosure, after the first electrode portion 201 is formed, it is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes may be performed, such as patterning processes including photolithography, cleaning and chemical mechanical polishing, to gradually remove the third dielectric layer to expose a portion of the surface of the first electrode portion 201.

[0186] A capacitor dielectric layer 203 and a second electrode portion 202 can be sequentially formed on a portion of the exposed first electrode portion 201 through one or more thin film deposition processes. The thin film deposition processes may include, but are not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. This disclosure does not limit the specific processes.

[0187] Optionally, the capacitor dielectric layer 203 is located on at least a portion of the surface of the first electrode portion 201, and the second electrode portion 202 is located on the surface of the capacitor dielectric layer 203 away from the first electrode portion 201. After the second electrode portion 202 is formed, the stacked structure is formed as a capacitor structure layer 1001.

[0188] Alternatively, the material of the capacitor dielectric layer 203 may include a high dielectric constant material. For example, the material of the capacitor dielectric layer 203 may include aluminum oxide (Al₂O₃), tantalum oxide (Ta₂O₃), titanium oxide (TiO₂), yttrium oxide (Y₂O₃), zirconium oxide (ZrO₂), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), Hafnium silicon oxide (HfSi) x O y Hafnium silicon nitride oxide (HfSiON), hafnium zirconate (HfZrO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y At least one of the following: praseodymium oxide (Pr2O3).

[0189] Furthermore, the material of the second electrode portion 202 may include at least one of a metallic material, a metal compound material, and a semiconductor material. For example, the material of the second electrode portion 202 may include titanium nitride (TiN), titanium silicide (TiSi2), or nickel silicide (NiSi). Optionally, the materials of the first electrode portion 201 and the second electrode portion 202 may be the same or different, and this disclosure does not limit this.

[0190] Combination Figures 25 to 27 As an option, it can be based on Figure 25 The intermediate shown forms a capacitor structure layer 1001. For example, after forming the capacitor structure layer 1001, the intermediate including the capacitor structure layer 1001 is flipped 180°, a portion of the initial gate structure 2209 is removed from the second side 02 to form a gate structure 400, and the sacrificial layer 2200 is removed to form an isolation structure 300. It should be noted that this disclosure does not limit the execution order of steps S2 and S3.

[0191] According to at least one embodiment of this disclosure, a semiconductor device includes a capacitor structure and a transistor located on one side of the capacitor structure in a first direction. The semiconductor body of the transistor extends along the first direction and includes a first portion and a second portion connected to each other in the first direction. The first portion is located on the side of the second portion away from the capacitor structure and has a relatively small size in a second direction intersecting the first direction. This allows the transistor to have a narrower transport path (understood as a narrow channel region) for charge carriers (e.g., electrons or holes) in its operating state, thus relatively increasing the carrier concentration per unit volume. Under the action of the transistor gate voltage, the electric field intensity in the narrow channel region is more concentrated, which can accelerate carrier migration, effectively reduce channel resistance, improve the transistor's drive current capability, and improve the transistor's switching speed, thereby optimizing the electrical performance of the semiconductor device and improving its yield.

[0192] Some embodiments of this disclosure also provide a memory system. Figure 28 This is a block diagram of a system with a memory system provided by way of example in this disclosure.

[0193] like Figure 28 As shown, system 3000 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 3100 located therein). Figure 14As shown, system 3000 may include host 3200 and memory system 3100. Memory system 3100 may have one or more memories 3110 and controller 3120. The memories 3110 may include semiconductor structures as described in the embodiments above (e.g., Figure 1 The semiconductor device 1000 is shown. The host 3200 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 3200 may be configured to send or receive data to and from the memory 3110.

[0194] In some embodiments, controller 3120 may be coupled to memory 3110 and host 3200 and configured to control memory 3110. For example, controller 3120 may be configured to control memory 3110 to perform operations such as read, erase, and program. Controller 3120 may also manage data stored in memory 3110 and communicate with host 3200. For example, controller 3120 may communicate with external devices (e.g., host 3200) according to a specific communication protocol. Although exemplary fabrication methods and structures of semiconductor devices have been described herein, it will be understood that one or more features may be omitted, substituted, or added from the structure of the semiconductor device. Furthermore, the materials of the exemplified layers are merely exemplary.

[0195] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to the technical solutions formed by the selected combination of the above-described technical features, but should also cover other technical solutions formed by any combination of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this disclosure.

Claims

1. A semiconductor device, comprising: Capacitor structure, A semiconductor body is located on one side of the capacitor structure in a first direction and extends along the first direction, wherein the semiconductor body includes a first part and a second part, and the second part is located between the first part and the capacitor structure in the first direction; as well as An isolation structure is located on one side of the semiconductor body in a second direction, which intersects the first direction. In the second direction, the size of the second part is larger than the size of the first part.

2. The semiconductor device according to claim 1, wherein, The second part protrudes from the first part in the second direction toward the isolation structure.

3. The semiconductor device according to claim 1, wherein, The material of the first part is the same as the material of the second part.

4. The semiconductor device according to claim 1, wherein in the second direction, the ratio between the size of the first portion and the size of the second portion is greater than or equal to 1 / 4 and less than or equal to 1 / 2.

5. The semiconductor device according to claim 1, wherein, In the first direction, the ratio between the size of the second part and the size of the first part is greater than or equal to 1 / 5 and less than or equal to 1 / 3.

6. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: The gate structure is located on both sides of the semiconductor body in the second direction, at least as opposed to the isolation structure.

7. The semiconductor device according to claim 6, wherein, The semiconductor body includes a first sidewall and a second sidewall facing away from each other in the second direction, wherein the first sidewall faces the gate structure in the second direction; and The plurality of semiconductor bodies include a first semiconductor body and a second semiconductor body that are adjacent in the second direction. Wherein, the first distance between the first semiconductor body and the second semiconductor body is greater than or equal to the second distance between them, the first distance being the distance between the portion of the first sidewall of the first semiconductor body near the capacitor structure and the portion of the first sidewall of the second semiconductor body near the capacitor structure; and the second distance being the distance between the remaining portion of the first sidewall of the first semiconductor body and the remaining portion of the first sidewall of the second semiconductor body.

8. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: The bit line structure is located on the side of the first part away from the second part in the first direction and extends along the second direction.

9. The semiconductor device according to claim 8, wherein, The isolation structure includes: Insulating conductor section; and An isolation medium portion surrounds the isolation conductor portion.

10. The semiconductor device according to claim 9, wherein, The insulating conductor portion includes a first protrusion facing the bit line structure in the first direction.

11. The semiconductor device according to claim 9, wherein, The isolation medium includes: The first isolation dielectric portion is located on the side of the isolation conductor portion away from the bit line structure in the first direction.

12. The semiconductor device according to claim 11, wherein, The first isolation medium includes: The second protrusion extends toward the bit line structure in the first direction and contacts the insulating conductor portion.

13. The semiconductor device according to claim 11, wherein, The isolation medium section further includes: A second isolation dielectric portion is located between the isolation conductor portion and the bit line structure in the first direction; and The first insulating dielectric layer is located between the insulating conductor portion and the second insulating dielectric portion, at least in the first direction.

14. The semiconductor device according to claim 13, wherein, The first isolation dielectric layer is also located between the isolation conductor portion and the semiconductor body, and between the first isolation dielectric portion and the semiconductor body.

15. The semiconductor device according to claim 14, wherein, The isolation medium section further includes: The second isolation dielectric layer is located between the bit line structure and the second isolation dielectric portion, and also between the semiconductor body and the first isolation dielectric portion.

16. A method for fabricating a semiconductor device, comprising: A semiconductor body extending along the first direction is formed; An isolation structure is formed on one side of the semiconductor body in a second direction, wherein the second direction intersects the first direction; as well as A capacitor structure is formed on one side of the semiconductor body in the first direction. The semiconductor body includes a first part and a second part, wherein the second part is located between the first part and the capacitor structure in the first direction; as well as In the second direction, the size of the second part is larger than the size of the first part.

17. The method according to claim 16, wherein, The semiconductor body extending along the first direction includes: A first trench extending along the first direction is formed in a semiconductor substrate, wherein a plurality of the first trenches are spaced apart in a third direction, at least partially dividing the semiconductor substrate into a plurality of strip semiconductor layers spaced apart in the third direction, wherein the first direction, the second direction and the third direction intersect each other; A second trench and a third trench are formed, respectively extending along the first direction, wherein the second trench and the third trench are alternately distributed in the second direction, dividing the strip semiconductor layer into a plurality of initial semiconductor bodies, each initial semiconductor body including sidewalls extending along the first direction; and The semiconductor body is formed by filling the first trench and the second trench, and removing a portion of the sidewalls of the initial semiconductor body via the third trench.

18. The method according to claim 17, wherein, An isolation structure formed on one side of the semiconductor body in a second direction intersecting the first direction includes: A sacrificial layer is formed in the third trench from the semiconductor body on the first side of the first direction; An isolation conductor portion is formed in the third trench, wherein the isolation conductor portion is located on one side of the sacrificial layer in the first direction; The remaining space in the third trench is filled with a first insulating medium; and The sacrificial layer is removed from the second side, which is opposite to the first side in the first direction, thereby forming the isolation structure.

19. The method according to claim 18, wherein, The isolation structure formed in the second direction intersecting the first direction on one side of the semiconductor body further includes: A first insulating dielectric portion is formed at least in the first direction between the sacrificial layer and the insulating conductor portion. The process of removing the sacrificial layer from the second side stops at the first isolation medium section.

20. The method according to claim 18, wherein, The material of the sacrificial layer is the same as the material of the insulating conductor portion.

21. The method according to claim 18, wherein, Forming a sacrificial layer in the third trench from the semiconductor body on the first side of the first direction includes: An initial sacrificial layer is formed to at least fill the third trench, wherein a first air gap is formed in the initial sacrificial layer; and To form the sacrificial layer, a portion of the initial sacrificial layer is removed. The surface of the sacrificial layer facing the first side includes a first concave surface formed based on the first air gap, and the first concave surface is recessed towards the second side along the first direction.

22. The method according to claim 21, wherein, An isolation conductor portion is formed in the third trench, wherein the isolation conductor portion, located on one side of the sacrificial layer in the first direction, comprises: Forming an initial isolation conductor portion that at least fills the third trench, wherein a second air gap is formed in the initial isolation conductor portion; and To form the isolation conductor portion, a portion of the initial isolation conductor portion is removed. The surface of the insulating conductor portion facing the first side includes a second concave surface formed based on the second air gap, and the second concave surface is recessed towards the second side along the first direction.

23. The method according to claim 22, wherein, The initial isolation conductor portion includes a first convex portion facing the first concave surface along the first direction.

24. The method according to claim 22, wherein, Filling the remaining space of the third trench with the first insulating medium includes: Forming an initial first insulating medium portion that at least fills the third trench, wherein the initial first insulating medium portion includes a second protrusion that contacts the second concave surface; and The initial first isolation medium portion is removed to form the first isolation medium portion.

25. A memory system, comprising: At least one semiconductor device as claimed in any one of claims 1 to 16; as well as A controller, coupled to the semiconductor device, is used to control the semiconductor device to store data.

Images