A three-dimensional memory array, fabrication method, memory, and electronic device

Abstract

The application discloses a three-dimensional memory array, a preparation method, a memory and an electronic device, and relates to the technical field of storage. The method comprises the following steps: forming a plurality of first dielectric layers and a plurality of second dielectric layers in an alternating stack on a substrate, forming a first recess penetrating the plurality of first dielectric layers and the plurality of second dielectric layers, etching the plurality of first dielectric layers exposed by the first recess, and forming a second recess. Since the etching rate of the first dielectric layer is greater than the etching rate of the second dielectric layer, the etching rate of the first dielectric layer close to the substrate is greater than the etching rate of the first dielectric layer far from the substrate, so that the layer size deviation of the second recess is corrected based on the different etching rates of the first dielectric layer, the sizes of the different layers of the second recess are as similar as possible or the same, the size difference of each layer of the storage unit formed subsequently is improved, and the consistency of the performance of the storage units of different layers is improved.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a three-dimensional storage array, a fabrication method, a memory, and an electronic device. Background Technology

[0002] With the rapid development of semiconductor technology, the demand for high-capacity storage is constantly increasing. Memory uses a stacking method of memory cells to increase the storage density per unit area, which is expected to break through the limitations of size miniaturization and further enhance the competitiveness of capacity. Since the fabrication of stacked memory cells usually relies on high aspect ratio through-hole technology, existing methods cannot avoid the problem of width differences of through-holes at different depths, resulting in significant differences in the size of subsequent memory cell layers, ultimately causing inconsistencies in the size between memory cell layers. Summary of the Invention

[0003] This application provides a three-dimensional storage array, a fabrication method, a memory, and an electronic device to correct via size differences, improve the size differences of storage cells in different layers, and enhance the consistency of performance of storage cells in different layers.

[0004] In a first aspect, this application provides a method for fabricating a three-dimensional memory array. The method includes: providing a substrate; forming a plurality of alternately stacked first dielectric layers and a plurality of second dielectric layers on the substrate; forming a first groove penetrating the plurality of first dielectric layers and the plurality of second dielectric layers; and etching the plurality of first dielectric layers exposed by the first groove to form a second groove. The plurality of first dielectric layers includes a first first dielectric layer and a second first dielectric layer, with the first first dielectric layer located between the substrate and the second first dielectric layer, and the etching rate of the first first dielectric layer being greater than the etching rate of the second first dielectric layer. This ensures that the etching rate of the first dielectric layer closer to the substrate is greater than that of the first dielectric layer farther from the substrate. Therefore, during the etching process of the plurality of first dielectric layers exposed by the first groove, the interlayer dimensional deviation of the second groove can be corrected based on the different etching rates of the plurality of first dielectric layers, making the dimensions of the second grooves in different layers as similar or identical as possible. This improves the dimensional differences of the memory cells formed subsequently and enhances the consistency of the performance of the memory cells in different layers.

[0005] In one possible implementation, the plurality of first dielectric layers are doped with a first doping element, and the doping concentration of the first first dielectric layer is less than that of the second first dielectric layer. Therefore, by doping the first dielectric layers, the etching rate of the first dielectric layers can be controlled so that the etching rate of the first dielectric layer closer to the substrate is greater than that of the first dielectric layer farther from the substrate. This allows for the correction of interlayer dimensional deviations in the second trench based on the different etching rates of the plurality of first dielectric layers.

[0006] In one possible implementation, the dielectric material of the first dielectric layer is a nitride, and the dielectric material of the second dielectric layer is an oxide. This allows for an oxide-nitride-oxide-nitride (ONON) structure. Since the ONON structure has a relatively mature manufacturing process, it simplifies the implementation of three-dimensional memory arrays, thereby reducing design complexity and production costs.

[0007] For example, the dielectric material for nitrides can be SiN, and the dielectric material for oxides can be SiO2. This makes implementation relatively simple, thereby reducing design complexity and production costs.

[0008] In one possible implementation, the dielectric materials of the first dielectric layer and the second dielectric layer are oxides. This reduces interlayer stress, lowers the requirements for photolithographic alignment accuracy, or reduces the risk of substrate breakage.

[0009] In one possible implementation, the dielectric material of the first dielectric layer and the dielectric material of the second dielectric layer are the same, and multiple second dielectric layers are doped with a second doping element, wherein the first doping element and the second doping element are different. Therefore, using the same dielectric material to form the first and second dielectric layers reduces design complexity and production costs. Furthermore, by making the first doping element in the first dielectric layer different from the second doping element in the second dielectric layer, the first and second dielectric layers can have different etching selectivity.

[0010] In one possible implementation, the dielectric material of the first dielectric layer and the dielectric material of the second dielectric layer are the same, and multiple second dielectric layers are doped with a second doping element, the first doping element and the second doping element are also the same, and the doping concentration of the first dielectric layer and the doping concentration of the second dielectric layer are different, so that the second dielectric layer and the first dielectric layer have an etching selectivity ratio.

[0011] In one possible implementation, the second doping element includes one or a combination of phosphorus, boron, and carbon.

[0012] In one possible implementation, the first doping element includes one or a combination of phosphorus, boron, and carbon.

[0013] In one possible implementation, etching the plurality of first dielectric layers exposed by the first groove includes: providing a first temperature on the side of the substrate facing away from the plurality of first dielectric layers, and providing a second temperature, greater than the first temperature, on the side of the plurality of first dielectric layers facing away from the substrate. Then, the plurality of first dielectric layers exposed by the first groove are etched. Thus, by controlling the temperature of the substrate, the temperature of the first dielectric layers closer to the substrate can be increased towards the first dielectric layers farther from the substrate, so that the etching rate of the first dielectric layers closer to the substrate is greater than the etching rate of the first dielectric layers farther from the substrate. This allows the interlayer dimensional deviation of the second groove to be corrected based on the different etching rates of the plurality of first dielectric layers.

[0014] In one possible implementation, the first temperature is less than 0°C, and the second temperature is greater than 0°C. This allows for efficient use of temperature, achieving a decreasing etching rate from the first dielectric layer near the substrate to the etching rate of the first dielectric layer farther from the substrate.

[0015] Secondly, this application provides a three-dimensional memory array, comprising: a substrate, a plurality of first dielectric layers and a plurality of second dielectric layers alternately stacked on the substrate, and a trench structure. The trench structure includes a first trench and a plurality of mutually spaced second trenches. The first trench penetrates through the plurality of first dielectric layers and the plurality of second dielectric layers, and the second trenches are recessed from the first trench into the first dielectric layer. The plurality of second trenches communicate with the first trench, and the orthographic projections of the plurality of second trenches on the substrate coincide, thereby improving the size difference of subsequently formed memory cells and enhancing the consistency of performance of different memory cells.

[0016] In one possible implementation, the plurality of first dielectric layers are doped with a first dopant element. The plurality of first dielectric layers includes a first first dielectric layer and a second first dielectric layer, with the first first dielectric layer located between the substrate and the second first dielectric layer, and the doping concentration of the first first dielectric layer being lower than that of the second first dielectric layer. Therefore, by doping the first dielectric layers, the etching rate of the first dielectric layers can be controlled so that the etching rate of the first dielectric layer closer to the substrate is greater than that of the first dielectric layer farther from the substrate. This allows for the correction of interlayer dimensional deviations in the second trench based on the different etching rates of the plurality of first dielectric layers.

[0017] In one possible implementation, the dielectric material of the first dielectric layer is a nitride, and the dielectric material of the second dielectric layer is an oxide. This allows for an oxide-nitride-oxide-nitride (ONON) structure. Since the ONON structure has a relatively mature manufacturing process, it simplifies the implementation of three-dimensional memory arrays, thereby reducing design complexity and production costs.

[0018] In one possible implementation, the dielectric materials of the first dielectric layer and the second dielectric layer are oxides. This reduces interlayer stress, lowers the requirements for photolithographic alignment accuracy, or reduces the risk of substrate breakage.

[0019] In one possible implementation, the dielectric material of the first dielectric layer and the dielectric material of the second dielectric layer are the same, and multiple second dielectric layers are doped with a second doping element, wherein the first doping element and the second doping element are different. Therefore, using the same dielectric material to form the first and second dielectric layers reduces design complexity and production costs. Furthermore, by making the first doping element in the first dielectric layer different from the second doping element in the second dielectric layer, the first and second dielectric layers can have different etching selectivity.

[0020] In one possible implementation, the second doping element includes one or a combination of phosphorus, boron, and carbon.

[0021] In one possible implementation, the first doping element includes one or a combination of phosphorus, boron, and carbon.

[0022] Thirdly, this application provides a memory comprising: a controller and at least one three-dimensional storage array, wherein the controller is electrically connected to the at least one three-dimensional storage array. The three-dimensional storage array is a three-dimensional storage array prepared by the methods of the first aspect or embodiments thereof, or the three-dimensional storage array is a three-dimensional storage array of the second aspect or embodiments thereof.

[0023] Fourthly, this application provides an electronic device comprising: a circuit board and a memory, wherein the memory is disposed on the circuit board. The memory is the memory described in the second aspect or in the embodiments thereof.

[0024] Furthermore, the technical effects of the corresponding solutions in the second to fourth aspects can be referred to the technical effects that can be obtained by the corresponding solutions in the first aspect, and the repetitions will not be detailed. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of an electronic device in an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of a memory structure in an embodiment of this application;

[0027] Figure 3 This is a flowchart of the fabrication method of the three-dimensional storage array in the embodiments of this application;

[0028] Figure 4This is a schematic diagram of the three-dimensional storage array in the embodiment of this application during the fabrication process;

[0029] Figure 5 This is another structural schematic diagram of the three-dimensional storage array in the embodiment of this application during the fabrication process;

[0030] Figure 6 This is another structural schematic diagram of the three-dimensional storage array in the embodiment of this application during the fabrication process;

[0031] Figure 7 An equivalent circuit diagram for a single memory cell;

[0032] Figure 8 This is a schematic diagram of semiconductor process equipment.

[0033] Figure 9 This is another schematic diagram of semiconductor process equipment.

[0034] Figure label:

[0035] 1-Electronic device; 2-Memory; 3-Circuit board; 4-Housing; 100-Substrate; 110_1 / 110_2 / 110_3 / 110_4-First dielectric layer; 120_1 / 120_2 / 120_3 / 120_4-Second dielectric layer; 10-First groove; 11-Through hole; 20-Second groove; M0-Transistor; C0-Capacitor; 200-Memory cell; 300-Semiconductor process equipment; 310-Process cavity; 320-Substrate stage; 330-Gas source; 340-RF source; 350-ESC source; 360-First temperature control device; 361-Cooling device; 370-Second temperature control device; 371-Electromagnetic induction heating control device. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The specific operational methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of this application, "multiple" can be understood as "at least two". Furthermore, it should be understood that in the description of this application, terms such as "first" and "second" are used only for distinguishing purposes and should not be construed as indicating or implying relative importance, nor as indicating or implying order.

[0037] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0038] The three-dimensional storage array provided in this application embodiment can be applied to electronic devices with storage functions, such as the memory in an electronic device. Electronic devices include, but are not limited to, terminal devices, communication devices, and electronic components. Terminal devices include, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices, workstations, etc. Communication devices include, but are not limited to, wireless networks, fixed networks, servers, and smart broadband. Electronic components include, but are not limited to, memory (e.g., SRAM), processing chips (e.g., central processing unit (CPU), graphics processing unit (GPU), artificial intelligence (AI) processors, digital signal processors (DSPs), and neural network processors), system-on-chips (SoCs), etc., which are not listed here. It is understood that the specific implementation of the storage array can be determined according to the actual application scenario and is not limited here.

[0039] The following description, in conjunction with the accompanying drawings, describes the three-dimensional storage array, fabrication method, memory, and electronic device provided in the embodiments of this application.

[0040] Figure 1 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. (Refer to...) Figure 1 The electronic device 1 may include a memory 2 and a circuit board 3, which are electrically connected. For example, the memory 2 may be fixed to the circuit board 3 using a bonding or other connection method to achieve an electrical connection between them, thereby transmitting signals.

[0041] For example, the electronic device 1 may also include a housing 4 having an accommodating space, in which the circuit board 3 is disposed and fixed to the housing 4. Furthermore, the circuit board 3 includes, but is not limited to, a printed circuit board (PCB).

[0042] Figure 2This is a schematic diagram of a memory structure in an embodiment of this application, with reference to... Figure 2 The memory may include a controller and a memory array. The controller is electrically connected to the memory array, thereby enabling the controller to access the memory array. The memory may include one or more memory arrays; the specific number of memory arrays can be flexibly designed according to the actual application scenario and is not limited here.

[0043] For example, the electronic device may also include a processor, a cache, etc., wherein the memory may be integrated into the processor, and the memory may be a die or a packaged device. Alternatively, the memory may be independently disposed on a circuit board, and the memory may be a packaged device. For example, the processor may be a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor, and a neural network processor, etc.

[0044] Because three-dimensional storage arrays significantly improve storage density and performance through vertical stacking technology, the storage array in the memory of this application embodiment can be a three-dimensional storage array, improving the storage density and performance of the memory, breaking through the storage density limitations of traditional planar storage arrays, and meeting the ever-increasing data storage demands. Based on this, the memory with comprehensive functions in this application embodiment can be a three-dimensional memory. Exemplarily, the memory includes, but is not limited to, three-dimensional dynamic random access memory (DRAM), three-dimensional NAND flash memory (NAND), etc.

[0045] Figure 3 This is a flowchart of the fabrication method of the three-dimensional storage array in the embodiments of this application, with reference to... Figure 3 The method for fabricating the three-dimensional storage array in this application embodiment includes:

[0046] S10, Provide a substrate.

[0047] For example, substrate 100 includes, but is not limited to, Si substrate, SiGe substrate, Ge substrate, silicon on insulator (SOI) substrate, etc.

[0048] S20. Forming a plurality of alternatingly stacked first dielectric layers and a plurality of second dielectric layers on a substrate.

[0049] For example, refer to Figure 4 , Figure 4This is a schematic diagram illustrating the fabrication process of the three-dimensional storage array in this application embodiment. A deposition process is used to alternately deposit first dielectric layers 110_1, 110_2, 110_3, and 110_4 and second dielectric layers 120_1, 120_2, 120_3, and 120_4 on a substrate 100, forming a stacked structure composed of multiple first dielectric layers 110_1 to 110_4 and multiple second dielectric layers 120_1 to 120_4. Exemplarily, an etch stop layer (ESL) may also be present between the first dielectric layer 110_1 and the substrate 100. Alternatively, a second dielectric layer may also be present between the first dielectric layer 110_1 and the substrate 100; this is not limited here.

[0050] It is understood that, in order to clearly illustrate the first and second dielectric layers in the embodiments of this application, the embodiments of this application are illustrated using four first dielectric layers and four second dielectric layers as an example. In other embodiments of this application, the number of first dielectric layers and the number of second dielectric layers may not be less than 100, for example, 100, 110, 120, 150, 200, etc., and are not limited here. Furthermore, the number of first dielectric layers and the number of second dielectric layers may be the same or different.

[0051] For example, the total thickness of the stacked structure formed by the plurality of first dielectric layers and the plurality of second dielectric layers may be not less than 10 μm, for example, it may be 10 μm, 12 μm, 15 μm, 20 μm, etc., and is not limited here.

[0052] S30, forming a first groove that penetrates multiple first dielectric layers and multiple second dielectric layers.

[0053] For example, refer to Figure 5 , Figure 5 This is another structural schematic diagram of the fabrication process of the three-dimensional storage array in this application embodiment. A dry etching process is used to vertically etch the multiple first dielectric layers 110_1~110_4 and the multiple second dielectric layers 120_1~120_4, forming a first groove 10 penetrating through the multiple first dielectric layers 110_1~110_4 and the multiple second dielectric layers 120_1~120_4. Due to the large number of first dielectric layers 110_1~110_4 and second dielectric layers 120_1~120_4, the thickness of the stacked structure formed by the multiple first dielectric layers 110_1~110_4 and the multiple second dielectric layers 120_1~120_4 is relatively large. This inevitably leads to differences in the width of the first groove 10 at different depths, resulting in a difference between the width of the opening of the first groove 10 and the width of the bottom of the first groove 10, i.e., a Top to Bottom (T2B) bias.

[0054] For example, the first groove 10 has a high aspect ratio, such as not less than 50:1. For example, the aspect ratio can be 50:1, 80:1, 100:1, 150:1, 200:1, etc., and is not limited here.

[0055] For example, refer to Figure 5 The first groove 10 can be a through hole 11. In other embodiments of this application, the first groove 10 can also be a trench.

[0056] S40. Etch the plurality of first dielectric layers exposed by the first groove to form a second groove. The first dielectric layers 110_1 to 110_4 and the second dielectric layers 120_1 to 120_4 have a high etching selectivity, so that the plurality of first dielectric layers 110_1 to 110_4 are mainly etched in step S40.

[0057] For example, refer to Figure 6 (a) and (b) in the text, Figure 6 (a) is a schematic diagram of a three-dimensional storage array during its fabrication process in related technologies. Figure 6 (b) is another structural schematic diagram of the three-dimensional storage array in the embodiment of this application during the fabrication process. A lateral etching process is used to etch multiple first dielectric layers 110_1 to 110_4 exposed by the first groove 10, forming multiple mutually spaced second grooves 20 recessed from the first groove 10 toward the first dielectric layers 110_1 to 110_4. (Refer to...) Figure 6 In (a), due to the good uniformity of the lateral etching process, the width difference of the first groove 10 will still be retained in the formed second groove 20, resulting in a significant difference in the size of the second groove 20 in different layers. That is, the size of the second groove 20 closer to the substrate 100 is smaller than the size of the second groove 20 farther from the substrate 100. This leads to a significant difference in the size of the memory cells formed in subsequent layers, ultimately causing inconsistency in the size of the memory cells between layers. To solve this problem, in the embodiments of this application, referring to... Figure 6In (b) of the diagram, the plurality of first dielectric layers includes a first first dielectric layer 110_1 and a second first dielectric layer 110_2. The first first dielectric layer 110_1 is located between the substrate 100 and the second first dielectric layer 110_2, and the etching rate of the first first dielectric layer 110_1 is greater than the etching rate of the second first dielectric layer 110_2, such that the etching rate of the first dielectric layer closer to the substrate 100 is greater than the etching rate of the first dielectric layer farther from the substrate 100. Therefore, in the lateral etching process, the interlayer dimensional deviation of the second groove 20 can be corrected based on the different etching rates of the plurality of first dielectric layers, making the dimensions of the second grooves 20 in different layers as close as possible or the same, thereby ensuring that the orthographic projections of the plurality of second grooves 20 on the substrate 100 coincide, thus improving the dimensional differences of the subsequently formed memory cells and enhancing the consistency of the performance of the memory cells in different layers.

[0058] For example, the first first dielectric layer 110_1 and the second first dielectric layer 110_2 can be adjacent, or separated by one, two, three or more first dielectric layers. This allows the etching rates of the first dielectric layers 110_1 to 110_4 to decrease, further making the dimensions of the second grooves 20 in different layers approximately or identical.

[0059] Understandably, to clearly demonstrate the difference in etching rates of the first dielectric layers in the embodiments of this application, the above description uses the example of the first dielectric layer 110_1 as the first first dielectric layer and the first dielectric layer 110_2 as the second first dielectric layer. In other embodiments of this application, the first dielectric layer 110_2 may be the first first dielectric layer and the first dielectric layer 110_3 may be the second first dielectric layer, or the first dielectric layer 110_3 may be the first first dielectric layer and the first dielectric layer 110_4 may be the second first dielectric layer, or the first dielectric layer 110_1 may be the first first dielectric layer and the first dielectric layer 110_3 may be the second first dielectric layer, etc., and the specifics will not be elaborated here.

[0060] Understandably, after step S40, the second dielectric layers 120_1 to 120_4 can be etched to reduce the size difference of the first grooves 10 at different layers of the second dielectric layers 120_1 to 120_4, so that the sizes of the first grooves 10 at different layers of the second dielectric layers 120_1 to 120_4 are as similar as possible or the same. Furthermore, after step S40, the remaining structures in the three-dimensional memory array can be fabricated, and the fabrication process can be basically the same as in the prior art, which will not be elaborated here.

[0061] Based on this, embodiments of this application provide a three-dimensional storage array, referring to... Figure 6The three-dimensional memory array may include a substrate 100, a plurality of first dielectric layers 110_1 to 110_4 and a plurality of second dielectric layers 120_1 to 120_4 alternately stacked on the substrate 100, and a groove structure. The groove structure includes a first groove 10 and a plurality of spaced-apart second grooves 20. The first groove 10 penetrates the plurality of first dielectric layers 110_1 to 110_4 and the plurality of second dielectric layers 120_1 to 120_4. The second grooves 20 are recessed from the first groove 10 into the first dielectric layers 110_1 to 110_4, and the plurality of second grooves 20 are connected to the first groove 10. Because the interlayer size deviation of the second grooves 20 can be corrected based on the different etching rates of the plurality of first dielectric layers 110_1 to 110_4 during the lateral etching process, the sizes of the second grooves 20 in different layers can be made as similar or identical as possible. This allows the orthographic projections of the plurality of second grooves 20 on the substrate 100 to coincide, thereby improving the size differences of the memory cells formed subsequently and enhancing the consistency of the performance of the memory cells in different layers.

[0062] Understandably, orthographic projection coincidence refers to coincidence within the allowable error range.

[0063] Exemplarily, a defined structure can be formed in the second groove 20. Exemplarily, the three-dimensional memory array has multiple memory cells, which can be formed on the substrate 100 in a stacked manner. Exemplarily, referring to... Figure 7 , Figure 7 This is an equivalent circuit diagram of a memory cell 200. The memory cell 200 may include a transistor M0 and a capacitor C0. The gate of transistor M0 is connected to the word line (WL), the first electrode of transistor M0 is connected to the bit line (BL), the second electrode of transistor M0 is connected to the first electrode plate of capacitor C0, and the second electrode plate of capacitor C0 is connected to the plate line (PL). Therefore, during read / write operations, the corresponding memory cell is selected via WL, controlling the transistor M0 in that memory cell to conduct. Combined with the potential switching on BL and PL, read / write operations are performed on that memory cell. For example, the first electrode of transistor M0 can be the source, and the second electrode can be the drain. Alternatively, the second electrode of transistor M0 can be the source, and the first electrode can be the drain.

[0064] As an example, in a three-dimensional memory array, word lines and board lines can extend along a direction perpendicular to the substrate 100, and bit lines can extend along a direction parallel to the substrate 100. Based on this, word lines can be placed in the first recess 10, and transistors M0 can be placed in the second recess 20, which can improve the size difference of transistors M0 in each layer of memory cells and improve the consistency of transistor M0 performance in different layers of memory cells. Alternatively, board lines can be placed in the first recess 10, and capacitors C0 can be placed in the second recess 20, which can improve the size difference of capacitors C0 in each layer of memory cells and improve the consistency of capacitor C0 performance in different layers of memory cells. Alternatively, bit line dielectric layers can be placed in the first recess 10, and bit lines can be placed in the second recess 20, which can improve the size difference of bit lines in each layer and improve the consistency of bit line performance in different layers.

[0065] As another example, in a three-dimensional memory array, bit lines and board lines can extend in a direction perpendicular to the substrate 100, and word lines can extend in a direction parallel to the substrate 100. Based on this, bit lines can be placed in the first recess 10, and transistors M0 can be placed in the second recess 20. This can improve the size difference of transistors M0 in each memory cell layer and enhance the consistency of transistor M0 performance across different memory cell layers. Alternatively, board lines can be placed in the first recess 10, and capacitors C0 can be placed in the second recess 20. This can improve the size difference of capacitors C0 in each memory cell layer and enhance the consistency of capacitor C0 performance across different memory cell layers. Alternatively, word line dielectric layers can be placed in the first recess 10, and word lines can be placed in the second recess 20. This can improve the size difference of word lines in each layer and enhance the consistency of word line performance across different layers.

[0066] In one embodiment of this application, the etching rate of the first dielectric layer near the substrate 100 can be increased to a higher rate than that of the first dielectric layer away from the substrate 100 by doping the first dielectric layer. For example, the plurality of first dielectric layers 110_1 to 110_4 are doped with a first dopant element, and the doping concentration of the first first dielectric layer 110_1 is lower than that of the second first dielectric layer 110_2. This results in a higher doping concentration of the first dielectric layer near the substrate 100 than that away from the substrate 100, thereby increasing the etching rate of the first dielectric layer near the substrate 100. This allows for the correction of interlayer dimensional deviations in the second trench 20 based on the different etching rates of the plurality of first dielectric layers.

[0067] For example, in step S20, when depositing the first dielectric layers 110_1 to 110_4, a first doping element is used to dope the first dielectric layers 110_1 to 110_4 of different layers, so that the doping concentration of the first dielectric layers 110_1 to 110_4 tends to increase, so that the etching rate of the first dielectric layers 110_1 to 110_4 tends to decrease, thereby the interlayer size deviation of the second groove 20 can be corrected based on the different etching rates of the multiple first dielectric layers.

[0068] For example, the first doping element includes one or a combination of phosphorus (P), boron (B) and carbon (C).

[0069] As an example, the dielectric material of the first dielectric layers 110_1 to 110_4 is a nitride, and the dielectric material of the second dielectric layers 120_1 to 120_4 is an oxide. This allows for an oxide-nitride-oxide-nitride (ONON) structure. Since the ONON structure has a relatively mature manufacturing process, it simplifies the implementation of three-dimensional memory arrays, thereby reducing design complexity and production costs. Exemplarily, the dielectric material of the nitride can be SiN, allowing for the doping of a first dopant element during SiN deposition. In other embodiments of this application, the dielectric material of the nitride can also be other nitride materials, and is not limited thereto. The dielectric material of the oxide can be SiO2. In other embodiments of this application, the dielectric material of the oxide can also be other oxide materials, and is not limited thereto.

[0070] Figure 8 This is a schematic diagram of semiconductor process equipment, for reference. Figure 8 Semiconductor process equipment 300 includes: a process chamber 310, a substrate stage 320, a gas source 330, a radio frequency (RF) source 340, and an electrostatic-chuck (ESC) source 350. The substrate stage 320 is disposed within the process chamber 310. The gas source 330 and RF source 340 are respectively connected to a gas distribution plate 311 within the process chamber 310. The ESC source 350 is connected to the substrate stage 320. The ESC source 350 controls the substrate stage 320 to electrostatically attach the substrate 100 to the substrate stage 320. The gas source 330 provides gas. The RF source 340 provides RF power to the lower electrode and / or upper electrode within the process chamber 310. Figure 8When fabricating a three-dimensional memory array using the semiconductor process equipment shown, a substrate 100 can be placed on a substrate stage 320, and the substrate 100 can be electrostatically adsorbed onto the substrate stage 320 under the control of an ESC source 350. Then, a plurality of alternately stacked first dielectric layers 110_1 to 110_4 and a plurality of second dielectric layers 120_1 to 120_4 are formed on the substrate 100, and the first dielectric layers 110_1 to 110_4 are doped with a first doping element. Next, an etching gas is introduced through a gas source 330 to perform a vertical etching process, forming a first groove 10 penetrating the plurality of first dielectric layers 110_1 to 110_4 and the plurality of second dielectric layers 120_1 to 120_4. Then, an etching gas is introduced through a gas source 330 to perform a lateral etching process, etching the plurality of first dielectric layers 110_1 to 110_4 exposed by the first groove 10 to form a second groove 20.

[0071] For example, semiconductor process equipment can be plasma etching equipment. It is understood that... Figure 8 The hardware structure of the semiconductor process equipment 300 shown does not constitute a limitation on the semiconductor process equipment 300. The semiconductor process equipment 300 provided in the embodiments of this application may include more or fewer components than shown. The same applies below, and will not be repeated.

[0072] In another embodiment of this application, since nitride-based dielectric layers generally have greater stress compared to oxide-based dielectric layers, they inevitably generate greater interlayer stress. This interlayer stress poses significant process challenges to the fabrication of three-dimensional memory structures. For example, interlayer stress can cause warping of the substrate 100 surface, thus requiring higher photolithographic alignment accuracy; or, interlayer stress can cause the substrate 100 to bend and break. Therefore, in one embodiment of this application, the dielectric materials of the first dielectric layers 110_1 to 110_4 and the second dielectric layers 120_1 to 120_4 are both made of oxide, reducing interlayer stress, lowering the requirements for photolithographic alignment accuracy, or reducing the risk of substrate 100 breakage. Furthermore, since the first dielectric layers 110_1 to 110_4 are doped with the first dopant element, the first dielectric layers 110_1 to 110_4 and the second dielectric layers 120_1 to 120_4 can have an etching selectivity ratio, so that in step S40, the first dielectric layers 110_1 to 110_4 can be etched mainly.

[0073] For example, the dielectric material of the first dielectric layers 110_1 to 110_4 is the same as the dielectric material of the second dielectric layers 120_1 to 120_4. Therefore, using the same dielectric material to form the first dielectric layers 110_1 to 110_4 and the second dielectric layers 120_1 to 120_4 can reduce design complexity and production costs. Furthermore, the multiple second dielectric layers 120_1 to 120_4 are doped with second doping elements, and the first doping elements are different from the second doping elements. This allows the first dielectric layers 110_1 to 110_4 and the second dielectric layers 120_1 to 120_4 to have an etching selectivity ratio, so that in step S40, the first dielectric layers 110_1 to 110_4 can be etched primarily. For example, in step S20, when depositing the second dielectric layers 120_1 to 120_4, a second doping element is used to dope the different layers of the second dielectric layers 120_1 to 120_4, so that the second dielectric layers 120_1 to 120_4 and the first dielectric layers 110_1 to 110_4 can have an etching selectivity ratio.

[0074] In other embodiments of this application, the dielectric materials of the first dielectric layers 110_1 to 110_4 and the second dielectric layers 120_1 to 120_4 are the same, as are the first and second doping elements. Furthermore, the doping concentrations of the first dielectric layers 110_1 to 110_4 and the second dielectric layers 120_1 to 120_4 are different, which can also allow the second dielectric layers 120_1 to 120_4 to have an etching selectivity ratio with the first dielectric layers 110_1 to 110_4. Moreover, the specific values ​​of the doping concentrations of the first dielectric layers 110_1 to 110_4 and the second dielectric layers 120_1 to 120_4, while satisfying the etching selectivity ratio, can be flexibly designed according to the needs of the actual application scenario, and will not be elaborated here.

[0075] For example, the second doping element includes one or a combination of phosphorus (P), boron (B) and carbon (C).

[0076] For example, the doping concentration of the second doped element in the plurality of second dielectric layers 120_1 to 120_4 can be the same, which can reduce the difficulty of fabrication and reduce production costs. Alternatively, the doping concentration of the second doped element in the plurality of second dielectric layers 120_1 to 120_4 can also be different. It is understood that the doping concentration of the second doped element in the second dielectric layers 120_1 to 120_4 can be based on enabling the first dielectric layers 110_1 to 110_4 and the second dielectric layers 120_1 to 120_4 to have a high etching selectivity.

[0077] In another embodiment of this application, in step S40, the temperature of the substrate 100 can be adjusted to make the etching rate of the first dielectric layer near the substrate 100 greater than the etching rate of the first dielectric layer away from the substrate 100. Exemplarily, step S40, etching the plurality of first dielectric layers 110_1 to 110_4 exposed by the first groove 10, may include: providing a first temperature on the side of the substrate 100 opposite to the plurality of first dielectric layers 110_1 to 110_4, and providing a second temperature on the side of the plurality of first dielectric layers 110_1 to 110_4 opposite to the substrate 100, wherein the second temperature is greater than the first temperature. This can cause the temperature of the first dielectric layers 110_1 to 110_4 to tend to increase, so that the etching rate of the first dielectric layer near the substrate 100 is greater than the etching rate of the first dielectric layer away from the substrate 100, and the etching rate of the first dielectric layers 110_1 to 110_4 tends to decrease. Therefore, etching the plurality of first dielectric layers exposed by the first groove 10 can correct the interlayer size deviation of the second groove 20 based on the different etching rates of the plurality of first dielectric layers.

[0078] For example, the first temperature can be less than 0°C, and the second temperature can be greater than 0°C. Thus, temperature can be used reasonably to achieve the effect of a decreasing etching rate for the first dielectric layer 110_1 to the first dielectric layer 110_4.

[0079] For example, the first temperature may not exceed -20℃. For instance, the first temperature can be between -20℃ and -40℃. Based on this, the first temperature can be -20℃, -25℃, -30℃, -35℃, -40℃, etc. Of course, the specific value of the first temperature can be flexibly designed according to the needs of the actual application scenario, and is not limited here.

[0080] For example, the second temperature can be no less than 20°C. For instance, the second temperature can be between 20°C and 40°C. Based on this, the second temperature can be 20°C, 25°C, 30°C, 35°C, 40°C, etc. Of course, the specific value of the second temperature can be flexibly designed according to the needs of the actual application scenario, and is not limited here.

[0081] Figure 9 This is another schematic diagram of semiconductor process equipment, see reference. Figure 9The semiconductor process equipment 300 includes: a process chamber 310, a substrate stage 320, a gas source 330, a radio frequency (RF) source 340, an electrostatic-chuck (ESC) source 350, a first temperature control device 360, and a second temperature control device 370. The first temperature control device 360 ​​is connected to the substrate stage 320 and provides a first temperature. The second temperature control device 370 is connected to a gas distribution plate 311 and provides a second temperature. Figure 9 The implementation of the remaining structures of the semiconductor process equipment shown can be referred to Figure 9 The specific implementation methods of the corresponding structures in the semiconductor process equipment shown are not detailed here.

[0082] For example, in adopting Figure 9 When fabricating a three-dimensional memory array using the semiconductor process equipment shown, a substrate 100 can be placed on a substrate stage 320, and the substrate 100 can be electrostatically adsorbed onto the substrate stage 320 under the control of an ESC source 350. Then, a plurality of alternatingly stacked first dielectric layers and a plurality of second dielectric layers are formed on the substrate 100. Next, an etching gas is introduced through a gas source 330 to perform a vertical etching process, forming a first trench 10 penetrating the plurality of first dielectric layers and the plurality of second dielectric layers. Then, a first temperature control device 360 ​​provides a first temperature to cool the temperature of the side of the substrate 100 facing the substrate stage 320. A second temperature control device 370 provides a second temperature to raise the temperature of the side of the substrate 100 facing away from the substrate stage 320. This allows the temperature of the first dielectric layers 110_1 to 110_4 to increase. Furthermore, an etching gas is introduced through the gas source 330 to perform a lateral etching process, etching the plurality of first dielectric layers exposed by the first trench 10.

[0083] For example, refer to Figure 9 The first temperature control device 360 ​​can be a cooling device (Chiller) 361. In other embodiments of this application, the first temperature control device 360 ​​can also be other devices that can reduce the temperature of the substrate 100, which are not limited here.

[0084] For example, refer to Figure 9 The second temperature control device 370 can be an electromagnetic induction controller 371. In other embodiments of this application, the first temperature control device 360 ​​can also be a laser or other device that can reduce the temperature of the substrate 100, which is not limited here.

[0085] In another embodiment of this application, the doping of the first dielectric layers 110_1 to 100_4 with the first doping element and the temperature control of the substrate 100 can be combined to further make the etching rate of the first dielectric layer closer to the substrate 100 greater than the etching rate of the first dielectric layer farther from the substrate 100, so as to correct the interlayer size deviation of the second groove 20 based on the different etching rates of the plurality of first dielectric layers 110_1 to 100_4.

[0086] The above content is only a specific implementation of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application.

Claims

1. A method for fabricating a three-dimensional storage array, characterized in that, include: Provide a substrate; A plurality of alternatingly stacked first dielectric layers and a plurality of second dielectric layers are formed on the substrate; A first groove is formed that penetrates the plurality of first dielectric layers and the plurality of second dielectric layers; The plurality of first dielectric layers exposed by the first groove are etched to form a second groove; wherein the plurality of first dielectric layers include a first first dielectric layer and a second first dielectric layer, the first first dielectric layer is located between the substrate and the second first dielectric layer, and the etching rate of the first first dielectric layer is greater than the etching rate of the second first dielectric layer.

2. The method according to claim 1, characterized in that, The plurality of first dielectric layers are doped with a first doping element, and the doping concentration of the first first dielectric layer is less than that of the second first dielectric layer.

3. The method according to claim 2, characterized in that, The dielectric material of the first dielectric layer is a nitride, and the dielectric material of the second dielectric layer is an oxide.

4. The method according to claim 2, characterized in that, The dielectric material of the first dielectric layer and the dielectric material of the second dielectric layer are oxides.

5. The method according to claim 4, characterized in that, The dielectric material of the first dielectric layer is the same as that of the second dielectric layer, and the plurality of second dielectric layers are doped with a second doping element, wherein the first doping element is different from the second doping element.

6. The method according to claim 5, characterized in that, The second doping element includes one or a combination of phosphorus, boron and carbon.

7. The method according to any one of claims 1-6, characterized in that, The first doping element includes one or a combination of phosphorus, boron and carbon.

8. The method according to any one of claims 1-7, characterized in that, The etching of the plurality of first dielectric layers exposed by the first groove includes: A first temperature is provided on the side of the substrate opposite to the plurality of first dielectric layers, and a second temperature is provided on the side of the plurality of first dielectric layers opposite to the substrate, wherein the second temperature is greater than the first temperature; The plurality of first dielectric layers exposed by the first groove are etched.

9. The method according to claim 8, characterized in that, The first temperature is less than 0°C, and the second temperature is greater than 0°C.

10. A three-dimensional storage array, characterized in that, include: Substrate; A plurality of first dielectric layers and a plurality of second dielectric layers are alternately stacked on the substrate; The groove structure includes a first groove and a plurality of mutually spaced second grooves. The first groove penetrates the plurality of first dielectric layers and the plurality of second dielectric layers. The second grooves are recessed from the first groove into the first dielectric layer. The plurality of second grooves communicate with the first groove, and the orthographic projections of the plurality of second grooves on the substrate coincide.

11. The three-dimensional storage array according to claim 10, characterized in that, The plurality of first dielectric layers are doped with a first doping element, and the plurality of first dielectric layers include a first first dielectric layer and a second first dielectric layer. The first first dielectric layer is located between the substrate and the second first dielectric layer, and the doping concentration of the first first dielectric layer is less than that of the second first dielectric layer.

12. The three-dimensional storage array according to claim 11, characterized in that, The dielectric material of the first dielectric layer is a nitride, and the dielectric material of the second dielectric layer is an oxide.

13. The three-dimensional storage array according to claim 11, characterized in that, The dielectric material of the first dielectric layer and the dielectric material of the second dielectric layer are oxides.

14. The three-dimensional storage array according to claim 13, characterized in that, The dielectric material of the first dielectric layer is the same as that of the second dielectric layer, and the plurality of second dielectric layers are doped with a second doping element, wherein the first doping element is different from the second doping element.

15. The three-dimensional storage array according to claim 14, characterized in that, The second doping element includes one or a combination of phosphorus, boron and carbon.

16. The three-dimensional storage array according to any one of claims 11-15, characterized in that, The first doping element includes one or a combination of phosphorus, boron and carbon.

17. A memory, characterized in that, include: A controller and at least one three-dimensional storage array, wherein the controller is electrically connected to the at least one three-dimensional storage array; The three-dimensional storage array is a three-dimensional storage array prepared by the method described in any one of claims 1-9, or the three-dimensional storage array is a three-dimensional storage array as described in any one of claims 10-16.

18. An electronic device, characterized in that, include: The circuit board and the memory as described in claim 17, wherein the memory is disposed on the circuit board.

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