Memory device, method of manufacturing memory device, and memory system

Abstract

The application discloses a memory device, a manufacturing method of the memory device, and a storage system. The memory device comprises a plurality of semiconductor bodies arranged in an array, a plurality of storage structures, and a first shielding structure. The semiconductor body comprises a first end portion and a second end portion opposite to each other along a first direction, and a middle portion between the first end portion and the second end portion. The first direction, a row direction of the array, and a column direction of the array intersect with each other in pairs. One storage structure is coupled with one first end portion, and the storage structure and the semiconductor body are arranged opposite to each other along the first direction. The first shielding structure is at least partially arranged between the first end portions of two adjacent semiconductor bodies. The application can improve the comprehensive performance of the memory device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a storage device, a method for manufacturing the storage device, and a storage system. Background Technology

[0002] Memory devices are one of the most important components in electronic systems. With the rapid development of semiconductor technology, optimizing the overall performance of memory devices has become a key research direction in the industry. Summary of the Invention

[0003] This application provides a storage device, a method for manufacturing the storage device, and a storage system for optimizing the overall performance of the storage device.

[0004] According to one aspect of this application, a storage device is provided, comprising a plurality of semiconductor bodies arranged in an array, a plurality of storage structures, and a first shielding structure. The semiconductor bodies include a first end and a second end opposite to each other along a first direction, and an intermediate portion located between the first end and the second end. The first direction, the row direction of the array, and the column direction of the array intersect each other. One of the storage structures is coupled to one of the first ends, and the storage structure is disposed opposite to the semiconductor body along the first direction. The first shielding structure is at least partially disposed between the first ends of two adjacent semiconductor bodies.

[0005] In some embodiments, the first shielding structure includes a plurality of first shielding portions, the first shielding portions extending along the row direction, and the plurality of first shielding portions being arranged at intervals along the column direction.

[0006] In some embodiments, the first shielding structure includes a plurality of second shielding portions, the second shielding portions extending along the column direction and the plurality of second shielding portions being arranged at intervals along the row direction.

[0007] In some embodiments, the first shielding structure includes a plurality of first shielding portions extending along the row direction and a plurality of second shielding portions extending along the column direction, wherein the plurality of first shielding portions and the plurality of second shielding portions are combined to form a mesh structure.

[0008] In some embodiments, the first shielding structure includes a metal shielding layer.

[0009] In some embodiments, the memory device further includes a plurality of gate structures extending along the row direction and coupled to each of the semiconductor bodies in the same row, the plurality of gate structures being spaced apart along the column direction.

[0010] In some embodiments, the first shielding structure and the gate structure are spaced apart along the first direction.

[0011] In some embodiments, the first shielding structure includes a first shielding portion extending along the row direction, one end of the first shielding portion being located between the first ends of two adjacent semiconductor bodies, and the other end being located between two adjacent gate structures.

[0012] In some embodiments, the first shielding structure includes a first shielding portion extending along the row direction and located between two adjacent gate structures along the column direction.

[0013] In some embodiments, the storage device further includes a second shielding structure located on one side of the semiconductor body along the column direction; the first shielding structure and the second shielding structure are spaced apart along the first direction.

[0014] In some embodiments, the first shielding structure includes a first shielding portion extending along the row direction; the second shielding structure includes a third shielding portion extending along the row direction; the dimension of the first shielding portion along the column direction is equal to the dimension of the third shielding portion along the column direction.

[0015] In some embodiments, the first shielding structure includes a first shielding portion extending along the row direction; the second shielding structure includes a third shielding portion extending along the row direction; the dimension of the first shielding portion along the column direction is smaller than the dimension of the third shielding portion along the column direction.

[0016] In some embodiments, the first shielding structure includes a first shielding portion extending along the row direction; the second shielding structure includes a third shielding portion extending along the row direction; the distance between the sidewall of the first shielding portion along the column direction and the sidewall of the corresponding semiconductor body is greater than or equal to the distance between the sidewall of the third shielding portion along the column direction and the sidewall of the corresponding semiconductor body.

[0017] According to another aspect of this application, a method for manufacturing a storage device is provided, comprising the following steps:

[0018] A plurality of semiconductor bodies are provided in an array, each semiconductor body including a first end and a second end opposite to each other along a first direction, and an intermediate portion located between the first end and the second end, wherein the first direction, the row direction of the array, and the column direction of the array intersect each other.

[0019] A first shielding structure is formed, at least partially located between the first ends of two adjacent semiconductor bodies;

[0020] Multiple memory structures are formed, one of the memory structures is coupled to one of the first ends, and the memory structure and the semiconductor body are disposed opposite to each other along the first direction.

[0021] In some embodiments, the first shielding structure formed at least partially between the first ends of two adjacent semiconductor bodies includes:

[0022] An initial isolation structure is formed, at least partially located between two adjacent semiconductor bodies;

[0023] Remove a portion of the initial isolation structure to form an isolation structure with an initial shielding groove at the end along the first direction;

[0024] An initial shielding structure is formed, the initial shielding structure fills the initial shielding groove, and the initial shielding structure covers the end of the isolation structure along the first direction and the end of the semiconductor body along the first direction;

[0025] Remove the portions of the initial shielding structure that cover the isolation structure and the portions that cover the semiconductor body to form the first shielding structure that fills the initial shielding groove.

[0026] According to another aspect of this application, a storage system is provided, comprising:

[0027] At least one storage device as described above;

[0028] A controller, coupled to the storage device, is used to control the storage device to store data.

[0029] According to the embodiments of this application, the memory device, the method for manufacturing the memory device, and the memory system include a plurality of semiconductor bodies arranged in an array, a plurality of memory structures, and a first shielding structure. Each semiconductor body includes a first end, a second end, and an intermediate portion located between the first and second ends, all facing each other along a first direction. The first direction intersects both the row and column directions of the array. Each memory structure is coupled to a first end, and the memory structure and the semiconductor body are disposed opposite each other along the first direction. The first shielding structure is partially or entirely disposed between the first ends of two adjacent semiconductor bodies. This shields the potential coupling between the first ends of two adjacent semiconductor bodies, improving the overall performance of the memory device. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A schematic diagram of a storage device according to an embodiment of this application is shown.

[0032] Figure 2a A partial cross-sectional view of a storage device according to an embodiment of this application is shown.

[0033] Figure 2b A partial cross-sectional view of the storage device in one embodiment of this application is shown from another perspective.

[0034] Figure 2c A partial cross-sectional view of the storage device in one embodiment of this application is shown from another perspective.

[0035] Figure 2d A partial cross-sectional view of a storage device according to another embodiment of this application is shown.

[0036] Figure 2e A partial cross-sectional view of a storage device according to another embodiment of this application is shown.

[0037] Figure 2f A partial cross-sectional view of a storage device according to another embodiment of this application is shown.

[0038] Figure 2g A partial cross-sectional view of a storage device according to another embodiment of this application is shown.

[0039] Figures 3a-3d A schematic diagram of the formation process of the semiconductor body of the memory device in one embodiment of this application is shown.

[0040] Figures 4a-4c A schematic diagram illustrating the formation process of the initial isolation structure in one embodiment of this application is shown.

[0041] Figures 5a-5c A schematic diagram of the formation process of the initial shielding groove in one embodiment of this application is shown.

[0042] Figures 6a-6c A schematic diagram of the formation process of the initial shielding structure in one embodiment of this application is shown.

[0043] Figures 7a-7c A schematic diagram of the formation process of the first shielding structure in one embodiment of this application is shown.

[0044] Figures 8a-8cA schematic diagram of the formation process of the first shielding structure in another embodiment of this application is shown.

[0045] Figures 9a-9c A schematic diagram of the formation process of the first shielding structure in another embodiment of this application is shown.

[0046] Figure 10 A schematic diagram of a storage system according to an embodiment of this application is shown.

[0047] Explanation of reference numerals in the attached figures:

[0048] 10000, Electronic devices;

[0049] 1000, Storage system; 100, Storage device; 200, Controller; 2000, Host;

[0050] 100a, Storage array; 100b, Storage cell; 100c, Peripheral circuitry;

[0051] 10. Semiconductor body; 11. First end; 12. Second end; 13. Middle part; 10a. Initial semiconductor layer; 10a1. Opening; 10a2. Intermediate semiconductor layer; 10b. Initial isolation layer; 10c. Basic structure; 10c1. Trench;

[0052] 20. Storage structure; 21. First electrode; 22. Capacitor dielectric; 23. Second electrode; 20a. Storage node contact;

[0053] 30. First shielding structure; 30a. Initial shielding structure; 31. First shielding part; 32. Second shielding part;

[0054] 40. Gate structure;

[0055] 50. Second shielding structure; 51. Third shielding part;

[0056] 60. Isolation structure; 60a. Initial isolation structure; 61. Initial shielding groove; 611. First initial shielding groove; 612. Second initial shielding groove;

[0057] 70. Bit line;

[0058] X, row direction; Y, column direction; Z, first direction. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0060] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0061] See Figure 1 Some embodiments of this application provide a memory device 100, including peripheral circuitry 100c and a memory array 100a. The peripheral circuitry 100c and the memory array 100a are formed, for example, on different wafers and bonded face-to-face. Compared to side-by-side arrangements, stacked peripheral circuitry 100c and memory array 100a can reduce chip size and improve array efficiency. Optionally, more than one memory array 100a may be stacked together using bonding technology to further improve array efficiency.

[0062] Peripheral circuitry 100c includes, for example, digital, analog, and / or mixed-signal circuitry for facilitating the operation of memory array 100a. Exemplarily, peripheral circuitry 100c includes one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or voltage generators, current or voltage references, portions (e.g., sub-circuits) of the aforementioned functional circuitry, or active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). Exemplarily, peripheral circuitry 100c is implemented using complementary metal-oxide-semiconductor (CMOS) technology.

[0063] Storage array 100a includes, for example, a dynamic random access memory (DRAM) array. Storage array 100a includes multiple storage cells 100b arranged in an array.

[0064] Combined Figures 2a-2cSpecifically, the memory array 100a includes multiple semiconductor bodies 10 and multiple memory structures 20 arranged in an array. Each memory structure 20 is coupled to a semiconductor body 10, and the memory structure 20 and the semiconductor body 10 are positioned opposite each other along a first direction. The first direction Z, the row direction X of the array, and the column direction Y of the array intersect each other pairwise, for example, they are perpendicular to each other or the included angle is acute. Meanwhile, considering other design requirements and process tolerances, the actual number of semiconductor bodies 10 is not equal to the actual number of memory structures 20; for example, the difference in their numbers is limited according to overall performance requirements. Also, due to process tolerances, the actual positions of the semiconductor bodies 10 and the memory structures 20 are not strictly aligned; for example, the positional offset range between them is limited according to overall performance requirements.

[0065] The semiconductor body 10 is made of at least one of the following materials: monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The cross-sectional shape of the semiconductor body 10 in a plane parallel to the row direction X and column direction Y of the array is, for example, a square, rectangle, trapezoid, circle, ellipse, or a combination thereof. The semiconductor body 10 includes a first end 11 and a second end 12 opposite each other along the first direction Z, and an intermediate portion 13 located between the first end 11 and the second end 12. The first end 11, for example, forms the source of a vertical gate transistor (VGT), the second end 12, for example, forms the drain of a vertical gate transistor, and the intermediate portion 13, for example, forms the channel of a vertical gate transistor. The first direction Z, the row direction X of the array, and the column direction Y of the array intersect each other, for example, they are perpendicular to each other or the included angle is acute.

[0066] Optionally, the first end 11 and the second end 12 are doped with an N-type dopant, which includes any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb).

[0067] Optionally, the first end 11 and the second end 12 are doped with a P-type dopant, which includes any one or a combination of boron (B), gallium (Ga), and indium (In).

[0068] The storage structure 20 is, for example, a capacitor. The storage structure 20 is coupled to the first end 11. Exemplarily, the storage structure 20 is coupled to the first end 11 by contacting a storage node contact (SNC) 20a disposed at the first end 11. Optionally, the capacitor includes a first electrode 21, a capacitor dielectric 22, and a second electrode 23 sequentially disposed along a first direction Z, with the first electrode 21 contacting the storage node contact 20a disposed at the first end 11.

[0069] Continue reading Figure 1 , Figures 2a-2c Furthermore, the memory array 100a also includes a first shielding structure 30. The first shielding structure 30 is entirely disposed between the first ends 11 of two adjacent semiconductor bodies 10. Alternatively, the first shielding structure 30 is partially disposed between the first ends 11 of two adjacent semiconductor bodies 10, that is, a portion of the first shielding structure 30 is located between the first ends 11 of two adjacent semiconductor bodies 10, and the remainder is located in other locations, such as in the region between adjacent columns.

[0070] It is important to note that in the 4F2 architecture of vertical gate transistors, adjacent memory nodes are close together. Potential coupling between adjacent bits can cause difficulties in charge writing, making it difficult to fully charge the memory node capacitor, thus affecting the initial margin. For example, if a memory cell 100b needs to be written with data "1", and an adjacent memory cell 100b stores data "0", due to potential coupling, the potential of the lightly doped region of the source of the memory cell 100b to be written will be pulled down by the surrounding memory cells 100b, resulting in a smaller write current for data "1", which in turn prevents the capacitor from being fully charged.

[0071] Based on this, in the 4F2 architecture of vertical gate transistors with adjacent memory nodes being close together, the first shielding structure 30 shields the potential coupling between the first ends 11 of the two adjacent semiconductor bodies 10, for example, shielding the mutual coupling effect between data "0" and data "1" in adjacent memory cells 100b, making charge writing easier, so that the charge of the memory structure 20, such as the capacitor, is more easily filled or closer to being filled, thereby increasing the effective current size, increasing the initial design margin, and thus improving the overall performance of the memory device 100.

[0072] Continue reading Figure 2c In some embodiments, the first shielding structure 30 includes a plurality of first shielding portions 31 extending along the row direction X and a plurality of second shielding portions 32 extending along the column direction Y, wherein the plurality of first shielding portions 31 and the plurality of second shielding portions 32 are combined to form a mesh structure. In this way, the first shielding structure 30 plays a shielding role between two adjacent rows of semiconductor bodies 10 and between two adjacent columns of semiconductor bodies 10, thereby improving the shielding effect.

[0073] See Figure 2dIn other embodiments, the first shielding structure 30 includes a plurality of first shielding portions 31 extending along the row direction X and spaced apart along the column direction Y. In other words, the first shielding structure 30 includes a plurality of elongated first shielding portions 31 extending along the row direction X and spaced apart along the column direction Y. Thus, the first shielding portions 31 provide shielding between the first ends 11 of two adjacent columns of semiconductor bodies 10.

[0074] See Figure 2e In other embodiments, the first shielding structure 30 includes a plurality of second shielding portions 32 extending along the column direction Y and spaced apart along the row direction X. In other words, the first shielding structure 30 includes a plurality of elongated second shielding portions 32 extending along the column direction Y and spaced apart along the row direction X. Thus, the second shielding portions 32 provide shielding between the first ends 11 of two adjacent rows of semiconductor bodies 10.

[0075] Optionally, the extension lengths of the plurality of first shielding parts 31 along the row direction X may be equal or unequal, and the extension lengths of the plurality of second shielding parts 32 along the column direction Y may be equal or unequal. The specific lengths can be adjusted according to design requirements and are not limited here.

[0076] In some embodiments, the first shielding structure 30 includes a metal shielding layer. The material of the metal shielding layer includes, for example, at least one of tungsten (W) and titanium nitride (TiN). The metal shielding layer achieves its shielding effect, for example, by applying a fixed external voltage. Based on this, the metal shielding layer can be formed using the same or similar processes as other metal conductive layers in the memory array 100a, thereby simplifying the fabrication process.

[0077] Combination Figure 1 and Figure 2a In some embodiments, the memory device 100 further includes a plurality of gate structures 40, which extend along the row direction X and are coupled to each semiconductor body 10 in the same row. The plurality of gate structures 40 are arranged at intervals along the column direction Y. The semiconductor body 10, the corresponding memory structure 20, and the corresponding gate structure 40 constitute a memory cell 100b, and the plurality of memory cells 100b are arranged in an array to form a memory array 100a.

[0078] Further, the gate structure 40 is coupled to the sidewall of the semiconductor body 10. Optionally, the gate structure 40 includes a gate dielectric disposed on the sidewall of the semiconductor body 10. Optionally, the gate structure 40 includes a gate dielectric, a gate adhesive layer, and a gate metal layer sequentially disposed on the sidewall of the semiconductor body 10. The material of the gate dielectric includes, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the gate adhesive layer includes, for example, at least one of titanium, titanium nitride, tantalum, and tantalum nitride. The material of the gate metal layer includes, for example, at least one of tungsten, cobalt, copper, aluminum, crystalline silicon, and silicides. The gate adhesive layer can block the diffusion of metal material in the gate metal layer and can also improve the adhesion between the gate metal layer and the gate dielectric.

[0079] Optionally, within a memory cell 100b, the gate structure 40 is coupled to one sidewall of the semiconductor body 10. This increases the density of the memory cells 100b.

[0080] Continue reading Figure 2a Optionally, in two adjacent memory cells 100b along the column direction Y, the gate structures 40 of the two memory cells 100b are arranged opposite to each other, that is, the gate structures 40 are arranged between the semiconductor bodies 10 of the two memory cells 100b facing each other.

[0081] Optionally, the length of the first shielding portion 31 extending in the row direction X is equal to the length of the gate structure 40 extending in the row direction X, thereby improving the shielding effect.

[0082] In some embodiments, the first shielding structure 30 and the gate structure 40 are spaced apart along the first direction Z, i.e., along the extension direction of the channel. In this way, the first shielding structure 30 acts as a shield between the first ends 11 of two adjacent semiconductor bodies 10 while avoiding the area where the gate structure 40 is located, thereby reducing the risk of adverse effects on the gate structure 40 caused by the formation process of the first shielding structure 30.

[0083] See Figure 2f In some embodiments, the first shielding structure 30 includes a first shielding portion 31 extending along the row direction X. One end of the first shielding portion 31 along the first direction Z is located between the first end portions 11 of two adjacent semiconductor bodies 10, and the other end is located between two adjacent gate structures 40. Thus, the first shielding structure 30, located between two adjacent semiconductor bodies 10, provides shielding for both adjacent memory nodes that are relatively close and adjacent gate structures 40 that are relatively close.

[0084] Continue reading Figure 2aIn some embodiments, the first shielding structure 30 includes a first shielding portion 31 extending along the row direction X. Along the column direction Y, the first shielding portion 31 is located between two adjacent gate structures 40. Thus, the first shielding portion 31 is positioned away from the area where the gate structures 40 are located, thereby reducing the risk of adverse effects on the gate structures 40 during the formation process of the first shielding structure 30.

[0085] Combination Figure 2a and Figure 2c In some embodiments, the memory device 100 further includes a second shielding structure 50 located on one side of the semiconductor body 10 along the column direction Y. Along the first direction Z, the first shielding structure 30 and the second shielding structure 50 are spaced apart. The second shielding structure 50, for example, reduces interference between the gate structures 40 of adjacent memory cells 100b by applying an external fixed voltage.

[0086] Optionally, the second shielding structure 50 includes a dielectric layer disposed on the sidewall of the semiconductor body 10 and a conductive layer disposed on the side of the dielectric layer opposite to the semiconductor layer. The material of the dielectric layer includes, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the conductive layer includes, for example, at least one of titanium, titanium nitride, tantalum, and tantalum nitride.

[0087] Optionally, the second shielding structure 50 and the gate structure 40 are located on opposite sides of the semiconductor body 10 along the column direction Y, that is, the second shielding structure 50 is disposed between the semiconductor bodies 10 of two back-to-back memory cells 100b. Based on this, the second shielding structure 50 can be formed simultaneously during the formation of the gate structure 40, thereby simplifying the fabrication process and saving production costs.

[0088] continue Figure 2a and Figure 2c In some embodiments, the first shielding structure 30 includes a first shielding portion 31 extending along the row direction X, and the second shielding structure 50 includes a third shielding portion 51 extending along the row direction X. For example, the first shielding structure 30 includes a plurality of first shielding portions 31 spaced apart along the column direction Y, and the second shielding structure 50 includes a plurality of third shielding portions 51 spaced apart along the column direction Y. Exemplarily, a portion of the plurality of first shielding portions 31 is positionally corresponding to the plurality of third shielding portions 51, and another portion is positionally corresponding to the plurality of gate structures 40.

[0089] continue Figure 2a and Figure 2c Optionally, the dimension of the first shielding portion 31 along the column direction Y is smaller than the dimension of the third shielding portion 51 along the column direction Y. Based on this, the opposite sides of the first shielding portion 31 along the column direction Y are less likely to short-circuit with the first ends 11 of the corresponding two semiconductor bodies 10.

[0090] See Figure 2g Optionally, the dimension of the first shielding part 31 along the column direction Y is equal to the dimension of the third shielding part 51 along the column direction Y. Based on this, since the first shielding part 31 and the second shielding part 32 have the same dimension parameter in the column direction Y, the parameter settings during their formation are the same or similar, thereby simplifying the manufacturing process and saving production costs. Furthermore, the larger dimension of the first shielding part 31 along the column direction Y results in lower resistance, making it less susceptible to interference from surrounding structures, thus better achieving its shielding function.

[0091] Optionally, the distance between the sidewall of the first shielding portion 31 along the column direction Y and the sidewall of the corresponding semiconductor body 10 is greater than or equal to the distance between the sidewall of the second shielding portion 32 along the column direction Y and the sidewall of the corresponding semiconductor body 10. In other words, in a cross-sectional view of the plane formed by the row direction X and the column direction Y of the array, the region where the first shielding portion 31 is located is located within the region where the second shielding portion 32 is located, or the region where the first shielding portion 31 is located coincides with the region where the second shielding portion 32 is located. Based on this, the size of the first shielding portion 31 along the column direction Y is less than or equal to the size of the second shielding portion 32 along the column direction Y, and the side of the first shielding portion 31 along the column direction Y does not extend beyond the side of the second shielding portion 32 along the column direction Y, so that the forming process of the first shielding portion 31 can refer to the form process of the second shielding portion 32, and the forming process of the first shielding portion 31 is less likely to damage the semiconductor body 10. Furthermore, after the first shielding portion 31 is formed, it is less likely to short-circuit with the first end 11 of the semiconductor body 10 that is disposed opposite to it.

[0092] See Figure 1 , Figure 2a and Figure 2b In some embodiments, the memory device 100 further includes a plurality of bit lines 70 extending along the column direction Y and coupled to each semiconductor body 10 in the same column, with the plurality of bit lines 70 spaced apart along the row direction X. The material of the bit lines 70 includes at least one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), crystalline silicon, and silicides.

[0093] Based on the same inventive concept, this application also provides a method for manufacturing a storage device, the method comprising the following steps:

[0094] Step S1: Provide a plurality of semiconductor bodies arranged in an array. Each semiconductor body includes a first end and a second end opposite to each other along a first direction, and an intermediate portion located between the first end and the second end. The first direction, the row direction of the array, and the column direction of the array intersect each other.

[0095] Step S2: Form a first shielding structure that is at least partially located between the first ends of two adjacent semiconductor bodies;

[0096] Step S3: Form multiple memory structures, one memory structure is coupled to a first end, and the memory structure and the semiconductor body are arranged opposite each other along a first direction.

[0097] The following will be combined with the appendix Figures 3a-7c The specific process of some steps of the above preparation method in one embodiment is described in detail.

[0098] See Figures 3a-3d Step S1, the formation process of the array of multiple semiconductor bodies 10 includes, for example:

[0099] An initial semiconductor layer 10a is provided. The material of the initial semiconductor layer 10a includes, for example, at least one selected from single-crystal silicon, polycrystalline silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials. The initial semiconductor layer 10a is doped at both ends along a first direction Z using, for example, an ion implantation or diffusion process, with an N-type dopant or a P-type dopant to form well regions. The dopant includes, for example, any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb); or, the dopant includes, for example, any one or a combination of boron (B), gallium (Ga), or indium (In).

[0100] A portion of the initial semiconductor layer 10a is removed by, for example, a dry etching process or a combination of dry and wet etching processes, or by a patterning process of photolithography, cleaning and chemical mechanical polishing, to form a plurality of openings 10a1 spaced apart along the row direction X, wherein the remaining portion of the initial semiconductor layer 10a forms a plurality of intermediate semiconductor layers 10a2 spaced apart along the row direction X.

[0101] A plurality of openings 10a1 are filled using a thin film deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, to form an initial isolation layer 10b. The initial isolation layer 10b and the intermediate semiconductor layer 10a2 are alternately arranged along the row direction X to form a base structure 10c. The material of the initial isolation layer 10b includes, for example, at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0102] By means of, for example, dry etching or a combination of dry and wet etching, or by patterning processes such as photolithography, cleaning and chemical mechanical polishing, a portion of the base structure 10c is removed to form a plurality of trenches 10c1 spaced along the column direction Y, and a plurality of intermediate semiconductor layers 10a2 are divided into a plurality of arrayed semiconductor bodies 10.

[0103] Step S2, forming a first shielding structure 30 that is at least partially located between the first ends 11 of two adjacent semiconductor bodies 10, for example including:

[0104] See Figures 4a-4c In step S21, an initial isolation structure 60a is formed, at least partially located between two adjacent semiconductor bodies 10. Specifically, a gate structure 40 is formed within a trench 10c1 by, for example, one or more thin film deposition processes and, for example, a punch etch process. The initial isolation structure 60a filling the trench 10c1 is formed on the surface of the gate structure 40 by, for example, one or more thin film deposition processes.

[0105] See Figures 5a-5c In step S22, a portion of the initial isolation structure 60a is removed to form an isolation structure 60 having an initial shielding groove 61 at its end along the first direction Z. Specifically, a portion of the end of the initial isolation structure 60a along the first direction Z is removed by, for example, a dry etching process or a combination of dry and wet etching processes, or by a patterning process of photolithography, cleaning, and chemical mechanical polishing to form the initial shielding groove 61. The initial shielding groove 61 includes a plurality of first initial shielding grooves 611 spaced apart along the column direction Y and a plurality of second initial shielding grooves 612 spaced apart along the row direction X.

[0106] See Figures 6a-6c In step S23, an initial shielding structure 30a is formed. The initial shielding structure 30a fills the initial shielding trench 61 and covers the end of the isolation structure 60 along the first direction Z and the end of the semiconductor body 10 along the first direction Z. Specifically, conductive material is deposited through, for example, one or more thin film deposition processes to form the initial shielding structure 30a, which fills the first initial shielding trench 611 and the second initial shielding trench 612 and covers the end of the isolation structure 60 along the first direction Z and the end of the semiconductor body 10 along the first direction Z.

[0107] See Figures 7a-7cIn step S24, the portions covering the end of the isolation structure 60 and the end of the semiconductor body 10 of the initial shielding structure 30a are removed to form a first shielding structure 30 that fills the initial shielding groove 61, that is, to form a first shielding portion 31 that fills the first initial shielding groove 611 and a second shielding portion 32 that fills the second initial shielding groove 612. Specifically, by, for example, a chemical mechanical polishing (CMP) process, the portions covering the end of the isolation structure 60 and the end of the semiconductor body 10 of the initial shielding structure 30a are removed to form a plurality of first shielding portions 31 arranged at intervals along the column direction Y and a plurality of second shielding portions 32 arranged at intervals along the row direction X, which are flush with the semiconductor body 10, thereby forming a mesh-like first shielding structure 30.

[0108] Combined Figure 2a In step S3, a plurality of memory structures 20 are formed, each memory structure 20 being coupled to a first end 11, and the memory structure 20 and the semiconductor body 10 being disposed opposite each other along a first direction. Specifically, the formation process of the memory structure 20 refers to the formation process of the memory structure 20 in related technologies. The main difference between this embodiment and related technologies is that a first shielding structure 30 is formed before the memory structure 20 is coupled to the first end 11 of the semiconductor body 10.

[0109] Based on this, in the 4F2 architecture of vertical gate transistors with adjacent memory nodes being close together, the first shielding structure 30 shields the potential coupling between the first ends 11 of the two adjacent semiconductor bodies 10, thereby increasing the effective current and improving the overall performance of the memory device 100.

[0110] The following will combine Figure 2d , Figures 8a-8c The specific process of some steps of the above preparation method in another embodiment is described in detail.

[0111] The formation processes of the semiconductor body 10, gate structure 40, and initial isolation structure 60a in this embodiment are the same as or similar to those in other embodiments. The main difference between this embodiment and other embodiments lies in the formation process of the first shielding structure 30. The specific process of forming the first shielding structure 30 in this embodiment will be described in detail below.

[0112] See Figure 8a and Figure 8bAfter forming the semiconductor body 10, the gate structure 40, and the initial isolation structure 60a, a portion of the end of the initial isolation structure 60a along the first direction Z is removed by, for example, a dry etching process or a combination of dry and wet etching processes, or by a patterning process of photolithography, cleaning, and chemical mechanical polishing, to form an initial shielding trench 61. The initial shielding trench 61 includes a plurality of first initial shielding trenches 611 spaced apart along the column direction Y.

[0113] Combination Figure 8b and Figure 8c Subsequently, conductive material is deposited through, for example, one or more thin film deposition processes, to form a first initial shielding structure 30a that fills the first initial shielding trench 611 and covers the end of the isolation structure 60 along the first direction Z and the end of the semiconductor body 10 along the first direction Z.

[0114] Combination Figure 8c and Figure 2d Then, by means of a process such as chemical mechanical polishing (CMP), the ends of the covering isolation structure 60 and the ends of the covering semiconductor body 10 of the first initial shielding structure 30a are removed, forming a plurality of first shielding portions 31 arranged at intervals along the column direction Y, which are flush with the semiconductor body 10, thereby forming a first shielding structure 30 composed of a plurality of strip structures.

[0115] See Figure 2d Based on this, in the 4F2 architecture of vertical gate transistors with adjacent memory nodes that are close to each other, the first shielding part 31 shields the potential coupling between the first ends 11 of the two adjacent semiconductor bodies 10, thereby increasing the effective current and improving the overall performance of the memory device 100.

[0116] The following will combine Figure 2e , Figures 9a-9c The specific process of some steps of the above preparation method in another embodiment is described in detail.

[0117] The formation processes of the semiconductor body 10, gate structure 40, and initial isolation structure 60a in this embodiment are the same as or similar to those in other embodiments. The main difference between this embodiment and other embodiments lies in the formation process of the first shielding structure 30. The specific process of forming the first shielding structure 30 in this embodiment will be described in detail below.

[0118] See Figure 9a and Figure 9bAfter forming the semiconductor body 10, the gate structure 40, and the initial isolation structure 60a, a portion of the end of the initial isolation structure 60a along the first direction Z is removed by, for example, a dry etching process or a combination of dry and wet etching processes, or by a patterning process of photolithography, cleaning, and chemical mechanical polishing, to form an initial shielding trench 61. The initial shielding trench 61 includes a plurality of second initial shielding trenches 612 arranged at intervals along the row direction X.

[0119] Combination Figure 9b and Figure 9c Subsequently, conductive material is deposited through, for example, one or more thin film deposition processes, to form a second initial shielding structure 30a that fills the second initial shielding groove 612 and covers the end of the isolation structure 60 along the first direction Z and the end of the semiconductor body 10 along the first direction Z.

[0120] Combination Figure 9c and Figure 2e Then, by means of a process such as chemical mechanical polishing (CMP), the ends of the covering isolation structure 60 and the ends of the covering semiconductor body 10 of the first initial shielding structure 30a are removed, forming a plurality of second shielding portions 32 arranged at intervals along the row direction X and flush with the semiconductor body 10, thereby forming a first shielding structure 30 composed of a plurality of strip structures.

[0121] See Figure 2e Based on this, in the 4F2 architecture of vertical gate transistors with adjacent memory nodes that are close to each other, the second shielding part 32 shields the potential coupling between the first ends 11 of the two adjacent semiconductor bodies 10, thereby increasing the effective current and improving the overall performance of the memory device 100.

[0122] See Figure 2a In some embodiments, when it is necessary to form the second shielding structure 50, the second shielding structure 50 can be formed simultaneously during the formation of the gate structure 40, thereby simplifying the fabrication process and saving production costs.

[0123] Specifically, after forming a basic structure consisting of an initial isolation layer and intermediate semiconductor layers arranged alternately along the row direction, a portion of the basic structure is removed using, for example, a dry etching process or a combination of dry and wet etching processes, or a patterning process involving photolithography, cleaning, and chemical mechanical polishing. This creates multiple trenches spaced apart along the column direction, which divide the multiple intermediate semiconductor layers into multiple arrayed semiconductor bodies. The multiple trenches include first trenches and second trenches arranged alternately along the column direction.

[0124] Subsequently, an initial gate structure is formed in the first trench and an initial second shielding structure is formed in the second trench through, for example, one or more thin film deposition processes.

[0125] Subsequently, a portion of the initial gate structure and the initial second shielding structure is removed by, for example, an etching process, to form a gate structure and a second shielding structure located on opposite sides of the semiconductor body along the column direction.

[0126] See Figure 10 Based on the same inventive concept, this application also provides a storage system 1000. The storage system 1000 includes a controller 200 and at least one storage device 100 of the above embodiments. The controller 200 is coupled to the storage device 100 and is used to control the storage device 100 to store data.

[0127] Optionally, the controller 200 and the individual storage device 100 are integrated into the memory card. Memory cards include Personal Computer Memory Card International Association (PCMCIA or PC), Compact Flash (CF), Smart Media (SM), Memory Stick, Multimedia Card (MMC), Secure Digital Memory Card (SD), Universal Flash Storage (UFS), etc.

[0128] Optionally, the controller 200 and multiple storage devices 100 are integrated into a solid state drive (SSD).

[0129] In some embodiments, the storage system 1000 is used for mobile phones, desktop computers, laptops, tablets, in-vehicle computers, game consoles, printers, positioning devices, wearable electronic devices 10000, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or other electronic devices 10000 having storage components located therein.

[0130] Optionally, the electronic device 10000 includes a host 2000 and a storage system 1000 having one or more storage devices 100 and a controller 200. The host 2000 may be a processor of the electronic device 10000, such as a central processing unit (CPU) or a system-on-chip (SoC). The host 2000 is configured to send data to or receive data from the storage device 100.

[0131] Optionally, the controller 200 is coupled to the storage device 100 and the processor, and the controller 200 is configured to manage data stored in the storage device 100 and communicate with the processor.

[0132] Optionally, the controller 200 is configured to control the operation of the storage device 100, such as read, erase, and program operations.

[0133] Optionally, the controller 200 is configured to manage various functions related to data stored in or to be stored in the storage device 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0134] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. Furthermore, in the description of this application, unless otherwise stated, "multiple" means at least two, for example, two, three, four, etc. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0135] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A storage device, characterized in that, include: A plurality of semiconductor bodies arranged in an array, each semiconductor body including a first end and a second end opposite to each other along a first direction, and an intermediate portion located between the first end and the second end, wherein the first direction, the row direction of the array, and the column direction of the array intersect each other. Multiple memory structures, one of which is coupled to a first end, and the memory structure is disposed opposite to the semiconductor body along the first direction; A first shielding structure is at least partially disposed between the first ends of two adjacent semiconductor bodies.

2. The storage device according to claim 1, characterized in that, The first shielding structure includes a plurality of first shielding parts, which extend along the row direction and are arranged at intervals along the column direction.

3. The storage device according to claim 1, characterized in that, The first shielding structure includes a plurality of second shielding parts, which extend along the column direction and are arranged at intervals along the row direction.

4. The storage device according to claim 1, characterized in that, The first shielding structure includes a plurality of first shielding portions extending along the row direction and a plurality of second shielding portions extending along the column direction, wherein the plurality of first shielding portions and the plurality of second shielding portions are combined to form a mesh structure.

5. The storage device according to claim 1, characterized in that, The first shielding structure includes a metal shielding layer.

6. The storage device according to claim 1, characterized in that, The memory device further includes a plurality of gate structures that extend along the row direction and are coupled to each of the semiconductor bodies in the same row, and the plurality of gate structures are arranged at intervals along the column direction.

7. The storage device according to claim 6, characterized in that, Along the first direction, the first shielding structure and the gate structure are spaced apart.

8. The storage device according to claim 6, characterized in that, The first shielding structure includes a first shielding portion extending along the row direction, one end of the first shielding portion along the first direction being located between the first ends of two adjacent semiconductor bodies, and the other end being located between two adjacent gate structures.

9. The storage device according to claim 6, characterized in that, The first shielding structure includes a first shielding portion extending along the row direction, and along the column direction, the first shielding portion is located between two adjacent gate structures.

10. The storage device according to claim 1, characterized in that, The storage device further includes a second shielding structure located on one side of the semiconductor body along the column direction; Along the first direction, the first shielding structure and the second shielding structure are spaced apart.

11. The storage device according to claim 1, characterized in that, The first shielding structure includes a first shielding portion extending along the row direction; The second shielding structure includes a third shielding portion extending along the row direction; The dimension of the first shielding part along the column direction is equal to the dimension of the third shielding part along the column direction.

12. The storage device according to claim 1, characterized in that, The first shielding structure includes a first shielding portion extending along the row direction; The second shielding structure includes a third shielding portion extending along the row direction; The dimension of the first shielding part along the column direction is smaller than the dimension of the third shielding part along the column direction.

13. The storage device according to claim 1, characterized in that, The first shielding structure includes a first shielding portion extending along the row direction; The second shielding structure includes a third shielding portion extending along the row direction; The distance between the sidewall of the first shielding part along the column direction and the sidewall of the corresponding semiconductor body is greater than or equal to the distance between the sidewall of the third shielding part along the column direction and the sidewall of the corresponding semiconductor body.

14. A method for manufacturing a storage device, characterized in that, Includes the following steps: A plurality of semiconductor bodies are provided in an array, each semiconductor body including a first end and a second end opposite to each other along a first direction, and an intermediate portion located between the first end and the second end, wherein the first direction, the row direction of the array, and the column direction of the array intersect each other. A first shielding structure is formed, at least partially located between the first ends of two adjacent semiconductor bodies; Multiple memory structures are formed, one of the memory structures is coupled to one of the first ends, and the memory structure and the semiconductor body are disposed opposite to each other along the first direction.

15. The method for manufacturing a storage device according to claim 14, characterized in that, The first shielding structure, which is at least partially located between the first ends of two adjacent semiconductor bodies, includes: An initial isolation structure is formed, at least partially located between two adjacent semiconductor bodies; Remove a portion of the initial isolation structure to form an isolation structure with an initial shielding groove at the end along the first direction; An initial shielding structure is formed, the initial shielding structure fills the initial shielding groove, and the initial shielding structure covers the end of the isolation structure along the first direction and the end of the semiconductor body along the first direction; Remove the portions of the initial shielding structure that cover the isolation structure and the portions that cover the semiconductor body to form the first shielding structure that fills the initial shielding groove.

16. A storage system, characterized in that, include: At least one storage device as described in any one of claims 1-13; A controller, coupled to the storage device, is used to control the storage device to store data.

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