Semiconductor device and manufacturing method thereof, electronic device

Abstract

A semiconductor device includes: a plurality of layers of memory cell arrays stacked along a direction perpendicular to a substrate, the memory cell arrays including at least one column of a plurality of memory cells distributed along a second direction; a plurality of bit lines extending along the direction perpendicular to the substrate through the memory cells of different layers; the memory cells at the same positions of different layers being connected to the same bit line; a plurality of word lines extending along the second direction, distributed in different layers, and distributed along a first direction with the bit lines; the memory cell including a transistor and a first capacitor electrode, the transistor including a semiconductor layer surrounding a word line, and the first capacitor electrode being disposed on a side of the semiconductor layer away from the bit line; a plurality of semiconductor layers of a plurality of transistors in the same column surrounding the same word line and being distributed along the second direction at intervals; the semiconductor layer being connected to the bit line through a first connection layer and connected to the first capacitor electrode through a second connection layer. The scheme provided by the embodiment of the disclosure can increase the on-state current of the transistor of the three-dimensional memory architecture of the horizontal word line.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, making it possible for even the slightest differences in the manufacturing process to affect device performance.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device, which can increase the on-state current of the device.

[0006] This application provides a semiconductor device, characterized in that it includes: a multilayer array of memory cells stacked along a direction perpendicular to the substrate, the array of memory cells including at least one column of a plurality of memory cells distributed along a second direction;

[0007] Multiple bit lines extend through the memory cells in different layers along a direction perpendicular to the substrate; memory cells at the same position in different layers are connected to the same bit line;

[0008] Multiple word lines are distributed in different layers. The word lines and the bit lines are distributed along a first direction, and the word lines extend along a second direction. The first direction and the second direction are parallel to the substrate and intersect each other.

[0009] The memory cell includes a transistor and a first capacitor electrode. The transistor includes a semiconductor layer surrounding the word line, and the first capacitor electrode is disposed on the side of the semiconductor layer opposite to the bit line. Multiple semiconductor layers of multiple transistors in the same column surround the same word line, and the multiple semiconductor layers of multiple transistors in the same column are spaced apart along a second direction. The semiconductor layer is connected to the bit line through a first connection layer disposed between the semiconductor layer and the bit line, and is connected to the first capacitor electrode through a second connection layer disposed between the semiconductor layer and the first capacitor electrode.

[0010] In some embodiments, a plurality of the first interconnect layers distributed along a direction perpendicular to the substrate are connected to form an integral structure.

[0011] In some embodiments, the first capacitor electrode forms a cylindrical structure with its opening direction opposite to that of the semiconductor layer, and the second connecting layer covers the outer bottom wall of the first capacitor electrode facing the semiconductor layer and a portion of the outer side wall connected to the outer bottom wall.

[0012] In some embodiments, the semiconductor layer is covered by the first interconnect layer on the side facing the bit line.

[0013] In some embodiments, the semiconductor layer has a protrusion facing the first capacitor electrode on the side facing the first capacitor electrode, and the semiconductor layer is only partially covered by the second connection layer on the side facing the first capacitor electrode, and the area not covered by the second connection layer is distributed on both sides of the area covered by the second connection layer, which are disposed opposite to each other along a second direction.

[0014] In some embodiments, the maximum dimension of the region of the word line surrounded by the semiconductor layer in the direction perpendicular to the substrate is greater than the maximum dimension of the region not surrounded by the semiconductor layer in the direction perpendicular to the substrate.

[0015] In some embodiments, the semiconductor layer has a recess opposite to the first capacitor electrode on the side facing the first capacitor electrode, and the semiconductor layer on the side facing the first capacitor electrode is covered by the second interconnect layer.

[0016] In some embodiments, the word lines have a consistent dimension along the direction perpendicular to the substrate.

[0017] In some embodiments, the semiconductor device further includes a tenth insulating layer, the tenth insulating layer including a vertical portion disposed between adjacent bit lines along a second direction and extending through multiple layers, and a plurality of surrounding portions extending from the vertical portion and respectively surrounding the word lines of different layers on a side away from the substrate, a side facing the substrate, and a side away from the bit lines, the surrounding portions being disposed between adjacent semiconductor layers along the second direction.

[0018] In some embodiments, multiple surrounding portions of different layers of the same tenth insulating layer are spaced apart along a direction perpendicular to the substrate, or multiple surrounding portions of the same tenth insulating layer are connected to form an integral structure on the side of the word line away from the bit line, and fill the area between adjacent word lines along a direction perpendicular to the substrate.

[0019] In some embodiments, the bit lines are distributed on a portion of the surface of the first interconnect layer facing the bit lines.

[0020] In some embodiments, the transistor further includes a gate insulating layer disposed between the semiconductor layer and the word line surrounding the word line, wherein multiple gate insulating layers of multiple transistors distributed in the same column along the second direction in the same layer are connected to form an integral structure, and the integral structure formed by the multiple gate insulating layers extends continuously on the side facing the substrate, the side away from the substrate, and the side away from the bit line, and is disconnected between adjacent semiconductor layers along the second direction on the side facing the bit line.

[0021] In some embodiments, the memory cell further includes a capacitor, the capacitor and the transistor of the same memory cell are distributed along the first direction, the capacitor includes a dielectric layer and a second capacitor electrode, the dielectric layer is disposed between the first capacitor electrode and the second capacitor electrode, the second capacitor electrode fills the cylindrical structure formed by the first capacitor electrode and is distributed on the side of the first capacitor electrode away from the substrate, the side facing the substrate, and two outer sidewalls disposed opposite to each other along the second direction.

[0022] In some embodiments, multiple second capacitor electrodes of multiple capacitors adjacent to each other along a second direction are connected to form an integral structure;

[0023] A single structure formed by connecting multiple second capacitor electrodes fills the area between adjacent first capacitor electrodes along the second direction, or an isolation layer extending perpendicular to the substrate exists between adjacent first capacitor electrodes along the second direction, the isolation layer spacing the adjacent second capacitor electrodes along the second direction.

[0024] This disclosure provides a method for manufacturing a semiconductor device, including:

[0025] A stacked structure comprising multiple alternating first insulating layers and first sacrificial layers is formed on a substrate;

[0026] A plurality of first holes and a plurality of third holes are formed through the stacked structure along a direction perpendicular to the substrate. The plurality of first holes are spaced apart along a second direction, and the plurality of third holes are spaced apart along the second direction. The first holes and the third holes are spaced apart along a first direction. A second insulating layer is formed covering the sidewalls of the first holes and the sidewalls of the third holes. A first dummy layer is formed filling the first holes and the third holes. The first direction and the second direction are parallel to the substrate and intersect.

[0027] A second hole is formed between adjacent first holes along the second direction, penetrating the stacked structure in a direction perpendicular to the substrate. The sidewall of the second hole exposes the second insulating layer in the first hole. Based on the second hole, the first sacrificial layer is etched in a direction parallel to the substrate until the second insulating layer in the third hole is exposed, forming a first channel extending along the second direction.

[0028] A fourth insulating layer, a second dummy layer, a fifth insulating layer, and a second sacrificial layer are formed in the first channel from the outside to the inside; the fourth insulating layer, the second dummy layer, and the fifth insulating layer surround the second sacrificial layer in sequence, and the second dummy layer has a plurality of first grooves spaced apart along a second direction on the side facing the substrate and the side away from the substrate, with the opening direction of the first grooves facing the second hole; a first connecting layer and a bit line connected to the first connecting layer are formed in the second hole;

[0029] A first trench is formed on the side of the third hole away from the first hole, penetrating the stacked structure and extending along the second direction. Based on the first trench, the first sacrificial layer, the fourth insulating layer, and the second dummy layer are etched along a direction parallel to the substrate, such that the second dummy layer forms a plurality of dummy sub-layers spaced apart along the second direction, and a second groove is formed on the side of the first channel away from the bit line and located between adjacent third holes along the second direction. A second connection layer and a first capacitor electrode connected to the second connection layer are sequentially formed in the second groove, and the first capacitor electrode is disposed on the side of the second connection layer away from the bit line.

[0030] Based on the etching of the first hole, the second sacrificial layer and the fifth insulating layer in the first channel are removed, and the dummy sub-layer facing the first hole is etched away. A word line extending in the second direction is formed in the first channel, and a gate insulating layer and a semiconductor structure layer are sequentially surrounded around the word line. The semiconductor structure layer connects the first connection layer and the second connection layer. The semiconductor structure layer is broken into multiple segments spaced apart in the second direction on the side facing the bit line. The dummy sub-layer is etched away to expose the area where the semiconductor structure layer is connected to the dummy sub-layer. The semiconductor structure layer is etched away to break into multiple semiconductor layers spaced apart in the second direction.

[0031] In some embodiments, when etching the first sacrificial layer, the fourth insulating layer, and the second dummy layer along a direction parallel to the substrate based on the first trench, a third groove located in the first channel and communicating with the second groove is also formed;

[0032] The second groove sequentially forms a second connecting layer and a first capacitor electrode connected to the second connecting layer, including:

[0033] A seventh insulating film, a second connecting layer film, a second conductive film, and a third dummy layer film are sequentially deposited in the first trench, the second groove, and the third groove. The second connecting layer film, the second conductive film, and the third dummy layer film in the first trench are etched away, while the second connecting layer film, the second conductive film, and the third dummy layer film in the second groove are retained, forming a seventh insulating layer, a second connecting layer, a first capacitor electrode, and a third dummy layer. The seventh insulating layer covers the inner walls of the first trench and the second groove and fills the third groove.

[0034] Before etching away the second sacrificial layer and the fifth insulating layer in the first channel based on the first hole, and before etching away the dummy sublayer towards the bit line side, the process further includes:

[0035] The third dummy layer is etched away to expose the inner wall of the first capacitor electrode;

[0036] Based on the first trench etching of the seventh insulating layer, the second insulating layer, and the first dummy layer, the two outer sidewalls of the second connection layer disposed opposite each other along the second direction, and the two outer sidewalls disposed perpendicular to the substrate direction are exposed. The exposed second connection layer is etched, and the second connection layer covering the side of the first capacitor electrode facing the first hole is retained, exposing the two outer sidewalls of the first capacitor electrode disposed opposite each other along the second direction, and the two outer sidewalls disposed opposite each other along the perpendicular to the substrate direction.

[0037] A second capacitor electrode is formed, which fills the second groove where the first capacitor electrode is located, and covers the outer sidewalls of the first electrode exposed on the side facing the substrate and the side away from the substrate, and covers the two outer sidewalls of the first electrode that are disposed opposite each other along the second direction; and a plurality of capacitor electrodes in the same column distributed along the second direction are connected to form an integral structure, which fills the area between adjacent first capacitor electrodes along the second direction.

[0038] In some embodiments, forming a first connection layer and a bit line connected to the first connection layer in the second hole includes:

[0039] A sixth insulating film, a first connecting layer film, and a first conductive film are sequentially deposited in the second hole to form a sixth insulating layer, a first connecting sublayer, and a bit line. The sixth insulating layer and the first connecting sublayer sequentially cover the bottom wall and sidewall of the second hole, and the bit line fills the second hole.

[0040] Before removing the second sacrificial layer and the fifth insulating layer in the first channel by etching based on the first hole, the method further includes: etching the first interconnect layer based on the first hole to expose the bit line, and etching the bit line to reduce the size of the bit line along the second direction.

[0041] This disclosure provides a method for manufacturing a semiconductor device, including:

[0042] A stacked structure comprising multiple alternating first insulating layers and first sacrificial layers is formed on a substrate;

[0043] A plurality of first holes and a plurality of third holes are formed through the stacked structure along a direction perpendicular to the substrate. The plurality of first holes are spaced apart along a second direction, and the plurality of third holes are spaced apart along the second direction. The first holes and the third holes are spaced apart along a first direction. A first dummy layer is formed to fill the first holes and the third holes. The first direction and the second direction are parallel to the substrate and intersect.

[0044] A plurality of fifth holes are formed through the stacked structure perpendicular to the substrate and spaced apart along the second direction. The fifth holes are disposed between adjacent third holes along the second direction, and the sidewalls of the fifth holes expose the first dummy layer in the third holes. The first insulating layer is etched parallel to the substrate based on the fifth holes to form a fourth groove. A third sacrificial layer is formed covering the inner wall of the fifth holes and the inner wall of the fourth groove, and a fourth dummy layer is formed filling the fifth holes and the fourth groove.

[0045] A second hole is formed between adjacent first holes along a second direction, penetrating the stacked structure in a direction perpendicular to the substrate. The sidewall of the second hole exposes a first dummy layer in the first hole. Based on the second hole, the first insulating layer is etched in a direction parallel to the substrate to form a fifth groove. A fourth sacrificial layer is formed covering the inner wall of the second hole and the inner wall of the fifth groove, and a fifth dummy layer is formed filling the second hole and the fifth groove.

[0046] The first dummy layer and the first insulating layer are etched away, and the third sacrificial layer and the fourth sacrificial layer are etched away. A second channel extending in a second direction is formed between adjacent first sacrificial layers. The second channel includes a connecting region connecting the first hole and the second hole and an intermediate region connecting the connecting region. A plurality of isolation sublayers are formed to fill the plurality of the intermediate regions.

[0047] A twelfth insulating layer and a sixth dummy layer are formed to sequentially cover the sidewall of the first hole, the sidewall of the third hole, and the inner wall of the connecting area, and the sixth dummy layer fills the connecting area;

[0048] A first connection layer and a bit line connected to the first connection layer are formed in the second hole;

[0049] The fourth dummy layer is removed by etching, and the third sacrificial layer in the fourth groove is etched to form a fifteenth insulating layer that fills the third groove.

[0050] The first sacrificial layer is etched to form a sixth groove. A second connection layer and a first capacitor electrode connected to the second connection layer are sequentially formed in the sixth groove. The first capacitor electrode is disposed on the side of the second connection layer away from the bit line.

[0051] A sixth dummy layer is etched in the first and third vias, such that the sixth dummy layer forms a surrounding structure around the first sacrificial layer on the side away from the substrate, the side facing the substrate, and the side away from the first via; a first channel is formed between a plurality of first vias and a plurality of third vias adjacent in a first direction, extending in a second direction, the first channel exposing the inner surface of the sixth dummy layer in the connected region; a word line extending in a second direction is formed in the first channel, a gate insulating layer and a semiconductor structure layer are sequentially surrounding the word line, the semiconductor structure layer connects the first interconnect layer and the second interconnect layer, the semiconductor structure layer is broken into multiple segments spaced apart in the second direction on the side facing the bit line; the sixth dummy layer is etched away to expose the region where the semiconductor structure layer is connected to the sixth dummy layer, the semiconductor structure layer is etched so that the semiconductor structure layer is broken into multiple semiconductor layers spaced apart in the second direction.

[0052] In some embodiments, before the second connection layer and the first capacitor electrode connected to the second connection layer are sequentially formed in the sixth groove, the following is further included:

[0053] The fifteenth insulating layer is etched based on the sixth groove to reduce the dimension of the fifteenth insulating layer in the direction perpendicular to the substrate;

[0054] The sixth groove sequentially forms a second connecting layer and a first capacitor electrode connected to the second connecting layer, comprising:

[0055] A sixteenth insulating layer, a second connecting layer, and a first capacitor electrode are formed, sequentially covering the inner wall of the sixth groove;

[0056] Before forming a first channel extending in a second direction between a plurality of first holes and a plurality of third holes adjacent in a first direction, the method further includes:

[0057] The inner wall of the first capacitor electrode is exposed;

[0058] The second connection layer is etched to expose the two outer sidewalls of the second connection layer that are disposed opposite each other along the second direction, and the two outer sidewalls that are disposed opposite each other along the direction perpendicular to the substrate. The second connection layer covering the side of the first capacitor electrode facing the first hole is preserved, and the two outer sidewalls of the first capacitor electrode that are disposed opposite each other along the second direction and the two outer sidewalls that are disposed opposite each other along the direction perpendicular to the substrate are exposed.

[0059] A second capacitor electrode is formed, which fills the second groove where the first capacitor electrode is located, and covers the exposed outer sidewalls of the first electrode facing the substrate and away from the substrate, and covers the two outer sidewalls of the first electrode that are disposed opposite to each other along the second direction.

[0060] In some embodiments, forming a first connection layer and a bit line connected to the first connection layer in the second hole includes:

[0061] The second hole and the fifth groove are exposed, forming a fourteenth insulating layer that fills the fifth groove and covers the bottom and side walls of the second hole, and the thickness of the fourteenth insulating layer in the second hole is reduced;

[0062] A first interconnect layer film and a first conductive film are sequentially deposited in the second hole to form a first interconnect sublayer and a bit line. The first interconnect sublayer covers the bottom wall and sidewall of the second hole, and the bit line fills the second hole.

[0063] Before forming a first channel extending along a second direction between a plurality of first holes and a plurality of third holes adjacent along a first direction, the method further includes: etching the first connection layer based on the first holes to expose the bit line, and etching the bit line such that the size of the bit line along the second direction is reduced.

[0064] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed according to the manufacturing method of any of the semiconductor devices described above.

[0065] This disclosure provides a semiconductor device and its manufacturing method, as well as an electronic device. The semiconductor device includes: a multilayer array of memory cells stacked perpendicular to a substrate direction, the memory cell array including at least one column of multiple memory cells distributed along a second direction; multiple bit lines extending through memory cells in different layers along a direction perpendicular to the substrate; memory cells at the same position in different layers connected to the same bit line; multiple word lines distributed in different layers, word lines and bit lines distributed along a first direction, and word lines extending along a second direction; the first and second directions are parallel to the substrate and intersect; each memory cell includes a transistor and a first capacitor electrode, the transistor including a semiconductor layer surrounding the word line, and the first capacitor electrode disposed on the side of the semiconductor layer away from the bit line; multiple semiconductor layers of multiple transistors in the same column surrounding the same word line, and the multiple semiconductor layers of multiple transistors in the same column being spaced apart along the second direction; the semiconductor layer is connected to the bit line through a first connection layer disposed between the semiconductor layer and the bit line, and the first capacitor electrode is connected through a second connection layer disposed between the semiconductor layer and the first capacitor electrode. The semiconductor device of this application, by providing the first connection layer and the second connection layer, can reduce contact resistance and increase the on-state current of transistors in a three-dimensional memory architecture including semiconductor layers surrounding horizontal word lines.

[0066] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings.

[0067] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0068] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0069] Figures 1A to 1F Schematic cross-sectional views of the semiconductor device provided in the embodiments of this disclosure along the AA' and BB' directions parallel to the substrate and the CC', DD', EE', and FF' directions perpendicular to the substrate;

[0070] Figure 2A , Figure 2B and Figure 2C Cross-sectional views along the AA', BB', and DD' directions respectively, provided in some embodiments after the formation of the first and third holes;

[0071] Figures 3A to 3F Cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the formation of the second hole and the first channel are provided in some embodiments;

[0072] Figures 4A to 4F Cross-sectional views of the formation of the fourth insulating layer, the second dummy layer, the fifth insulating layer, and the second sacrificial layer along the AA' direction, the B1B1' direction, the CC' direction, the DD' direction, the EE' direction, and the FF' direction, respectively, provided in some embodiments;

[0073] Figures 5A to 5E Cross-sectional views along the AA', B1B1', CC', EE', and FF' directions after the formation of the sixth insulating layer, the first connecting sublayer, and the bit line, respectively, are provided in some embodiments.

[0074] Figures 6A to 6D These are cross-sectional views along the AA', B1B1', DD', and FF' directions after forming a dummy sublayer, provided in some embodiments.

[0075] Figures 7A to 7CCross-sectional views along the AA', BB', and FF' directions respectively, provided in some embodiments after forming the seventh insulating layer, the second connecting layer, the first capacitor electrode, and the third dummy layer;

[0076] Figures 8A to 8D Cross-sectional views along the AA', BB', DD', and FF' directions respectively, provided in some embodiments after the formation of the dielectric layer and the second capacitor electrode;

[0077] Figures 9A to 9D These are cross-sectional views along the AA', BB', CC', and DD' directions after thinning the bit line, provided in some embodiments.

[0078] Figures 10A to 10E Cross-sectional views along the AA', BB', DD', EE', and FF' directions after the first channel is exposed, provided in some embodiments;

[0079] Figures 11A to 11E Cross-sectional views along the AA', BB', DD', EE', and FF' directions after the formation of the semiconductor layer, gate insulating layer, and word line are provided in some embodiments.

[0080] Figures 12A to 12F Cross-sectional schematic diagrams of semiconductor devices provided for other embodiments along the AA', BB', CC', DD', EE', and FF' directions, respectively;

[0081] Figure 13A , Figure 13B and Figure 13C Cross-sectional views along the AA', BB', and FF' directions respectively, provided in some embodiments after the formation of the first and third holes;

[0082] Figures 14A to 14C These are cross-sectional views along the AA', BB', and DD' directions respectively, provided in some embodiments after the formation of the fifth hole and the fourth groove;

[0083] Figures 15A to 15D These are cross-sectional views along the AA', BB', CC', and DD' directions respectively, provided in some embodiments after the formation of the second hole and the fifth groove;

[0084] Figures 16A to 16F Cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the first and third holes are exposed, respectively, according to some embodiments.

[0085] Figures 17A to 17FCross-sectional views along the AA', BB', CC', DD', EE', and FF' directions respectively, provided in some embodiments after forming an annular structure surrounding the first sacrificial layer;

[0086] Figures 18A to 18E Cross-sectional views along the AA', BB', CC', DD', and FF' directions after the second hole and the fifth groove are exposed, respectively, according to some embodiments;

[0087] Figures 19A to 19D Cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the first connecting sublayer and bit line are provided in some embodiments;

[0088] Figures 20A to 20C Cross-sectional views along the AA', BB', and DD' directions after the fifth hole and the fourth groove are exposed, respectively, according to some embodiments;

[0089] Figures 21A to 21C Cross-sectional views along the AA', BB', and DD' directions respectively, provided in some embodiments after the formation of the sixteenth insulating layer, the second connecting layer, the first capacitor electrode, and the seventh dummy layer;

[0090] Figures 22A to 22C Cross-sectional views along the AA', BB', and DD' directions after the first capacitor electrode is exposed, respectively, provided in some embodiments;

[0091] Figures 23A to 23D Cross-sectional views along the AA', BB', DD', and FF' directions respectively, provided in some embodiments after the formation of the dielectric layer and the second capacitor electrode;

[0092] Figures 24A to 24D These are cross-sectional views along the AA', BB', CC', and FF' directions after thinning the bit line, provided in some embodiments.

[0093] Figures 25A to 25F Cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after the formation of the first channel are provided in some embodiments;

[0094] Figures 26A to 26D The following are cross-sectional views along the AA', DD', EE', and FF' directions after the formation of the semiconductor layer, gate insulating layer, and word line, respectively, according to some embodiments. Detailed Implementation

[0095] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0096] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0097] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0098] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0099] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0100] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0101] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0102] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0103] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0104] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0105] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with an interconnected relationship.

[0106] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0107] Figures 1A to 1F The following are schematic cross-sectional views of the semiconductor device provided in the embodiments of this disclosure along the AA' and BB' directions parallel to the substrate 1 and the CC', DD', EE', and FF' directions perpendicular to the substrate 1. Figures 12A to 12F Cross-sectional schematic diagrams of the semiconductor device provided for other embodiments along the AA', BB', CC', DD', EE', and FF' directions, respectively. Figures 1A to 1F , Figures 12A to 12F As shown, this disclosure provides a semiconductor device, including: a multilayer array of memory cells stacked along a direction perpendicular to a substrate 1, the array of memory cells including at least one column of a plurality of memory cells distributed along a second direction Y;

[0108] Multiple bit lines 30 extend through the memory cells in different layers along a direction perpendicular to the substrate 1; memory cells at the same position in different layers are connected to the same bit line 30.

[0109] Multiple word lines 40 are distributed in different layers. The word lines 40 and the bit lines 30 are distributed along a first direction X, and the word lines 40 extend along a second direction Y. The first direction X and the second direction Y are parallel to the substrate 1 and intersect. In some embodiments, the first direction X and the second direction Y are perpendicular.

[0110] The memory cell includes a transistor and a first capacitor electrode 41. The transistor includes a semiconductor layer 23 surrounding the word line 40. The first capacitor electrode 41 is disposed on the semiconductor layer 23 on the side away from the bit line 30. Multiple semiconductor layers 23 of multiple transistors in the same column surround the same word line 40, and the multiple semiconductor layers 23 of multiple transistors in the same column are spaced apart along a second direction Y. The semiconductor layer 23 is connected to the bit line 30 through a first connection layer 61 disposed between the semiconductor layer 23 and the bit line 30, and is connected to the first capacitor electrode 41 through a second connection layer 62 disposed between the semiconductor layer 23 and the first capacitor electrode 41.

[0111] The first connecting layer 61 and the second connecting layer 62 can reduce the contact resistance between the semiconductor layer 23 and the electrode.

[0112] The solution provided in this disclosure, by setting a first connection layer and a second connection layer, can reduce contact resistance and increase the on-state current of transistors in a three-dimensional memory architecture including a semiconductor layer surrounding horizontal word lines.

[0113] In some embodiments, the semiconductor device may include a plurality of memory cells arrayed along a first direction X and a second direction Y. Each layer may include a plurality of word lines 40.

[0114] In some embodiments, a bit line 30 may be connected to memory cells in two adjacent vertical columns along the first direction X. A vertical column of memory cells may include multiple memory cells at the same location in multiple layers. However, the embodiments of this disclosure are not limited thereto, and memory cells adjacent along the first direction X may be connected to different bit lines 30.

[0115] In some embodiments, a plurality of the first interconnect layers 61 distributed along a direction perpendicular to the substrate 1 can be connected to form an integral structure. The solution provided by the embodiments of this disclosure can form a plurality of first interconnect layers 61 of transistors at one time, simplifying the process.

[0116] In some embodiments, the first capacitor electrode 41 may form a cylindrical structure with its opening direction opposite to that of the semiconductor layer 23, and the second connecting layer 62 may cover the outer bottom wall of the first capacitor electrode 41 facing the semiconductor layer 23 and a portion of the outer side wall connected to the outer bottom wall.

[0117] In some embodiments, the semiconductor layer 23 is covered by the first interconnect layer 61 on the side facing the bit line 30.

[0118] In some embodiments, the semiconductor layer 23 has a protrusion facing the first capacitor electrode 41 on the side facing the first capacitor electrode 41, and the semiconductor layer 23 on the side facing the first capacitor electrode 41 is only partially covered by the second connection layer 62, and the area not covered by the second connection layer 62 is distributed on both sides of the area covered by the second connection layer 62, which are disposed opposite to each other along the second direction. Figure 1A As shown, only the middle region of the semiconductor layer 23 facing the first capacitor electrode 41 is covered by the first capacitor electrode 41, while there are regions at both ends that are not covered by the first capacitor electrode 41.

[0119] In some embodiments, the maximum dimension of the region of the word line 40 surrounded by the semiconductor layer 23 in the direction perpendicular to the substrate 1 is greater than the maximum dimension of the region not surrounded by the semiconductor layer 23 in the direction perpendicular to the substrate 1. For example... Figure 1E As shown, the word line 40 has an alternating thick and thin structure along the second direction Y, with the area surrounded by the semiconductor layer 23 being thicker and the area not surrounded by the semiconductor layer 23 being thinner. The area not surrounded by the semiconductor layer 23 can reserve space for the structure that encapsulates the semiconductor thin film, so as to cut the semiconductor layers of different transistors.

[0120] In some embodiments, the semiconductor layer 23 has a recess facing away from the first capacitor electrode 41 on the side facing the first capacitor electrode 41, and the semiconductor layer 23 on the side facing the first capacitor electrode 41 is covered by the second interconnect layer 62. For example... Figure 12A As shown. In this embodiment, the semiconductor layer 23 facing the first capacitor electrode 41 is completely covered by the second connection layer 62. In this embodiment, the size of the semiconductor layer 23 along the second direction Y can be reduced, so that the spacing between different semiconductor layers 23 is larger, ensuring that the semiconductor layers 23 of different transistors are cut off.

[0121] In some embodiments, the word lines 40 have a uniform dimension along the direction perpendicular to the substrate 1. In this embodiment, there is no need to reserve space for the structure encapsulating the semiconductor thin film, which is beneficial for controlling the device size.

[0122] In some embodiments, the bit lines 30 are distributed on a portion of the surface of the first connection layer 61 facing the bit lines 30. The solution provided by this disclosure allows the bit lines 30 to be distributed only on a portion of the surface of the first connection layer 61, thereby reducing the bit line size, increasing the distance between bit lines, and reducing the coupling capacitance between bit lines.

[0123] In some embodiments, the transistor further includes a gate insulating layer 24 disposed between the semiconductor layer 23 and the word line 40 and surrounding the word line 40. Multiple gate insulating layers 24 of multiple transistors distributed in the same column along the second direction Y in the same layer are connected to form an integral structure. The integral structure formed by multiple gate insulating layers 24 extends continuously on the side facing the substrate 1, the side away from the substrate 1, and the side away from the bit line 30, and is disconnected between adjacent semiconductor layers 23 along the second direction Y on the side facing the bit line 30.

[0124] In some embodiments, the memory cell may further include a capacitor, wherein the capacitor and the transistor of the same memory cell are distributed along the first direction X, the capacitor includes a dielectric layer 43 and a second capacitor electrode 42, the dielectric layer 43 is disposed between the first capacitor electrode 41 and the second capacitor electrode 42, the second capacitor electrode 42 fills the cylindrical structure formed by the first capacitor electrode 41 and is distributed on the side of the first capacitor electrode 41 away from the substrate 1, the side facing the substrate 1, and two outer sidewalls disposed opposite to each other along the second direction Y.

[0125] In some embodiments, multiple second capacitor electrodes 42 of multiple capacitors adjacent along the second direction Y are connected to form an integral structure;

[0126] A single integrated structure formed by connecting multiple second capacitor electrodes 42 fills the region between adjacent first capacitor electrodes 41 along the second direction Y. Alternatively, an isolation layer extending perpendicular to the substrate 1 exists between adjacent first capacitor electrodes 41 along the second direction Y, the isolation layer spacing adjacent second capacitor electrodes 42 along the second direction Y. The isolation layer includes a thirteenth insulating layer 53 and a seventeenth insulating layer 57.

[0127] In some embodiments, the semiconductor device further includes a tenth insulating layer 20, the tenth insulating layer 20 including a vertical portion disposed between adjacent bit lines 30 along the second direction Y and extending through multiple layers, and a plurality of surrounding portions extending from the vertical portion, respectively surrounding different layers of word lines 40 on a side away from the substrate 1, a side facing the substrate 1, and a side away from the bit lines 30, the surrounding portions being disposed between adjacent semiconductor layers 23 along the second direction Y. The vertical portion and the surrounding portions can be an integral structure.

[0128] In some embodiments, multiple surrounding portions of different layers of the same tenth insulating layer 20 are spaced apart along a direction perpendicular to the substrate 1, or multiple surrounding portions of the same tenth insulating layer 20 are connected to form an integral structure on the side of the word line 40 away from the bit line 30, and fill the area between adjacent word lines 40 along a direction perpendicular to the substrate 1.

[0129] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. In this embodiment, a film pattern is formed through a "patterning process" or a "photolithography process." The "patterning process" includes processes such as film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire manufacturing process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning or photolithography process contains at least one "pattern".

[0130] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0131] 101) Form the first hole K1 and the third hole K3;

[0132] A substrate 1 is provided, and a buffer layer thin film is grown on the substrate 1 to form a buffer layer 9; the buffer layer thin film may be silicon germanium (SiGe) or the like, which can protect the substrate 1. In some embodiments, the buffer layer 9 may not be provided.

[0133] A first insulating film and a first sacrificial layer film are alternately deposited on the buffer layer 9 to form a stacked structure comprising a plurality of alternately arranged first insulating layers 11 and first sacrificial layers 10;

[0134] The stacked structure is etched along a direction perpendicular to substrate 1 to form a plurality of first holes K1 penetrating the stacked structure along a direction perpendicular to substrate 1; and a plurality of third holes K3 penetrating the stacked structure along a direction perpendicular to substrate 1 are formed; wherein the plurality of first holes K1 are spaced apart along a second direction Y; the plurality of third holes K3 are spaced apart along the second direction Y, the first holes K1 and the third holes K3 correspond to each other, and the first holes K1 and the corresponding third holes K3 are distributed along a first direction X;

[0135] A second insulating film is deposited to form a second insulating layer 12 covering the bottom and sidewalls of the first hole K1 and the third hole K3;

[0136] The second insulating layer 12 is etched away from the bottom wall of the first hole K1 and the bottom wall of the third hole K3, exposing the buffer layer 9.

[0137] A first dummy layer film is deposited and smoothed to form a first dummy layer 71 filling the first hole K1 and the third hole K3; the side of the first dummy layer 71 facing away from the substrate 1 is flush with the topmost first insulating layer 11; as shown Figure 2A , Figure 2B and Figure 2C As shown, where, Figure 2A , Figure 2B and Figure 2C These are cross-sectional views along the AA', BB', and DD' directions after the formation of the first hole K1 and the third hole K3, respectively, provided in some embodiments.

[0138] In some embodiments, the dimension of the third hole K3 along the first direction X can be greater than the dimension along the second direction Y. The dimension of the third hole K3 along the first direction X can be greater than the dimension of the first hole K1 along the first direction X.

[0139] In some embodiments, the orthographic projection of the first hole K1 onto the substrate 1 can be square, circular, or the like.

[0140] In some embodiments, substrate 1 may be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0141] In some embodiments, the first insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The materials of the subsequent second to nineteenth insulating films are similar to those of the first insulating film, and will not be described again.

[0142] In some embodiments, the first sacrificial layer film may be a film layer with an etching selectivity ratio to the first insulating film, such as silicon nitride (SiN). The materials of the subsequent second to fourth sacrificial layer films are similar to those of the first sacrificial layer film and will not be described further.

[0143] In some embodiments, the first dummy layer film may be a material that has an etching selectivity ratio with the buffer layer film, the first insulating film, and the first sacrificial layer film, such as polysilicon. The materials of the subsequent second to seventh dummy layer films are similar to those of the first dummy layer film, and will not be described again.

[0144] 102) Form the second hole K2 and the first channel B1;

[0145] A third insulating film is deposited to form a third insulating layer 13 covering the aforementioned structure; the third insulating layer 13 covers the first dummy layer 71 and can protect the first dummy layer 71 in subsequent operations;

[0146] The third insulating layer 13 and the stacked structure are etched along a direction perpendicular to the substrate 1 to form a plurality of second holes K2 penetrating the third insulating layer 13 and the stacked structure along a direction perpendicular to the substrate 1; the second holes K2 are located between adjacent first holes K1 along the second direction Y, and the second holes K2 are spaced apart along the second direction Y; the sidewalls of the second holes K2 expose the second insulating layer 12;

[0147] Based on the second hole K2, the first sacrificial layer 10 is etched along a direction parallel to the substrate 1 to form a first channel B1 extending along the second direction Y. The first sacrificial layer 10 can be etched until the second insulating layer 12 in the third hole K3 is exposed on the side facing the first hole K1. The first channel B1 exposes the second insulating layer 12 in a row of second holes K2 distributed along the second direction Y, facing the first hole K1. Figures 3A to 3F As shown, where, Figures 3A to 3F The following are cross-sectional views along the directions AA', BB', CC', DD', EE', and FF' after the formation of the second hole K2 and the first channel B1, as provided in some embodiments.

[0148] 103) Forming the fourth insulating layer 14, the second dummy layer 72, the fifth insulating layer 15, and the second sacrificial layer 8;

[0149] A fourth insulating film, a second dummy layer film, a fifth insulating film, and a second sacrificial layer film are deposited sequentially. The fourth insulating film, the second dummy layer film, the fifth insulating film, and the second sacrificial layer film sequentially cover the inner wall of the first channel B1, the bottom wall and the side wall of the second hole K2, and the second sacrificial layer film fills the first channel B1.

[0150] The second sacrificial layer film, the fifth insulating film, and the second dummy layer film are etched away from the bottom and sidewalls of the second hole K2. The second dummy layer film in the first channel B1 is also etched, such that the second dummy layer films distributed in the channel B1 on the side of the second sacrificial layer film facing the substrate 1 and the side facing away from the substrate 1 are partially removed, and the second dummy layer films located between adjacent first insulating layers 11 and surrounding the first hole K1 are substantially removed (see reference). Figure 4A This forms a fourth insulating layer 14, a second dummy layer 72, a fifth insulating layer 15, and a second sacrificial layer 8, as follows: Figures 4A to 4F As shown, where, Figures 4A to 4FCross-sectional views along the AA', B1B1', CC', DD', EE', and FF' directions after the formation of the fourth insulating layer 14, the second dummy layer 72, the fifth insulating layer 15, and the second sacrificial layer 8, respectively, are provided in some embodiments. The B1B1' direction is parallel to the substrate 1 and passes through the film layer of the second dummy layer 72 facing the substrate 1. At this time, multiple first grooves A1 are formed on both the side of the second sacrificial layer 8 facing the substrate 1 and the side facing away from the substrate 1, and the multiple first grooves A1 are spaced apart by the second dummy layer 72.

[0151] In some embodiments, the second sacrificial layer film, the fifth insulating film, and the second dummy layer film can be etched by wet etching.

[0152] in, Figure 4B In the middle, a fourth insulating layer 14 is provided between the second dummy layer 72 and the second insulating layer 12 in the first hole K1; Figure 4C In the middle, the surface of the second insulating layer 12 facing the second hole K2 is covered with a fourth insulating layer 14; Figure 4D In the middle, the surface of the second dummy layer 72 opposite to the fifth insulating layer 15 has a fourth insulating layer 14 distributed thereon; Figure 4E In the middle, the first insulating layer 11 is covered by the fourth insulating layer 14 on the side facing the second dummy layer 72. Figure 4E and Figure 4F In the middle, the first insulating layer 11 is covered by the fourth insulating layer 14 on the side facing the second dummy layer 72.

[0153] 104) Form the sixth insulating layer 16, the first connecting sublayer 61, and the bit line 30;

[0154] After sequentially depositing a sixth insulating film, a first connecting layer film, and a first conductive film, the layers are smoothed to form a sixth insulating layer 16, a first connecting sublayer 61, and a bit line 30. The sixth insulating layer 16 fills the first groove A1 and covers the bottom and sidewalls of the second hole K2. The first connecting layer film covers the bottom and sidewalls of the second hole K2 on which the sixth insulating layer 16 is formed. The bit line 30 fills the second hole K2. Figures 5A to 5E As shown, where, Figures 5A to 5E The images show cross-sectional views along the AA', B1B1', CC', EE', and FF' directions after the formation of the sixth insulating layer 16, the first connecting sublayer 61, and the bit line 30, as provided in some embodiments. The third insulating layer 13 was removed during grinding; the bit line 30 can be flush with the topmost first insulating layer 11 on the side facing away from the substrate 1.

[0155] In some embodiments, the first interconnect layer film is a conductive film layer that can reduce the contact resistance between the bit line 30 and the subsequently formed semiconductor layer 23, including but not limited to indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0156] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0157] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0158] Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0159] Alternatively, it could be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping.

[0160] The materials for the second to fourth conductive films are similar to those for the first conductive film, and will not be described in detail here.

[0161] 105) A virtual sublayer 72' is formed;

[0162] A first hard mask thin film is deposited to form a first hard mask layer 81 covering the aforementioned structure; the first hard mask thin film may be, for example, doped polysilicon.

[0163] The first hard mask layer 81 and the stacked structure are etched along a direction perpendicular to the substrate 1 to form a first trench T1 that penetrates the first hard mask layer 81 and the stacked structure (the etching can stop on the buffer layer 9). The first trench T1 extends along the second direction Y. The first trench T1 is disposed on the side of the third hole K3 opposite to the first hole K1. The first trench T1 exposes the second insulating layer 12 in a plurality of third holes K3 distributed along the second direction Y.

[0164] Based on the first trench T1, the first sacrificial layer 10, the fourth insulating layer 14, and the second dummy layer 72 are sequentially etched along a direction parallel to the substrate 1 to form the second trench A2 and the third trench A3, such that the second dummy layer 72 forms multiple dummy sublayers 72' spaced apart along the second direction Y, as shown below. Figures 6A to 6D As shown, where, Figures 6A to 6DCross-sectional views along the AA', B1B1', DD', and FF' directions are provided in some embodiments after the formation of the dummy sublayer 72'. The dummy sublayer 72' is a ring structure surrounding the second sacrificial layer 8. Subsequently, the semiconductor thin film can be exposed by etching the dummy sublayer 72', and the semiconductor layer 23 of the multiple transistors distributed along the second direction Y can be disconnected by etching the exposed semiconductor thin film. At this time, in the first channel B1, multiple third grooves A3 are formed on both the side of the second sacrificial layer 8 facing the substrate 1 and the side facing away from the substrate 1, spaced apart along the second direction Y. Adjacent third grooves A3 along the second direction Y are spaced apart by the dummy sublayer 72'. Adjacent second grooves A2 and third grooves A3 along the first direction X are connected.

[0165] 106) Form a seventh insulating layer 17, a second connecting layer 62, a first capacitor electrode 41 and a third dummy layer 73;

[0166] A seventh insulating film, a second connecting layer film, a second conductive film, and a third dummy layer film are deposited sequentially. The seventh insulating film fills the third groove A3 and covers the inner walls of the second groove A2 and the first trench T1. The second connecting layer film and the second conductive film sequentially cover the inner walls of the second groove A2 and the first trench T1. The third dummy layer film, the second conductive film, and the second connecting layer film in the first trench T1 are etched away, while the third dummy layer film, the second conductive film, and the second connecting layer film in the second groove A2 are retained, forming a seventh insulating layer 17, a second connecting layer 62, a first capacitor electrode 41, and a third dummy layer 73. Figures 7A to 7C As shown, where, Figures 7A to 7C These are cross-sectional views along the AA', BB', and FF' directions after the formation of the seventh insulating layer 17, the second connecting layer 62, the first capacitor electrode 41, and the third dummy layer 73, respectively, according to some embodiments. The third dummy layer 73 fills the second groove A2.

[0167] 107) Forming a dielectric layer 43 and a second capacitor electrode 42;

[0168] Based on the first trench T1, the third dummy layer 73 is etched away to expose the inner wall of the first capacitor electrode 41.

[0169] Based on the first trench T1, the seventh insulating layer 17 and the second insulating layer 12 are etched to expose the first dummy layer 71 in the third hole K3. The first dummy layer 71 in the third hole K3 is etched away to expose the two outer sidewalls of the second connection layer 62 that are arranged opposite each other along the second direction Y, and the two outer sidewalls that are arranged opposite each other along the direction perpendicular to the substrate 1. The exposed second connection layer 62 is etched away, and the second connection layer 62 covering the side of the first capacitor electrode 41 facing the first hole K1 is retained. The two outer sidewalls of the first capacitor electrode 41 that are arranged opposite each other along the second direction Y, and the two outer sidewalls that are arranged opposite each other along the direction perpendicular to the substrate 1 are exposed. When etching the seventh insulating layer 17 and the second insulating layer 12, the seventh insulating layer 17 and the second insulating layer 12 facing the side of the first hole K1 are retained, and the second dummy layer 72 (dummy sublayer 72') is not exposed.

[0170] After sequentially depositing a dielectric layer thin film and a third conductive thin film, the layers are smoothed to form a dielectric layer 43 and a second capacitor electrode 42. The dielectric layer 43 covers the inner wall of the first capacitor electrode 41, the two outer walls of the first capacitor electrode 41 arranged opposite each other along the direction perpendicular to the substrate 1 (the outer wall facing the substrate 1 and the outer wall facing away from the substrate 1), and the two outer walls of the first capacitor electrode 41 arranged opposite each other along the second direction Y. The second capacitor electrode 42 fills the second groove A2 where the first capacitor electrode 41 is located. Multiple second capacitor electrodes 42 in different layers and in the same column are connected to form an integral structure. This integral structure fills the area between adjacent first capacitor electrodes 41 along the direction perpendicular to the substrate 1, and the area between adjacent first capacitor electrodes 41 along the second direction Y, such as... Figures 8A to 8D As shown, Figures 8A to 8D The images shown are cross-sectional views along the AA', BB', DD', and FF' directions, respectively, after the formation of the dielectric layer 43 and the second capacitor electrode 42, as provided in some embodiments. The first hard mask layer 81 was removed during grinding.

[0171] In some embodiments, the second capacitor electrode 42 may include a first sublayer 421 and a second sublayer 422. The first sublayer 421 may be a conductive material with good adhesion, such as TiN, and the second sublayer 422 may be a conductive material with low resistivity, such as tungsten. The first sublayer 421 is distributed on the inner bottom wall and inner sidewall of the first capacitor electrode 41, as well as on the outer sidewall facing the substrate 1 and the outer sidewall facing away from the substrate 1, and on two outer sidewalls disposed opposite each other along the second direction Y. The second sublayer 422 fills the region between adjacent first capacitor electrodes 41 along the direction perpendicular to the substrate 1, and the region between adjacent first capacitor electrodes 41 along the second direction Y. In this embodiment, the first sublayer 421 fills the second groove A2, but it is not limited to this. When the size of the second groove A2 is large, the second sublayer 422 may fill the second groove A2.

[0172] In some embodiments, the dielectric film may be a Low-K material, such as silicon oxide. Alternatively, it may be a High-K material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0173] 108) Thinning line 30;

[0174] Deposit an eighth insulating film to form an eighth insulating layer 18 covering the structure formed above;

[0175] The eighth insulating layer 18 is etched to expose the first dummy layer 71 in the first hole K1 on the side away from the substrate 1, and the first dummy layer 71 in the first hole K1 is removed by etching.

[0176] The second insulating layer 12 in the first hole K1 is etched, and the fourth insulating layer 14 covering the outside of the second insulating layer 12 is etched, exposing the first connecting layer 61 in the second hole K2, and exposing the dummy sublayer 72' facing the first hole K1. The dummy sublayer 72' facing the first hole K1 is etched. At this time, the second sacrificial layer 8 is covered by the fifth insulating layer 15, and the second sacrificial layer 8 is not exposed in the first hole K1. The dummy sublayer 72' surrounds the second sacrificial layer 8 on three sides.

[0177] The first interconnect layer 61 is etched to expose the bit line 30. At this time, the cross-section of the first interconnect layer 61 parallel to the substrate 1 forms two independent segments distributed along the first direction X. Etching the bit line 30 reduces its size along the second direction Y, thereby increasing the distance between adjacent bit lines 30 along the second direction Y, thus reducing the coupling capacitance between adjacent bit lines 30 along the second direction Y. Figures 9A to 9D As shown, Figures 9A to 9D The images shown are cross-sectional views along the AA', BB', CC', and DD' directions after thinning the bit line 30, as provided in some embodiments. However, the embodiments disclosed herein are not limited to these, and the bit line 30 may not be thinned.

[0178] 109) First channel B1 is exposed;

[0179] A ninth insulating film is deposited, which covers the first connecting layer 61 on the side facing the bit line 30. The ninth insulating film and the fifth insulating layer 15 are etched to expose the second sacrificial layer 8, forming a ninth insulating layer 19 and a fourth hole K4. The ninth insulating layer 19 covers the first connecting layer 61 on the side facing the bit line 30, and also covers a portion of the surface of the two sides of the bit line 30 that are opposite each other along the second direction Y. The fourth hole K4 is the first hole K1 with an enlarged aperture.

[0180] The second sacrificial layer 8 is etched away to expose the fifth insulating layer 15 located on the side of the second sacrificial layer 8 opposite to the bit line 30;

[0181] Etch the fifth insulating layer 15 and the seventh insulating layer 17 to expose the second interconnect layer 62 facing the bit line 30, and expose the first interconnect layer 61 located in the first channel B1 away from the bit line 30; and expose the surface of the dummy sublayer 72' facing the second sacrificial layer 8, i.e., the inner surface of the dummy sublayer 72'; as Figures 10A to 10E As shown, Figures 10A to 10E The images show cross-sectional views along the directions AA', BB', DD', EE', and FF' after the first channel B1 is exposed, as provided in some embodiments. At this point, the first channel B1 is exposed.

[0182] 110) Forming a semiconductor layer 23, a gate insulating layer 24, and a word line 40;

[0183] A semiconductor thin film, a gate insulating film, and a fourth conductive film are sequentially deposited on a substrate 1 forming the aforementioned structure. The semiconductor thin film and the gate insulating film sequentially cover the inner walls of the first channel B1 and the fourth hole K4. The fourth conductive film fills the first channel B1 and covers the inner walls of the fourth hole K4. The semiconductor thin film, the gate insulating film, and the fourth conductive film in the fourth hole K4 are etched away, while the semiconductor thin film, the gate insulating film, and the fourth conductive film in the first channel B1 are retained, forming multiple semiconductor layers 23 (referred to as semiconductor structure layers) of multiple transistors, multiple gate insulating layers 24 (referred to as gate insulating structure layers) of multiple transistors, and word lines 40; as Figures 11A to 11E As shown, Figures 11A to 11E The figures show cross-sectional views along the AA', BB', DD', EE', and FF' directions after the formation of the semiconductor layer 23, gate insulating layer 24, and word line 40, respectively, according to some embodiments. At this time, the semiconductor layer 23 of the multiple transistors is connected on the side away from the substrate 1, the side facing the substrate 1, and the side away from the bit line 30, and is disconnected on the side facing the bit line 30 (disconnected at the location of the fourth hole K4).

[0184] In exemplary embodiments of this disclosure, the material of the semiconductor layer 23 may be silicon or polycrystalline silicon, which have a band gap of less than 1.65 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV. Alternatively, it may be a transition metal dichalcogenide or bipolar semiconductor material that uses both electrons and holes as driving charges, such as molybdenum disulfide (MoS2), tungsten disulfide (WS2), molybdenum diselenide (MoSe2), etc.

[0185] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0186] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0187] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0188] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0189] In exemplary embodiments of this disclosure, the material of the gate insulating layer 24 may comprise one or more high-K dielectric materials, such as dielectric materials with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0190] 111) Disconnect multiple semiconductor layers 23 of multiple transistors;

[0191] The dummy sublayer 72' is etched away to expose the semiconductor structure layer on the side away from the substrate 1, the side facing the substrate 1, and the side away from the bit line 30.

[0192] The semiconductor structure layer exposed by etching is disconnected between the multiple semiconductor layers 23 of the multiple transistors. At this time, the multiple semiconductor layers 23 of the multiple transistors are disconnected on the side away from the substrate 1, the side facing the substrate 1, and the side away from the bit line 30.

[0193] A tenth insulating film is deposited to form a tenth insulating layer 20. This tenth insulating layer 20 fills the cavities formed after the dummy sublayer 72' and the semiconductor structure layer are etched, and also fills the fourth hole K4, as shown below. Figures 1A to 1F As shown. Specifically, the tenth insulating layer 20 includes a vertical portion disposed in the fourth hole K4 and a surrounding portion encircling the word line 40. The tenth insulating layer 20 includes a vertical portion extending through multiple layers between adjacent bit lines 30 along the second direction Y, and a plurality of surrounding portions extending from the vertical portion, each encircling a different layer of the word line 40. The surrounding portions are disposed between adjacent semiconductor layers 23 along the second direction Y, and the plurality of surrounding portions in different layers are spaced apart along a direction perpendicular to the substrate 1. The location of the surrounding portions can be referenced to the location of the dummy sublayer 72'.

[0194] The semiconductor device manufacturing method provided in this disclosure avoids the semiconductor layer of the transistor being affected by high temperatures by manufacturing the capacitor first and then the transistor. Furthermore, by forming a ring structure, the difficulty of disconnecting the semiconductor layers of different transistors is reduced. Additionally, the solution provided in this disclosure reduces contact resistance and increases on-state current by providing a first connection layer and a second connection layer.

[0195] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0196] 201) Form the first hole K1 and the third hole K3;

[0197] A substrate 1 is provided, and a buffer layer thin film is grown on the substrate 1 to form a buffer layer 9; the buffer layer thin film may be silicon germanium (SiGe) or the like, which can protect the substrate 1. In some embodiments, the buffer layer 9 may not be provided.

[0198] A first insulating film and a first sacrificial layer film are alternately deposited on the buffer layer 9 to form a stacked structure comprising a plurality of alternately arranged first insulating layers 11 and first sacrificial layers 10;

[0199] The stacked structure is etched along a direction perpendicular to substrate 1 to form a plurality of first holes K1 penetrating the stacked structure along a direction perpendicular to substrate 1; and a plurality of third holes K3 penetrating the stacked structure along a direction perpendicular to substrate 1 are formed; wherein the plurality of first holes K1 are spaced apart along a second direction Y; the plurality of third holes K3 are spaced apart along the second direction Y, the first holes K1 and the third holes K3 correspond to each other, and the first holes K1 and the corresponding third holes K3 are distributed along a first direction X;

[0200] A first dummy layer film is deposited and smoothed to form a first dummy layer 71 filling the first hole K1 and the third hole K3; the side of the first dummy layer 71 facing away from the substrate 1 is flush with the topmost first sacrificial layer 10; as shown Figure 13A , Figure 13B and Figure 13C As shown, where, Figure 13A , Figure 13B and Figure 13C These are cross-sectional views along the AA', BB', and FF' directions respectively, provided in some embodiments after the formation of the first hole K1 and the third hole K3.

[0201] 202) Form the fifth hole K5 and the fourth groove A4;

[0202] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a plurality of fifth holes K5. The fifth holes K5 are located between adjacent third holes K3 along the second direction Y, and expose a portion of the sidewall of the first dummy layer 71 in the two adjacent third holes K3 facing the third hole K3. The size of the fifth hole K5 along the first direction X is smaller than the size of the third hole K3 along the first direction X. The fifth hole K5 and the first hole K1 are at a preset distance along the first direction X (the preset distance can be determined according to the size of the capacitor of the memory cell), and are close to the middle of the third hole K3.

[0203] Based on the fifth hole K5, the first insulating layer 11 is etched laterally (along the direction parallel to the substrate 1) to the end of the third hole K3 near the first hole K1, which can slightly exceed the end of the third hole K3 near the first hole K1, that is, etched to the area between the third hole K3 and the first hole K1 to form the fourth groove A4.

[0204] After sequentially depositing the third sacrificial layer film and the fourth dummy layer film, the layers are smoothed to form the third sacrificial layer 7 and the fourth dummy layer 74. The third sacrificial layer 7 covers the inner wall of the fifth hole K5 and the inner wall of the fourth groove A4. The fourth dummy layer 74 fills the fifth hole K4 and the fourth groove A4. The side of the fourth dummy layer 74 facing away from the substrate 1 is flush with the topmost first sacrificial layer 10. Figures 14A to 14C As shown, where, Figures 14A to 14C These are cross-sectional views along the AA', BB', and DD' directions respectively, provided in some embodiments after the formation of the fifth hole K5 and the fourth groove A4.

[0205] 203) Form the second hole K2 and the fifth groove A5;

[0206] The stacked structure is etched along a direction perpendicular to the substrate 1 to form a plurality of second holes K2 penetrating the stacked structure along a direction perpendicular to the substrate 1; the second holes K2 are located between adjacent first holes K1 along the second direction Y, and the plurality of second holes K2 are spaced apart along the second direction Y; the sidewalls of the second holes K2 expose the first dummy layer 71 in the first holes K1;

[0207] Based on the second hole K2, the first insulating layer 11 is etched along the direction parallel to the substrate 1 to form the fifth groove A5. When etching the first insulating layer 11, the third sacrificial layer 7 in the fourth groove A4 is not exposed.

[0208] After sequentially depositing the fourth sacrificial layer film and the fifth dummy layer film, the layers are smoothed to form the fourth sacrificial layer 6 and the fifth dummy layer 75. The fourth sacrificial layer 6 covers the inner wall of the second hole K2 and the inner wall of the fifth groove A5, and the fifth dummy layer 75 fills the second hole K2 and the fifth groove A5. Figures 15A to 15D As shown, where, Figures 15A to 15D These are cross-sectional views along the AA', BB', CC', and DD' directions respectively, provided in some embodiments after the formation of the second hole K2 and the fifth groove A5.

[0209] 204) Exposing the first hole K1 and the third hole K3;

[0210] A second hard mask film is deposited to form a second hard mask layer 82 covering the structure formed above; the second hard mask film may be, for example, SiN.

[0211] The second hard mask layer 82 is etched to expose the side of the first dummy layer 71 in the first hole K1 and the second hole K3 that is away from the substrate 1.

[0212] The first dummy layer 71 is etched away to expose the first hole K1 and the third hole K3, as well as the third sacrificial layer 7 connected to the first dummy layer 71.

[0213] The first insulating layer 11 is etched away to expose the third sacrificial layer 7 and the fourth sacrificial layer 6.

[0214] The etching exposes the third sacrificial layer 7 and the fourth sacrificial layer 6, exposes the two sides of the fourth dummy layer 74 that are disposed opposite each other along the second direction Y, and exposes the side of the fourth dummy layer 74 disposed in the fourth groove A4 facing the second hole K2, and exposes the side of the fifth dummy layer 75 disposed in the fifth groove A5 that faces the fifth hole K5, and exposes the two sides of the fifth dummy layer 75 that are disposed opposite each other along the second direction Y, forming the second channel B2, as shown. Figures 16A to 16F As shown, where, Figures 16A to 16F The following are cross-sectional views along the directions AA', BB', CC', DD', EE', and FF' after exposing the first hole K1 and the third hole K3, respectively, according to some embodiments. Figure 16A and Figure 16F The first hole K1 and the third hole K3 are enlarged versions of the original first hole K1 and third hole K3, including not only the regions of the original first hole K1 and third hole K3, but also the cavities formed after the removal of the third sacrificial layer 7 and the fourth sacrificial layer 6 distributed around the first dummy layer 71. The second channel B2 is located between the first hole K1 and the third hole K3, extending along the second direction Y, and is located between adjacent first sacrificial layers 10 along the direction perpendicular to the substrate 1, or between the first sacrificial layer 10 and the second hard mask layer 82. At this time, the first hole K1 and the third hole K3 are connected through the second channel B2. The second channel B2 may include a connecting region B21 connecting the first hole K1 and the third hole K3 and an intermediate region B22 connecting adjacent connecting regions B21. The intermediate region B22 is located between the fourth dummy layer 74 and the fifth dummy layer 75.

[0215] 205) Forming a ring structure surrounding the first sacrificial layer 10;

[0216] An eleventh insulating film is deposited, which covers the inner walls of the first hole K1 and the third hole K3 and fills the second channel B2. The eleventh insulating film of the first hole K1 and the third hole K3 is etched away, and the eleventh insulating film in the region (i.e., the connecting region B21) of the second channel B2 that connects the first hole K1 and the third hole K3 is also etched away, while the eleventh insulating film of the intermediate region B22 is retained. Multiple isolation sub-layers 21 are formed in the second channel B2 at intervals along the second direction Y. The isolation sub-layers 21 are distributed in the intermediate region B22 and connect the adjacent fourth dummy layer 74 and fifth dummy layer 75.

[0217] A twelfth insulating film is deposited to form a twelfth insulating layer 22 covering the inner walls of the first hole K1 and the third hole K3, as well as the inner wall of the connecting region B21; the twelfth insulating layer 22 on the bottom walls of the first hole K1 and the third hole K3 is etched away, while the twelfth insulating layer 22 on the side walls of the first hole K1, the side walls of the third hole K3, and the inner wall of the connecting region B21 is retained.

[0218] A sixth dummy layer film is deposited, covering the sidewalls of the first hole K1 and the third hole K3, and filling the connected region B21. The sixth dummy layer film on the bottom walls of the first hole K1 and the third hole K3 is etched away to form a sixth dummy layer 76. The sixth dummy layer 76 covers the sidewalls of the first hole K1 and the third hole K3, and fills the connected region B21. At this time, a ring structure surrounding the first sacrificial layer 10 is formed, as shown below. Figures 17A to 17F As shown, where, Figures 17A to 17F The figures shown are cross-sectional views along the AA', BB', CC', DD', EE', and FF' directions after forming the annular structure surrounding the first sacrificial layer 10 according to some embodiments. Compared to the previous embodiment, the annular structure provided in this disclosure occupies the space of the first insulating layer 11 in the vertical direction. Therefore, the thickness of the annular structure is increased, the morphology affected by deep hole etching is reduced, which can lower the requirements for the deep hole etching process and the etching selectivity requirement. Furthermore, the thicker annular structure is easier to remove than the thinner one. In addition, there is no need to increase the device size to meet the thickness requirements of the annular structure, which is beneficial for controlling the device size.

[0219] 206) Expose the second hole K2 and the fifth groove A5;

[0220] Remove the second hard mask layer 82;

[0221] After depositing the thirteenth insulating film, it is ground smooth to form the thirteenth insulating layer 53 that fills the first hole K1 and the third hole K3;

[0222] The thirteenth insulating layer 53 is etched to expose the fifth dummy layer 75 in the second hole K2 on the side away from the substrate 1; the fifth dummy layer 75 in the second hole K2 and the fifth groove A5 is removed by etching to expose the second hole K2 and the fifth groove A5.

[0223] Based on the second hole K2 and the fifth groove A5, the fourth sacrificial layer 6 in the fifth groove A5 is etched (possibly partially etching the first sacrificial layer 10), so that the surface of the isolation sublayer 21 facing the second hole K2 is exposed, such as... Figures 18A to 18E As shown, where, Figures 18A to 18EThe images are cross-sectional views along the directions AA', BB', CC', DD', and FF' after the second hole K2 and the fifth groove A5 are exposed, as provided in some embodiments.

[0224] 207) Form the first connecting sublayer 61 and bit line 30;

[0225] A fourteenth insulating film is deposited to form a fourteenth insulating layer 54 that fills the fifth groove A5 and covers the bottom and sidewalls of the second hole K2;

[0226] The fourteenth insulating layer 54 in the second hole K2 is etched to reduce the thickness of the fourteenth insulating layer 54 in the second hole K2 (i.e., the dimension of the fourteenth insulating layer 54 in the direction perpendicular to the sidewall of the second hole K2).

[0227] After sequentially depositing a first interconnecting layer film and a first conductive film, the surface is smoothed to form a first interconnecting sublayer 61 and a bit line 30. The first interconnecting layer film covers the bottom and sidewalls of the second hole K2, and the bit line 30 fills the second hole K2. Figures 19A to 19D As shown, where, Figures 19A to 19D These are cross-sectional views along the AA', BB', CC', and DD' directions after the formation of the first connecting sublayer 61 and bit line 30, as provided in some embodiments. After grinding, the topmost sixth dummy layer 76 is exposed on the side facing away from the substrate 1; the side of bit line 30 facing away from the substrate 1 can be flush with the topmost sixth dummy layer 76 facing away from the substrate 1.

[0228] In some embodiments, the fourth insulating layer 54 may not completely fill the fifth groove A5, and there may be a depression. The bit line 30 may extend into the fifth groove A5, that is, the bit line 30 may have a protrusion extending into the fifth groove A5.

[0229] 208) Exposing the fifth hole K5 and the fourth groove A4;

[0230] Deposit a third hard mask film to form a third hard mask layer 83 covering the structure formed above;

[0231] The third hard mask layer 83 is etched to expose the fourth dummy layer 74 in the fifth hole K5 on the side opposite to the substrate 1.

[0232] The fourth dummy layer 74 in the fifth hole K5 and the fourth groove A4 is removed by etching, exposing the fifth hole K5 and the fourth groove A4;

[0233] Based on the fifth hole K5 and the fourth groove A4, the third sacrificial layer 7 in the fourth groove A4 is etched (part of the first sacrificial layer 10 may be etched away), so that the surface of the isolation sublayer 21 facing the fifth hole K5 is exposed, such as... Figures 20A to 20CAs shown, where, Figures 20A to 20C These are cross-sectional views along the AA', BB', and DD' directions after the fifth hole K5 and the fourth groove A4 are exposed, as provided in some embodiments.

[0234] 209) Form the sixteenth insulating layer 56, the second connecting layer 62, the first capacitor electrode 41 and the seventh dummy layer 77;

[0235] A fifteenth insulating film is deposited, which covers the inner wall of the fifth hole K5 and fills the fourth groove A4 to form a fifteenth insulating layer 55;

[0236] The fifteenth insulating layer 55 of the fifth hole K5 is removed by etching, while the fifteenth insulating layer 55 in the fourth groove A4 is retained, exposing the first sacrificial layer 10;

[0237] The first sacrificial layer 10 is etched to the side of the third hole K3 facing the first hole K1 (it can be flush with the side of the third hole K3 facing the first hole K1 along the second direction Y, or it can extend beyond the side of the third hole K3 facing the first hole K1, or it can not extend beyond the side of the third hole K3 facing the first hole K1), forming the sixth groove A6;

[0238] The fifteenth insulating layer 55 is etched based on the sixth groove A6 to reduce the size of the fifteenth insulating layer 55 in the direction perpendicular to the substrate 1, thereby increasing the size of the sixth groove A6 in the direction perpendicular to the substrate 1 to increase the capacitance space; however, the embodiments of this disclosure are not limited to this, and in some embodiments, the size of the fifteenth insulating layer 55 in the direction perpendicular to the substrate 1 may not be reduced.

[0239] A sixteenth insulating film, a second connecting layer film, a second conductive film, and a seventh dummy layer film are sequentially deposited. The sixteenth insulating film, the second connecting layer film, and the second conductive film sequentially cover the inner walls of the fifth hole K5 and the sixth groove A6. The seventh dummy layer film fills the sixth groove A6. The seventh dummy layer film in the fifth hole K5 is etched away, while the seventh dummy layer film, the second conductive film, and the second connecting layer film in the sixth groove A6 are retained, forming a sixteenth insulating layer 56, a second connecting layer 62, a first capacitor electrode 41, and a seventh dummy layer 77. Figures 21A to 21C As shown, where, Figures 21A to 21C The images are cross-sectional views along the AA', BB', and DD' directions after the formation of the sixteenth insulating layer 56, the second connecting layer 62, the first capacitor electrode 41, and the seventh dummy layer 77, respectively, according to some embodiments.

[0240] 210) Exposing the first capacitor electrode 41;

[0241] The first capacitor electrode 41 in the fifth hole K5 is removed by etching, while the first capacitor electrode 41 in the sixth groove A6 is retained.

[0242] Based on the etching of the fifth hole K5, the seventh dummy layer 77 is removed, exposing the inner wall of the first capacitor electrode 41. Also, the sixth dummy layer 76 in the third hole K3 is etched, retaining the sixth dummy layer 76 disposed on the side facing the first hole K1 (the sixth dummy layers 76 disposed on both sides opposite to each other along the second direction Y are etched away), exposing the twelfth insulating layer 22.

[0243] Etching the twelfth insulating layer 22, the sixteenth insulating layer 56, and the fifteenth insulating layer 55 exposes two outer sidewalls of the second connecting layer 62 that are opposite each other along the second direction Y, and two outer sidewalls that are opposite each other along the direction perpendicular to the substrate 1; the etched exposed second connecting layer 62 retains the second connecting layer 62 covering the side of the first capacitor electrode 41 facing the first hole K1, exposing the two outer sidewalls of the first capacitor electrode 41 that are opposite each other along the second direction Y, and two outer sidewalls that are opposite each other along the direction perpendicular to the substrate 1; the area of ​​the area of ​​the twelfth insulating layer 22 can be larger than the area of ​​the area of ​​the sixth dummy layer 76, that is, the area of ​​the retained twelfth insulating layer 22 facing the sixth dummy layer 76 partially covers the sixth dummy layer 76, and partially exposes it; Figures 22A to 22C As shown, where, Figures 22A to 22C The images are cross-sectional views along the AA', BB', and DD' directions after the first capacitor electrode 41 is exposed, as provided in some embodiments.

[0244] 211) Forming a dielectric layer 43 and a second capacitor electrode 42;

[0245] A seventeenth insulating film is deposited on the aforementioned structure, the seventeenth insulating film is etched, and the seventeenth insulating film covering the surface of the sixth dummy layer 76 is retained to form a seventeenth insulating layer 57.

[0246] After sequentially depositing a dielectric layer thin film and a third conductive thin film, the surface is smoothed to form a dielectric layer 43 and a second capacitor electrode 42. The dielectric layer 43 covers the inner wall of the first capacitor electrode 41, the two outer walls of the first capacitor electrode 41 arranged opposite each other along the direction perpendicular to the substrate 1 (the outer wall facing the substrate 1 and the outer wall facing away from the substrate 1), and the two outer walls of the first capacitor electrode 41 arranged opposite each other along the second direction Y. The second capacitor electrode 42 fills the sixth groove A6 where the first capacitor electrode 41 is located, and fills the area between adjacent first capacitor electrodes 41 along the direction perpendicular to the substrate 1, and the area between adjacent thirteenth insulating layers 53 along the second direction Y. Figures 23A to 23D As shown, Figures 23A to 23DThese are cross-sectional views along the AA', BB', DD', and FF' directions respectively, provided in some embodiments after the formation of the dielectric layer 43 and the second capacitor electrode 42.

[0247] 212) Thinning of the position line 30;

[0248] An eighteenth insulating film is deposited to form an eighteenth insulating layer 58 covering the aforementioned structure;

[0249] Etch the eighteenth insulating layer 58 to expose the first hole K1;

[0250] The thirteenth insulating layer 53 inside the first hole K1 is etched away, and the sixth dummy layer 76 inside the first hole K1 is etched away, and the fourteenth insulating layer 54 is etched away to expose the first interconnect layer 61; at this time, the sixth dummy layer 76 disposed on the side of the first sacrificial layer 10 facing the first hole K1 is removed, and the sixth dummy layer 76 forms an annular structure surrounding the first sacrificial layer 10 on the side away from the substrate 1, the side facing the substrate 1, and the side away from the first hole K1;

[0251] The first interconnect layer 61 is etched to expose the bit line 30. At this time, the cross-section of the first interconnect layer 61 parallel to the substrate 1 forms two independent segments distributed along the first direction X. Etching the bit line 30 reduces its size along the second direction Y, thereby increasing the distance between adjacent bit lines 30 along the second direction Y, thus reducing the coupling capacitance between adjacent bit lines 30 along the second direction Y. Figures 24A to 24D As shown, Figures 24A to 24D These are cross-sectional views along the AA', BB', CC', and FF' directions after thinning the bit line 30, as provided in some embodiments.

[0252] 213) Forming the first channel B1;

[0253] A ninth insulating film is deposited and etched to retain the ninth insulating film covering the exposed surface of the first connecting layer 61 and the exposed surface of the bit line 30, forming a ninth insulating layer 19 and a fourth hole K4, exposing the first sacrificial layer 10; the ninth insulating layer 19 covers the side of the first connecting layer 61 facing the bit line 30, and also covers the two sidewalls of the bit line 30 that are arranged opposite each other along the second direction Y.

[0254] The first sacrificial layer 10 is etched away to expose the twelfth insulating layer 22 located on the side of the first sacrificial layer 10 away from the bit line 30, forming the first channel B1;

[0255] Etching the twelfth insulating layer 22, the sixteenth insulating layer 56, and the fourteenth insulating layer 54 exposes the surface of the sixth dummy layer 76 facing the first sacrificial layer 10, i.e., the inner surface of the sixth dummy layer 76; exposes the second interconnecting layer 62 facing the bit line 30; and exposes the first interconnecting layer 61 away from the bit line 30. Figures 25A to 25F As shown, Figures 25A to 25F The following are cross-sectional views along the AA', BB', CC', DD', EE' and FF' directions after the formation of the first channel B1, provided in some embodiments.

[0256] 214) Forming a semiconductor layer 23, a gate insulating layer 24, and a word line 40;

[0257] A semiconductor thin film, a gate insulating film, and a fourth conductive film are sequentially deposited on a substrate 1 forming the aforementioned structure. The semiconductor thin film and the gate insulating film sequentially cover the inner walls of the first channel B1 and the fourth hole K4. The fourth conductive film fills the first channel B1 and covers the inner walls of the fourth hole K4. The semiconductor thin film, the gate insulating film, and the fourth conductive film in the fourth hole K4 are etched away, while the semiconductor thin film, the gate insulating film, and the fourth conductive film in the first channel B1 are retained. This forms multiple semiconductor layers 23 (referred to as semiconductor structure layers) connected in an integrated structure of multiple transistors, multiple gate insulating layers 24 (referred to as gate insulating structure layers) connected in an integrated structure of multiple transistors, and word lines 40. Figures 26A to 26D As shown, Figures 26A to 26D The images show cross-sectional views along the AA', DD', EE', and FF' directions after the formation of the semiconductor layer 23, gate insulating layer 24, and word line 40, respectively, according to some embodiments. In this case, the multiple semiconductor layers 23 of the multiple transistors are connected on the side away from the substrate 1, the side facing the substrate 1, and the side away from the bit line 30, and are broken into multiple segments spaced apart along the second direction Y on the side facing the bit line 30 (the break occurs at the location of the fourth hole K4).

[0258] 215) Disconnect multiple semiconductor layers 23 of multiple transistors;

[0259] A nineteenth insulating film is deposited and etched to expose the sixth dummy layer 76, forming a nineteenth insulating layer covering the end face of the semiconductor layer 23 and the end face of the gate insulating layer 24.

[0260] The sixth dummy layer 76 is etched away to expose the semiconductor structure layer on the side away from the substrate 1, the side facing the substrate 1, and the side away from the bit line 30.

[0261] The semiconductor structure layer exposed by etching is disconnected between the multiple semiconductor layers 23 of the multiple transistors. At this time, the multiple semiconductor layers 23 of the multiple transistors are disconnected on the side away from the substrate 1, the side facing the substrate 1, and the side away from the bit line 30.

[0262] A tenth insulating film is deposited to form a tenth insulating layer 20. This tenth insulating layer 20 fills the cavity formed after the sixth dummy layer 76 and the semiconductor structure layer are etched, and also fills the fourth hole K4, as shown below. Figures 12A to 12F As shown. In this embodiment, the tenth insulating layer 20 includes a vertical portion disposed in the fourth hole K4 and a surrounding portion surrounding multiple word lines 40. That is, the tenth insulating layer 20 includes a vertical portion disposed between adjacent bit lines 30 along the second direction Y, penetrating multiple layers, and multiple surrounding portions extending from the vertical portion. The multiple surrounding portions are connected to form an integral structure (connected on the side of the word lines 40 away from the bit lines), and fill the area between adjacent word lines 40 along the direction perpendicular to the substrate 1. The location of the surrounding portions can be referenced to the location of the sixth dummy layer 76.

[0263] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0264] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A multilayer array of memory cells stacked perpendicular to the substrate, the array comprising at least one column of multiple memory cells distributed along a second direction; Multiple bit lines extend through the memory cells in different layers along a direction perpendicular to the substrate; memory cells at the same position in different layers are connected to the same bit line; Multiple word lines are distributed in different layers. The word lines and the bit lines are distributed along a first direction, and the word lines extend along a second direction. The first direction and the second direction are parallel to the substrate and intersect each other. The memory cell includes a transistor and a first capacitor electrode. The transistor includes a semiconductor layer surrounding the word line, and the first capacitor electrode is disposed on the side of the semiconductor layer opposite to the bit line. Multiple semiconductor layers of multiple transistors in the same column surround the same word line, and the multiple semiconductor layers of multiple transistors in the same column are spaced apart along a second direction. The semiconductor layer is connected to the bit line through a first connection layer disposed between the semiconductor layer and the bit line, and is connected to the first capacitor electrode through a second connection layer disposed between the semiconductor layer and the first capacitor electrode.

2. The semiconductor device according to claim 1, characterized in that, Multiple first connecting layers distributed along a direction perpendicular to the substrate are connected to form an integral structure.

3. The semiconductor device according to claim 1, characterized in that, The first capacitor electrode forms a cylindrical structure with its opening direction opposite to that of the semiconductor layer, and the second connecting layer covers the outer bottom wall of the first capacitor electrode facing the semiconductor layer and a portion of the outer side wall connected to the outer bottom wall.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor layer is covered by the first interconnect layer on the side facing the bit line.

5. The semiconductor device according to claim 1, characterized in that, The semiconductor layer has a protrusion facing the first capacitor electrode on the side facing the first capacitor electrode, and the semiconductor layer is only partially covered by the second connection layer on the side facing the first capacitor electrode, and the area not covered by the second connection layer is distributed on both sides of the area covered by the second connection layer, which are arranged opposite to each other along the second direction.

6. The semiconductor device according to claim 5, characterized in that, The maximum dimension of the region of the word line surrounded by the semiconductor layer in the direction perpendicular to the substrate is greater than the maximum dimension of the region not surrounded by the semiconductor layer in the direction perpendicular to the substrate.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor layer has a recess facing away from the first capacitor electrode on the side facing the first capacitor electrode, and the semiconductor layer facing the first capacitor electrode is covered by the second interconnecting layer.

8. The semiconductor device according to claim 7, characterized in that, The word lines have a consistent dimension along the direction perpendicular to the substrate.

9. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a tenth insulating layer, the tenth insulating layer including a vertical portion disposed between adjacent bit lines along a second direction and penetrating multiple layers, and a plurality of surrounding portions extending from the vertical portion, respectively surrounding the word lines on a side away from the substrate, a side facing the substrate, and a side away from the bit lines, the surrounding portions being disposed between adjacent semiconductor layers along the second direction.

10. The semiconductor device according to claim 9, characterized in that, Multiple surrounding portions of different layers of the same tenth insulating layer are spaced apart along a direction perpendicular to the substrate, or multiple surrounding portions of the same tenth insulating layer are connected to form an integral structure on the side of the word line away from the bit line, and fill the area between adjacent word lines along a direction perpendicular to the substrate.

11. The semiconductor device according to claim 1, characterized in that, The bit lines are distributed on a portion of the surface of the first connection layer facing the bit lines.

12. The semiconductor device according to claim 1, characterized in that, The transistor further includes a gate insulating layer disposed between the semiconductor layer and the word line surrounding the word line. Multiple gate insulating layers of multiple transistors distributed in the same column along the second direction in the same layer are connected to form an integral structure. The integral structure formed by the multiple gate insulating layers extends continuously on the side facing the substrate, the side away from the substrate, and the side away from the bit line, and is disconnected between adjacent semiconductor layers along the second direction on the side facing the bit line.

13. The semiconductor device according to claim 3, characterized in that, The storage cell further includes a capacitor. The capacitor and the transistor in the same storage cell are distributed along the first direction. The capacitor includes a dielectric layer and a second capacitor electrode. The dielectric layer is disposed between the first capacitor electrode and the second capacitor electrode. The second capacitor electrode fills the cylindrical structure formed by the first capacitor electrode and is distributed on the side of the first capacitor electrode away from the substrate, the side facing the substrate, and two outer sidewalls disposed opposite to each other along the second direction.

14. The semiconductor device according to claim 13, characterized in that, Multiple second capacitor electrodes of multiple capacitors adjacent to each other along the second direction are connected to form an integral structure; A single structure formed by connecting multiple second capacitor electrodes fills the area between adjacent first capacitor electrodes along the second direction, or an isolation layer extending perpendicular to the substrate exists between adjacent first capacitor electrodes along the second direction, the isolation layer spacing the adjacent second capacitor electrodes along the second direction.

15. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure comprising multiple alternating first insulating layers and first sacrificial layers is formed on a substrate; A plurality of first holes and a plurality of third holes are formed through the stacked structure along a direction perpendicular to the substrate. The plurality of first holes are spaced apart along a second direction, and the plurality of third holes are spaced apart along the second direction. The first holes and the third holes are spaced apart along a first direction. A second insulating layer is formed covering the sidewalls of the first holes and the sidewalls of the third holes. A first dummy layer is formed filling the first holes and the third holes. The first direction and the second direction are parallel to the substrate and intersect. A second hole is formed between adjacent first holes along the second direction, penetrating the stacked structure in a direction perpendicular to the substrate. The sidewall of the second hole exposes the second insulating layer in the first hole. Based on the second hole, the first sacrificial layer is etched in a direction parallel to the substrate until the second insulating layer in the third hole is exposed, forming a first channel extending along the second direction. A fourth insulating layer, a second dummy layer, a fifth insulating layer, and a second sacrificial layer are formed in the first channel from the outside to the inside; the fourth insulating layer, the second dummy layer, and the fifth insulating layer surround the second sacrificial layer in sequence, and the second dummy layer has a plurality of first grooves spaced apart along the second direction on the side facing the substrate and the side facing away from the substrate, and the opening direction of the first grooves faces the second hole; A first connection layer and a bit line connected to the first connection layer are formed in the second hole; A first trench is formed on the side of the third hole away from the first hole, penetrating the stacked structure and extending along the second direction. Based on the first trench, the first sacrificial layer, the fourth insulating layer, and the second dummy layer are etched along a direction parallel to the substrate, such that the second dummy layer forms a plurality of dummy sub-layers spaced apart along the second direction, and a second groove is formed on the side of the first channel away from the bit line and located between adjacent third holes along the second direction. A second connection layer and a first capacitor electrode connected to the second connection layer are sequentially formed in the second groove, and the first capacitor electrode is disposed on the side of the second connection layer away from the bit line. Based on the etching of the first hole, the second sacrificial layer and the fifth insulating layer in the first channel are removed, and the dummy sub-layer is etched away on the side facing the first hole. A word line extending in the second direction is formed in the first channel, and a gate insulating layer and a semiconductor structure layer are sequentially surrounded around the word line. The semiconductor structure layer connects the first connection layer and the second connection layer. The semiconductor structure layer is broken into multiple segments spaced apart in the second direction on the side facing the bit line. The dummy sublayer is etched away to expose the region where the semiconductor structure layer is connected to the dummy sublayer. The semiconductor structure layer is then etched to break it into multiple semiconductor layers spaced apart along a second direction.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that, When the first sacrificial layer, the fourth insulating layer, and the second dummy layer are etched along the direction parallel to the substrate based on the first trench, a third groove located in the first channel is also formed and communicates with the second groove. The second groove sequentially forms a second connecting layer and a first capacitor electrode connected to the second connecting layer, including: A seventh insulating film, a second connecting layer film, a second conductive film, and a third dummy layer film are sequentially deposited in the first trench, the second groove, and the third groove. The second connecting layer film, the second conductive film, and the third dummy layer film in the first trench are etched away, while the second connecting layer film, the second conductive film, and the third dummy layer film in the second groove are retained, forming a seventh insulating layer, a second connecting layer, a first capacitor electrode, and a third dummy layer. The seventh insulating layer covers the inner walls of the first trench and the second groove and fills the third groove. Before etching away the second sacrificial layer and the fifth insulating layer in the first channel based on the first hole, and before etching away the dummy sublayer towards the bit line side, the process further includes: The third dummy layer is etched away to expose the inner wall of the first capacitor electrode; Based on the first trench etching of the seventh insulating layer, the second insulating layer, and the first dummy layer, the two outer sidewalls of the second connection layer disposed opposite each other along the second direction, and the two outer sidewalls disposed perpendicular to the substrate direction are exposed. The exposed second connection layer is etched, and the second connection layer covering the side of the first capacitor electrode facing the first hole is retained, exposing the two outer sidewalls of the first capacitor electrode disposed opposite each other along the second direction, and the two outer sidewalls disposed opposite each other along the perpendicular to the substrate direction. A second capacitor electrode is formed, which fills the second groove where the first capacitor electrode is located, and covers the outer sidewalls of the first electrode exposed on the side facing the substrate and the side away from the substrate, and covers the two outer sidewalls of the first electrode that are disposed opposite each other along the second direction; and a plurality of capacitor electrodes in the same column distributed along the second direction are connected to form an integral structure, which fills the area between adjacent first capacitor electrodes along the second direction.

17. The method for manufacturing a semiconductor device according to claim 15, characterized in that, Forming a first connection layer and a bit line connected to the first connection layer in the second hole includes: A sixth insulating film, a first connecting layer film, and a first conductive film are sequentially deposited in the second hole to form a sixth insulating layer, a first connecting sublayer, and a bit line. The sixth insulating layer and the first connecting sublayer sequentially cover the bottom wall and sidewall of the second hole, and the bit line fills the second hole. Before removing the second sacrificial layer and the fifth insulating layer in the first channel by etching based on the first hole, the method further includes: etching the first interconnect layer based on the first hole to expose the bit line, and etching the bit line to reduce the size of the bit line along the second direction.

18. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure comprising multiple alternating first insulating layers and first sacrificial layers is formed on a substrate; A plurality of first holes and a plurality of third holes are formed through the stacked structure along a direction perpendicular to the substrate. The plurality of first holes are spaced apart along a second direction, and the plurality of third holes are spaced apart along the second direction. The first holes and the third holes are spaced apart along a first direction. A first dummy layer is formed to fill the first holes and the third holes. The first direction and the second direction are parallel to the substrate and intersect. A plurality of fifth holes are formed through the stacked structure perpendicular to the substrate and spaced apart along the second direction. The fifth holes are disposed between adjacent third holes along the second direction, and the sidewalls of the fifth holes expose the first dummy layer in the third holes. The first insulating layer is etched parallel to the substrate direction based on the fifth holes to form a fourth groove. A third sacrificial layer is formed covering the inner wall of the fifth hole and the inner wall of the fourth groove, and a fourth dummy layer is formed filling the fifth hole and the fourth groove; A second hole is formed between adjacent first holes along the second direction, penetrating the stacked structure in a direction perpendicular to the substrate. The sidewall of the second hole exposes a first dummy layer in the first hole. A fifth groove is formed by etching the first insulating layer in a direction parallel to the substrate based on the second hole. A fourth sacrificial layer is formed covering the inner wall of the second hole and the inner wall of the fifth groove, and a fifth dummy layer is formed filling the second hole and the fifth groove; The first dummy layer and the first insulating layer are etched away, and the third sacrificial layer and the fourth sacrificial layer are etched away. A second channel extending in a second direction is formed between adjacent first sacrificial layers. The second channel includes a connecting region connecting the first hole and the second hole and an intermediate region connecting the connecting region. A plurality of isolation sublayers are formed to fill the plurality of the intermediate regions. A twelfth insulating layer and a sixth dummy layer are formed to sequentially cover the sidewall of the first hole, the sidewall of the third hole, and the inner wall of the connecting area, and the sixth dummy layer fills the connecting area; A first connection layer and a bit line connected to the first connection layer are formed in the second hole; The fourth dummy layer is removed by etching, and the third sacrificial layer in the fourth groove is etched to form a fifteenth insulating layer that fills the third groove. The first sacrificial layer is etched to form a sixth groove, and a second connection layer and a first capacitor electrode connected to the second connection layer are sequentially formed in the sixth groove. The first capacitor electrode is disposed on the side of the second connection layer away from the bit line. A sixth dummy layer is etched in the first and third holes, such that the sixth dummy layer forms a surrounding structure around the first sacrificial layer on the side away from the substrate, the side facing the substrate, and the side away from the first hole; a first channel is formed between a plurality of first holes and a plurality of third holes adjacent in the first direction and extending in the second direction, the first channel exposing the inner surface of the sixth dummy layer in the connected region; a word line extending in the second direction is formed in the first channel, a gate insulating layer and a semiconductor structure layer are sequentially surrounding the word line, the semiconductor structure layer connects the first interconnect layer and the second interconnect layer, and the semiconductor structure layer is broken into multiple segments spaced apart in the second direction on the side facing the bit line; The sixth dummy layer is etched away to expose the region where the semiconductor structure layer is connected to the sixth dummy layer. The semiconductor structure layer is then etched to break it into multiple semiconductor layers spaced apart along the second direction.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that, Before the second connecting layer and the first capacitor electrode connected to the second connecting layer are sequentially formed in the sixth groove, the following is also included: The fifteenth insulating layer is etched based on the sixth groove to reduce the dimension of the fifteenth insulating layer in the direction perpendicular to the substrate; The sixth groove sequentially forms a second connecting layer and a first capacitor electrode connected to the second connecting layer, comprising: A sixteenth insulating layer, a second connecting layer, and a first capacitor electrode are formed, sequentially covering the inner wall of the sixth groove; Before forming a first channel extending in a second direction between a plurality of first holes and a plurality of third holes adjacent in a first direction, the method further includes: The inner wall of the first capacitor electrode is exposed; The second connection layer is etched to expose the two outer sidewalls of the second connection layer that are disposed opposite each other along the second direction, and the two outer sidewalls that are disposed opposite each other along the direction perpendicular to the substrate. The second connection layer covering the side of the first capacitor electrode facing the first hole is preserved, and the two outer sidewalls of the first capacitor electrode that are disposed opposite each other along the second direction and the two outer sidewalls that are disposed opposite each other along the direction perpendicular to the substrate are exposed. A second capacitor electrode is formed, which fills the second groove where the first capacitor electrode is located, and covers the exposed outer sidewalls of the first electrode facing the substrate and away from the substrate, and covers the two outer sidewalls of the first electrode that are disposed opposite to each other along the second direction.

20. The method for manufacturing a semiconductor device according to claim 18, characterized in that, Forming a first connection layer and a bit line connected to the first connection layer in the second hole includes: The second hole and the fifth groove are exposed, forming a fourteenth insulating layer that fills the fifth groove and covers the bottom and side walls of the second hole, and the thickness of the fourteenth insulating layer in the second hole is reduced; A first interconnect layer film and a first conductive film are sequentially deposited in the second hole to form a first interconnect sublayer and a bit line. The first interconnect sublayer covers the bottom wall and sidewall of the second hole, and the bit line fills the second hole. Before forming a first channel extending along a second direction between a plurality of first holes and a plurality of third holes adjacent along a first direction, the method further includes: etching the first connection layer based on the first holes to expose the bit line, and etching the bit line such that the size of the bit line along the second direction is reduced.

21. An electronic device, characterized in that, This includes the semiconductor device as described in any one of claims 1 to 14, or the semiconductor device formed by the manufacturing method of the semiconductor device as described in any one of claims 15 to 20.

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