Integrated device and method of forming the same

Abstract

An integrated device and a method of fabricating the same are provided. The integrated device includes a first transistor over a substrate and having a first gate, a first channel having an inner sidewall surrounding the first gate, and a first dielectric separating the first channel from the first gate; a second transistor over the first transistor and having a second gate, a second channel having an inner sidewall surrounding the second gate, and a second dielectric separating the second channel from the second gate; a via coupling the first gate to the second channel; a first insulating layer surrounding the first transistor and having an inner sidewall spaced apart from the first transistor by a first gap; and a second insulating layer surrounding the second transistor and having an inner sidewall spaced apart from the second transistor by a second gap.

Description

Technical Field

[0001] The embodiments of the present invention relate to an integrated device and a method for manufacturing the same. Background Technology

[0002] Many modern integrated devices include memory components. Memory components store information in a plurality of memory cells. Some forms of memory cells, such as random access memory (RAM), are used to temporarily store information during circuit operation. Some types of RAM include dynamic RAM (DRAM) and static RAM (SRAM). Some embodiments of DRAM include cells that use a transistor and a capacitor to store information. These are often referred to as 1T1C DRAM cells. Summary of the Invention

[0003] Embodiments of the present invention provide an integrated device, comprising: a first transistor covering a substrate and having a first gate, a first channel having an inner sidewall surrounding the first gate, and a first dielectric material separating the first channel from the first gate; a second transistor covering a read transistor and having a second gate, a second channel having an inner sidewall surrounding the second gate, and a second dielectric material separating the second channel from the second gate; a via coupling the first gate to the second channel; a first insulating layer surrounding the first transistor and having an inner sidewall spaced from the first transistor through a first gap; and a second insulating layer surrounding the second transistor and having an inner sidewall spaced from the second transistor through a second gap.

[0004] Embodiments of the present invention provide a method for forming an integrated device, comprising: forming a first character line on a substrate, the first character line being separated from the substrate in a first direction and extending in a second direction perpendicular to the first direction; forming a first insulating layer covering the first character line; forming a first first line on the first insulating layer, separated from the first character line in the first direction through the first insulating layer, the first first line extending in a third direction perpendicular to the first and second directions; etching through the first first line and into a first opening of the first character line; continuously forming a first channel, a first dielectric, and a first gate in the first opening to fill the first opening; etching around the first channel... A portion of the first insulating layer of the channel creates a first gap extending from the outermost wall of the first channel to the first bit line; an interlayer dielectric is formed on the first insulating layer to cover the first gap; a via and a source / drain connector are formed on the first gate and electrically coupled to the first gate; a second bit line is formed extending on the source / drain connector and spaced from the source / drain connector; a second opening is etched through the second bit line and exposes the source / drain connector; a second channel, a second dielectric, and a second gate are continuously formed in the second opening to fill the second opening; and a second character line is formed extending on the second gate and electrically coupled to the second gate.

[0005] Embodiments of the present invention provide a method for forming an integrated device, comprising: forming a first character line on a substrate; forming a first insulating layer on the first character line; forming a first bit line on the first insulating layer; forming a first transistor gate stack extending from the first bit line to the first character line, including a first channel, a first dielectric, and a first gate; etching the first insulating layer surrounding the first transistor gate stack to form a first gap between the inner sidewall of the first insulating layer and the first transistor gate stack; forming a second insulating layer on the first insulating layer and the first transistor gate stack; forming a second bit line on the second insulating layer; forming a second transistor gate stack extending between the second bit line and the first gate, including a second channel, a second dielectric, and a second gate; etching the second insulating layer surrounding the second transistor gate stack to form a second gap between the inner sidewall of the second insulating layer and the second transistor gate stack; and forming a second character line electrically coupled to the second gate. Attached Figure Description

[0006] The various aspects of this disclosure are best understood when read in conjunction with the accompanying drawings. The drawings are intended to clearly illustrate relevant aspects of the embodiments. The drawings may illustrate the relationships between various structures and / or components within the embodiments. It should be noted that the drawings are not necessarily drawn to scale. In some cases, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A and Figure 1B The illustrations include cross-sectional and perspective views of an integrated device with two vertical transistors in a memory cell, and first and second gaps between the channels of the vertical transistors and the inner sidewalls surrounding the insulating layer.

[0008] Figure 2 The circuit diagrams of some embodiments of the integrated device are illustrated. The integrated device has 2 TOC DRAM memory cells.

[0009] Figures 3A to 3D The illustration shows a top view and a cross-sectional view of an integrated device with two vertical transistors in a memory cell, and first and second gaps of non-uniform thickness.

[0010] Figure 4 The diagram illustrates a cross-sectional view of an integrated device having two vertical transistors of different sizes within a memory cell, with first and second gaps between the channels of the vertical transistors and the inner walls surrounding the insulating layer of each transistor.

[0011] Figures 5A to 5BSections 6A to 6B, 7 to 10, 11A to 11C, 12, 13A to 13B, and 14 to 18 illustrate cross-sectional and top views of methods for forming an integrated device according to some embodiments, the integrated device having two vertical transistors in a memory cell, with first and second gaps between first and second channels of the vertical transistors and the inner sidewalls surrounding an insulating layer.

[0012] Figure 19 A flowchart illustrating a method for forming an integrated device according to some embodiments is provided. The integrated device has two vertical transistors in a memory cell and first and second gaps between first and second channels of the vertical transistors and the inner sidewalls surrounding an insulating layer. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or illustrations to implement various features of the provided object. Specific illustrations of components and configurations described below are for the purpose of simplifying this disclosure. These are, of course, merely illustrative and are not intended to be limiting. For example, in the following description, the formation of a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various illustrations throughout this disclosure. Such repetition is for the sake of brevity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of explanation, spatially relative terms such as "below," "under," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. In some embodiments, the terms "about" and / or "approximately" may be interpreted as meaning + / - 10% or + / - 5%, while in other embodiments, the terms "about" and / or "approximately" may be interpreted as meaning within normal manufacturing tolerances of a given wafer fab manufacturing process.

[0015] Memory cells are used to store bits of information for use by electronic devices during operation. DRAM memory cells, including one transistor and one capacitor (e.g., 1T1C DRAM cells), have been used to build memory arrays, partly because memory cells have a small footprint. However, recent advances in manufacturing technology have introduced the opportunity for DRAM memory cells, including two transistors (e.g., 2T0C DRAM cells), to form memory arrays with comparable device density, reduced power consumption, and lower shutdown current than 1T1C cells using low-temperature (e.g., below 400 degrees Celsius) back-end of line (BEOL) processes.

[0016] Further development of 2T0C DRAM cells faces numerous challenges, including capacitive coupling between different memory cells, reducing the voltage held at the memory cell storage node. This reduced voltage response necessitates higher voltages for the same operation, and shorter memory windows when storing bits (e.g., the amount of time before leakage renders the held data unreliable). Furthermore, variations in hydrogen diffusion and oxygen vacancy density in transistor channels alter the critical voltage of the memory cell, leading to further inaccuracies or failures.

[0017] This disclosure details a 2TOC memory cell having an air gap extending between the outer walls of the read and write transistor channels and the inner walls of the insulating layers surrounding the read and write transistors, respectively. The air gap introduces a layer with a low dielectric constant (e.g., air with a dielectric constant of approximately 1), reducing capacitive coupling of the memory cells in the memory array. Furthermore, the air gap substantially eliminates hydrogen and oxygen diffusion between the channels and the insulating layers, resulting in more consistent operation, less variation in the threshold voltage, and improved lifetime of the integrated device.

[0018] Figure 1A and Figure 1B The illustration shows a cross-sectional view 100a and a perspective view 100b of an integrated device according to some embodiments. The integrated device has two vertical transistors in a memory cell, with first and second gaps between the vertical transistor channels and the respective inner sidewalls surrounding the insulating layer.

[0019] like Figure 1AAs shown in cross-sectional view 100a, memory cell 104 covers substrate 102. Memory cell 104 includes write transistor 108 coupled to read transistor 106. Write transistor 108 and read transistor 106 are channel-all-around (CAA) vertical transistors. Read transistor 106 includes a first gate 110 having a base portion 110a and a first protrusion 110b extending from the base portion toward substrate 102. In some embodiments, the first protrusion 110b includes a portion of read transistor 106 surrounded by a first outer wall 110c, and the base portion also includes a portion of read transistor further from substrate 102 than the first outer wall 110c. Read transistor 106 also includes a first dielectric 112 covering the first outer wall 110c of the first gate 110, and a first channel 114 surrounding the first dielectric 112 and separated from the first gate 110 by the first dielectric 112. In some cases, the combination of the first gate 110, the first dielectric 112, and the first channel 114 is also referred to as a first transistor gate stack. In some embodiments, the read transistor 106 is referred to as the first transistor, and the write transistor 108 is referred to as the second transistor. An axis extending approximately perpendicular to the surface of the substrate 102 extends through the first and second gates.

[0020] A first character line 116 extends between the first channel 114 and the substrate 102 and extends around the first outer sidewall 114a of the first channel 114. The first character line 116 is electrically coupled to the first surface 114b of the first channel 114 closest to the substrate 102. A first intermetallic (IM) layer 118 extends between the first character line 116 and the first surface 114b of the first channel 114. A first IM line 120 surrounds the first outer sidewall 114a of the first channel 114 and is spaced from the first character line 116. A second IM layer 122 extends between the first IM line 120 and the first channel 114 of the read transistor 106.

[0021] The read transistor 106 is surrounded by a first insulating layer 124. A first gap 126 separates the first inner sidewall 124a of the first insulating layer 124 from the read transistor 106. The write transistor 108 is surrounded by a second insulating layer 128 and separated from the second inner sidewall 128a of the second insulating layer 128 by a second gap 130. The first gap 126 and the second gap 130 have several advantages. Separating the first channel 114 of the read transistor 106 and the second channel 132 of the write transistor 108 from the first and second inner sidewalls 124a and 128a of the first and second insulating layers 124 and 128, respectively, reduces the amount of diffusion that occurs between the first and second insulating layers 124 and 128.

[0022] The diffusion of oxygen, hydrogen, and / or other materials into or out of the first and second channels 114, 132 alters the characteristics of the read and write transistors 106, 108, including the device's critical voltage. As the density and size of integrated devices decrease, the tolerance for variations in parameters such as critical voltage also decreases. Increases or decreases in the critical voltage due to diffusion can lead to data loss or memory cell failure, reducing memory array lifetime and manufacturing yield. This problem is mitigated by introducing first and second gaps 126, 130 extending along the first and second channels 114, 132 to reduce diffusion, thereby improving device lifetime and performance, as well as manufacturing process yield.

[0023] The first and second air gaps 126 and 130 further improve the mechanical stability of the integrated device because the air gaps increase the device's ability to handle stresses from physical impacts during the manufacturing process or packaging layers. The first and second air gaps 126 and 130 also have low dielectric constants (e.g., about 1), reducing parasitic capacitances caused by proximity of memory cells in the memory array. Reduced parasitic capacitance lowers the operating voltage of the memory cells and improves the memory window of the integrated device.

[0024] like Figure 1B As shown in the perspective view, read transistor 106 and write transistor 108 have their longest dimensions in the first direction 134. The first character line 116 extends in a second direction 136 perpendicular to the first direction 134. The first bit line 120 extends in a third direction 138 perpendicular to the first direction 134 and the second direction 136. In some embodiments, a memory cell is part of a memory array 139 including additional memory cells 141. Memory cells 104 and additional memory cells 141 are arranged in a plurality of rows 140 and a plurality of columns 142. For example, memory cell 104 and the first additional memory cell 141a are substantially aligned in the first column 142a, and the second additional memory cell 141b and the third additional memory cell 141c are substantially aligned in the second column 142b. Furthermore, memory cell 104 and the third additional memory cell 141c are aligned in the first column 140a, and the first additional memory cell 141a and the second additional memory cell 141b are substantially aligned in the second column 140b. In some embodiments, a plurality of rows 140 extend in a third direction 138, and a plurality of columns 142 extend in a second direction 136.

[0025] Figure 2 Circuit diagram 200 illustrates some embodiments of an integrated device having 2T0C DRAM memory cells.

[0026] The read transistor 106 has a first source / drain region 202 coupled to the first bit line 120 and a second source / drain region 204 coupled to the first character line 116. The write transistor 108 has a third source / drain region 206 coupled to the second bit line 208 and a fourth source / drain region 210 coupled to the first gate 110. The write transistor 108 has a second gate 212 coupled to the second character line 214.

[0027] Memory cell 104 holds bit information in two states: a "1" state and a "0" state. The state of the device is based on a threshold voltage of read transistor 106 and a charge held at the first gate 110 of read transistor 106. When the charge held at the first gate 110 causes the first gate 110 to have a voltage higher than the threshold voltage, the read transistor conducts current between the first source / drain region 202 and the second source / drain region 204, and memory cell 104 is in either the "1" state or the "0" state. When the charge held at the first gate 110 causes the first gate 110 to have a voltage lower than the threshold voltage, memory cell 104 is in the other of the "1" state or the "0" state. In some embodiments, the current conduction between the first source / drain region 202 and the second source / drain region 204 corresponds to the "1" state. In other embodiments, the current conduction between the first source / drain region 202 and the second source / drain region 204 corresponds to the "0" state.

[0028] The state of memory cell 104 is determined by performing a "read" operation. In some embodiments, the "read" operation includes applying a reference voltage to the first character line 120 and applying a low voltage (e.g., a voltage below the threshold voltage of the write transistor 108) to the second character line 214. The state of memory cell 104 is then determined based on the voltage and / or current read at the first character line 116.

[0029] Data is stored in memory cell 104 by performing a "write" operation. The "write" operation involves applying a high voltage (e.g., a voltage higher than the threshold voltage of write transistor 108) to the second character line 214 and applying a voltage corresponding to the desired state to the second bit line 208. Since the voltage at the second gate 212 of write transistor 108 is higher than the threshold voltage of write transistor 108, charge corresponding to the voltage at the second bit line 208 is stored at the first gate 110 of read transistor 106. After charge storage, the second character line is driven to a low voltage, reducing current flow between the third source / drain region 206 and the fourth source / drain region 210. The reduced current flow traps charge in the first gate 110, storing the desired state (e.g., a "1" state or a "0" state) in memory cell 104.

[0030] Figures 3A to 3DTop views 300a, 300b and cross-sectional views 300c, 300d illustrate an embodiment of an integrated device having two vertical transistors in a memory cell and having first and second gaps and uniform and non-uniform thicknesses. Figure 3C 300c sectional view along Figure 3A The line A-A' of the top view 300a is cut off. Figure 3D 300d sectional view along Figure 3A The line B-B' of the top view 300a is cut off.

[0031] like Figure 3A As shown in the top view 300a, in some embodiments, the first gap 126 has a first thickness 302 in the second direction 136 and a second thickness 304 in the third direction 138, and the first thickness 302 is greater than the second thickness 304. In a further embodiment, the first thickness 302 is more than 10% greater than the second thickness 304. The second thickness 304 is equal to or less than the width of the first character line 116 (outline shown in dashed lines) located below the first gap 126. The first gap 126 does not extend beyond the outer wall of the first character line 116, causing the first character line 116 to be an etching process forming the first gap 126 (see [reference]). Figure 11A The etch stop layer (1102). For example... Figure 3B As shown in the top view 300b, in some embodiments, the first thickness 302 and the second thickness 304 of the first gap 126 are substantially equal (e.g., have thicknesses within 10% of each other), and the first thickness 302 and the second thickness 304 are greater than the width of the first character line 116 in the third direction 138.

[0032] like Figure 3C As shown in cross-sectional view 300c, in some embodiments, a first distance 306 is measured in the third direction 138 between a first inner sidewall 124a of the first insulating layer 124 and a first outer sidewall 114a of the first channel 114. In some embodiments, the first distance 306 is between about 3 nm and 10 nm, between 1 nm and 7 nm, between 1 nm and 10 nm, or in another similar range. The first gap 126 does not extend beyond the outer sidewall 116a of the first character line 116 in the third direction 138. A source / drain connector 308 extends below the second gap 130. In some embodiments, the source / drain connector 308 has a wider width in the third direction 138 than the first character line 116.

[0033] like Figure 3D As shown in the cross-sectional view 300d, in some embodiments, the second distance 310 is measured in the second direction 136 between the first inner wall 124a of the first insulating layer 124 and the first outer wall 114a of the first channel 114. The second distance 310 is greater than the first distance (see...). Figure 3C(306). In some embodiments, the second gap has a first distance in the third direction 138 (see 306). Figure 3C (306) and has a second distance 310 in the second direction 136, and the second gap 130 does not extend beyond the outer wall 308a of the source / drain connector 308.

[0034] Figure 4 The illustration shows a cross-sectional view 400 of an integrated device having two vertical transistors of different sizes, the integrated device having first and second gaps in the memory cell between the channels of the vertical transistors and the inner walls of the respective surrounding insulating layers.

[0035] In some embodiments, the read transistor 106 and write transistor 108 have different characteristics to improve the performance of memory cell 104. For example, in some embodiments, write transistor 108 has a second channel 132 with a thickness less than that of the first channel 114. The reduced thickness of the second channel 132 reduces the number of charge carriers available during operation, increases the threshold voltage of write transistor 108 compared to read transistor 106, and reduces leakage in the second channel 132. In some embodiments, read transistor 106 has a capacitance between the first gate 110 and the first channel 114 that is greater than the capacitance between the second gate 212 and the second channel 132, which arises from the increased length and width of read transistor 106. The increased capacitance can result in a higher retention window for memory cell 104.

[0036] In some embodiments, an axis 402, generally perpendicular to the substrate 102 extending relative to the surfaces 408 of the read transistor 106 and the write transistor 108, extends through the lateral centers of the first gate 110 and the second gate 212. The write transistor 108 directly covers the read transistor 106, and the geometric center 404 of the write transistor 108 is substantially aligned with the geometric center 406 of the read transistor 106 in a first direction perpendicular to the substrate 102 relative to the surfaces 408 of the read transistor 106 and the write transistor 108.

[0037] The read transistor 106 and the write transistor 108 each include a first base portion 106a, the first base portion 106a including the outermost walls of the first gate 110, the first dielectric 112 and the first channel 114 and the surface of the first gate 110, the first dielectric 112 and the first channel 114 that is farthest from the substrate 102, and a second base portion 108a, the second base portion 108a including the outermost walls of the second gate 212, the second dielectric 410 and the second channel 132 and the surface of the second gate 212, the second dielectric 410 and the second channel 132 that is farthest from the substrate. The read transistor 106 and write transistor 108 further include a first bottom portion 106b, which includes a surface closest to the first gate 110, the first dielectric 112, and the first channel 114 of the substrate 102, and a second bottom portion 108b, which includes a surface closest to the second gate 212, the second dielectric 410, and the second channel 132 of the substrate 102. The read transistor 106 and write transistor 108 further include a first sleeve portion 106c extending between the first base portion 106a and the first bottom portion 106b, and a second sleeve portion 108c extending between the second base portion 108a and the second bottom portion 108b, respectively. The first sleeve portion 106c has its longest dimension in a first direction substantially perpendicular to the surface of the first gate 110 furthest from the substrate 102, and includes an outer wall of the first gate 110, the first dielectric 112, and the first channel 114 extending between the first base portion 106a and the first bottom portion 106b. The second sleeve portion 108c has the longest dimension in a first direction substantially perpendicular to the surface of the second gate 212 furthest from the substrate 102, and includes the outer sidewalls of the second gate 212, the second dielectric 410, and the second channel 132 extending between the second base portion 108a and the second bottom portion 108b. The first channel 114, the second channel 132, the first dielectric 112, the second dielectric 410, the first gate 110, and the second gate 212 may also be individually described as having a base portion with the outermost outer sidewall, a lower surface furthest from the substrate, and an upper surface furthest from the substrate 102, a bottom portion with a bottom surface closest to the substrate 102, and a sleeve portion extending between the bottom portion and the base portion.

[0038] Figures 5A to 5BSections 6A to 6B, 7 to 10, 11A to 11C, 12, 13A to 13B, and 14 to 18 illustrate cross-sectional views 500a, 600a, 700-1000, 1100a, 1200, 1300a, 1400-1800 and top views 500b, 600b, 1100b-1100c, 1300b, which are some embodiments of a method of forming an integrated device having two vertical transistors in a memory cell, with first and second gaps between first and second channels of the vertical transistors and the inner sidewalls surrounding an insulating layer. Although Figures 5A to 5B Sections 6A to 6B, 7 to 12, 13A to 13B, and 14 to 18 pertain to method descriptions and should be understood. Figures 5A to 5B The structures disclosed in 6A to 6B, 7 to 12, 13A to 13B, and 14 to 18 are not limited to this method, but can exist independently of the method as structures. Figures marked "B" (e.g., Figure 5B , 6B (and 13B) are the corresponding diagrams marked "A" (e.g., respectively) Figure 5A , 6A The top view of 13A, and Figure 5A , 6A and 13A respectively along Figure 5B , 6B Obtained from the A-A' line of 13B.

[0039] like Figure 5AAs shown in cross-sectional view 500a, a first character line 116, a first portion 124b of a first insulating layer 124, and a first first line 120 are formed over a substrate 102. An etch stop layer 502 extends between the first character line 116 and the substrate 102. In some embodiments, one or more additional conductor layers (not shown) extend between the etch stop layer 502 and the substrate 102. In some embodiments, the first character line 116 and the first first line 120 are independently conductive materials or include conductive materials, such as tantalum nitride (TaN), tungsten (W), titanium nitride (TiN), ruthenium (Ru), or another BEOL-compatible conductive material. In some embodiments, the first insulating layer 124 is an insulating material or includes insulating materials, such as silicon dioxide (SiO2) or the like. In some embodiments, the first insulating layer 124 is formed using a deposition process, such as atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or a similar process. In some embodiments, the first character line 116 and the first bit line 120 are formed using one of deposition (e.g., ALD, PVD, CVD, or similar processes) and etching processes (e.g., forming and patterning a shielding layer and performing anisotropic etching), damascene processes, or similar processes. In some embodiments, the first character line 116 and the first bit line 120 have a thickness between approximately 100 angstroms and 400 angstroms, between 200 angstroms and 500 angstroms, between 100 angstroms and 500 angstroms, or similar ranges.

[0040] like Figure 5B As shown in the top view 500b, the first character line 116 (shown in dashed lines) extends in the second direction 136, and the first first line 120 extends in the third direction 138. The first first line 120 crosses the first character line 116 at the first intersection 504. The first first line 120 is separated from the first character line 116 in the first direction 134 by the first insulating layer 124.

[0041] like Figure 6A As shown in cross-sectional view 600a, a first shielding layer 604 is formed over the first insulating layer 124 and the first first line 120. In some embodiments, the first shielding layer 604 is a photoresist, hard shield, or the like, or includes a photoresist, hard shield, or the like. In some embodiments, the first shielding layer is formed using a deposition process, an immersion process, a spin coating process, a sputtering process, or a similar process. The first shielding layer 604 is then patterned to expose areas of the first insulating layer 124 and the first first line 120, which correspond to the first channel to be formed thereafter (see [reference]). Figure 1A 114), the first dielectric (see 114), the first dielectric material (see 114) Figure 1A (112) and the first gate (see 112) and the first gate (see 112) Figure 1A The position of 110). In some embodiments, the first shielding layer 604 is patterned using an etching process, photolithography or a similar process.

[0042] After the first shielding layer 604 is patterned, a first etching process 602 is performed. The first etching process 602 removes portions of the first insulating layer 124, the first first line 120, and the first character line 116 below the opening in the first shielding layer 604. The first etching process 602 creates a first opening 606 extending from the first first line 120 to the first character line 116. After the first etching process 602, the first first line 120 has inner sidewalls extending in a continuous, uninterrupted loop around the first opening 606. In some embodiments, the first etching process 602 is one or more anisotropic dry etching processes or includes one or more anisotropic dry etching processes. The first shielding layer 604 is then removed. Figure 6B As shown in the top view 600b, in the first etching process (see...) Figure 6A After 602), the first character line 116 is exposed.

[0043] like Figure 7 As shown in cross-sectional view 700, a first conformal IM layer 702, a first conformal channel 704, a first conformal dielectric 706, and a first conformal gate layer 708 are formed over the first character line 120 and the first insulating layer 124. The first conformal IM layer 702 is configured to bond the first conformal channel 704 to the first character line 116 and the first character line 120 to reduce memory cells (see...). Figure 1A Mechanical failure of 104). In some embodiments, the first conformal IM layer 702 is a conductive material or includes conductive materials such as titanium (Ti), tantalum (Ta), molybdenum (Mo), gallium (Ga), chromium (Cr), aluminum (Al), or the like. After deposition, a first portion 702a of the first conformal IM layer 702 extending between the first character line 116 and the first first line 120 interacts with oxygen atoms from the first insulating layer 124, causing the first portion 702a to include a metal oxide, such as titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), or the like. A second portion 702b of the first conformal IM layer 702 extending directly between the first conformal channel 704 and one of the first character line 116 or the first first line 120 has less exposure to oxygen atoms in the first insulating layer 124 and includes a lower proportion of metal oxide than the first portion 702a.

[0044] In some embodiments, the first conformal channel 704 is a semiconductor material or includes a semiconductor material, such as IG2MO (In... x Ga y Zn zMO, where M is titanium (Ti), aluminum (Al), tungsten (W), cerium (Ce), tin (Sn), zirconium (Zr), neodymium (Nd), samarium (Sm), or lutetium (Lu), and where x, y, and z are 0, 1, or between 0 and 1), IGZO, or the like. In some embodiments, the first conformal dielectric 706 is a high dielectric constant dielectric (e.g., a material having a relative dielectric constant greater than 20) or includes a high dielectric constant dielectric, such as hafnium oxide (HfO2), hafnium zirconium oxide (HZO), or the like. In some embodiments, the first conformal gate layer 708 is a conductive material or includes a conductive material, such as tantalum nitride (TaN), tungsten (W), titanium nitride (TiN), ruthenium (Ru), or the like.

[0045] In some embodiments, the first conformal IM layer 702, the first conformal channel 704, the first conformal dielectric 706, and the first conformal gate layer 708 are formed independently using a deposition process such as ALD, PVD, CVD, or the like. In some embodiments, the first conformal IM layer 702 has a thickness between approximately 5 angstroms and 8 angstroms, between 7 angstroms and 10 angstroms, between 5 angstroms and 10 angstroms, or similar ranges. In some embodiments, the first conformal channel 704 has a thickness between approximately 30 angstroms and 150 angstroms, between 60 angstroms and 200 angstroms, between 30 angstroms and 200 angstroms, or similar ranges. In some embodiments, the first conformal dielectric 706 has a thickness between approximately 30 angstroms and 100 angstroms, between 60 angstroms and 150 angstroms, between 30 angstroms and 150 angstroms, or similar ranges.

[0046] like Figure 8 As shown in the cross-sectional view 800, the second shielding layer 804 is formed in the first conformal gate layer (see...). Figure 7 Above the first conformal gate layer (see 708). In some embodiments, the second shielding layer 804 is a photoresist, hard shield, or the like, or includes a photoresist, hard shield, or the like. In some embodiments, the second shielding layer 804 is formed using a deposition process, an immersion process, a spin coating process, a sputtering process, or the like. The second shielding layer 804 is then patterned to cover the first conformal gate layer (see 708). Figure 7 The region 708 corresponds to the location of the first gate 110 to be formed thereafter. In some embodiments, the second shielding layer 804 is patterned using an etching process, photolithography, or the like.

[0047] After the second shielding layer 804 is patterned, a second etching process 802 is performed. The second etching process 802 removes the first conformal gate layer exposed by the patterning of the second shielding layer 804 (see [link to original text]). Figure 7The top surface of the first conformal dielectric 706 is exposed in part 708. In some embodiments, the second etching process 802 is one or more anisotropic dry etching processes or includes one or more anisotropic dry etching processes. The second shielding layer 804 is then removed.

[0048] like Figure 9 As shown in the cross-sectional view 900, a third shielding layer 904 is formed between the first gate 110 and the first conformal dielectric (see...). Figure 7 Above 706). In some embodiments, the third shielding layer 904 is a photoresist, hard shield, or the like, or includes a photoresist, hard shield, or the like. In some embodiments, the third shielding layer 904 is formed using a deposition process, an immersion process, a spin coating process, a sputtering process, or the like. The third shielding layer 904 is then patterned to cover the first conformal dielectric (see 706). Figure 7 706) corresponds to the first dielectric 112, the first channel 114, and the first and second IM layers to be formed thereafter (see 706). Figure 1A The area at positions 118 and 122. In some embodiments, the third shielding layer 904 is patterned using an etching process, photolithography, or the like.

[0049] After the third shielding layer 904 is patterned, a third etching process 902 is performed. The third etching process 902 removes the first conformal dielectric exposed by the patterning of the third shielding layer 904 (see [link to third etching process]). Figure 7 706), the first conformal channel (see ...) Figure 7 The third etch process 904 and a portion of the first conformal IM layer 702 expose the first bit line 120 and the first insulating layer 124. In some embodiments, the third etch process 902 is one or more anisotropic dry etch processes or includes one or more anisotropic dry etch processes. The third shielding layer 904 is then removed.

[0050] like Figure 10 As shown in the cross-sectional view 1000, a second portion 124c of the first insulating layer 124 is formed over the first first line 120, the first gate 110, the first dielectric 112, and the first portion 124b of the first insulating layer 124. In some embodiments, the second portion 124c of the first insulating layer 124 is made of the same material as or includes the same material as the first portion 124b of the first insulating layer 124. In some embodiments, a planarization process (e.g., chemical mechanical planarization (CMP)) is performed after the deposition of the second portion 124c to produce a second portion 124c of the first insulating layer 124 having a substantially flat upper surface extending directly over the first gate 110.

[0051] As shown in the cross-sectional view 1100a of FIG11a, a fourth shielding layer 1104 is formed over the first insulating layer 124. In some embodiments, the fourth shielding layer 1104 is a photoresist, hard shield, or the like, or includes photoresist, hard shield, or the like. In some embodiments, the fourth shielding layer 1104 is formed using a deposition process, an immersion process, a spin coating process, a sputtering process, or the like. The fourth shielding layer 1104 is then patterned to expose the area of ​​the first insulating layer 124 corresponding to the location of the first gap 126 to be formed thereafter. In some embodiments, the fourth shielding layer 1104 is patterned using an etching process, photolithography, or the like.

[0052] In some embodiments, such as Figure 11B As shown in the top view 1100b, the exposed area of ​​the first insulating layer does not extend beyond the outer wall of the first character line 116 in the third direction 138 and extends beyond the outer wall of the first character line 120 in the second direction 136. In other embodiments, such as Figure 11C As shown in the top view 1100c, the exposed area of ​​the first insulating layer 124 does not simultaneously extend beyond the outer walls of both the first character line 116 and the first line 120 in either the second direction 136 or the third direction 138. That is, the exposed area (and the first gap 126 to be formed thereafter) includes a first portion 126a that extends beyond the outer wall of the first character line 116 in the third direction 138 but does not extend beyond the outer wall of the first line 120 in the second direction 136, and a second portion 126b that extends beyond the outer wall of the first line 120 in the second direction 136 but does not extend beyond the outer wall of the first character line 116 in the third direction 138.

[0053] like Figure 11A As shown, after the fourth shielding layer 1104 is patterned, a fourth etching process 1102 is performed. In some embodiments, the fourth etching process 1102 includes one or more anisotropic dry etching steps alternating with a plurality of wet etching steps. In other embodiments, the fourth etching process 1102 includes one or more anisotropic dry etching steps followed by a plurality of wet etching steps. The etching chemistry of the dry etching steps is selected based on the material of the first insulating layer 124 (e.g., the dry etching steps etch the material through the first insulating layer 124 faster than the materials of the first gate 110, the first dielectric 112, the first bit line 120, and the first character line 116). In some embodiments, a first portion of the exposed area extends beyond the outer wall of the first character line 116 (see...). Figure 11C126a) Directly above the first character line 120, reducing the amount of anisotropic etching performed on the portion of the first insulating layer 124 flush with the first character line 116. In other embodiments, the exposed area does not extend beyond the outer wall of the first character line 116 to prevent dry etching steps from removing material from the first insulating layer 124 that is not directly above the first character line 116.

[0054] The etching chemistry of the wet etching step is selected to include materials left as byproducts of the dry etching step (e.g., materials remaining on the newly exposed sidewalls of the first insulating layer 124 as residues of the dry etching step or materials that have chemically reacted with the etchant of the dry etching step) and the first conformal IM layer (see [reference]). Figure 7 Part 1 of 702 (see Figure 7 The metal oxide material (702a) is used. These different materials are selected in the alternating etching steps, and the fourth etching process 1102 removes portions of the first insulating layer 124 exposed by the patterning of the fourth shielding layer 1104, as well as the first conformal IM layer between the first first line 120 and the first character line 116 (see 702a). Figure 7 Part 1 of 702 (see Figure 7 (702a). The fourth etching process 1102 results in a first void 126 remaining between the first inner sidewall 124a of the first insulating layer 124 and the outer sidewall of the first channel 114, and the first IM layer 118 and the second IM layer 122 remaining on the first channel 114. In some embodiments, the fourth etching process 1102 is or includes one or more anisotropic dry etching processes. The fourth shielding layer 1104 is then removed.

[0055] An air gap extending between the first inner sidewall 124a of the first insulating layer 124 and the outer sidewall of the first channel 114 reduces the transfer of oxygen, hydrogen, and / or other materials between the first insulating layer 124 and the first channel 114, reducing contamination of the first channel 114 that could lead to changes in the critical voltage and other parameters of the read transistor 106. Furthermore, the first gap 126 has a dielectric constant of approximately 1, resulting in the read transistor 106 interacting with additional memory cells (see [link to documentation]). Figure 1B The capacitive coupling between transistors (141) is reduced.

[0056] like Figure 12As shown in the cross-sectional view 1200, a first interlayer dielectric (ILD) layer 1202 is formed over the read transistor 106 and the first insulating layer 124. The first ILD layer 1202 covers the read transistor 106 and the first insulating layer 124 without filling the first void 126. The aspect ratio of the deposition process used to form the first ILD layer 1202 and the narrow opening at the top of the first void 126 cause the first ILD layer 1202 to cover the first void 126 early in the deposition process, reducing the amount of material from the first ILD layer 1202 entering the first void 126. In some embodiments, the first ILD layer 1202 is or includes an insulating material, such as silicon nitride (Si3N4) or silicon carbonitride (SiO2). x C y N z (where x, y, and z are approximately 1, or another ratio of silicon, carbon, and nitrogen), or the like. In some embodiments, the first ILD layer 1202 is formed using a deposition process, such as ALD, PVD, CVD, or the like, followed by a planarization process (e.g., CMP process) to result in the first ILD layer 1202 having a substantially flat upper surface.

[0057] After the first ILD layer 1202 is formed, a first via interconnect 1204 is formed extending through the first ILD layer 1202 to contact the first gate 110. In some embodiments, the first via interconnect 1204 is or includes a conductive material, such as tantalum nitride (TaN), tungsten (W), titanium nitride (TiN), ruthenium (Ru), or another BEOL-compatible conductive material. In some embodiments, the first via interconnect 1204 is formed using an damascene process, a deposition and etching process, or the like.

[0058] like Figure 13A As shown in cross-sectional view 1300a, a source / drain connector 308, a second insulating layer 128, and a second bit line 208 are formed on the first ILD layer 1202. In some embodiments, the source / drain connector 308 and the second bit line 208 independently comprise a conductive material, such as tantalum nitride (TaN), tungsten (W), titanium nitride (TiN), ruthenium (Ru), or another BEOL-compatible conductive material. In some embodiments, the second insulating layer 128 is or comprises an insulating material, such as silicon dioxide (SiO2) or the like. In some embodiments, the second insulating layer 128 comprises the same material as the first insulating layer 124. In some embodiments, the source / drain connector 308 and the second bit line 208 are formed using damascene processes, deposition and patterning processes, or the like. In some embodiments, the second insulating layer 128 is formed using deposition processes, such as ALD, PVD, CVD, or the like. Figure 13BAs shown in the top view 1300b, in some embodiments, the source / drain connector 308 has a rectangular profile when viewed from above. In other embodiments, the source / drain connector 308 has a circular, elliptical, or other different shaped profile when viewed from above.

[0059] like Figure 14 As shown in the cross-sectional view 1400, a fourth shielding layer 1404 is formed over the second insulating layer 128 and the second bit line 208. In some embodiments, the fourth shielding layer 1404 is or includes photoresist, hard shielding, or the like. In some embodiments, the fourth shielding layer 1404 is formed using a deposition process, an immersion process, a spin coating process, a sputtering process, or the like. The fourth shielding layer 1404 is then patterned to expose the second insulating layer 128 and the second bit line 208 corresponding to the second channels that will be formed thereafter (see...). Figure 1A 132), the second dielectric (see ... Figure 4 410) and the second gate (see Figure 16 The area at position 212. In some embodiments, the fourth shielding layer 1404 is patterned using an etching process, photolithography, or the like.

[0060] After the fourth shielding layer 1404 is patterned, a fourth etching process 1402 is performed. The fourth etching process 1402 removes portions of the second insulating layer 128, the second bit line 208, and the source / drain connector 308 beneath the opening in the fourth shielding layer 1404. The fourth etching process 1402 creates a second opening 1406 extending from the second bit line 208 to the source / drain connector 308. In some embodiments, the fourth etching process 1402 is or includes one or more anisotropic dry etching processes. The fourth shielding layer 1404 is then removed.

[0061] like Figure 15 As shown in cross-sectional view 1500, a second conformal IM layer 1502, a second conformal channel 1504, a second conformal dielectric 1506, and a second conformal gate layer 1508 are formed over the second bit line 208 and the first insulating layer 124. The second conformal IM layer 1502 is configured to bond the second conformal channel 1504 to the source / drain connector 308 and the second bit line 208 to reduce memory cells (see [reference]). Figure 1A Mechanical failure of 104). In some embodiments, the second conformal IM layer 1502 is or includes a first conformal IM layer (see 104). Figure 7The conductive material can be the same as or different from that of the second conformal IM layer 128, such as titanium (Ti), tantalum (Ta), molybdenum (Mo), gallium (Ga), chromium (Cr), aluminum (Al), or the like. After deposition, a first portion 1502a extending between the source / drain connector 308 and the second bit line 208 in the second conformal IM layer 1502 interacts with oxygen atoms from the second insulating layer 128, causing the first portion 1502a to include a metal oxide, such as titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), or the like. A second portion 1502b extending directly between the second conformal channel 1504 and either the source / drain connector 308 or the second bit line 208 in the second conformal IM layer 1502 has less exposure to oxygen atoms in the second insulating layer 128 and includes a lower proportion of metal oxide than the first portion 1502a.

[0062] In some embodiments, the second conformal channel 1504 is or includes the same material or a different semiconductor material as the first channel 114, such as IG2MO (In... x Ga y Zn z MO, where M is titanium (Ti), aluminum (Al), tungsten (W), cerium (Ce), tin (Sn), zirconium (Zr), neodymium (Nd), samarium (Sm), or lutetium (Lu), and where x, y, and z are 0, 1, or between 0 and 1), IGZO, or the like. In some embodiments, the second conformal dielectric 1506 is or includes the same material as the first dielectric 112 or a different high-k dielectric (e.g., a material with a relative permittivity greater than 20), such as hafnium oxide (HfO2), hafnium zirconium oxide (HZO), or the like. In some embodiments, the second conformal gate layer 1508 is or includes the same material as the first gate 110 or a different conductive material, such as tantalum nitride (TaN), tungsten (W), titanium nitride (TiN), ruthenium (Ru), or the like.

[0063] In some embodiments, the second conformal IM layer 1502, the second conformal channel 1504, the second conformal dielectric 1506, and the second conformal gate layer 1508 are formed independently using a deposition process, such as ALD, PVD, CVD, or similar processes. In some embodiments, the second conformal IM layer 1502 has a thickness within a substantially the same range as the thickness of the first IM layer 118. In some embodiments, the second conformal channel 1504 has a thickness within a substantially the same range as the thickness of the first channel 114, and is based on differences in the channel characteristics required for writing transistors (see [link to documentation]). Figure 1A The thickness of the first channel 114 is greater than, equal to, or less than that of the first channel 114. In some embodiments, the second conformal dielectric 1506 has a thickness within approximately the same range as the first dielectric 112, and is based on the difference in dielectric properties required for writing the transistor (see [reference]). Figure 1A The thickness of the first dielectric 112 is greater than, equal to or less than 108).

[0064] For example, sectional view 1600 Figure 16 As shown, the second conformal IM layer 1502 and the second conformal channel (see...) Figure 15 1504), second conformal dielectric (see 1504), second conformal dielectric (see 1504) Figure 15 1506) and the second conformal gate layer (see 1506) Figure 15 The 1508 layer is etched to form a second channel 132, a second dielectric 410, and a second gate 212. In some cases, the combination of the second channel 132, the second dielectric 410, and the second gate 212 is also referred to as a second gate stack. The second conformal gate layer (see [link to documentation]) Figure 15 (1508) is similar to the first conformal gate layer (see 1508) Figure 7 The 708) is etched in a manner in which a sixth shielding layer (not shown) is formed and patterned to cover the second conformal gate layer corresponding to the base portion 212a of the second gate 212 (see 708). Figure 15 Part of 1508). The sixth shielding layer was subsequently removed.

[0065] After the sixth shielding layer is removed, the seventh shielding layer 1602 is formed in the second gate 212 and the second conformal dielectric (see...). Figure 15 Above 1506). In some embodiments, the seventh shielding layer 1602 is or includes photoresist, hard shielding, or similar materials. In some embodiments, the seventh shielding layer 1602 is formed using a deposition process, immersion process, spin coating process, sputtering process, or similar process. The seventh shielding layer 1602 is then patterned to cover the second dielectric 410, the second channel 132, and the third and fourth IM layers to be formed thereafter (see 1506). Figure 17 The second conformal dielectric at positions 1706 and 1708 (see 1706 and 1708) Figure 15 The seventh shielding layer 1602 is patterned using an etching process, photolithography, or similar process in some embodiments.

[0066] After the seventh shielding layer 1602 is patterned, a seventh etching process 1604 is performed. The seventh etching process 1604 removes the second conformal dielectric exposed by the patterning of the seventh shielding layer 1602 (see [link to original text]). Figure 15 1506), the second conformal channel (see ...) Figure 15 The seventh etch process 1604 exposes the second bit line 208 and the first insulating layer 124 in portions of the second conformal IM layer 1504 and the second conformal IM layer 1502. In some embodiments, the seventh etch process 1604 is or includes one or more anisotropic dry etch processes. The seventh shielding layer 1602 is then removed.

[0067] For example, sectional view 1700 Figure 17 As shown, a second portion 128c of the second insulating layer 128 is formed over the second bit line 208, the second gate 212, and the first portion 128b of the second insulating layer 128, and a second void 130 is formed between the second inner sidewall 128a and the second channel 132 of the second insulating layer 128. In some embodiments, the second portion 128c of the second insulating layer 128 is or comprises the same material as the first portion 128b of the second insulating layer 128. In some embodiments, a planarization process (e.g., chemical mechanical planarization (CMP)) is performed after the deposition of the second portion 128c, resulting in the second portion 128c of the second insulating layer 128 having a substantially flat upper surface extending directly over the second gate 212.

[0068] After the second portion 128c of the second insulating layer 128 is formed, a second gap 130 is formed between the second inner sidewall 128a and the second channel 132 of the second insulating layer 128. The second gap is similar to the first gap (see...). Figure 11A The eighth shielding layer 1704 is formed and patterned to expose a region of the second insulating layer 128 corresponding to the location of the second gap 130 to be formed thereafter. In some embodiments, the exposed region of the second insulating layer 128 (and the first gap 126 to be formed thereafter) does not extend beyond the outer wall of the source / drain connector 308 in the third direction 138 or the second direction 136 because the size of the source / drain connector 308 is selected as the etch stop of the eighth etch process 1702 that forms the second gap 130.

[0069] The eighth etching process 1702 is similar to the fourth etching process (see...). Figure 11A The eighth etching process 1702 is performed in the same manner as step 1102. In some embodiments, the eighth etching process 1702 includes one or more anisotropic dry etching steps alternating with a plurality of wet etching steps. In other embodiments, the eighth etching process 1702 includes one or more anisotropic dry etching steps followed by a plurality of wet etching steps. The eighth etching process 1702 results in the second void 130 remaining between the second inner sidewall 128a of the second insulating layer 128 and the outer sidewall of the second channel 132, and the third IM layer 1706 and the fourth IM layer 1708 remaining on the second channel 132. In some embodiments, the eighth etching process 1702 is or includes one or more anisotropic dry etching processes. The eighth etching process 1702 is then removed.

[0070] The second gap 130 extending between the second inner sidewall 128a of the second insulating layer 128 and the outer sidewall of the second channel 132 mitigates the transfer of oxygen, hydrogen, and / or other materials between the second insulating layer 128 and the second channel 132 of the write transistor 108, reducing contamination of the second channel 132 that could lead to changes in the voltage threshold and other parameters of the write transistor 108. Furthermore, the second gap 130 has a dielectric constant of approximately 1, resulting in a transistor with the second gap 130 and additional memory cells (see [link to original text]). Figure 1B The capacitive coupling between 141) is reduced.

[0071] like Figure 18 As shown in the cross-sectional view 1800, a second interlayer dielectric (ILD) layer 1802, a second via interconnect 1804, a second character line 214, and a third insulating layer 1806 are formed over the write transistor 108 and the second insulating layer 128. The second ILD layer 1802 covers the write transistor 108 and the second insulating layer 128 without filling the second gap 130 in the same manner as the first ILD layer 1202 covers the first gap 126 without filling it. In some embodiments, the second ILD layer 1802 is or comprises the same material as the first ILD layer 1202 or a different insulating material, such as silicon nitride (Si3N4) or silicon carbide (SiO2). x C y N z (where x, y, and z are approximately 1, or another ratio of silicon, carbon, and nitrogen) or the like. In some embodiments, the second ILD layer 1802 is formed using the same process as the first ILD layer 1202.

[0072] After the second ILD layer 1802 is formed, a second via interconnect 1804 is formed extending through the second ILD layer 1802 to contact the second gate 212. In some embodiments, the second via interconnect 1804 is or includes the same material as the first via interconnect 1204 or a different conductive material, such as tantalum nitride (TaN), tungsten (W), titanium nitride (TiN), ruthenium (Ru), or another BEOL-compatible conductive material. In some embodiments, the second via interconnect 1804 is formed using the same process as the first via interconnect 1204.

[0073] After the second via interconnect 1804 is formed, a second character line 214 and a third insulating layer 1806 are formed on the write transistor 108. The second character line 214 is electrically coupled to the second gate 212 through the second via interconnect 1804. In some embodiments, the second character line 214 comprises a conductive material, such as tantalum nitride (TaN), tungsten (W), titanium nitride (TiN), ruthenium (Ru), or another BEOL-compatible conductive material. In some embodiments, the third insulating layer 1806 is or comprises an insulating material, such as silicon dioxide (SiO2) or the like. In some embodiments, the third insulating layer 1806 comprises the same material as the first insulating layer 124. In some embodiments, the second character line 214 is formed using the same process as the first character line 116. In some embodiments, the third insulating layer 1806 is formed using the same process as the first insulating layer 124.

[0074] Figure 19 A flowchart 1900 illustrates a method for forming an integrated device having two vertical transistors in a memory cell, wherein the memory cell has first and second channels of the vertical transistors and first and second gaps between the inner sidewalls surrounding an insulating layer. While method 1900 is described below as a series of steps or events, it should be understood that the order of description of the steps or events should not be construed as limiting. For example, some steps may occur in a different order and / or simultaneously with other steps or events besides those described herein. Furthermore, not all of the described steps may be necessary to implement one or more aspects or embodiments described herein. Additionally, one or more steps described herein may be performed in one or more separate steps and / or stages.

[0075] In 1902, the first character line was formed on the base. Figures 5A to 5B The description corresponds to the sectional view 500a and the top view 500b in step 1902.

[0076] In 1904, the first insulating layer was formed on top of the first character line. Figures 5A to 5B The description corresponds to the sectional view 500a and the top view 500b in step 1904.

[0077] In 1906, the first line was formed on top of the first insulating layer. Figures 5A to 5B The description corresponds to the sectional view 500a and the top view 500b in step 1906.

[0078] In 1908, the first opening was etched through the first character line and into the first character line. Figures 6A to 6B The description corresponds to the sectional view 600a and the top view 600b in step 1908.

[0079] In 1910, a first transistor gate stack was formed, extending from the first bit line to the first character line and including a first channel, a first dielectric, and a first gate. Figures 7 to 9 The illustrations are cross-sectional views 700, 800, and 900 corresponding to some embodiments of step 1910.

[0080] In 1912, a first insulating layer surrounding the first transistor gate stack was etched to form a first gap between the inner wall of the first insulating layer and the first transistor gate stack. Figures 11A to 11C The illustrations include sectional views 1100a and top views 1100b and 1100c corresponding to some embodiments of step 1912.

[0081] In 1914, an interlayer dielectric was formed on top of the first insulating layer, covering the first void. Figure 12 This describes a cross-sectional view 1200 corresponding to some embodiments of step 1914.

[0082] In 1916, a via and source / drain connector were formed on the first gate and electrically coupled to the first gate. Figure 12 , 13A Sectional views 1200, 1300a and top view 1300b, corresponding to some embodiments of step 1916, are described in 13B.

[0083] In 1918, a second insulating layer and a second bit line were formed on top of the first insulating layer and the first transistor gate stack. Figure 13A and 13B The illustrations include a cross-sectional view 1300a and a top view 1300b corresponding to some embodiments of step 1918.

[0084] In 1920, the second opening was etched through the second bit line and into the source / drain connector. Figure 14 This describes a cross-sectional view 1400 corresponding to some embodiments of step 1920.

[0085] In 1922, a second transistor gate stack was formed, extending from the second bit line to the source / drain junction and including a second channel, a second dielectric, and a second gate. Figures 15-16 The illustrations are cross-sectional views 1500 and 1600 corresponding to some embodiments of step 1922.

[0086] In 1924, a second insulating layer surrounding the second transistor gate stack was etched to form a second gap between the inner wall of the second insulating layer and the second transistor gate stack. Figure 17 This describes a cross-sectional view 1700 corresponding to some embodiments of step 1924.

[0087] In 1926, a second interlayer dielectric was formed on top of the second insulating layer, covering the second void. Figure 18This describes a cross-sectional view 1800 corresponding to some embodiments of step 1926.

[0088] In 1928, a through-hole and a second character line were formed on the second gate and electrically coupled to the second gate. Figure 18 This describes a cross-sectional view 1800 corresponding to some embodiments of step 1928.

[0089] Therefore, this disclosure describes a modified 2T0C memory cell structure with an air gap protection channel.

[0090] Therefore, in some embodiments, this disclosure relates to an integrated device comprising: a first transistor covering a substrate and having a first gate, a first channel having an inner sidewall surrounding the first gate, and a first dielectric material separating the first channel from the first gate; a second transistor covering a readout transistor and having a second gate, a second channel having an inner sidewall surrounding the second gate, and a second dielectric material separating the second channel from the second gate; a via coupling the first gate to the second channel; a first insulating layer surrounding the first transistor and having an inner sidewall spaced from the first transistor through a first gap; and a second insulating layer surrounding the second transistor and having an inner sidewall spaced from the second transistor through a second gap.

[0091] In some embodiments, the integrated device further includes: a first character line extending below a first bottom surface of the first channel and electrically coupled to the first bottom surface; a first bit line extending above the first character line and surrounding a first sleeve portion of the first channel; a second character line extending directly above the second gate and electrically coupled to the second gate; and a second bit line extending above the first bit line and surrounding a second sleeve portion of the second channel.

[0092] In some embodiments, the first gap extends from the upper surface of the first character line to above the upper surface of the first bit line.

[0093] In some embodiments, the intermetallic layer separates the first bit line from the first sleeve portion of the first channel and separates the first character line from the first bottom surface of the first channel, wherein the outer surface of the first sleeve portion between the first bit line and the first character line is exposed to the first gap.

[0094] In some embodiments, the first gap extends above the first bit line and exposes the outermost surface of the first channel; and wherein the second gap extends above the second bit line and exposes the outermost surface of the second channel.

[0095] In some embodiments, when viewed from a first cross-sectional view, the first gap is separated from the second gap in a first direction, and the first gap has a first thickness measured in a second direction perpendicular to the first direction; wherein, when viewed from a second cross-sectional view, the first gap has a second thickness measured in a third direction perpendicular to both the first and second directions; and wherein the second thickness is greater than the first thickness by more than 10%.

[0096] In some embodiments, the integrated device further includes an interlayer dielectric (ILD) layer extending around the via and between the first void and the second void.

[0097] In some embodiments, the first transistor further includes: a substrate portion including the outermost wall of the first gate, the first dielectric, and the first channel, and the surface of the first gate, the first dielectric, and the first channel furthest from the substrate; a bottom portion including the surface of the first gate, the first dielectric, and the first channel closest to the substrate; and a sleeve portion extending between the substrate portion and the bottom portion, the sleeve portion having a longest dimension in a first direction substantially perpendicular to the surface of the first gate furthest from the substrate.

[0098] In some embodiments, the integrated device further includes: a first character line, wherein the surface of the first gate, the first dielectric, and the first channel closest to the substrate is directly located between the inner sidewalls of the first character line; and a first line, wherein the upper surface of the first line extends upward beyond the outermost sidewalls of the first gate, the first dielectric, and the first channel in a second direction perpendicular to the first direction and in a third direction perpendicular to the first direction and the second direction.

[0099] In other embodiments, this disclosure relates to a method of forming an integrated device, comprising: forming a first character line on a substrate, the first character line being separated from the substrate in a first direction and extending in a second direction perpendicular to the first direction; forming a first insulating layer covering the first character line; forming a first first line on the first insulating layer, separated from the first character line through the first insulating layer in the first direction, the first first line extending upward in a third direction perpendicular to the first and second directions; etching through the first first line and into a first opening of the first character line; continuously forming a first channel, a first dielectric, and a first gate in the first opening to fill the first opening; etching around the first character line... A portion of the first insulating layer of a channel creates a first gap extending from the outermost wall of the first channel to the first bit line; an interlayer dielectric is formed on the first insulating layer to cover the first gap; a via and a source / drain connector are formed on the first gate and electrically coupled to the first gate; a second bit line is formed extending on the source / drain connector and spaced from the source / drain connector; a second opening is etched through the second bit line and exposes the source / drain connector; a second channel, a second dielectric, and a second gate are continuously formed in the second opening to fill the second opening; and a second character line is formed extending on the second gate and electrically coupled to the second gate.

[0100] In some embodiments, the method further includes: forming a second insulating layer over the source / drain connector, wherein after the second bit line is formed, the second insulating layer separates the source / drain connector from the second bit line; and etching a portion of the second insulating layer surrounding the first channel to create a second gap extending between the outermost wall of the second channel and the source / drain connector.

[0101] In some embodiments, etching a portion of the first insulating layer surrounding the first channel further includes: forming a shielding layer over the first insulating layer; patterning the shielding layer to form an opening directly over the first gate in the shielding layer; and performing a plurality of alternating dry and wet etching processes to remove portions of the first insulating layer above the first character line and below the first character line.

[0102] In some embodiments, the method further includes: forming a first conformal intermetallic layer within the first opening prior to forming the first channel, wherein etching a portion of the first insulating layer surrounding the first channel further exposes a portion of the first conformal intermetallic layer; and removing a portion of the first conformal intermetallic layer between the first bit line and the first character line.

[0103] In some embodiments, after the first channel, the first dielectric and the first gate are sequentially formed in the first opening, the upper surface of the first bit line extends beyond the outermost wall of the first channel in the first direction and the second direction.

[0104] In some embodiments, the first gap separates the inner sidewall of the first insulating layer from the first channel.

[0105] In other embodiments, this disclosure relates to a method of forming an integrated device, comprising: forming a first character line on a substrate; forming a first insulating layer on the first character line; forming a first bit line on the first insulating layer; forming a first transistor gate stack extending from the first bit line to the first character line, including a first channel, a first dielectric, and a first gate; etching the first insulating layer surrounding the first transistor gate stack to form a first gap between the inner sidewall of the first insulating layer and the first transistor gate stack; forming a second insulating layer on the first insulating layer and the first transistor gate stack; forming a second bit line on the second insulating layer; forming a second transistor gate stack extending between the second bit line and the first gate, including a second channel, a second dielectric, and a second gate; etching the second insulating layer surrounding the second transistor gate stack to form a second gap between the inner sidewall of the second insulating layer and the second transistor gate stack; and forming a second character line electrically coupled to a second gate.

[0106] In some embodiments, the first channel has a first thickness, and the second channel has a second thickness that is less than the first thickness.

[0107] In some embodiments, the first and second character lines are separated in a first direction and extend in a second direction perpendicular to the first direction; wherein the first and second character lines extend upward in a third direction perpendicular to the first and second directions; wherein etching the first insulating layer stacked around the gate of the first transistor to form the first gap results in the first gap having a first thickness in the first direction and a second thickness in the second direction, the second thickness being less than the first thickness.

[0108] In some embodiments, the method further includes etching a first opening through the first bit line and exposing the first character line before forming the first transistor gate stack, wherein after etching the first opening, the first bit line has an inner sidewall extending around the first opening in a continuous, uninterrupted loop.

[0109] In some embodiments, after the second transistor gate stack is formed, an axis extending substantially perpendicular to the substrate surface extends through the first gate and the second gate.

[0110] The foregoing has outlined the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. An integrated device, characterized in that, include: A first transistor covers a substrate and has a first gate, a first channel having an inner sidewall surrounding the first gate, and a first dielectric separating the first channel from the first gate. The second transistor covers the first transistor and has a second gate, a second channel having an inner sidewall surrounding the second gate, and a second dielectric separating the second channel from the second gate; Through-hole, electrically coupling the first gate to the second channel; A first insulating layer surrounds the first transistor and has an inner sidewall spaced from the first transistor through a first gap; as well as A second insulating layer surrounds the second transistor and has an inner sidewall that is spaced from the second transistor through a second gap.

2. The integrated device according to claim 1, characterized in that, Also includes: The first character line extends below the first bottom surface of the first channel and is electrically coupled to the first bottom surface; The first line extends above the first character line and surrounds the first sleeve portion of the first channel; The second character line extends directly above the second gate and is electrically coupled to the second gate; as well as The second position line extends above the first position line and surrounds the second sleeve portion of the second channel.

3. The integrated device according to claim 1, characterized in that, When viewed from the first cross-sectional view, the first gap is separated from the second gap in a first direction, and the first gap has a first thickness measured in a second direction perpendicular to the first direction; When viewed from the second cross-sectional view, the first gap has a second thickness measured in a third direction perpendicular to both the first and second directions; and The second thickness is more than 10% greater than the first thickness.

4. The integrated device according to claim 1, characterized in that, It also includes an interlayer dielectric layer that surrounds the via and extends between the first gap and the second gap.

5. The integrated device according to claim 1, characterized in that, The first transistor further includes: The substrate portion includes the outermost wall of the first gate, the first dielectric, and the first channel, as well as the surfaces of the first gate, the first dielectric, and the first channel that are furthest from the substrate; The bottom portion includes the first gate, the first dielectric, and the surface of the first channel closest to the substrate; and The sleeve portion extends between the base portion and the bottom portion, and the sleeve portion has the longest dimension in a first direction that is substantially perpendicular to the surface of the first gate furthest from the base.

6. A method for forming an integrated device, characterized in that, include: A first character line is formed above the substrate, the first character line being separated from the substrate in a first direction and extending in a second direction perpendicular to the first direction; A first insulating layer is formed to cover the first character line; A first bit line is formed above the first insulating layer, and is separated from the first character line in the first direction through the first insulating layer. The first bit line extends upward in a third direction that is substantially perpendicular to the first direction and the second direction. The first opening is etched through the first bit line and into the first character line; A first channel, a first dielectric, and a first gate are formed in the first opening to fill the first opening; Etching a portion of the first insulating layer surrounding the first channel creates a first gap extending from the outermost wall of the first channel to the first character line; An interlayer dielectric is formed above the first insulating layer to cover the first gap; A via and a source / drain connector are formed above the first gate and electrically coupled thereto; A second bit line is formed that extends above and is spaced from the source / drain connector; Etch a second opening through the second bit line and expose the source / drain connection; A second channel, a second dielectric, and a second gate are formed in the second opening, and the second opening is filled. as well as A second character line is formed that extends above the second gate and is electrically coupled to it.

7. The method according to claim 6, characterized in that, Etching the portion of the first insulating layer surrounding the first channel further includes: A shielding layer is formed above the first insulating layer; The shielding layer is patterned to form an opening directly above the first gate in the shielding layer; and Multiple alternating dry and wet etching processes are performed to remove portions of the first insulating layer above the first character line and below the first character line.

8. A method for forming an integrated device, characterized in that, include: The first character line is formed above the base; A first insulating layer is formed above the line of the first character; A first line is formed above the first insulating layer; A first transistor gate stack is formed extending from the first bit line to the first character line, including a first channel, a first dielectric, and a first gate; Etch the first insulating layer surrounding the first transistor gate stack to form a first gap between the inner sidewall of the first insulating layer and the first transistor gate stack; A second insulating layer is formed above the first insulating layer and the first transistor gate stack; A second bit line is formed above the second insulating layer; A second transistor gate stack is formed extending between the second bit line and the first gate, including a second channel, a second dielectric, and a second gate; Etch the second insulating layer surrounding the second transistor gate stack to form a second gap between the inner sidewall of the second insulating layer and the second transistor gate stack; as well as A second character line is formed that is electrically coupled to the second gate.

9. The method according to claim 8, characterized in that, The first channel has a first thickness, and the second channel has a second thickness that is less than the first thickness.

10. The method according to claim 8, characterized in that, After the second transistor gate stack is formed, an axis extending substantially perpendicular to the substrate surface extends through the first gate and the second gate.

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