Semiconductor device including bit line and gate structures

Abstract

A semiconductor device includes a substrate including a cell region and a peripheral region, an active pattern on the cell region of the substrate, a bit line extending in a direction on the active pattern, and a peripheral gate structure on the peripheral region. The bit line includes a first conductive pattern connected to the active pattern and a first metal pattern on the first conductive pattern. The peripheral gate structure includes a peripheral gate dielectric layer on the peripheral region of the substrate, a peripheral conductive pattern on the peripheral gate dielectric layer, and a peripheral metal pattern on the peripheral conductive pattern. A thickness of the peripheral metal pattern is greater than a thickness of the first metal pattern.

Description

Cross-reference to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2025-0054751, filed on April 25, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices, and more particularly, to semiconductor devices including bit lines on cell regions and peripheral gate structures on peripheral regions. Background Technology

[0003] Due to their small size, versatility, and / or low-cost manufacturing, semiconductor devices are considered essential components in the electronics industry. Semiconductor devices are categorized into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices that include both memory and logic elements.

[0004] With the latest trend towards high speed and low power consumption in electronic devices, semiconductor devices within these devices also require high operating speeds and / or low operating voltages. To meet this requirement, it is necessary to increase the integration density of semiconductor devices. However, as the integration density of semiconductor devices increases, they may suffer from electrical characteristic degradation and low production yield. Therefore, many studies are underway to improve the electrical characteristics and production yield of semiconductor devices. Summary of the Invention

[0005] The embodiments provide semiconductor devices capable of improving electrical characteristics.

[0006] According to an embodiment, a semiconductor device may include: a substrate including a cell region and a peripheral region; an active pattern located on the cell region of the substrate; a bit line extending along a direction on the active pattern; and a peripheral gate structure located on the peripheral region, wherein the bit line may include a first conductive pattern connected to the active pattern and a first metal pattern located on the first conductive pattern, wherein the peripheral gate structure may include a peripheral gate dielectric layer located on the peripheral region of the substrate, a peripheral conductive pattern located on the peripheral gate dielectric layer, and a peripheral metal pattern located on the peripheral conductive pattern, and wherein the thickness of the peripheral metal pattern may be greater than the thickness of the first metal pattern.

[0007] According to an embodiment, a semiconductor device may include: a substrate including a cell region and a peripheral region; an active pattern located on the cell region of the substrate; a word line extending across the active pattern along a first direction; a bit line extending on the word line along a second direction intersecting the first direction; a peripheral gate structure located on the peripheral region; and a pad layer covering the sidewalls and upper surface of the peripheral gate structure, wherein the peripheral gate structure may include a peripheral gate dielectric layer located on the peripheral region of the substrate, a peripheral gate electrode located on the peripheral gate dielectric layer, a peripheral capping pattern located on the peripheral gate electrode, and a buffer pattern located between the peripheral capping pattern and the peripheral gate electrode.

[0008] According to an embodiment, a semiconductor device may include: a substrate including a cell region and a peripheral region; an active pattern located on the cell region of the substrate; a word line extending across the active pattern along a first direction; a bit line structure extending on the word line along a second direction intersecting the first direction; a bit line structure including a bit line and a bit line capping pattern located on the bit line; a node contact connected to the active pattern; a landing pad connected to the node contact; and a peripheral gate structure located on the peripheral region, wherein the bit line may include a first conductive pattern extending on the active pattern along the second direction and a first metal pattern located on the first conductive pattern, wherein the peripheral gate structure may include a peripheral gate dielectric layer located on the peripheral region of the substrate, a peripheral conductive pattern located on the peripheral gate dielectric layer, a peripheral metal pattern located on the peripheral conductive pattern, a peripheral capping pattern located on the peripheral metal pattern, and a buffer pattern located between the peripheral capping pattern and the peripheral metal pattern, and wherein the thickness of the peripheral metal pattern may be greater than the thickness of the first metal pattern.

[0009] According to an embodiment, a method of manufacturing a semiconductor device may include: providing a substrate including a cell region and a peripheral region; forming a first device isolation layer defining an active pattern on the cell region; forming a peripheral gate dielectric layer that at least partially covers the peripheral region of the substrate; forming a peripheral conductive layer on the peripheral gate dielectric layer; forming a first preliminary conductive layer on the first device isolation layer and the active pattern; forming a metal layer covering the first preliminary conductive layer and the peripheral gate dielectric layer; forming a mask pattern that partially covers the metal layer on the peripheral region; using the mask pattern as an etching mask to etch a portion of the metal layer to form a first metal layer and a second metal layer connected to the first metal layer and having a different thickness than the first metal layer; patterning the peripheral conductive layer and the second metal layer to form a peripheral gate electrode on the peripheral region; and patterning the first preliminary conductive layer and the first metal layer to form a bit line connected to the active pattern.

[0010] According to some embodiments, forming a first preliminary conductive layer may include partially etching an active pattern to form a recessed region, and depositing a conductive material to fill the recessed region.

[0011] According to some embodiments, the thickness of the first metal layer may be less than the thickness of the second metal layer.

[0012] According to some embodiments, the first metal layer may not expose the first preliminary conductive layer on the cell region. Attached Figure Description

[0013] Figure 1 This is a plan view of a semiconductor device according to some embodiments.

[0014] Figure 2 yes Figure 1 A magnified view of part "E1".

[0015] Figure 3A It is along Figure 2 The cross-sectional view taken by line A-A' in the diagram.

[0016] Figure 3B It is along Figure 2 The cross-sectional view taken by line B-B' in the diagram.

[0017] Figures 4 to 11 This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments. Specific Implementation

[0018] The embodiments described herein are non-limiting examples; therefore, this disclosure is not limited thereto and can be implemented in various other forms. The semiconductor device and its manufacturing method according to embodiments will now be described in detail with reference to the accompanying drawings.

[0019] Figure 1 This is a plan view of a semiconductor device according to some embodiments. Figure 2 yes Figure 1 A magnified view of part "E1". Figure 3A It is along Figure 2 The cross-sectional view taken by line A-A' in the diagram. Figure 3B It is along Figure 2 The cross-sectional view taken by line B-B' in the diagram.

[0020] Reference Figure 1 , Figure 2 , Figure 3A and Figure 3BThe semiconductor device may include a substrate 100. In some embodiments, the substrate 100 may be a semiconductor substrate. For example, the substrate 100 may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium phosphide (GaP), or gallium arsenide (GaAs). In some embodiments, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. The substrate 100 may have a plate shape extending along a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may be horizontal directions that are orthogonal to each other.

[0021] The substrate 100 may include a cell region CR and a peripheral region PR. The peripheral region PR may surround the cell region CR.

[0022] An active pattern AP can be disposed on a cell region CR of substrate 100. The upper portion of the cell region CR of substrate 100 protruding along a third direction D3 can be defined as the active pattern AP. The third direction D3 can intersect with the first direction D1 and the second direction D2. For example, the third direction D3 can be a vertical direction orthogonal to the first direction D1 and the second direction D2. For example, the third direction D3 can be a direction perpendicular to the bottom surface (or lower surface) of substrate 100. The active patterns AP can be spaced apart from each other.

[0023] A first device isolation layer STI1 can be configured to define the active pattern AP. The first device isolation layer STI1 can be disposed on the cell region CR of the substrate 100. Each active pattern AP can be surrounded by the first device isolation layer STI1.

[0024] The second device isolation layer STI2 can be disposed on the peripheral region PR of the substrate 100. The second device isolation layer STI2 can surround the cell region CR of the substrate 100. In some embodiments, the second device isolation layer STI2 and the first device isolation layer STI1 can have an integral structure that is connected to each other without boundaries.

[0025] The first device isolation layer STI1 may include an insulating material. For example, the first device isolation layer STI1 may include at least one of silicon oxide and silicon nitride. The second device isolation layer STI2 may include a first isolation insulating layer (also referred to as a first insulating material) 11, a second isolation insulating layer (also referred to as a second insulating material) 12 located on the first isolation insulating layer 11, and a third isolation insulating layer (also referred to as a second insulating material) 13 located on the second isolation insulating layer 12. For example, the first isolation insulating layer 11 may include silicon oxide, the second isolation insulating layer 12 may include silicon nitride, and the third isolation insulating layer 13 may include silicon oxide.

[0026] A word line WL extending along a first direction D1 can be provided. The word line WL can be arranged along a second direction D2. The word line WL can be disposed on the cell region CR of the substrate 100. The word line WL can be disposed on the first device isolation layer STI1 and the active pattern AP. The word line WL can be a gate structure embedded in the active pattern AP and the first device isolation layer STI1. The active pattern AP can include a sludge region. The cell transistor can be defined by the word line WL and the active pattern AP.

[0027] Each word line WL may include a gate insulating layer 152 on the active pattern AP, a gate electrode 151 on the gate insulating layer 152, and a gate capping layer 153 on the gate electrode 151. The gate insulating layer 152 and the gate capping layer 153 may include insulating materials. For example, the gate insulating layer 152 may include silicon oxide, and the gate capping layer 153 may include silicon nitride (SiN). x The gate electrode 151 may include a conductive material.

[0028] The lower insulating layer 110 may be disposed on the first device isolation layer STI1 and the second device isolation layer STI2. The lower insulating layer 110 may include an insulating material. For example, the lower insulating layer 110 may include materials comprising silicon oxide and silicon nitride (SiN). x (Multiple layers)

[0029] Bit line structures 130 extending along a second direction D2 can be disposed on the active pattern AP and the lower insulating layer 110. Bit line structures 130 can be disposed on the cell region CR of the substrate 100. Bit line structures 130 can be spaced apart from each other along a first direction D1. Bit line structures 130 can be disposed on the lower insulating layer 110 and the active pattern AP. Bit line structures 130 can be connected (e.g., electrically connected) to the active pattern AP.

[0030] Bit line structure 130 may include bit line BL and bit line capping pattern 135. Bit line BL may include a first conductive pattern 131, a first barrier pattern 132 and a first metallic pattern 133 stacked sequentially on top of each other.

[0031] The first conductive pattern 131 may contact the active pattern AP. For example, a bit line BL can be connected (e.g., electrically connected) to the active pattern AP via the first conductive pattern 131. The first conductive pattern 131 may be disposed in a recessed region RS formed on the top surface (or upper surface) of the substrate 100 and exposing the active pattern AP. The recessed region RS may have an elliptical shape in a plan view, and the width of the recessed region RS in the minor axis direction may be greater than the width of the bit line structure 130. For example, the first conductive pattern 131 may comprise polysilicon.

[0032] A first barrier pattern 132 may be disposed on a first conductive pattern 131. The first barrier pattern 132 may include titanium (Ti) and / or titanium nitride (TiN). In some embodiments, a silicide pattern may be disposed between the first barrier pattern 132 and the first conductive pattern 131.

[0033] A first metal pattern 133 may be disposed on a first barrier pattern 132. The first metal pattern 133 may extend along a second direction D2 on the first barrier pattern 132. The first metal pattern 133 may include a metal. For example, the first metal pattern 133 may include at least one of tungsten (W) and cobalt (Co).

[0034] Bit line capping pattern 135 may be disposed on bit line BL. Bit line capping pattern 135 may cover the top surface (or upper surface) of first metal pattern 133. Bit line capping pattern 135 may include a first capping pattern 136, a second capping pattern 137, and a third capping pattern 138 stacked sequentially along a third direction D3. For example, each of the first to third capping patterns 136, 137, and 138 may include silicon oxide and silicon nitride (SiN). x At least one of the following.

[0035] Bit line spacer 139 may fill the remaining portion of the recessed region RS. For example, bit line spacer 139 may cover the sidewalls of the first conductive pattern 131, the sidewalls of the first barrier pattern 132, the sidewalls of the first metallic pattern 133, and the sidewalls of the first capping pattern 136. Bit line spacer 139 may include an insulating material. In some embodiments, bit line spacer 139 may include multiple insulating layers.

[0036] Node contacts NC can be provided. Node contacts NC can be disposed on the cell regions CR of the substrate 100. Node contacts NC can be disposed on the active pattern AP. Node contacts NC can be connected (e.g., electrically connected) to the active pattern AP. Node contacts NC can be disposed between bit line structures 130. Node contacts NC can be disposed on the sidewalls of the bit line structure 130. Node contacts NC may include a conductive material. For example, node contacts NC may include polysilicon.

[0037] A landing pad LP can be provided. The landing pad LP can be provided on the node contact NC. The landing pad LP can be connected (e.g., electrically connected) to the node contact NC. The landing pad LP can include a conductive material. For example, the landing pad LP can include metal. In some embodiments, a metal silicide layer can be provided between the node contact NC and the landing pad LP. In some embodiments, a barrier layer can be provided between the node contact NC and the landing pad LP.

[0038] An upper insulating pattern 190 may be disposed between landing pads LP. The upper insulating pattern 190 may surround the sidewalls of the landing pads LP. The upper insulating pattern 190 may fill the space between the landing pads LP. For example, the upper insulating pattern 190 may include silicon oxide and silicon nitride (SiN). x At least one of the following.

[0039] An insulating barrier 170 may be provided. The insulating barrier 170 may be provided on the gate capping layer 153 of the word line WL. The insulating barrier 170 may be provided between node contacts NC that are adjacent to each other along the second direction D2. The insulating barrier 170 may be provided between bit line structures 130 that are adjacent to each other along the first direction D1. The insulating barrier 170 may include an insulating material.

[0040] A data storage pattern DSP can be configured. The data storage pattern DSP can be connected (e.g., electrically connected) to an active pattern AP via landing pads (LP) and node contacts (NC). In some embodiments, the data storage pattern DSP can be a capacitor including a bottom electrode, a dielectric layer, and a top electrode. For example, a semiconductor device including a data storage pattern DSP can be dynamic random access memory (DRAM). In some embodiments, the data storage pattern DSP can include a magnetic tunnel junction pattern. For example, a semiconductor device including a data storage pattern DSP can be magnetic random access memory (MRAM). In some embodiments, the data storage pattern DSP can include a phase change material or a variable resistance material. For example, a semiconductor device including a data storage pattern DSP can be phase change random access memory (PRAM) or resistive random access memory (ReRAM). In some embodiments, the data storage pattern DSP can include various structures and / or materials capable of storing data.

[0041] A dummy line structure 140 can be provided. The dummy line structure 140 can be provided on the peripheral region PR of the substrate 100. The dummy line structure 140 can extend along the second direction D2. The dummy line structure 140 can be provided between the bit line structure 130 and the peripheral gate structure 200 described below. The dummy line structure 140 can be horizontally spaced from the bit line structure 130 and the peripheral gate structure 200.

[0042] The dummy line structure 140 may include a dummy line DL and a dummy capping pattern 146 located on the lower insulating layer 110. The dummy line DL may include a second conductive pattern 141, a second barrier pattern 142, and a second metal pattern 143. The second conductive pattern 141, the second barrier pattern 142, and the second metal pattern 143 may be sequentially stacked on the lower insulating layer 110 along a third direction D3.

[0043] The second conductive pattern 141 and the first conductive pattern 131 may comprise the same material. The second barrier pattern 142 and the first barrier pattern 132 may comprise the same material. The second metal pattern 143 and the first metal pattern 133 may comprise the same metal. For example, the second conductive pattern 141 may comprise polycrystalline silicon. For example, the second barrier pattern 142 may comprise titanium (Ti) and / or titanium nitride (TiN). For example, the second metal pattern 143 may comprise at least one of tungsten (W) and cobalt (Co). The dummy capping pattern 146 may comprise an insulating material. For example, the dummy capping pattern 146 may comprise silicon oxide and silicon nitride (SiN). x At least one of the following.

[0044] The peripheral gate structure 200 may be disposed on the peripheral region PR of the substrate 100. In some embodiments, the peripheral gate structure 200 may be used as a sub-word line driver or as the gate of a transistor included in a sense amplifier.

[0045] The peripheral gate structure 200 may include a peripheral gate dielectric layer 210, a peripheral gate electrode 230, a buffer pattern 240, and a peripheral capping pattern 250. The peripheral gate dielectric layer 210 may be disposed on the peripheral region PR of the substrate 100. The peripheral gate dielectric layer 210 may include a peripheral insulating layer 211 covering the top surface (or upper surface) of the substrate 100 and a high-dielectric layer 213 located on the peripheral insulating layer 211. For example, the peripheral insulating layer 211 may include silicon oxide, and the high-dielectric layer 213 may include at least one of hafnium oxide, zirconium oxide, aluminum oxide, and lanthanum oxide.

[0046] A peripheral gate electrode 230 may be disposed on a peripheral gate dielectric layer 210. The peripheral gate electrode 230 may include a peripheral conductive pattern 231, a peripheral barrier pattern 232, and a peripheral metal pattern 233. The peripheral conductive pattern 231 may contact the top surface (or upper surface) of the high dielectric layer 213. The peripheral conductive pattern 231 may include, for example, doped polysilicon. The peripheral barrier pattern 232 may be disposed on the peripheral conductive pattern 231. The peripheral barrier pattern 232 may cover the top surface (or upper surface) of the peripheral conductive pattern 231. For example, the peripheral barrier pattern 232 may include titanium (Ti) and / or titanium nitride (TiN). The peripheral metal pattern 233 may cover the top surface (or upper surface) of the peripheral barrier pattern 232. For example, the peripheral metal pattern 233 may include the same metal as the first metal pattern 133, and may include at least one of tungsten (W) and cobalt (Co).

[0047] A buffer pattern 240 may be disposed on the peripheral gate electrode 230. For example, the buffer pattern 240 may be disposed between the peripheral gate electrode 230 and the peripheral capping pattern 250 described below. The buffer pattern 240 may contact and cover the top surface (or upper surface) of the peripheral gate electrode 230. For example, the buffer pattern 240 may comprise silicon nitride (SiN). x ).

[0048] The bottom surface (or lower surface) of buffer pattern 240 may be located at a level higher than the top surface (or upper surface) of dummy line DL or the top surface (or upper surface) of second metal pattern 143. The bottom surface of buffer pattern 240 may be located at a level higher than the top surface (or upper surface) of bit line BL. The top surface (or upper surface) of buffer pattern 240 may be located at a level lower than the top surface (or upper surface) of dummy capping pattern 146. The top surface of buffer pattern 240 may be located at a level lower than the top surface (or upper surface) of bit line capping pattern 135.

[0049] A peripheral capping pattern 250 can be disposed on a buffer pattern 240. The peripheral capping pattern 250 can cover the top surface of the buffer pattern 240. The peripheral capping pattern 250 can include, for example, silicon oxide and silicon nitride (SiN). x At least one of the following.

[0050] The peripheral metal pattern 233 of the peripheral gate electrode 230 may have a first thickness T1, and the first metal pattern 133 of the bit line BL may have a second thickness T2. The first thickness T1 of the peripheral metal pattern 233 may be referred to as the length of the peripheral metal pattern 233 in the third direction D3. The second thickness T2 of the first metal pattern 133 may be referred to as the length of the first metal pattern 133 in the third direction D3. The first thickness T1 of the peripheral metal pattern 233 may be greater than the second thickness T2 of the first metal pattern 133.

[0051] The top surface (or upper surface) of the peripheral metal pattern 233 may be located at a higher level than the top surface (or upper surface) of the first metal pattern 133. For example, the distance between the top surface of the peripheral metal pattern 233 and the bottom surface of the substrate 100 may be greater than the distance between the top surface of the first metal pattern 133 and the bottom surface of the substrate 100.

[0052] The second metal pattern 143 of the dummy line DL may have a third thickness T3. The third thickness T3 of the second metal pattern 143 may be referred to as the length of the second metal pattern 143 in the third direction D3. The third thickness T3 of the second metal pattern 143 may be less than the first thickness T1 of the outer metal pattern 233. The third thickness T3 of the second metal pattern 143 may be substantially the same as the second thickness T2 of the first metal pattern 133.

[0053] The top surface (or upper surface) of the second metal pattern 143 may be substantially coplanar with the top surface of the first metal pattern 133. For example, the distance between the top surface of the second metal pattern 143 and the bottom surface of the substrate 100 may be substantially the same as the distance between the top surface of the first metal pattern 133 and the bottom surface of the substrate 100.

[0054] The top surface (or upper surface) of the peripheral gate structure 200 may be coplanar with the top surface of the dummy line structure 140. For example, the top surface (or upper surface) of the peripheral capping pattern 250 may be coplanar with the top surface (or upper surface) of the dummy capping pattern 146. The thickness of the dummy capping pattern 146 may be greater than the thickness of the peripheral capping pattern 250.

[0055] According to an embodiment, since the second thickness T2 of the first metal pattern 133 is formed to be smaller, the parasitic capacitance of the bit line BL can be reduced. Therefore, compared to the parasitic capacitance of the bit line BL, the capacitance of the data storage pattern DSP can be increased. As a result, the sensing margin of the semiconductor device can be improved.

[0056] Because the first thickness T1 of the peripheral metal pattern 233 is formed to be relatively large, the resistance of the peripheral metal pattern 233 can be reduced. Therefore, the signal transmission speed to the peripheral gate structure 200 can be improved. In addition, a semiconductor device with improved electrical characteristics can be provided.

[0057] A pad layer 181 may be disposed on the peripheral region PR of the substrate 100. The pad layer 181 may be disposed on the dummy line structure 140, the peripheral gate structure 200, and the peripheral spacer 182. The pad layer 181 may cover the sidewalls and top surface (or upper surface) of the dummy line structure 140, and the sidewalls and top surface (or upper surface) of the peripheral gate structure 200. The pad layer 181 may include an insulating material and may include, for example, silicon oxide and silicon nitride (SiN). x At least one of the following.

[0058] A peripheral spacer 182 can be disposed on the peripheral region PR of the substrate 100. The peripheral spacer 182 can be disposed between the pad layer 181 and the peripheral gate structure 200, and between the pad layer 181 and the dummy line structure 140. The peripheral spacer 182 can be disposed on the sidewalls of the dummy line structure 140 and the sidewalls of the peripheral gate structure 200. The peripheral spacer 182 can cover the sidewalls of the dummy line DL and the sidewalls of the dummy capping pattern 146. The peripheral spacer 182 can cover the sidewalls of the peripheral gate dielectric layer 210, the sidewalls of the peripheral gate electrode 230, the sidewalls of the buffer pattern 240, and the sidewalls of the peripheral capping pattern 250. The peripheral spacer 182 may include an insulating material and may include, for example, silicon oxide and silicon nitride (SiN). x At least one of the following.

[0059] An insulating filler layer 183 may be disposed between the dummy line structure 140 and the peripheral gate structure 200. The insulating filler layer 183 may fill the space between the dummy line structure 140 and the peripheral gate structure 200 on the pad layer 181. The insulating filler layer 183 may include an insulating material and may include, for example, silicon oxide and silicon nitride (SiN). x At least one of the following.

[0060] An interlayer insulating layer 185 may be disposed on the pad layer 181 and the filler insulating layer 183. The interlayer insulating layer 185 may cover the top surface (or upper surface) of the pad layer 181 and the top surface (or upper surface) of the filler insulating layer 183. The top surface (or upper surface) of the interlayer insulating layer 185 may be substantially coplanar with the top surface (or upper surface) of the bit line capping pattern 135. For example, the interlayer insulating layer 185 may comprise silicon oxide and silicon nitride (SiN). x At least one of the following.

[0061] The conductive structure 195 may be disposed on the interlayer insulating layer 185. The conductive structure 195 may be disposed on the peripheral region PR of the substrate 100. The conductive structure 195 may include a conductive material. For example, the conductive structure 195 may include a metal.

[0062] At least one of the conductive structures 195 may include a protrusion 195p connected to the peripheral gate structure 200. The protrusion 195p may penetrate the interlayer insulating layer 185 and the pad layer 181 to connect (e.g., electrically connect) to the peripheral gate electrode 230 of the peripheral gate structure 200. The protrusion 195p may penetrate the peripheral capping pattern 250 and the buffer pattern 240 of the peripheral gate structure 200. The protrusion 195p may be vertically spaced from the peripheral barrier pattern 232 and the peripheral conductive pattern 231.

[0063] Figures 4 to 11 This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments.

[0064] Reference Figure 4 A substrate 100 comprising a cell region CR and a peripheral region PR can be provided. A first device isolation layer STI1 defining an active pattern AP can be formed on the cell region CR of the substrate 100. The first device isolation layer STI1 can be formed by forming trenches on the cell region CR of the substrate 100 and filling the trenches with an insulating material.

[0065] A second device isolation layer STI2 can be formed on the peripheral region PR of the substrate 100. The second device isolation layer STI2 can be formed by forming trenches on the peripheral region PR of the substrate 100 and sequentially depositing a first insulating material 11, a second insulating material 12, and a third insulating material 13 in the trenches. For example, the first insulating material may include silicon oxide, and the second insulating material may include silicon nitride (SiN). x The third insulating material may include silicon oxide.

[0066] Reference Figure 5 A peripheral gate dielectric layer 210 can be formed on the peripheral region PR of the substrate 100. The peripheral gate dielectric layer 210 can be formed by sequentially depositing a peripheral insulating layer 211 on the substrate 100 and depositing a high-dielectric layer 213 on the peripheral insulating layer 211. The peripheral gate dielectric layer 210 can cover at least a portion of the peripheral region PR of the substrate 100.

[0067] A lower insulating layer 110 can be formed on the cell region CR of the substrate 100. The lower insulating layer 110 can cover the first device isolation layer STI1 and the active pattern AP of the substrate 100. For example, the lower insulating layer 110 can be formed by sequentially depositing multiple insulating materials.

[0068] A preliminary peripheral conductive layer 231p may be formed on the lower insulating layer 110 and the peripheral gate dielectric layer 210. The preliminary peripheral conductive layer 231p may cover the top surface (or upper surface) of the lower insulating layer 110 and the top surface (or upper surface) of the peripheral gate dielectric layer 210. The preliminary peripheral conductive layer 231p may include, for example, doped polysilicon.

[0069] Reference Figure 5 and Figure 6 The initial peripheral conductive layer 231p can be partially removed, allowing the top surface of the lower insulating layer 110 to be exposed. The remaining portion of the initial peripheral conductive layer 231p can be referred to as the peripheral conductive pattern 231.

[0070] The recessed regions RS can be formed by patterning the substrate 100 and the lower insulating layer 110 on the unit region CR of the substrate 100. For example, each of the recessed regions RS can have an elliptical shape in a planar view. For example, the recessed regions RS can be arranged in a zigzag or honeycomb pattern in a planar view.

[0071] A first preliminary conductive layer 131p can be formed on the cell region CR of the substrate 100. The first preliminary conductive layer 131p can fill the recessed region RS and can be disposed on the lower insulating layer 110. A portion of the first preliminary conductive layer 131p can extend onto the peripheral region PR. The first preliminary conductive layer 131p can include, for example, polysilicon.

[0072] A barrier layer BML can be formed on the first preliminary conductive layer 131p and the peripheral gate dielectric layer 210. The barrier layer BML may include, for example, titanium (Ti) and / or titanium nitride (TiN). A metal layer ML may be formed on the barrier layer BML. The metal layer ML may include, for example, at least one of tungsten (W) and cobalt (Co).

[0073] Reference Figure 7 A buffer layer 240p can be formed on the metal layer ML. The buffer layer 240p can completely cover the top surface of the metal layer ML. The buffer layer 240p can include, for example, silicon nitride.

[0074] A mask pattern MK can be formed on the peripheral region PR of the substrate 100. For example, the mask pattern MK can cover a portion of the metal layer ML on the peripheral region PR.

[0075] Reference Figure 7 and Figure 8 The metal layer ML can be etched using an etching process performed with a mask pattern MK as the etching mask. The metal layer ML can be partially etched to form a first metal layer ML1 and a second metal layer ML2 with different thicknesses. The first metal layer ML1 and the second metal layer ML2 can have different thicknesses. The thickness of the first metal layer ML1 can be less than the thickness of the second metal layer ML2. The first metal layer ML1 can cover a portion of the cell region CR and the peripheral region PR. The second metal layer ML2 can cover the remaining portion of the peripheral region PR. The first metal layer ML1 and the second metal layer ML2 can be connected to each other.

[0076] During the etching process of the metal layer ML, the buffer layer 240p can be etched together. The remaining portion of the buffer layer 240p can be referred to as the buffer pattern 240.

[0077] A capping layer CPL can be formed on the first metal layer ML1 and the second metal layer ML2. The capping layer CPL can cover the first metal layer ML1 and the buffer pattern 240. Forming the capping layer CPL can include, for example, depositing an insulating material and planarizing an insulating material. The capping layer CPL can include, for example, at least one of silicon oxide and silicon nitride.

[0078] Reference Figure 8 and Figure 9 The first metal layer ML1 and the second metal layer ML2 on the cell region CR and the peripheral region PR can be separated. Separating the first metal layer ML1 and the second metal layer ML2 may include forming a second mask pattern on the peripheral region PR and performing a patterning process using the second mask pattern. After performing the patterning process, the second metal layer ML2 may be referred to as the peripheral metal pattern 233.

[0079] During the patterning process, the capping layer CPL, the barrier layer BML, the first preliminary conductive layer 131p, the peripheral conductive pattern 231, the peripheral gate dielectric layer 210, and the lower insulating layer 110 can be etched together. The capping layer CPL can be etched and separated into the first preliminary capping pattern 136p on the cell region CR and the peripheral capping pattern 250 on the peripheral region PR. The barrier layer BML can be etched and separated into the first barrier layer BML1 on the cell region CR and the peripheral barrier pattern 232 on the peripheral region PR. During the patterning process, a peripheral gate electrode 230 including the peripheral conductive pattern 231, the peripheral barrier pattern 232, and the peripheral metal pattern 233 can be formed on the peripheral region PR. During the patterning process, a peripheral gate structure 200 including the peripheral gate dielectric layer 210, the peripheral gate electrode 230, the buffer pattern 240, and the peripheral capping pattern 250 can be formed. During the patterning process, the top surface (or upper surface) of the substrate 100 on the peripheral region PR and the top surface (or upper surface) of the second device isolation layer STI2 can be exposed.

[0080] A peripheral spacer 182 may be formed on the sidewall of the peripheral gate structure 200. A pad layer 181 may be formed covering the peripheral spacer 182 and the sidewall and top surface (or upper surface) of the peripheral gate structure 200.

[0081] A filler insulating layer 183 may be formed to fill the space between the peripheral spacers 182. Forming the filler insulating layer 183 may include depositing an insulating material on the pad layer 181 and performing a planarization process to expose the pad layer 181. A preliminary interlayer insulation layer IL may be formed on the pad layer 181 and the filler insulating layer 183.

[0082] Reference Figure 9 and Figure 10 A patterning process can be performed on the cell region CR to pattern the first preliminary conductive layer 131p and the first metal layer ML1. A first conductive pattern 131 and a second conductive pattern 141 can be formed by patterning the first preliminary conductive layer 131p. A first metal pattern 133 and a second metal pattern 143 can be formed by patterning the first metal layer ML1. A first barrier pattern 132 and a second barrier pattern 142 can be formed by patterning the first barrier layer BML1. During the patterning process, a bit line BL including the first conductive pattern 131, the first metal pattern 133, and the first barrier pattern 132 can be formed. During the patterning process, a dummy line DL including the second conductive pattern 141, the second metal pattern 143, and the second barrier pattern 142 can be formed.

[0083] During the patterning process, a first preliminary capping pattern 136p, a padding layer 181, and a preliminary interlayer insulating layer IL can be patterned. The first preliminary capping pattern 136p can be patterned to form a first capping pattern 136 and a dummy capping pattern 146. The padding layer 181 on the cell region CR can be patterned to form a second capping pattern 137. The preliminary interlayer insulating layer IL can be patterned to form a third capping pattern 138 on the cell region CR and an interlayer insulating layer 185 on the peripheral region PR. The patterning process can form a bitline capping pattern 135 including the first to third capping patterns 136, 137, and 138.

[0084] Reference Figure 11 A bit line spacer 139 can be formed on the sidewall of the bit line BL and the sidewall of the bit line capping pattern 135. The bit line spacer 139 can fill the recessed area RS.

[0085] Node contacts NC can be formed between bit line spacers 139. A preliminary pad layer LPp can be formed on the node contacts NC. The preliminary pad layer LPp may include a conductive material. The preliminary pad layer LPp may cover the interlayer insulating layer 185 on the peripheral region PR. The preliminary pad layer LPp may be connected (e.g., electrically connected) to the peripheral gate structure 200.

[0086] Refer again Figure 3A The landing pad LP can be formed by etching the initial pad layer LPp using a photoresist layer on the cell region CR. The remaining portion of the initial pad layer LPp set on the peripheral region PR can be referred to as the conductive structure 195.

[0087] An upper insulating pattern 190 can be formed between landing pads LP. The upper insulating pattern 190 can fill the space between the landing pads LP. For example, the upper insulating pattern 190 may include at least one of silicon oxide and silicon nitride. A data storage pattern DSP can be formed on the landing pads LP.

[0088] The semiconductor device according to an embodiment may include a bit line on a cell region and a peripheral gate structure on a peripheral region. The thickness of a first metal pattern on the bit line may be less than the thickness of a peripheral metal pattern on the peripheral gate structure. Because the thickness of the first metal pattern is smaller, the parasitic capacitance of the bit line can be reduced. Therefore, the ratio of the capacitance of the data storage pattern to the parasitic capacitance of the bit line can be increased, thereby improving the sensing margin of the semiconductor device.

[0089] Because the thickness of the peripheral metal pattern is relatively large, the resistance of the peripheral metal pattern can be reduced. Therefore, the signal transmission speed to the peripheral gate structure can be improved. Furthermore, a semiconductor device with improved electrical characteristics can be provided.

[0090] While exemplary embodiments have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: The substrate includes a cell region and a peripheral region; An active pattern located on a cell region of the substrate; Bit lines, which extend along the direction on the active pattern; as well as A peripheral gate structure is located on the peripheral region. The bit lines include: A first conductive pattern, which is connected to the active pattern; and A first metallic pattern is located on top of the first conductive pattern. The peripheral gate structure includes: A peripheral gate dielectric layer, which is located on the peripheral region of the substrate; A peripheral conductive pattern located on the peripheral gate dielectric layer; and The outer metallic pattern is located on the outer conductive pattern, and The thickness of the outer metal pattern is greater than the thickness of the first metal pattern.

2. The semiconductor device of claim 1, wherein, The outer metal pattern and the first metal pattern both consist of the same metal.

3. The semiconductor device as claimed in claim 1, wherein, The distance between the upper surface of the peripheral metal pattern and the lower surface of the substrate is greater than the distance between the upper surface of the first metal pattern and the lower surface of the substrate.

4. The semiconductor device of claim 1, wherein, The peripheral gate structure further includes: The outer cover pattern, which is located on the outer metal pattern; and A buffer pattern is located between the outer metal pattern and the outer capping pattern.

5. The semiconductor device of claim 4, further comprising: A conductive structure is located on the peripheral gate structure. The conductive structure includes a protrusion that penetrates the outer cover pattern and the buffer pattern and connects to the outer metal pattern.

6. The semiconductor device of claim 1, further comprising: A dummy line, located between the bit line and the peripheral gate structure. The dummy line includes: A second conductive pattern is located between the first conductive pattern and the peripheral conductive pattern; and The second metal pattern is located on the second conductive pattern. The dummy line is horizontally spaced from the bit line and the peripheral gate structure.

7. The semiconductor device of claim 6, wherein, The thickness of the outer metal pattern is greater than the thickness of the second metal pattern.

8. The semiconductor device of claim 6, wherein, The thickness of the first metal pattern is substantially equal to the thickness of the second metal pattern.

9. The semiconductor device of claim 1, further comprising: A node contact, located on the sidewall of the bit line and connected to the active pattern; A landing pad, which is connected to the node contact; as well as Data storage pattern, located on the landing pad, The data storage pattern is connected to the landing pad.

10. A semiconductor device, comprising: The substrate includes a cell region and a peripheral region; An active pattern located on a cell region of the substrate; The character line extends across the active pattern along a first direction; Bit lines extend along a second direction that intersects the first direction on the word lines; A peripheral gate structure located on the peripheral region; as well as A pad layer that covers the sidewalls and top surface of the peripheral gate structure. The peripheral gate structure includes: A peripheral gate dielectric layer, which is located on the peripheral region of the substrate; A peripheral gate electrode, which is located on the peripheral gate dielectric layer; The peripheral capping pattern is located on the peripheral gate electrode; and A buffer pattern is located between the peripheral capping pattern and the peripheral gate electrode.

11. The semiconductor device of claim 10, wherein, The peripheral gate electrode includes a peripheral conductive pattern and a peripheral metal pattern located on the peripheral conductive pattern, and The buffer pattern contacts the upper surface of the peripheral metal pattern.

12. The semiconductor device as claimed in claim 11, in, The bit line includes: A first conductive pattern extending along the second direction on the active pattern, and The first metallic pattern is located on the first conductive pattern, and The thickness of the outer metal pattern is greater than the thickness of the first metal pattern.

13. The semiconductor device of claim 10, further comprising: A dummy line structure is located between the bit line and the peripheral gate structure. The dummy line structure includes: A dummy line, located between the bit line and the peripheral gate electrode, and A dummy cover pattern is located on the dummy line, and The upper surface of the buffer pattern is located at a lower level than the upper surface of the dummy cover pattern.

14. The semiconductor device of claim 13, wherein, The upper surface of the dummy cover pattern is coplanar with the upper surface of the outer cover pattern.

15. The semiconductor device of claim 13, wherein, The lower surface of the buffer pattern is located at a level higher than the upper surface of the dummy line.

16. A semiconductor device, comprising: The substrate includes a cell region and a peripheral region; An active pattern located on a cell region of the substrate; The character line extends across the active pattern along a first direction; Bit line structure, which extends along a second direction intersecting the first direction on the word line, the bit line structure including bit line and bit line cover pattern located on the bit line; A node contact element connected to the active pattern; A landing pad, which is connected to the node contact; as well as A peripheral gate structure is located on the peripheral region. The bit lines include: A first conductive pattern extending along the second direction on the active pattern; and A first metallic pattern is located on top of the first conductive pattern. The peripheral gate structure includes: A peripheral gate dielectric layer, which is located on the peripheral region of the substrate; A peripheral conductive pattern is located on the peripheral gate dielectric layer; A peripheral metal pattern, which is located on the peripheral conductive pattern; The outer cover pattern, which is located on the outer metal pattern; and A buffer pattern is located between the outer cover pattern and the outer metal pattern, and The thickness of the outer metal pattern is greater than the thickness of the first metal pattern.

17. The semiconductor device of claim 16, wherein, The outer metal pattern and the first metal pattern include tungsten.

18. The semiconductor device of claim 16, further comprising: A dummy line is located between the bit line and the peripheral gate structure; as well as A dummy cover pattern is located on the dummy line. The dummy line includes: A second conductive pattern is located between the first conductive pattern and the peripheral conductive pattern; and The second metal pattern is located on the second conductive pattern. The dummy line is horizontally spaced from the bit line and the peripheral gate structure, and The thickness of the outer metal pattern is greater than the thickness of the second metal pattern.

19. The semiconductor device of claim 18, wherein, The thickness of the dummy cover pattern is greater than the thickness of the outer cover pattern.

20. The semiconductor device of claim 18, wherein, The thickness of the first metal pattern is substantially the same as the thickness of the second metal pattern.

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