Semiconductor memory device including self-aligned support hole

Abstract

According to some embodiments of the present disclosure, a semiconductor memory device includes a substrate, a plurality of lower electrodes each including a first portion disposed on the substrate and extending in a first direction perpendicular to an upper surface of the substrate, and a second portion stacked on the first portion and extending in the first direction, a first support pattern surrounding a sidewall of the first portion of each of the plurality of lower electrodes and including a plurality of first support holes, a second support pattern surrounding a sidewall of the second portion of each of the plurality of lower electrodes and including a plurality of second support holes, a dielectric layer disposed on the plurality of lower electrodes, the first support pattern, and the second support pattern, and an upper electrode covering the dielectric layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor memory device. Background Technology

[0002] With the continuous advancement of semiconductor technology, semiconductor devices are becoming increasingly integrated and miniaturized, and consequently, individual components of these devices are also trending towards smaller dimensions. In particular, in memory devices such as DRAM, it is desirable to form the lower electrode of a capacitor with a high aspect ratio to ensure sufficient capacitance. Typically, a support structure is needed to support the lower electrode to ensure the structural stability of the high aspect ratio lower electrode and improve process reliability.

[0003] As the height of the lower electrode increases, a method for forming the lower electrode and its support in multiple steps is being considered. Summary of the Invention

[0004] One aspect of this disclosure provides a semiconductor memory device including a self-aligned support aperture patterned using a self-alignment technique.

[0005] According to some embodiments of this disclosure, a semiconductor memory device includes a substrate, a plurality of lower electrodes, a first support pattern, a second support pattern, a dielectric layer, and an upper electrode. Each of the plurality of lower electrodes includes a first portion disposed on the substrate and extending in a first direction perpendicular to the upper surface of the substrate, and a second portion stacked on the first portion and extending in the first direction. The first support pattern surrounds the sidewalls of the first portion of each of the plurality of lower electrodes and includes a plurality of first support holes. The second support pattern surrounds the sidewalls of the second portion of each of the plurality of lower electrodes and includes a plurality of second support holes. The dielectric layer is disposed on the plurality of lower electrodes, the first support pattern, and the second support pattern. The upper electrode covers the dielectric layer. The second portion overlaps with at least a portion of the first portion in the first direction and is offset from the first portion in a second direction perpendicular to the first direction.

[0006] According to some embodiments of this disclosure, a semiconductor memory device includes: a substrate including an active pattern; a plurality of conductive patterns disposed on the active pattern; a plurality of lower electrodes electrically connected to the plurality of conductive patterns; a plurality of support patterns supporting the plurality of lower electrodes; a dielectric layer on the plurality of lower electrodes and the plurality of support patterns; and an upper electrode covering the dielectric layer. Each of the plurality of lower electrodes may include a first portion extending in a first direction perpendicular to the upper surface of the substrate and a second portion stacked on the first portion and extending in the first direction. The plurality of support patterns include a first support pattern surrounding the sidewalls of the first portion and including a plurality of first support holes, and a second support pattern surrounding the sidewalls of the second portion and including a plurality of second support holes. Each second portion overlaps with a corresponding first portion in the first direction and is offset from the first portion by a first distance in a second direction perpendicular to the first direction, and each of the plurality of second support holes is offset from a corresponding one of the plurality of first support holes by a first distance in the second direction.

[0007] According to some embodiments of this disclosure, a semiconductor memory device includes a substrate, a plurality of lower electrodes, each lower electrode including a first portion disposed on the substrate and extending in a first direction perpendicular to an upper surface of the substrate, and a second portion stacked on the first portion and extending in the first direction; a first support pattern including a plurality of first support layers, a first support hole pattern including first support holes aligned and spaced apart in the first direction formed in the plurality of first support layers, the first support pattern surrounding the sidewalls of the first portion of each of the plurality of lower electrodes; a second support pattern including a plurality of second support layers, a second support hole pattern including second support holes aligned and spaced apart in the first direction formed in the plurality of second support layers, the second support pattern surrounding the sidewalls of the second portion of each of the plurality of lower electrodes; a dielectric layer on the plurality of lower electrodes, the first support pattern, and the second support pattern; and an upper electrode on the dielectric layer. The second portion overlaps with a portion of the first portion in the first direction and is offset from the first portion in a second direction perpendicular to the first direction, and the first support hole pattern and the second support hole pattern are offset in the second direction.

[0008] According to some embodiments of this disclosure, a method of manufacturing a semiconductor memory device includes: forming a first mold layer and a first support pattern on the first mold layer; forming a plurality of first vias penetrating the first mold layer and the first support pattern in a first direction; forming first portions of a plurality of lower electrodes in the plurality of first vias; removing a portion of the first support pattern such that a portion of the first portions of the plurality of lower electrodes is exposed; forming a liner on the first portions of the plurality of lower electrodes and on the remaining portions of the first support pattern; removing a portion of the liner to form an opening exposing a portion of the first support pattern; and removing a portion of the first support pattern exposed through the opening to form a first support hole.

[0009] In some embodiments of this disclosure, the method may further include forming a liner on a first portion of a plurality of lower electrodes and on the remaining portion of a first support pattern, the formation of which may be performed by atomic layer deposition.

[0010] In some embodiments of this disclosure, the opening can be formed by a back etching process on the liner.

[0011] In some embodiments of this disclosure, the method may further include removing the first mold layer through the first support hole after the first support hole has been formed.

[0012] In some embodiments of this disclosure, the method may further include: forming a sacrificial layer on the side surface of a first portion of a plurality of lower electrodes through a first support hole; forming a second mold layer on a first support pattern and forming a second support pattern on the second mold layer; forming a plurality of second through holes by removing portions of the second mold layer and the second support pattern; and forming a plurality of second portions of lower electrodes in the plurality of second through holes.

[0013] In some embodiments of this disclosure, the method may further include removing a portion of the second support pattern to form a second support hole.

[0014] In some embodiments of this disclosure, the second portions of the plurality of lower electrodes may overlap with at least a portion of the first portions of the plurality of lower electrodes in a first direction, and may be located at different positions in a second direction perpendicular to the first direction.

[0015] In some embodiments of this disclosure, the second support hole may be located at a different position in the second direction than the first support hole.

[0016] In some embodiments of this disclosure, the method may further include: removing the second mold layer and the sacrificial layer through the second support hole, forming a dielectric layer on a plurality of lower electrodes, a first support pattern and a second support pattern, and forming an upper electrode on the dielectric layer.

[0017] According to some embodiments of this disclosure, a first support hole is formed in a first support pattern before forming the second portion of the plurality of lower electrodes, thereby reducing the difficulty of the process.

[0018] According to some embodiments of this disclosure, because the support pattern can be patterned without using separate photoresist and / or mask layers, the process cost can be reduced. Attached Figure Description

[0019] Figure 1 The layout of a semiconductor memory device according to some embodiments of the present disclosure is shown.

[0020] Figure 2 and Figure 3 It is shown Figure 1 An enlarged view of a portion of a semiconductor memory device.

[0021] Figure 4 It shows along Figure 2 or Figure 3 A cross-sectional view of a semiconductor memory device taken by line A-A'.

[0022] Figure 5 It shows along Figure 2 or Figure 3 A cross-sectional view of a semiconductor memory device taken by line B-B'.

[0023] Figures 6 to 10 This illustrates some embodiments according to this disclosure. Figure 2 or Figure 3 A cross-sectional view of a portion of a semiconductor memory device taken by line A-A' or B-B'.

[0024] Figure 11 The layout of a semiconductor memory device according to some embodiments of the present disclosure is shown.

[0025] Figure 12 and Figure 13 It is shown Figure 11 An enlarged view of a portion of a semiconductor memory device.

[0026] Figure 14 It shows along Figure 12 or Figure 13 A cross-sectional view of a semiconductor memory device taken by line C-C'.

[0027] Figures 15 to 21 This is used to explain the method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure, along with the corresponding Figure 2 or Figure 3 A cross-sectional view taken by line A-A' or B-B'.

[0028] Figures 22 to 26 This is used to explain the method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure, along with the corresponding Figure 2 or Figure 3 A cross-sectional view taken from line B-B'.

[0029] Figures 27 to 29 This is used to explain the method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure, along with the corresponding Figure 2 or Figure 3 A cross-sectional view taken from line B-B'. Detailed Implementation

[0030] In the following, semiconductor memory devices according to some embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0031] Throughout this specification, when a component is described as “comprising” a particular element or group of elements, it should be understood that the component may consist solely of that element or group of elements, or may consist of that element or group of elements in combination with other additional elements, unless the context clearly and / or explicitly states the opposite.

[0032] Ordinal numbers such as "first," "second," and "third" may be used solely to identify certain elements, steps, etc., to distinguish them from other elements, steps, etc. Terms not used in this specification, such as "first" or "second," may still be referred to as "first" or "second" in the claims. Furthermore, a term referred to by a specific ordinal number (e.g., "first") in one claim may be described using a different ordinal number (e.g., "second") in other parts of the specification or in another claim.

[0033] This document may use spatial relative terms such as “below,” “below,” “lower,” “above,” “upper,” “top,” “bottom,” “front,” and “rear” to describe positional relationships, such as those shown in the accompanying figures. It should be understood that these spatial relative terms cover not only the device orientation shown in the figures but also other different orientations of the device.

[0034] Terms such as “same,” “equal,” “plane,” “coplanar,” “parallel,” and “perpendicular” used herein cover states of complete or substantial consistency, including, for example, deviations that may arise due to manufacturing processes. The word “approximately” may be used in this document to emphasize this meaning unless the context or other expression otherwise indicates otherwise.

[0035] It should be understood that when an element is described as being “connected,” “coupled,” or “above” another element, the element may be directly connected, coupled, or located above the other element, or there may be intermediate elements present. Conversely, when an element is described as being “directly connected,” “directly coupled,” or “in contact,” “in contact with,” or any form using the word “in contact,” there are no intermediate elements at the contact location.

[0036] In this document, components described as “electrical connections” are configured to transmit electrical signals from one component to another (although the strength of the electrical signal may attenuate during transmission and the transmission may be selective).

[0037] Figure 1 The layout of a semiconductor memory device according to some embodiments of the present disclosure is shown. Figure 2 and Figure 3 It is shown Figure 1 An enlarged view of a portion of a semiconductor memory device. Figure 2 and Figure 3 It can be Figure 1 The region R1. For convenience, in Figures 1 to 3 In the figure, components other than the first support pattern 150, the second support pattern 250, the lower electrode BE, the first support hole 150H and the second support hole 250H are omitted.

[0038] refer to Figure 1 and Figure 2 A semiconductor memory device according to some embodiments of the present disclosure may include a plurality of lower electrodes BE and support patterns 150 and 250.

[0039] Each of the plurality of lower electrodes BE may include a first portion BE_1 and a second portion BE_2. The second portion BE_2 may be disposed on the first portion BE_1. The second portion BE_2 may overlap a portion of the first portion BE_1 in a first direction D1 (e.g., the vertical direction). In some embodiments, the area of ​​the second portion BE_2 may be larger than the area of ​​the first portion BE_1 (e.g., in a plan view), such that the second portion BE_2 may completely overlap the first portion BE_1 in the first direction D1.

[0040] The first portion BE_1 and the second portion BE_2 can be located at different positions in the second direction D2. For example, in a plan view, the center of the second portion BE_2 may not overlap perpendicularly with the center of the corresponding first portion BE_1. For example, the second portion BE_2 may be offset from the first portion BE_1 in the second direction D2. This is merely an example, and the offset can occur in another direction perpendicular to the first direction D1. In embodiments, each of the plurality of second portions BE_2 is shown offset relative to a corresponding one of the plurality of first portions BE_1 in the same direction (e.g., in the second direction D2), but this disclosure is not limited thereto. Each of the plurality of second portions BE_2 may be offset relative to a corresponding one of the plurality of first portions BE_1 in different directions from each other. For example, in a plan view, the second portion BE_2 may be offset relative to the first portion BE_1.

[0041] Multiple lower electrodes BE can extend longitudinally along a first direction D1. For example, each of the first portion BE_1 and the second portion BE_2 can extend longitudinally along the first direction D1. Multiple lower electrodes BE can be arranged along a second direction D2 and a third direction D3. For example, the second direction D2 and the third direction D3 can be horizontal.

[0042] The lower electrode BE can be arranged with a grid pattern. The lower electrode BE can be spaced apart along the second direction D2 and the third direction D3. For example, the lower electrode BE can be arranged in a matrix pattern (e.g., in a plan view), and the support patterns 150 and 250 can be formed in a grid pattern (e.g., in a plan view). For example, the lower electrode BE can be arranged along the second direction D2 and the third direction D3 at a first pitch G. For example, the first portion BE_1 and the second portion BE_2 of the lower electrode BE can be spaced apart along the second direction D2 and the third direction D3 at a first pitch G. For example, the fourth lower electrode BE can be located at the corner of a square, and the square at the corner can be repeated along the second direction D2 and the third direction D3. For example, the square where the lower electrode BE is located at its corner can be a virtual square. The lower electrode BE can be arranged linearly along the fourth direction D4. Here, the second direction D2 and the third direction D3 can each be perpendicular to the first direction D1. The fourth direction D4 can intersect with the second direction D2 and the third direction D3. For example, the fourth direction D4 can form a predetermined angle, such as 45 degrees, with each of the second direction D2 and the third direction D3. The fourth direction D4 can be horizontal and perpendicular to the first direction D1 (e.g., the vertical direction).

[0043] The first support pattern 150 and the second support pattern 250 can support the lower electrode BE. The first support pattern 150 and the second support pattern 250 can surround the sidewall of the lower electrode BE. For example, the first support pattern 150 can surround the sidewall of a first portion BE_1 of the lower electrode BE, and the second support pattern 250 can surround the sidewall of a second portion BE_2 of the lower electrode BE. The first support pattern 150 and the second support pattern 250 can each be arranged perpendicular to the first direction D1. For example, the first support pattern 150 and the second support pattern 250 can extend in a direction perpendicular to the first direction D1. The first support pattern 150 and the second support pattern 250 can be spaced apart in the first direction D1. For example, the second support pattern 250 can be spaced upwards from the first support pattern 150.

[0044] Each of the first support pattern 150 and the second support pattern 250 may include a plurality of first support holes 150H and a plurality of second support holes 250H, respectively.

[0045] The first support hole 150H can be spaced apart from each other at a predetermined distance. The second support hole 250H can also be spaced apart from each other at a predetermined distance. The first support hole 150H and the second support hole 250H can each be arranged with a grid pattern. For example, the first support hole 150H and the second support hole 250H can be arranged in a matrix such that the first pattern 150 and the second pattern 250 form a grid pattern, for example, in a plan view. The first support hole 150H and the second support hole 250H can each be spaced apart in the second direction D2 and the third direction D3. For example, the first support hole 150H and the second support hole 250H can each be arranged along the second direction D2 and the third direction D3 with a first pitch G. For example, the first support hole 150H and the second support hole 250H can be spaced apart in the second direction D2 and the third direction D3 with a first pitch G. For example, the first support hole 150H and the second support hole 250H can have the same pitch in the second direction D2 and the third direction D3.

[0046] Each of the first support hole 150H and the second support hole 250H can have a circular closed curve shape. For example, each of the first support hole 150H and the second support hole 250H can have a circular or elliptical shape, for example in a plan view. For example, each of the first support hole 150H and the second support hole 250H can have a cylindrical shape or an elliptical cylindrical shape.

[0047] Each first support hole 150H may be located within a first portion BE_1 of a plurality of lower electrodes BE adjacent to the first support hole 150H. The plurality of first portions BE_1 adjacent to the first support hole 150H may be located at a corner of a square, and the first support hole 150H may be located inside the square. In some embodiments, the plurality of first portions BE_1 adjacent to the first support hole 150H may be located at a corner of a square, and the first support hole 150H may be located at the center of the square. For example, in a plan view, connecting four adjacent first portions BE_1 with lines can form a square, and the first support hole 150H may be located at the center of the square. For example, the distance between the center of the first support hole 150H and the center of each of the plurality of first portions BE_1 adjacent to the first support hole 150H (e.g., four first portions BE_1) may be the same.

[0048] Each second support hole 250H can be located within a second portion BE_2 of a plurality of lower electrodes BE adjacent to the second support hole 250H. The plurality of second portions BE_2 adjacent to the second support hole 250H can be located at the corners of a square, and the second support hole 250H can be located inside the square. In some embodiments, the plurality of second portions BE_2 adjacent to the second support hole 250H can be located at the corners of a square, and the second support hole 250H can be located at the center of the square. For example, in a plan view, connecting four adjacent second portions BE_2 with lines can form a square, and the second support hole 250H can be located at the center of the square. For example, the distance between the center of the second support hole 250H and the center of each of the plurality of second portions BE_2 adjacent to the second support hole 250H (e.g., four second portions BE_2) can be the same.

[0049] The second portion BE_2 of the plurality of lower electrodes BE can be offset / deviated from the first portion BE_1 of the plurality of lower electrodes BE in the second direction D2, and the first support hole 150H and the second support hole 250H can be offset / deviated in the second direction D2. Furthermore, the grid patterns formed by the first portions BE_1 and the second portions BE_2 of the plurality of lower electrodes BE, respectively, and the grid patterns formed by the first support hole 150H and the second support hole 250H, respectively, can have the same spacing.

[0050] As described above, the square structure, with a set of four first support holes 150H and a set of four second support holes 250H at corresponding corners of the square, repeats along the second direction D2 and the third direction D3. The first support holes 150H and the second support holes 250H can be arranged linearly along the fourth direction D4. For example, the first part BE_1 and the first support holes 150H can be arranged alternately along the fourth direction D4, and the second part BE_2 and the second support holes 250H can be arranged alternately along the fourth direction D4. For example, the fourth direction D4 can form a 45-degree angle with each of the second direction D2 and the third direction D3.

[0051] refer to Figure 3 The first support hole 150H_1 and the second support hole 250H_1 can have the same characteristics as... Figure 2 The first support hole 150H and the second support hole 250H have different shapes. The first support hole 150H_1 and the second support hole 250H_1 can have closed curve shapes including apex / vertex. For example, the first support hole 150H_1 and the second support hole 250H_1 can have closed curve shapes in which four quadrants are symmetrically formed. For example, in a plan view, the closed curve shape of each of the first support hole 150H_1 and the second support hole 250H_1 can be composed of four quadrants / arcs, all of which bulge towards the center of the first support hole 150H_1 and the second support hole 250H_1, and the two ends of each quadrant / arc are tangent to the adjacent quadrant / arc, thereby forming a complete closed curve. In some embodiments, the first support hole 150H_1 and the second support hole 250H_1 can have rhombus or diamond shapes, for example, in a plan view.

[0052] Figure 4 It shows along Figure 2 or Figure 3 A cross-sectional view of a semiconductor memory device taken by line A-A'. Figure 5 It shows along Figure 2 or Figure 3 A cross-sectional view of a semiconductor memory device taken by line B-B'.

[0053] refer to Figure 4 and Figure 5 The semiconductor memory device according to some embodiments of the present disclosure may include a plurality of conductive patterns 102, an isolation layer 104, a capacitor structure CAP, a first support pattern 150 and a second support pattern 250.

[0054] Multiple conductive patterns 102 may be embedded in an insulating layer 104. The upper surface of each of the multiple conductive patterns 102 may be located at the same vertical level as the upper surface of the insulating layer 104. In some embodiments, the upper surface of each of the multiple conductive patterns 102 may be located at a lower vertical level than the upper surface of the insulating layer 104. The multiple conductive patterns 102 may be electrically connected to a lower electrode BE. The insulating layer 104 may electrically isolate the multiple conductive patterns 102 from each other. The multiple conductive patterns 102 may include a conductive material. The insulating layer 104 may include an insulating material such as silicon oxide.

[0055] An etch stop layer 110 may be disposed on the isolation layer 104. For example, the etch stop layer 110 may comprise silicon nitride, silicon oxynitride, or a combination thereof. The etch stop layer 110 prevents etchant from entering below the lower electrode BE during a wet etching process, thereby preventing the isolation layer 104 from being etched.

[0056] A capacitor structure CAP can include multiple lower electrodes BE, dielectric layers CIL, and upper electrodes UE.

[0057] Multiple lower electrodes BE can be disposed on multiple conductive patterns 102. Specifically, a first portion BE_1 of the multiple lower electrodes BE can be disposed on the multiple conductive patterns 102. A second portion BE_2 of the multiple lower electrodes BE can be stacked on the first portion BE_1. The first portion BE_1 and the second portion BE_2 can be located at different positions in the second direction D2. For example, the second portion BE_2 can be offset from the first portion BE_1 in the second direction D2. The centerline of the second portion BE_2 can be located at a position in the second direction D2 that is offset by a distance OD from the centerline of the first portion BE_1. Here, the centerlines of the first portion BE_1 and the second portion BE_2 can extend in the first direction D1. For example, the side surface of the second portion BE_2 can have a stepped difference from the side surface of the first portion BE_1.

[0058] The plurality of lower electrodes BE can have a cylindrical shape. For example, each of the first portion BE_1 and the second portion BE_2 can have a cylindrical shape extending longitudinally along the first direction D1. However, this disclosure is not limited thereto, and each of the plurality of lower electrodes BE can have a cup-shaped or bottom-closed cylindrical cross-sectional structure.

[0059] Multiple lower electrodes BE can be electrically connected to the conductive pattern 102. The multiple lower electrodes BE can include metals such as Ti, W, Ni, or Co, or metal nitrides such as TiN, TiSiN, TiAlN, TaN, TaSiN, or WN. In an embodiment, the lower electrode BE can include TiN.

[0060] A dielectric layer CIL can be disposed between multiple lower electrodes BE and upper electrodes UE. The dielectric layer CIL can conformally cover a first portion BE_1 and a second portion BE_2 of the multiple lower electrodes BE, as well as a first support pattern 150 and a second support pattern 250. For example, the dielectric layer CIL can be conformally disposed on the etch stop layer 110, the first portion BE_1 and the second portion BE_2 of the multiple lower electrodes BE, the first support pattern 150, and the second support pattern 250. The dielectric layer CIL can include metal oxides such as HfO2, ZrO2, Al2O3, La2O3, Ta2O3, or TiO2, dielectric materials with a perovskite structure such as SrTiO3 (STO), BaTiO3, PZT, or PLZT, or combinations thereof.

[0061] The upper electrode UE can be disposed on the dielectric layer CIL. The upper electrode UE can cover the dielectric layer CIL. The upper electrode UE can include metals such as Ti, W, Ni or Co, or metal nitrides such as TiN, TiSiN, TiAlN, TaN, TaSiN or WN.

[0062] The first support pattern 150 and the second support pattern 250 can be disposed inside the capacitor structure CAP. For example, the first support pattern 150 and the second support pattern 250 can be disposed between multiple lower electrodes BE and the dielectric layer CIL. The first support pattern 150 and the second support pattern 250 can be disposed between adjacent lower electrodes BE. For example, the first support pattern 150 and the second support pattern 250 can be disposed between adjacent lower electrodes BE. The first support pattern 150 and the second support pattern 250 can connect to / contact adjacent lower electrodes BE and can support the lower electrodes BE, such as the sidewalls of the lower electrodes BE.

[0063] A first support pattern 150 may surround the side surface of a first portion BE_1 of the plurality of lower electrodes BE. The top of the first support pattern 150 may be located at the same vertical level as the top of the first portion BE_1 of the plurality of lower electrodes BE. A second support pattern 250 may surround the side surface of a second portion BE_2 of the plurality of lower electrodes BE. The top surface of the second support pattern 250 may be located at the same vertical level as the top of the second portion BE_2 of the plurality of lower electrodes BE. In some embodiments, when the first support pattern 150 is a single layer, the top surface of the first support pattern 150 may be located at the same vertical level as the top surface of the first portion BE_1 of the plurality of lower electrodes BE.

[0064] The first support pattern 150 may include a plurality of first support layers 151, 152, and 153, wherein a first support hole pattern including first support holes 151H, 152H, and 153H is formed. The second support pattern 250 may include a plurality of second support layers 251, 252, and 253, wherein a second support hole pattern including second support holes 251H, 252H, and 253H is formed. In this disclosure, the first support pattern 150 and the second support pattern 250 are shown as each comprising three layers, but the disclosure is not limited thereto. In some embodiments, the first support pattern 150 and the second support pattern 250 may each comprise a different number of layers. Hereinafter, the first support pattern 150 and the second support pattern 250 will be described as each comprising three layers.

[0065] Multiple first support layers 151, 152, and 153 may include a first-1 support layer 151, a first-2 support layer 152, and a first-3 support layer 153. The first-1 support layer 151, the first-2 support layer 152, and the first-3 support layer 153 may be located at different vertical levels. The first-1 support layer 151, the first-2 support layer 152, and the first-3 support layer 153 may be spaced apart from each other in a first direction D1. The first-1 support layer 151 may be spaced apart from the etch stop layer 110 in the first direction D1. The first-2 support layer 152 may be disposed above the first-1 support layer 151, and the first-3 support layer 153 may be disposed above the first-2 support layer 152. A dielectric layer CIL and an upper electrode UE may be disposed between support layers 151, 152, and 153. The upper surface of the first-3 support layer 153 may be located at the same vertical level as the upper surface of the first portion BE_1 of the plurality of lower electrodes BE. The upper surface of the first-3 support layer 153 may be coplanar with the upper surface of the first portion BE_1 of the plurality of lower electrodes BE.

[0066] The top surface of the first support pattern 150 can contact the bottom surface of the second portion BE_2 of the plurality of lower electrodes BE. The upper surface 153U of the first-3 support layer 153 is located at the same vertical level as the upper surface of the first portion BE_1 of the plurality of lower electrodes BE, and the second portion BE_2 of the plurality of lower electrodes BE is offset from the first portion BE_1 in the second direction D2. Therefore, the upper surface 153U of the first-3 support layer 153 can contact the bottom surface of the second portion BE_2 of the plurality of lower electrodes BE.

[0067] The first-1 support layer 151, the first-2 support layer 152, and the first-3 support layer 153 may each include first support holes 151H, 152H, and 153H. The first support holes 151H, 152H, and 153H may be formed in the first-1 support layer 151, the first-2 support layer 152, and the first-3 support layer 153, respectively. Therefore, the first support holes 151H, 152H, and 153H may be spaced apart from each other in the first direction D1. The first support holes 151H, 152H, and 153H may be aligned in the first direction D1. For example, the first support hole pattern includes first support holes 151H, 152H, and 153H aligned and spaced apart in the first direction D1.

[0068] The thicknesses of the first-1 support layer 151, the first-2 support layer 152, and the first-3 support layer 153 can be different. Here, the thickness of each of the first-1 support layer 151, the first-2 support layer 152, and the first-3 support layer 153 can be defined as the thickness in the first direction D1. For example, the thickness of the first-3 support layer 153 can be greater than the thicknesses of the first-1 support layer 151 and the first-2 support layer 152. However, this is merely exemplary, and the thicknesses of the first-1 support layer 151, the first-2 support layer 152, and the first-3 support layer 153 can vary.

[0069] The second support pattern 250 may include a second-1 support layer 251, a second-2 support layer 252, and a second-3 support layer 253. The second-1 support layer 251, the second-2 support layer 252, and the second-3 support layer 253 may be located at different vertical levels. The second-1 support layer 251, the second-2 support layer 252, and the second-3 support layer 253 may be spaced apart from each other in a first direction D1. The second-1 support layer 251 may be spaced apart from the etch stop layer 110 in the first direction D1. The second-2 support layer 252 may be disposed above the second-1 support layer 251, and the second-3 support layer 253 may be disposed above the second-2 support layer 252. The dielectric layer CIL and the upper electrode UE may be disposed between the second-1 support layer 251, the second-2 support layer 252, and the second-3 support layer 253. For example, the dielectric layer CIL and the upper electrode UE can be vertically overlapped between the second-1 support layer 251 and the second-2 support layer 252, and the dielectric layer CIL and the upper electrode UE can also be vertically overlapped between the second-2 support layer 252 and the second-3 support layer 253. The upper surface of the second-3 support layer 253 can be located at the same vertical level as the upper surface of the second portion BE_2 of the plurality of lower electrodes BE. The upper surface of the second-3 support layer 253 can be coplanar with the upper surface of the second portion BE_2 of the plurality of lower electrodes BE.

[0070] The second-1 support layer 251, the second-2 support layer 252, and the second-3 support layer 253 may each include second support holes 251H, 252H, and 253H. The second support holes 251H, 252H, and 253H may be formed in the second-1 support layer 251, the second-2 support layer 252, and the second-3 support layer 253, respectively. Therefore, the second support holes 251H, 252H, and 253H may be spaced apart in the first direction D1. The second support holes 251H, 252H, and 253H may be aligned in the first direction D1. For example, the second support hole pattern includes second support holes 251H, 252H, and 253H that are aligned (e.g., overlap each other) and spaced apart in the first direction D1.

[0071] The first support hole pattern, including first support holes 151H, 152H, and 153H, and the second support hole pattern, including second support holes 251H, 252H, and 253H, can be offset in the second direction D2. The first support holes 151H, 152H, and 153H can be located at the same distance (e.g., distance DA) from adjacent first portions BE_1 of the plurality of lower electrodes BE, and the second support holes 251H, 252H, and 253H can be located at the same distance (e.g., distance DB) from adjacent second portions BE_2 of the plurality of lower electrodes BE. For example, distance DA and distance DB can be the same.

[0072] The thicknesses of the second-1 support layer 251, the second-2 support layer 252, and the second-3 support layer 253 can be different. Here, the thickness of each of the second-1 support layer 251, the second-2 support layer 252, and the second-3 support layer 253 can be defined as the thickness in the first direction D1. For example, the thickness of the second-3 support layer 253 can be greater than the thickness of the second-1 support layer 251 and the second-2 support layer 252. However, this is merely exemplary, and the thicknesses of the second-1 support layer 251, the second-2 support layer 252, and the second-3 support layer 253 can vary.

[0073] Each of the first support pattern 150 and the second support pattern 250 may include at least one of silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), or tantalum oxide (TaO). In some embodiments, the first support pattern 150 and the second support pattern 250 may include the same material, but this disclosure is not limited thereto. For example, the first support pattern 150 and the second support pattern 250 may include different materials.

[0074] Figures 6 to 10 This is a cross-sectional view illustrating a portion of a semiconductor memory device according to some embodiments of the present disclosure. For convenience, explanations and references will be made accordingly. Figures 1 to 5 The parts described are different. For example, unless the context otherwise indicates, the combination... Figures 1 to 5 The part described in the diagram also applies. Figures 6 to 10 The example shown. Figures 6 to 8 It can correspond to along Figure 2 or Figure 3 The cross section intercepted by line B-B', and Figures 9 to 10 It can correspond to along Figure 2 or Figure 3 The cross section intercepted by line A-A'.

[0075] refer to Figure 6In a semiconductor memory device according to some embodiments of the present disclosure, the first support pattern 150 may include a first curved portion 153c.

[0076] The first curved portion 153c may define the upper surface and side surface of the first support pattern 150. The first curved portion 153c may have a circular shape. For example, the first curved portion 153c may define the upper surface and side surface of the first-3 support layer 153A. The first curved portion 153c may protrude toward the second support pattern 250. The first curved portion 153c may protrude upward. For example, the first-3 support layer 153 may have a fan-shaped cross-section or a sector-shaped cross-section.

[0077] The side surface of the support layer 153A may be circular. The side surface of the first-3 support layers 153A may be curved. The first-3 support layers 153A may have a width that increases in the downward direction (e.g., in the horizontal direction). The width at the lower end of the first-3 support layers 153A (e.g., in the horizontal direction) may be greater than the width at the upper end of the first-3 support layers 153A (e.g., in the horizontal direction). The width (e.g., in the horizontal direction) of the first support hole 153H formed in the first-3 support layers 153A may increase in the downward direction. The upper end of the first-3 support layers 153A may be located at the same vertical level as the topmost part of the first portion BE_1 of the plurality of lower electrodes BE.

[0078] refer to Figure 7 In a semiconductor memory device according to some embodiments of the present disclosure, the second support pattern 250 may include a second curved portion 253c.

[0079] The second curved portion 253c may define the upper surface and side surface of the second support pattern 250. The second curved portion 253c may have a circular shape. For example, the second curved portion 253c may define the upper surface and side surface of the second-3 support layer 253A. The second curved portion 253c may protrude in a direction away from the first support pattern 150, for example, protruding upwards. The second curved portion 253c may protrude in the same direction as the first curved portion 153c. The second curved portion 253c may protrude upwards. For example, the second-3 support layer 253 may have a fan-shaped cross-section or a sector-shaped cross-section.

[0080] The side surface of the support layer 253A may be circular. The side surface of the second-3 support layer 253A may be curved. The second-3 support layer 253A may have a width that increases in the downward direction (e.g., in the horizontal direction). The width at the lower end of the second-3 support layer 253A (e.g., in the horizontal direction) may be greater than the width at the upper end of the second-3 support layer 253A (e.g., in the horizontal direction). The width of the second support hole 253H formed in the second-3 support layer 253A may increase in the downward direction. The upper end of the second-3 support layer 253A may be located at the same vertical level as the topmost part of the second portion BE_2 of the plurality of lower electrodes BE.

[0081] refer to Figure 8 The top of the first portion BE_1 of the plurality of lower electrodes BE can be located at a higher vertical level than the top of the first support pattern 150. For example, the first portion BE_1 of the plurality of lower electrodes BE can protrude upward from the top of the first support pattern 150. The upper surface of the first support pattern 150 can be spaced apart from the second portion BE_2 of the plurality of lower electrodes BE in the first direction D1. For example, the upper surface of the first support pattern 150 may not contact the bottom surface of the second portion BE_2 of the plurality of lower electrodes BE.

[0082] For example, the upper surface of the first-3 support layer 153 may be located at a vertical level lower than the top of the first portion BE_1 of the plurality of lower electrodes BE. The upper surface of the first-3 support layer 153 may be spaced apart from the second portion BE_2 of the plurality of lower electrodes BE in the first direction D1. The upper surface of the first-3 support layer 153 may not contact the bottom surface of the second portion BE_2 of the plurality of lower electrodes BE. In some embodiments, the top of the second portion BE_2 of the plurality of lower electrodes BE may be located at a vertical level higher than the top of the second support pattern 250.

[0083] refer to Figure 9 A semiconductor memory device according to some embodiments of the present disclosure may include a substrate 300, an interlayer insulating layer 310, a bit line structure BL, bit line spacers 340, buried contacts 330, and an isolation layer 104. In embodiments of the present disclosure, a conductive pattern 102 (see...) Figure 4 (This can be a landing pad 102a.)

[0084] The substrate 300 may include a plurality of active patterns AC. The active patterns AC may be defined by a device isolation layer 305 formed in the substrate 300. The active patterns AC may have a strip shape. The plurality of active patterns AC may be arranged spaced apart from each other. The device isolation layer 305 may have a shallow trench isolation (STI) structure. Each device isolation layer 305 may include, for example, at least one of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, but this disclosure is not limited thereto. For ease of description, each device isolation layer 305 is shown as being formed of a single insulating film, but this disclosure is not limited thereto.

[0085] An interlayer insulating layer 310 may be disposed on the upper surface of the substrate 300. In an embodiment, the interlayer insulating layer 310 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0086] The bit line structure BL can be disposed on the substrate 300. For example, the bit line structure BL can be disposed on the upper surface of the interlayer insulating layer 310, or it can be disposed in a portion of the upper part of the substrate 300. The bit line structure BL may include a bit line contact 322, a bit line barrier layer 324, a bit line 326 and a bit line capping layer 328 stacked in sequence.

[0087] Bit line contact 322 can contact an active pattern AC (e.g., a source region). Bit line 326 can be electrically connected to the active pattern AC through bit line contact 322 and bit line blocking layer 324. Bit line contact 322 may include, for example, at least one of doped semiconductor material, conductive silicide compound, conductive metal nitride and / or metal.

[0088] Bit line blocking layer 324 may include a blocking metal such as titanium nitride (TiN). Bit line 326 may include a metal such as tungsten (W). Bit line capping layer 328 may include silicon nitride and / or silicon oxynitride.

[0089] Bit line spacers 340 can be disposed on the side surface of the bit line structure BL. In a bit line structure BL where bit line contacts 322 are formed, the bit line spacers 340 can be formed on the substrate 300 and the device isolation layer 305. In a bit line structure BL where bit line contacts 322 are not formed, the bit line spacers 340 can be disposed on the interlayer insulating layer 310. Bit line spacers 340 can also be disposed on the sidewalls of the bit line structure BL.

[0090] Bit line spacers 340 may be a single-layer film. However, as shown in the figure, bit line spacers 340 may be formed of multiple layers, having a multilayer structure including a first spacer 342 and a second spacer 344. For example, each of the first spacer 342 and the second spacer 344 may include one of silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), air, or combinations thereof, but this disclosure is not limited thereto.

[0091] The buried contact 330 may be disposed between adjacent bit line structures BL in the second direction D2. The buried contact 330 may penetrate a portion of the substrate 300. The buried contact 330 may be electrically connected to the active pattern AC. The buried contact 330 may be electrically connected to the active pattern AC and the capacitor structure CAP. The buried contact 330 may include, for example, at least one of the following: an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, or a metal.

[0092] Landing pad 102a may be formed on buried contact 330. Landing pad 102a may be electrically connected to buried contact 330. Landing pad 102a may be disposed between buried contact 330 and lower electrode BE. By increasing the contact area through landing pad 102a, the contact resistance between active pattern AC and lower electrode BE can be reduced. Landing pad 102a may include, for example, at least one of impurity-doped semiconductor material, conductive silicide compound, conductive metal nitride, conductive metal carbide, metal, or metal alloy.

[0093] refer to Figure 10 The semiconductor memory device according to some embodiments of this disclosure may further include a substrate 400, a lower insulating layer 410, a bit line structure BL, an active pattern 460, a gate electrode 420, a gate insulating layer 430, and buried layers 441 and 442. The semiconductor memory device of this disclosure may be a memory device including a vertical channel transistor (VCT). The vertical channel transistor may be a structure in which the channel length of the active pattern 460 extends in a direction perpendicular to the upper surface of the substrate 400. In embodiments of this disclosure, the conductive pattern 102 (see...) Figure 4 (This can be capacitor contact 102b.)

[0094] The lower insulating layer 410 and the bit line structure BL can be sequentially disposed on the substrate 400. The bit line structure BL can be disposed on the lower insulating layer 410. The bit line structure BL can include multiple conductive lines extending in a second direction D2 and spaced apart in a third direction D3. The bit line structure BL can include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0095] The active pattern 460 can be arranged spaced apart from each other on the bit line structure BL in the second direction D2 and the third direction D3. For example, the bottom of the active pattern 460 can be used as a first source / drain region, the top of the active pattern 460 can be used as a second source / drain region, and the portion between the first source / drain region and the second source / drain region can be used as a channel region.

[0096] Gate electrode 420 may extend in a third direction D3 on a side surface of active pattern 460. Gate electrode 420 may include a first gate electrode 421 facing one side surface of active pattern 460 and a second gate electrode 422 facing the other side surface of active pattern 460. Because an active pattern 460 is disposed between the first gate electrode 421 and the second gate electrode 422, the semiconductor memory device may have a dual-gate transistor structure. However, this disclosure is not limited thereto, and a single-gate transistor structure may also be implemented.

[0097] The gate electrode 420 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the gate electrode 420 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but this disclosure is not limited thereto.

[0098] A gate insulating layer 430 may be disposed on a side surface of the active pattern 460. The gate insulating layer 430 may be interposed between the active pattern 460 and the gate electrode 420. For example, the entire sidewall of the active pattern 460 may be surrounded by the gate insulating layer 430, and a portion of the sidewall of the gate electrode 420 may contact the gate insulating layer 430. For example, the gate insulating layer 430 may comprise silicon oxide, silicon oxynitride, a high-k dielectric having a higher dielectric constant than silicon oxide, or a combination thereof. The high-k dielectric may comprise a metal oxide or a metal oxynitride. For example, high-k dielectrics that can be used as the gate insulating layer 430 may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or combinations thereof, but this disclosure is not limited thereto.

[0099] Buried layers 441 and 442 can be disposed between adjacent active patterns 460 in the second direction D2. The first buried layer 441 can be disposed at the bottom of the space between two adjacent active patterns 460, and the second buried layer 442 can be formed on the first buried layer 441 to fill the remaining space between the two adjacent active patterns 460. The upper surface of the second buried layer 442 can be disposed at the same level as the upper surface of the active pattern 460, and the second buried layer 442 can cover / contact the upper surface of the gate electrode 420. The first buried layer 441 and the second buried layer 442 can be provided as a continuous material layer, for example, provided as a single body in some embodiments.

[0100] Capacitor contact 102b may be disposed on active pattern 460. Capacitor contact 102b may overlap with active pattern 460 in a first direction D1 and be spaced apart from other capacitor contacts in a second direction D2 and a third direction D3. Capacitor contact 102b may comprise doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof, but this disclosure is not limited thereto.

[0101] Figure 11 The layout of a semiconductor memory device according to some embodiments of the present disclosure is shown. Figure 12 and Figure 13 It is shown Figure 11 An enlarged view of a portion of a semiconductor memory device. Figure 14 It shows along Figure 12 or Figure 13 A cross-sectional view of a semiconductor memory device taken by line C-C'. Figure 12 and Figure 13 It can be or can correspond to Figure 11 Region R2. For convenience, explanations and references will be provided. Figures 1 to 5 The parts described are different. For example, unless the context otherwise indicates otherwise. Figures 1 to 5 The parts described in the text also apply to Figures 11 to 14 The illustrated embodiment

[0102] refer to Figure 11 , Figure 12 and Figure 14 In a semiconductor memory device according to some embodiments of the present disclosure, a plurality of lower electrodes BE can be arranged in a honeycomb structure.

[0103] The lower electrode BE can be arranged in a honeycomb structure. For example, the lower electrode BE can be positioned at the center and vertices of a hexagon. For example, six first parts BE_1 of the lower electrode BE can be arranged around one of the first parts BE_1 of the lower electrode BE at equal distances, and the lines connecting the centers of the six first parts BE_1 of the lower electrode BE can form a regular hexagon in a plan view. For example, six second parts BE_2 of the lower electrode BE can be arranged around one of the second parts BE_2 of the lower electrode BE at equal distances, and the lines connecting the six second parts BE_2 of the lower electrode BE can form a regular hexagon in a plan view. The hexagonal structure with the lower electrode BE can be repeated in the second direction D2 and the third direction D3. For example, the lower electrode BE can be arranged in a regular hexagonal structure.

[0104] The first support holes 150H can be spaced apart from each other at a predetermined distance. The second support holes 250H can also be spaced apart from each other at a predetermined distance. Each of the first support holes 150H and the second support holes 250H can be arranged to have a honeycomb structure. For example, six first support holes 150H can be arranged around a first portion BE_1 of the lower electrode BE at the same distance, and the lines connecting the centers of the six first support holes 150H can form a regular hexagon in a plan view. For example, six second support holes 250H can be arranged around a second portion BE_2 of the lower electrode BE at the same distance, and the lines connecting the six second support holes 250H can form a regular hexagon in a plan view.

[0105] Each of the first support hole 150H and the second support hole 250H can have a circular closed curve shape, for example, in a plan view. For example, each of the first support hole 150H and the second support hole 250H can have a circular or elliptical shape. For example, each of the first support hole 150H and the second support hole 250H can have a cylindrical or elliptical cylindrical shape.

[0106] Each of the first support hole 150H and the second support hole 250H can be located at a vertex of a regular hexagon, such that each of the first portions BE_1 is located at the center of the regular hexagon. Each of the first support hole 150H and the second support hole 250H can be located in three adjacent first portions BE_1.

[0107] The distance between the center of each first support hole 150H and the center of each of the plurality of first portions BE_1 adjacent to the first support hole 150H can be the same. The distance between the center of each second support hole 250H and the center of each of the plurality of second portions BE_2 adjacent to the second support hole 250H can be the same.

[0108] Because the second part BE_2 of the plurality of lower electrodes BE is offset from the first part BE_1 of the plurality of lower electrodes BE in the second direction D2, the second support hole 250H can be offset from the first support hole 150H in the second direction D2.

[0109] refer to Figure 13 The first support hole 150H_2 and the second support hole 250H_2 can have the same characteristics as... Figure 12 The first support hole 150H and the second support hole 250H have different shapes. The first support hole 150H_2 and the second support hole 250H_2 can have closed curve shapes including apex corners / vertices. For example, the first support hole 150H_2 and the second support hole 250H_2 can have closed curve shapes composed of three quadrants. For example, in a plan view, the closed curve shape of each of the first support hole 150H_2 and the second support hole 250H_2 can be composed of three quadrants / arcs, all of which bulge towards the center of the first support hole 150H_2 and the second support hole 250H_2, and the two ends of each quadrant / arc are tangent to the adjacent quadrant / arc, thus forming a complete closed curve. In some embodiments, the first support hole 150H_2 and the second support hole 250H_2 can have triangular shapes, for example, in a plan view. For example, each of the first support hole 150H_2 and the second support hole 250H_2 can have a triangular prism shape.

[0110] Figures 15 to 21 This is used to explain the method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure, along with the corresponding Figure 2 or Figure 3 A cross-sectional view taken by line A-A' or B-B'.

[0111] refer to Figure 15 Multiple isolation layers 104 and multiple conductive patterns 102 can be formed on the substrate, and an etch stop layer 110 can be formed on the multiple isolation layers 104 and multiple conductive patterns 102. The multiple isolation layers 104 can be disposed between the multiple conductive patterns 102. The multiple isolation layers 104 can electrically isolate the multiple conductive patterns 102 from each other.

[0112] Subsequently, a first mold layer 120 and a first support pattern 150 can be formed on the etch stop layer 110. The first mold layer 120 and the first support pattern 150 will be described as each comprising three layers as an example.

[0113] The first-1 mold layer 121, the first-1 support layer 151, the first-2 mold layer 122, the first-2 support layer 152, the first-3 mold layer 123, and the first-3 support layer 153 can be stacked sequentially on the etch stop layer 110.

[0114] Next, a plurality of first through holes TH_1 can be formed in the first direction D1, penetrating the first mold layer 120 and the first support pattern 150.

[0115] A plurality of first through holes TH_1 can be formed by removing portions of the first mold layer 120 and the first support pattern 150 to penetrate the first mold layer 120 and the first support pattern 150 in a first direction D1. Each of the plurality of first through holes TH_1 may have a constant horizontal width, for example, in a second direction and / or a third direction. In some embodiments, each of the plurality of first through holes TH_1 may have a tapered shape, wherein the horizontal width narrows in a direction moving from the upper side / end of the first through hole TH_1 toward the lower side / end.

[0116] The first via TH_1 can be formed by a dry etching process, wherein an etching mask is disposed on the first-3 support layer 153, and the portion exposed by the etching mask is removed. For example, the first-3 support layer 153, the first-3 mold layer 123, the first-2 support layer 152, the first-2 mold layer 122, the first-1 support layer 151, and the first-1 mold layer 121 can be removed sequentially, and a portion of the etching stop layer 110 can be removed, thereby exposing multiple conductive patterns 102.

[0117] The first portion BE_1 of the multiple lower electrodes BE can be formed inside the multiple first vias TH_1. The first portion BE_1 can be formed by processes such as CVD, ALD, or PEALD. The first portion BE_1 may include metals such as Ti, W, Ni, or Co, or metal nitrides such as TiN, TiSiN, TiAlN, TaN, TaSiN, or WN.

[0118] After the first portion BE_1 is formed, a planarization process can be performed. Through the planarization process, a portion of the first portion BE_1 and the etching mask in the upper part of the first portion BE_1 can be removed. Through the planarization process, the upper surface of the first portion BE_1 and the upper surface of the first-3 support layer 153 can become coplanar. The side surfaces of the first portion BE_1 can be covered or contacted by the first-3 support layer 153.

[0119] refer to Figure 16A portion of the first support pattern 150 can be removed, exposing a portion of the side surface of the first portion BE_1. For example, an etch-back process can be performed on the first-3 support layer 153. A portion of the first-3 support layer 153 can be selectively removed using the etch selectivity ratio between the first portion BE_1 and the first-3 support layer 153.

[0120] The thickness of the first-3 support layer 153 can be reduced by an etch-back process. Here, the thickness of the first-3 support layer 153 can be defined as the thickness in the first direction D1. As the thickness of the first-3 support layer 153 decreases, a portion of the side surface of the first portion BE_1 can be exposed. For example, a portion of the first portion BE_1 can protrude from the first-3 support layer 153 in the first direction D1.

[0121] refer to Figure 17 and Figure 18 The liner L can be formed on the first portion BE_1 and the remainder of the first support pattern 150.

[0122] The substrate L can be conformally formed using atomic layer deposition methods such as ALD or PEALD. For example, the substrate L can be formed on the side and top surfaces of the columnar first portion BE_1. The substrate L can comprise a material with etch selectivity relative to the first support pattern 150 and the first portion BE_1. For example, the substrate L can comprise silicon oxide. The substrate L can be formed along the surface of the first-3 support layer 153 and along the surface of the first portion BE_1 that protrudes from the first-3 support layer 153. For example, the substrate L can extend along the surfaces of the first-3 support layer 153 and the first portion BE_1 with a first thickness T1.

[0123] The upper surface L_1 of the liner L can be spaced apart from the upper surface of the first portion BE_1 by a first thickness T1. The upper surface L_1 of the liner L can be perpendicular to the first direction D1. For example, the upper surface L_1 of the liner L is located at a higher vertical level than the first portion BE_1 and can be defined as a surface perpendicular to the first direction D1.

[0124] The portions of the liner L formed on the side and top surfaces of the first portions BE_1 adjacent to each other in the second direction D2 and / or the third direction D3 may overlap / merge with each other. The portions of the liner L formed on the side and top surfaces of the first portions BE_1 adjacent to each other in the fourth direction D4 may be spaced apart from each other. A recessed surface L_2 may be formed between the first portions BE_1 adjacent to each other in the fourth direction D4.

[0125] As described above, the liner L may have a recessed surface L_2 formed between the first portions BE_1. In a plan view, the shape of the recessed surface L_2 may be a two-dimensional diagram with edge lines having closed curve shapes in which four quadrants are symmetrically formed. For example, in a plan view, the closed curve shape of the edge lines of the recessed surface L_2 may have the shape of four circular quadrants / arcs, such that each of the four quadrants / arcs protrudes toward the center of the recessed surface L_2 in the plan view, and each quadrant / arc contacts the adjacent quadrant / arc at both ends, so that the four quadrants / arcs together form a closed curve. The thickness of the liner L may be less than half the distance between the side surfaces of the first portions BE_1 that are adjacent to each other in the fourth direction D4. The recessed surface L_2 may be defined by the portion of the liner L disposed on the side surfaces of the adjacent first portions BE_1 and the portion of the liner L disposed on the upper surface of the first-3 support layer 153. In some embodiments, the lower surface of the recessed surface L_2 may be located at the same level as the upper surface of the first portions BE_1.

[0126] A liner L can be formed between adjacent first portions BE_1 in the second direction D2 and / or the third direction D3. The thickness of the liner L can be greater than half the distance between the side surfaces of the adjacent first portions BE_1 in the second direction D2 and / or the third direction D3. Therefore, no recessed surface can be formed between adjacent first portions BE_1 in the second direction D2 and / or the third direction D3. For example, the recessed surface does not overlap with the first portions BE_1 in the second direction D2 and the third direction D3.

[0127] refer to Figure 19 A portion of the liner L can be removed to form an opening OP. Through the opening OP, a portion of the first support pattern 150 can be exposed.

[0128] An etching process can be performed on the substrate L to expose a portion of the first support pattern 150. The etching process can reduce the thickness of the substrate L in the first direction D1. For example, a first thickness T1 can be removed from the substrate L in the first direction D1.

[0129] The upper surface of the first portion BE_1 can be exposed by removing a first thickness T1 of the liner L from its upper surface L_1. An opening OP can be formed by removing the first thickness T1 of the liner L from its recessed surface L_2. The shape of each opening OP can be the same as or substantially the same as the shape of the recessed surface L_2. For example, each opening OP can also have a closed curve shape in which four quadrants are symmetrically formed, for example, in a plan view. For example, in a plan view, the closed curve shape of the edge line of each opening OP can have the shape of four circular quadrants / arcs, such that each of the four quadrants / arcs bulges toward the center of the opening OP in the plan view, and each quadrant / arc contacts the adjacent quadrant / arc at both ends, so that the four quadrants / arcs together form a closed curve. In some embodiments, the opening OP can be formed by etching a circular closed curve shape. For example, the opening OP can have a circular or elliptical shape, for example, in a plan view.

[0130] Through the opening OP, the upper surface of the first-3 support layer 153 can be exposed. A portion of the liner L can remain on the side surface of the first part BE_1. The liner L on the side surface of the first part BE_1 can have a circular shape.

[0131] In embodiments of this disclosure, because the substrate L is formed without the use of separate photoresist and / or mask layers, the first support pattern 150 can be patterned without a photolithography process.

[0132] refer to Figure 20 A portion of the first support pattern 150 can be removed through the opening OP of the liner L to form a first support hole.

[0133] The opening OP of the liner L can expose a portion of the first-3 support layer 153. The portion of the first-3 support layer 153 exposed through the opening OP of the liner L can be removed. For example, a portion of the first-3 support layer 153 can be removed using a dry etching process that uses the liner L as an etching mask to form a first support hole 153H in the first-3 support layer 153.

[0134] Because the liner L has a uniform thickness, the first support hole 153H can be located at the center between the first portions BE_1, for example, at the center between each pair of first portions BE_1 in the fourth direction D4. As described above, the first support hole 153H can be formed in the first-3 support layer 153. The liner L can be removed, or a portion of the first portions BE_1 can be retained, for example, on the first-3 support layer 153, in some embodiments. For example, a portion of the first portions BE_1 can protrude from the upper surface of the first-3 support layer 153. In some embodiments, the first support hole 153H can have a circular shape.

[0135] refer to Figure 21 The first-3 mold layer 123 can be removed through the first support hole 153H. The first-3 mold layer 123 can be removed by a wet etching process. When the first-3 mold layer 123 is removed by a wet etching process, the first-2 support layer 152 can be exposed.

[0136] By repeating this process, the first-2 support hole 152H and the first-1 support hole 151H can be formed sequentially. Specifically, by performing a dry etching process using the first-3 support layer 153 as an etching mask, the first-2 support hole 152H can be formed in the first-2 support layer 152. For example, a portion of the first-2 support layer 152 exposed through the first support hole 153H can be removed.

[0137] Subsequently, by performing a wet etching process via the first-2 support hole 152H, the first-2 mold layer 122 can be removed, and the upper surface of the first-1 support layer 151 can be exposed. By performing a dry etching process using the first-2 support layer 152 and the first-3 support layer 153 as etching masks, the first-1 support hole 151H can be formed in the first-1 support layer 151. For example, a portion of the first-1 support layer 151 exposed through the first-2 support hole 152H and the first-3 support hole 153H can be removed. By performing a wet etching process via the first-1 support hole 151H, the first-1 mold layer 121 can be removed, and the etch stop layer 110 can be exposed.

[0138] Because the first-2 support hole 152H is formed by performing a dry etching process via the first-3 support hole 153H, the first-2 support hole 152H can be formed at a position aligned with the first-3 support hole 153H in the first direction D1. Furthermore, because the first-1 support hole 151H is formed by performing a dry etching process via the first-2 support hole 152H and the first-3 support hole 153H, the first-1 support hole 151H can be formed at a position aligned with the first-2 support hole 152H and the first-3 support hole 153H in the first direction D1. For example, the first to third support holes 151H, 152H, and 153H can overlap each other perpendicularly.

[0139] Figures 22 to 26 This is used to explain the method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure, along with the corresponding Figure 2 or Figure 3 A cross-sectional view taken from line B-B'. For convenience, explanations and references are provided. Figures 15 to 21 The parts described are different from the parts described. For example, with Figures 15 to 21 Related descriptions. Figures 15 to 21 This can also be applied to this embodiment, unless the context otherwise requires.

[0140] refer to Figure 22 The first mold layer 120 and the first support pattern 150 can be formed on the etch stop layer. For example, the first-1 mold layer 121, the first-1 support layer 151, the first-2 mold layer 122, the first-2 support layer 152 and the first-3 mold layer 123 can be stacked sequentially on the etch stop layer 110.

[0141] Then, can be with Figure 15 The through holes shown are similarly formed in a plurality of first through holes that penetrate the first mold layer 120 and the first support pattern 150 in the first direction D1.

[0142] The first via can be formed by a dry etching process, wherein an etching mask is disposed on the first-3 mold layer 123, and the portion exposed by the etching mask is removed. For example, the first-3 mold layer 123, the first-2 support layer 152, the first-2 mold layer 122, the first-1 support layer 151, and the first-1 mold layer 121 can be removed sequentially, and a portion of the etching stop layer 110 can be removed, thereby exposing the plurality of conductive patterns 102.

[0143] Next, the first portion BE_1 of the plurality of lower electrodes BE can be formed inside the plurality of first vias. After forming the first portion BE_1, a planarization process can be performed. Through the planarization process, the first portion BE_1 and a portion of the etching mask in the upper part of the first portion BE_1 can be removed. Through the planarization process, the upper surface of the first portion BE_1 and the upper surface of the first-3 mold layer 123 can become coplanar. The side surfaces of the first portion BE_1 can be covered by the first-3 mold layer 123.

[0144] refer to Figure 23 This process can remove a portion of the first stencil layer 120, exposing a portion of the side surface of the first portion BE_1. For example, an etch-back process can be performed on the first-3 stencil layer 123. A portion of the first-3 stencil layer 123 can be selectively removed using the etch selectivity ratio between the first portion BE_1 and the first-3 stencil layer 123.

[0145] The thickness of the first-3 mold layer 123 can be reduced by an etch-back process. Here, the thickness of the first-3 mold layer 123 can be defined as the thickness in the first direction D1. As the thickness of the first-3 mold layer 123 decreases, a portion of the side surface of the first portion BE_1 can be exposed. For example, a portion of the first portion BE_1 can protrude from the first-3 mold layer 123 in the first direction D1.

[0146] refer to Figure 24 The first-3 support layer 153 can be formed on the exposed first portion BE_1 and the remaining portion of the first module layer 120.

[0147] The first-3 support layer 153 may be conformally formed using an atomic layer deposition method such as ALD or PEALD. The first-3 support layer 153 may comprise the same material as the first support pattern 150 (e.g., the first-1 support layer 151 and the first-2 support layer 152). The first-3 support layer 153 may comprise a material with etch selectivity relative to the first mold layer 120 and the first portion BE_1. For example, the first-3 support layer 153 may comprise at least one of silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), or tantalum oxide (TaO). The first-3 support layer 153 may be formed along the surface of the first-3 mold layer 123 and along the surface of the first portion BE_1 protruding from the first-3 mold layer 123. For example, the first-3 support layer 153 may extend along the surfaces of the first-3 mold layer 123 and the first portion BE_1 with a first thickness T1.

[0148] The portions of the first-3 support layers 153 formed on the side and top surfaces of the first portions BE_1 adjacent to each other in the fourth direction D4 can be spaced apart from each other. A recessed surface 153_2 can be formed between the first portions BE_1 adjacent to each other in the fourth direction D4. In a plan view, the shape of the recessed surface 153_2 can be a two-dimensional diagram with edge lines having closed curve shapes in which four quadrants are symmetrically formed. For example, in a plan view, the closed curve shape of the edge lines of the recessed surface 153_2 can have the shape of four circular quadrants / arcs, such that each of the four quadrants / arcs protrudes towards the center of the recessed surface 153_2 in the plan view, and each quadrant / arc contacts the adjacent quadrant / arc at both ends, so that the four quadrants / arcs together form a closed curve.

[0149] refer to Figure 25 A portion of the first-3 support layer 153 can be removed to form the first support hole 153H. For example, an etch-back process can be performed on the first-3 support layer 153. The etch-back process can reduce the thickness of the first-3 support layer 153 in the first direction D1. For example, a first thickness T1 can be removed from the first-3 support layer 153 in the first direction D1.

[0150] By removing the first-3 support layer 153 of a first thickness T1 from its upper surface 153_1, the upper surface of the first portion BE_1 can be exposed. By removing the first-3 support layer 153 of a first thickness T1 from its recessed surface 153_2, a first support hole 153H can be formed. Through the first support hole 153H, the upper surface of the first-3 mold layer 123 can be exposed. In some embodiments, the side surfaces of the first-3 support layer 153 may have a circular shape.

[0151] In embodiments of this disclosure, since the first-3 support layer 153 is formed without the use of separate photoresist and / or mask layers, the first support pattern 150 can be patterned without a photolithography process.

[0152] refer to Figure 26 The first mold layer 120 can be removed through the first support holes 151H, 152H and 153H, and the first-2 support holes 152H and the first-1 support hole 151H can be formed as an example.

[0153] The first-3 mold layer 123 can be removed through the first support hole 153H. The first-3 mold layer 123 can be removed by a wet etching process. When the first-3 mold layer 123 is removed by a wet etching process, the upper surface of the first-2 support layer 152 can be exposed.

[0154] Subsequently, a first-2 support hole 152H can be formed in the first-2 support layer 152 using a dry etching process. The first-2 mold layer 122 can be removed through the first-2 support hole 152H, and a first-1 support hole 151H can be formed in the first-1 support layer 151, through which the first-1 mold layer 121 can be removed.

[0155] According to the manufacturing method of the embodiment, since the first-3 support layer 153 is formed after the first portion BE_1 is formed, the length of the first portion BE_1 in the first direction D1 can be increased. For example, the length of the first portion BE_1 in the first direction D1 can be increased by a first thickness T1. Therefore, a semiconductor memory device including a capacitor structure with improved capacitance can be manufactured, for example, at a lower manufacturing cost.

[0156] Figures 27 to 29 This is used to explain the method of manufacturing a semiconductor memory device according to some embodiments of the present disclosure, along with the corresponding Figure 2 or Figure 3 A cross-sectional view taken from line B-B'.

[0157] refer to Figure 27 The sacrificial layer 125 can be filled through the first support holes 151H, 152H, and 153H. For example, the sacrificial layer 125 may include silicon oxide. The sacrificial layer 125 may be disposed on the side surface of the first portion BE_1 and on the surface of the first support pattern 150. The upper surface of the sacrificial layer 125 may be coplanar with the upper surface of the first-3 support layer 153 and the upper surface of the first portion BE_1. After forming the sacrificial layer 125, a planarization process may be performed.

[0158] The second mold layer 220 and the second support pattern 250 can be formed on the first portion BE_1 and the first-3 support layer 153. The second mold layer 220 and the second support pattern 250 will be described as each comprising three layers. For example, the second-1 mold layer 221, the second-1 support layer 251, the second-2 mold layer 222, the second-2 support layer 252, the second-3 mold layer 223, and the second-3 support layer 253 can be sequentially stacked on the first portion BE_1 and the first-3 support layer 153.

[0159] Subsequently, a plurality of second through holes TH_2 can be formed in the first direction D1, penetrating the second mold layer 220 and the second support pattern 250. The method for forming the plurality of second through holes TH_2 can be the same as or substantially the same as the method for forming the plurality of first through holes TH_1.

[0160] Multiple second through holes TH_2 may be misaligned with multiple first through holes TH_1. Multiple second through holes TH_2 may at least partially overlap with multiple first through holes TH_1 in a first direction D1, and may be offset in a second direction D2.

[0161] A second portion BE_2 of the plurality of lower electrodes BE can be formed inside a plurality of second vias TH_2. The second portion BE_2 can be formed by processes such as CVD, ALD, or PEALD. The second portion BE_2 may include the same material as the first portion BE_1. For example, the second portion BE_2 may include metals such as Ti, W, Ni, or Co, or metal nitrides such as TiN, TiSiN, TiAlN, TaN, TaSiN, or WN.

[0162] Next, after forming the second part BE_2, a planarization process can be performed. Through the planarization process, the upper surface of the second part BE_2 and the upper surface of the second-3 support layer 253 can become coplanar. The side surfaces of the second part BE_2 can be covered or contacted by the second-3 support layer 253.

[0163] A portion of the second support pattern 250 can be removed, exposing a portion of the side surface of the second portion BE_2. For example, an etch-back process can be performed on the second-third support layer 253. A portion of the second-third support layer 253 can be selectively removed using the etch selectivity ratio between the second portion BE_2 and the second-third support layer 253.

[0164] The thickness of the second-3 support layer 253 can be reduced by an etching process. Here, the thickness of the second-3 support layer 253 can be defined as the thickness in the first direction D1. As the thickness of the second-3 support layer 253 decreases, a portion of the side surface of the second part BE_2 can be exposed. For example, a portion of the second part BE_2 can protrude from the second-3 support layer 253 in the first direction D1.

[0165] The liner L can be formed on the protruding second portion BE_2 and the remainder of the second support pattern 250.

[0166] The substrate L can be conformally formed using an atomic layer deposition method such as ALD or PEALD. The substrate L can comprise a material with etch selectivity relative to the second support pattern 250 and the second portion BE_2. For example, the substrate L can comprise silicon oxide. The substrate L can be formed along the surface of the second-third support layer 253 and along the surface of the second portion BE_2 that protrudes from the second-third support layer 253. For example, the substrate L can extend along the surfaces of the second-third support layer 253 and the second portion BE_2 with a first thickness T1.

[0167] refer to Figure 28 A portion of the liner L can be removed to form an opening OP. Through the opening OP, a portion of the second support pattern 250 can be exposed.

[0168] To expose a portion of the second support pattern 250, a back etching process can be performed on the liner L. The back etching process can reduce the thickness of the liner L in the first direction D1.

[0169] By removing a portion of the liner L of thickness T1 from its upper surface L_1, the upper surface of the second portion BE_2 can be exposed. An opening OP can be formed by removing the portion of the liner L of thickness T1 from its recessed surface L_2. Through the opening OP, the upper surface of the second-third support layer 253 can be exposed. A portion of the liner L can remain on the side surface of the second portion BE_2. The liner L on the side surface of the second portion BE_2 can have a circular shape.

[0170] In embodiments of this disclosure, because the substrate L is formed without the use of separate photoresist and / or mask layers, the second support pattern 250 can be patterned without a photolithography process. In some embodiments, the second support pattern 250 can be patterned by not forming a substrate and using photoresist and / or mask layers.

[0171] refer to Figure 29 A portion of the second support pattern 250 can be removed through the opening OP of the liner L to form a second support hole.

[0172] The opening OP of the liner L can expose a portion of the second-3 support layer 253. The portion of the second-3 support layer 253 exposed through the opening OP of the liner L can be removed. For example, a portion of the second-3 support layer 253 can be removed using a dry etching process that uses the liner L as an etching mask to form a second support hole 253H in the second-3 support layer 253. Because the liner L has a uniform thickness, the second support hole 253H can be located at the center between the second portions BE_2. As described above, the second support hole 253H can be formed in the second-3 support layer 253. The liner L can be removed, or a portion of the second portion BE_2 can remain on top of the second-3 support layer 253. That is, a portion of the second portion BE_2 can protrude from the upper surface of the second-3 support layer 253. In some embodiments, each second support hole 253H can have a circular shape.

[0173] The second-3 mold layer 223 can be removed through the second support hole 253H. The second-3 mold layer 223 can be removed by a wet etching process. When the second-3 mold layer 223 is removed by the wet etching process, the second-2 support layer 252 can be exposed. Subsequently, the second-2 support hole 252H can be formed by a dry etching process, and the second-2 mold layer 222 can be removed by a wet etching process. By repeating this process, the second-1 support hole 251H can be formed, and the second-1 mold layer 221 and the sacrificial layer 125 can be removed by a wet etching process.

[0174] Subsequently, a dielectric layer CIL and an upper electrode UE can be deposited sequentially through the first support holes 151H, 152H, 153H and the second support holes 251H, 252H, 253H to form a capacitor structure.

[0175] Although the invention has been described with reference to limited embodiments and drawings, it is not limited thereto, and various modifications and changes can be made by those skilled in the art without departing from the spirit of the invention and within the equivalent scope of the patent claims described below.

Claims

1. A semiconductor memory device, comprising: Substrate; A plurality of lower electrodes, each of the plurality of lower electrodes comprising a first portion and a second portion, the first portion being on the substrate and extending in a first direction perpendicular to the upper surface of the substrate, and the second portion being stacked on the first portion and extending in the first direction; A first support pattern surrounds the sidewall of the first portion of each of the plurality of lower electrodes and includes a plurality of first support holes; A second support pattern surrounds the sidewall of the second portion of each of the plurality of lower electrodes and includes a plurality of second support holes; A dielectric layer is formed on the plurality of lower electrodes, the first support pattern, and the second support pattern; and The upper electrode covers the dielectric layer. The second part overlaps with a portion of the first part in the first direction and is offset from the first part in a second direction perpendicular to the first direction.

2. The semiconductor memory device according to claim 1, wherein, Each of the plurality of second support holes is offset from each of the plurality of first support holes in the second direction.

3. The semiconductor memory device according to claim 1, wherein, Each of the plurality of first support holes is located between the first portions of the plurality of lower electrodes adjacent to a corresponding one of the plurality of first support holes, and Each of the plurality of second support holes is located between the second portions of the plurality of lower electrodes adjacent to a corresponding one of the plurality of second support holes.

4. The semiconductor memory device according to claim 3, wherein, In the plan view, the distance between the center of each of the plurality of first support holes and the center of each first portion of the plurality of adjacent lower electrodes in the plurality of first support holes is the same, and The distance between the center of each of the plurality of second support holes and the center of each of the plurality of second portions of the plurality of lower electrodes adjacent to the corresponding second support hole is the same.

5. The semiconductor memory device according to claim 2, wherein, In the plan view, each of the plurality of first support holes and the plurality of second support holes has a circular shape.

6. The semiconductor memory device according to claim 1, wherein, The top of the first support pattern is located at the same vertical level as the top of the first portion of each of the plurality of lower electrodes, and The top of the second support pattern is located at the same vertical level as the top of the second portion of each of the plurality of lower electrodes.

7. The semiconductor memory device according to claim 1, wherein, The top of the first portion of each of the plurality of lower electrodes is located at a higher vertical level than the top of the first support pattern.

8. The semiconductor memory device according to claim 1, wherein, The first support pattern includes a first curved portion, and The first curved portion protrudes toward the second support pattern.

9. The semiconductor memory device according to claim 8, wherein, The second support pattern includes a second curved portion, and The second curved portion protrudes in a direction away from the first support pattern.

10. The semiconductor memory device according to claim 1, wherein, Each of the plurality of lower electrodes has a columnar shape.

11. The semiconductor memory device according to claim 1, wherein, The first support pattern further includes multiple first support layers located at different vertical levels, and the second support pattern further includes multiple second support layers located at different vertical levels. The plurality of first support layers include first support holes aligned in the first direction, and the plurality of second support layers include second support holes aligned in the first direction.

12. The semiconductor memory device according to claim 11, wherein, The first support hole is offset from the second support hole in the second direction.

13. The semiconductor memory device according to claim 11, wherein, The plurality of first support layers include a first-1 support layer, a first-2 support layer located at a higher vertical level than the first-1 support layer, and a first-3 support layer located at a higher vertical level than the first-2 support layer; The plurality of second support layers include a second-1 support layer, a second-2 support layer located at a higher vertical level than the second-1 support layer, and a second-3 support layer located at a higher vertical level than the second-2 support layer; The upper surface of the first-3 support layer is located at the same vertical level as the upper surface of the first portion of each of the plurality of lower electrodes; and The upper surface of the second-3 support layer is located at the same vertical level as the upper surface of the second portion of each of the plurality of lower electrodes.

14. The semiconductor memory device according to claim 1, wherein, In the plan view, the first portions of the plurality of lower electrodes are arranged with a first grid pattern, wherein the first portions are spaced apart by a first pitch in the second direction and in a third direction perpendicular to the first and second directions, and The plurality of first support holes are arranged in a second grid pattern, wherein each of the plurality of first support holes is spaced apart from the adjacent first support holes in the second direction and the third direction by the first pitch, and is located at the center between four adjacent first portions of the plurality of lower electrodes.

15. The semiconductor memory device according to claim 1, wherein, The first portions of the plurality of lower electrodes are arranged in a honeycomb structure, wherein each first portion is located at the center and vertex of a hexagon, and Each of the plurality of first support holes is located at the center of three adjacent first portions of the plurality of lower electrodes.

16. A semiconductor memory device, comprising: Substrate, including active patterning; Multiple conductive patterns are disposed on the active pattern; Multiple lower electrodes are electrically connected to the multiple conductive patterns, respectively; Multiple support patterns support the multiple lower electrodes. A dielectric layer is formed on the plurality of lower electrodes and the plurality of support patterns; and The upper electrode covers the dielectric layer. Each of the plurality of lower electrodes includes: The first portion extends in a first direction perpendicular to the upper surface of the substrate; and The second part is stacked on top of the first part and extends in the first direction. The plurality of support patterns include: A first support pattern surrounds the sidewall of the first portion and includes a plurality of first support holes; and A second support pattern surrounds the sidewall of the second portion and includes a plurality of second support holes. Each second portion overlaps with a corresponding first portion in the first direction and is offset from the first portion by a first distance in a second direction perpendicular to the first direction. Each of the plurality of second support holes is offset from the corresponding one of the plurality of first support holes by the first distance in the second direction.

17. The semiconductor memory device according to claim 16, wherein, The top surface of the first support pattern contacts the bottom surface of the second part.

18. The semiconductor memory device according to claim 16, wherein, In the plan view, a plurality of first portions are arranged to form a grid pattern, wherein the first portions are spaced apart at constant intervals along the second direction and a third direction perpendicular to the first and second directions, and The plurality of first portions and the plurality of first support holes are arranged alternately along a fourth direction that forms a predetermined angle with each of the second direction and the third direction.

19. The semiconductor memory device according to claim 18, wherein, Each of the plurality of first support holes is spaced apart in the fourth direction from the first portion of the plurality of lower electrodes adjacent to a corresponding one of the plurality of first support holes.

20. A semiconductor memory device, comprising: Substrate; A plurality of lower electrodes, each of the plurality of lower electrodes comprising a first portion and a second portion, the first portion being on the substrate and extending in a first direction perpendicular to the upper surface of the substrate, and the second portion being stacked on the first portion and extending in the first direction; A first support pattern includes a plurality of first support layers, in which a first support hole pattern is formed including first support holes aligned and spaced apart in the first direction, the first support pattern surrounding the sidewall of the first portion of each of the plurality of lower electrodes. The second support pattern includes a plurality of second support layers, in which a second support hole pattern is formed including second support holes aligned and spaced apart in the first direction, the second support pattern surrounding the sidewall of the second portion of each of the plurality of lower electrodes; A dielectric layer is formed on the plurality of lower electrodes, the first support pattern, and the second support pattern; and The upper electrode is located on the dielectric layer. The second part overlaps with a portion of the first part in the first direction. The second part is offset from the first part in a second direction perpendicular to the first direction, and The plurality of first support holes and the plurality of second support holes are offset in the second direction.

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