Semiconductor device and manufacturing method thereof, and memory device and manufacturing method thereof

Abstract

The application provides a semiconductor device and a manufacturing method thereof and a memory device and a manufacturing method thereof, relates to the technical field of semiconductor, and aims to solve the problem that the traditional device structure is difficult to effectively compress the layer spacing in the vertical orientation while suppressing the floating body effect. The semiconductor device comprises a horizontally oriented active layer, a word line electrode and a back gate electrode, the active layer has a source region and a drain region; the active layer forms a first gate control region and a second gate control region at two ends in the vertical orientation respectively, and the first gate control region and the second gate control region are arranged alternately in the vertical orientation; the word line electrode is arranged in the first gate control region and supports the active layer; the back gate electrode is arranged in the second gate control region and supports the active layer, and the back gate electrode is electrically isolated from the word line electrode. The semiconductor device can reduce the layer spacing in the vertical orientation while suppressing the floating body effect.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a method for manufacturing the same, and a memory device and a method for manufacturing the same. Background Technology

[0002] 3D DRAM (3D Dynamic Random-Access Memory) is a dynamic random-access memory technology that breaks through the limitations of traditional planar memory architecture. It solves density bottlenecks and process challenges by vertically stacking storage capacitors and transistors instead of simply miniaturizing them in a two-dimensional plane.

[0003] In 3D DRAM, the channels of access transistors are typically completely surrounded by an insulating layer to achieve physical and electrical isolation from the substrate, forming a floating "body" region. During device operation, especially during the pre-charge phase of the bit lines, gate-drain leakage generates electron-hole pairs, with holes accumulating in the floating body region. These accumulated holes raise the body potential, causing the threshold voltage of the access transistor to drift and the current to become unstable. More seriously, the accumulated holes provide base bias for parasitic NPN bipolar transistors. During read operations or voltage transitions, these parasitic NPN bipolar transistors are triggered to turn on momentarily, generating a sharp leakage current spike. This causes the charge stored in the capacitor to drain rapidly, severely degrading data retention time and noise immunity.

[0004] Currently, gate-around structures are typically used to enhance channel control, or ultra-thin designs are employed to reduce hole accumulation space. However, gate-around structures lack independent body potential adjustment terminals, making their suppression of the floating body effect passive; while ultra-thin designs are extremely sensitive to process variations, making it difficult to guarantee uniformity in hundreds of layers. Furthermore, as the number of stacked layers increases, the interlayer spacing in the vertical orientation becomes a key factor limiting integration density, and traditional device structures struggle to effectively compress the interlayer spacing in the vertical orientation while suppressing the floating body effect. Summary of the Invention

[0005] The first aspect of this application aims to provide a semiconductor device that solves the technical problem that traditional device structures are unable to effectively compress the interlayer spacing in the vertical orientation while suppressing the floating body effect.

[0006] The semiconductor device provided in the first aspect of this application includes: A horizontally oriented active layer has a source region and a drain region; the active layer forms a first gate control region and a second gate control region at both ends of the vertical orientation, and the first gate control region and the second gate control region are alternately arranged in the vertical orientation; Word line electrodes are disposed in the first gate control region and support the active layer; and A back gate electrode is disposed in the second gate control region and supports the active layer, and the back gate electrode is electrically isolated from the word line electrode.

[0007] Furthermore, the size of the first gate control region in the vertical orientation is larger than the size of the second gate control region in the vertical orientation.

[0008] Furthermore, the first gate control region is provided with two word line electrodes, which are separated by a first dielectric layer in the vertical orientation and by a second dielectric layer in the horizontal orientation. The first dielectric layer is made of an oxide, and the second dielectric layer is made of a nitride.

[0009] Furthermore, the material of the back gate electrode is titanium nitride.

[0010] The beneficial effects of the semiconductor device proposed in this application are: In this semiconductor device, a first gate control region and a second gate control region are formed at both ends of the active layer in a vertical orientation, with the active layer as the boundary. A word line electrode supporting the active layer is disposed in the first gate control region, and a back gate electrode supporting the active layer is disposed in the second gate control region. The word line electrode and the back gate electrode are electrically isolated, forming a body contact between the active layer and the word line electrode and the back gate electrode. By applying a fixed bias voltage to the back gate electrode, a potential reference point can be provided for the originally floating channel body region. This allows for the active extraction of accumulated holes, rapidly discharging excess holes or electrons generated by collisional ionization, stabilizing the body region potential, and actively suppressing the floating body effect. This solves the threshold voltage drift problem and extends the data retention time. The word line electrode serves as the main control gate. Furthermore, the back gate electrode, which is independent of the word line electrode, can serve as an additional control terminal. During semiconductor device testing or operation, the voltage of the back gate electrode can be finely adjusted to compensate for threshold voltage deviations caused by process fluctuations. In other words, even if there are slight differences in the performance of the manufactured semiconductor devices, the bias voltage of the back gate electrode can be adjusted to bring them closer to the normal range, effectively improving the uniformity and yield of semiconductor devices.

[0011] By placing the back gate electrode and word line electrode at opposite ends of the active layer in the vertical orientation, the semiconductor device forms a "single-sided main gate + single-sided back gate" layout. Compared to the traditional device structure that fully surrounds the channel body region, this setup does not require the gate material to completely enclose the channel body region. It only needs to reserve a thin space for the back gate electrode, which can significantly reduce the vertical orientation layer spacing. This allows for the stacking of more memory layers without changing the overall device height, greatly improving the memory density.

[0012] The second aspect of this application aims to provide a storage device that solves the technical problem that traditional device structures are unable to effectively compress the interlayer spacing in the vertical orientation while suppressing the floating body effect.

[0013] The memory device provided in the second aspect of this application includes a vertically oriented bit line, a data storage cell separated from the bit line by the horizontal orientation, and the aforementioned semiconductor device, wherein a first isolation layer is disposed between the back gate electrode and the bit line; and a second isolation layer is disposed between the back gate electrode and the data storage cell.

[0014] The beneficial effects of the storage device in this application are: By incorporating the aforementioned semiconductor device into the storage device, the storage device thereby possesses all the advantages of the aforementioned semiconductor device, which will not be elaborated upon here.

[0015] The third aspect of this application aims to provide a method for manufacturing a semiconductor device to solve the technical problem that traditional device structures are unable to effectively compress the interlayer spacing in the vertical orientation while suppressing the floating body effect.

[0016] The method for manufacturing a semiconductor device provided in the third aspect of this application includes: A substrate is provided, the substrate including a substrate and a plurality of stacked structures disposed on the substrate, the stacked structures including sacrificial layers and channel layers alternately stacked in sequence along a direction away from the substrate; The plurality of stacked structures are longitudinally etched to form a first deep trench. Lateral etching is performed on the first deep trench to form a first gate control region and a second gate control region that are alternately arranged in the vertical orientation, and to form an active layer with gradually increasing thickness in part of the channel layer. A word line electrode is formed in the first gate control region; a back gate electrode is formed in the second gate control region.

[0017] Furthermore, the step of forming word line electrodes in the first gate control region includes: forming two word line electrodes in the first gate control region that are vertically separated by a first dielectric layer and horizontally separated by a second dielectric layer.

[0018] Further, the steps of forming two word line electrodes in the first gate control region, separated by a first dielectric layer in a vertical orientation and separated by a second dielectric layer in a horizontal orientation, and forming a back gate electrode in the second gate control region, include: A nitride layer is deposited in the first deep trench so that the first gate control region is partially filled with the nitride layer in the vertical orientation, and the second gate control region is completely filled with the nitride layer in the vertical orientation. A first dielectric layer is deposited in the region of the first gate control region that is not filled by the nitride layer, and the nitride layer of the first gate control region and the second gate control region is exposed; Laterally etch the first deep trench to remove part of the nitride layer in the first gate control region and the second gate control region, and expose the active layer; A conductive material layer is deposited in the first gate control region and the second gate control region to form two word line electrodes in the first gate control region that are vertically separated by the first dielectric layer, and a back gate electrode is formed in the second gate control region. A nitrogen-oxygen isolation layer is deposited in the first gate control region, and the nitrogen-oxygen isolation layer and the nitride layer in the first gate control region together form the second dielectric layer.

[0019] Furthermore, it also includes: depositing an oxide layer in the first deep trench such that any two adjacent active layers in the vertical orientation are separated by the oxide layer, and the active layers are exposed.

[0020] Furthermore, it also includes: doping the active layer to form a source region and a drain region at both ends of the active layer along the horizontal orientation, respectively; Bit lines are epitaxially grown outside the source region; The data storage unit is formed in the drain region, wherein the step of forming the data storage unit includes: longitudinally etching the plurality of stacked structures to form a second deep trench, the second deep trench being spaced apart from the first deep trench in the horizontal orientation, and sequentially depositing a bottom electrode, a high dielectric constant dielectric layer, a top electrode and a filling layer in the second deep trench.

[0021] Furthermore, the stacked structure includes a first sacrificial layer, a first channel layer, a second sacrificial layer, a second channel layer, a third sacrificial layer, and a third channel layer stacked sequentially along a direction away from the substrate, wherein the thickness of the first channel layer is greater than the thickness of the second channel layer, and the thickness of the third channel layer is greater than the thickness of the second channel layer.

[0022] The beneficial effects of the semiconductor device manufacturing method of this application are: In this semiconductor device manufacturing method, word line electrodes are formed in the first gate control region and back gate electrodes are formed in the second gate control region. Compared to a fully all-around gate transistor, the single-sided back gate structure obtained by this manufacturing method occupies less vertical space, thereby allowing more memory layers to be stacked in the same height space to increase the memory capacity per unit area. At the same time, this manufacturing method only requires adding a back gate electrode formation step, without introducing new and complex process modules or overhauling existing production lines, thus reducing the risk and cost of technology iteration.

[0023] The fourth aspect of this application aims to provide a method for manufacturing a storage device to solve the technical problem that traditional device structures are unable to effectively compress the interlayer spacing in the vertical orientation while suppressing the floating body effect.

[0024] The method for manufacturing a storage device provided in the fourth aspect of this application includes: Semiconductor devices are manufactured using the semiconductor device manufacturing method described above; A first isolation layer, a back gate electrode, and a second isolation layer are formed in the second gate control region in a horizontal orientation, wherein the first isolation layer is formed by deposition in the second gate control region, and the second isolation layer is formed by removing part of the nitride layer in the second gate control region; Bit lines that are electrically connected to each of the active layers are formed in the first deep trench.

[0025] The beneficial effects of the manufacturing method of the storage device in this application are: This configuration achieves physical isolation between the back gate electrode and the word line electrode, effectively preventing mutual interference between them during operation. Furthermore, in the manufacturing method of this memory device, a single etching process not only fully exposes the active layer in both the first and second gate control regions, but also forms a second isolation layer of the required thickness in the second gate control region. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments or background art of this application, the drawings used in the description of the embodiments or background art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0027] Figure 1 This is a cross-sectional view of a semiconductor device manufacturing method according to an embodiment of the present application, in which multiple stacked structures, an oxide layer, and a nitride layer are sequentially formed on a substrate. Figure 2 A cross-sectional view of the structure formed by etching a first deep trench, a second deep trench, a first gate control region, and a second gate control region according to the manufacturing method of the semiconductor device provided in the embodiments of this application; Figure 3 This is a cross-sectional view of the structure of a semiconductor device manufacturing method according to an embodiment of this application, wherein a nitride layer is partially filled in the first gate control region and a nitride layer is completely filled in the second gate control region. Figure 4 This is a cross-sectional view of the structure of a semiconductor device manufacturing method according to an embodiment of the present application, in which word line electrodes are formed in a first gate control region and a back gate electrode is formed in a second gate control region. Figure 5 A structural cross-sectional view of the storage device provided in an embodiment of this application; Figure 6 A flowchart illustrating a method for manufacturing a semiconductor device as provided in an embodiment of this application; Figure 7 A flowchart illustrating a method for manufacturing a storage device according to an embodiment of this application.

[0028] Explanation of reference numerals in the attached figures: 100 - Bit line; 110 - First conductive layer; 120 - Second conductive layer; 130 - Oxide layer; 200 - Data storage unit; 210 - Bottom electrode; 220 - High dielectric constant dielectric layer; 230 - Top electrode; 240 - Filling layer; 300 - Active layer; 310 - Source region; 311 - Source; 312 - Bit line node contact; 313 - Bit line ohmic contact layer; 320 - Drain region; 321 - Drain; 322 - Memory node contact; 323 - Memory ohmic contact layer; 301 - First gate control region; 302 - Second gate control region; 400 - Word line electrode; 410 - First dielectric layer; 420 - Second dielectric layer; 500 - Back gate electrode; 510 - First isolation layer; 520 - Second isolation layer; 610 - Substrate; 620 - Stacked structure; 621 - First sacrificial layer; 622 - First channel layer; 623 - Second sacrificial layer; 624 - Second channel layer; 625 - Third sacrificial layer; 626 - Third channel layer; 630 - First deep trench; 640 - Second deep trench; 650 - Oxide layer; 660 - Nitride layer; 710 - Nitride layer; 720 - Nitrogen-oxygen barrier layer. Detailed Implementation

[0029] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0030] like Figure 5As shown, this embodiment provides a semiconductor device including a horizontally oriented active layer 300, a word line electrode 400, and a back gate electrode 500. The active layer 300 has a source region 310 and a drain region 320. A first gate control region 301 and a second gate control region 302 are formed at both ends of the active layer 300 in a vertical orientation, and the first gate control region 301 and the second gate control region 302 are arranged alternately in the vertical orientation. The word line electrode 400 is disposed in the first gate control region 301 and supports the active layer 300. The back gate electrode 500 is disposed in the second gate control region 302 and supports the active layer 300, and the back gate electrode 500 is electrically isolated from the word line electrode 400.

[0031] In this semiconductor device, a first gate control region 301 and a second gate control region 302 are formed vertically at both ends of the active layer 300, with the active layer 300 as the boundary. A word line electrode 400 supporting the active layer 300 is disposed in the first gate control region 301, and a back gate electrode 500 supporting the active layer 300 is disposed in the second gate control region 302. The word line electrode 400 and the back gate electrode 500 are electrically isolated, forming a body contact between the active layer 300, the word line electrode 400, and the back gate electrode 500. By applying a fixed bias voltage to the back gate electrode 500, a potential reference point can be provided for the originally floating channel body region. This allows for the active extraction of accumulated holes, rapidly discharging excess holes or electrons generated by collisional ionization, stabilizing the body region potential, and actively suppressing the floating body effect. This solves the threshold voltage drift problem and extends the data retention time. The word line electrode 400 serves as the main control gate. Furthermore, the back gate electrode 500, which is independent of the word line electrode 400, can serve as an additional control terminal. During semiconductor device testing or operation, the voltage of the back gate electrode 500 can be finely adjusted to compensate for threshold voltage deviations caused by process fluctuations. In other words, even if there are slight differences in the performance of the manufactured semiconductor devices, the bias voltage of the back gate electrode 500 can be adjusted to bring them closer to the normal range, effectively improving the uniformity and yield of semiconductor devices.

[0032] By distributing the back gate electrode 500 and the word line electrode 400 at opposite ends of the active layer 300 in the vertical orientation, the semiconductor device forms a "single-sided main gate + single-sided back gate" layout. Compared to the traditional device structure that fully surrounds the channel body region, this arrangement does not require the gate material to completely enclose the channel body region. It only needs to reserve a thin space for the back gate electrode 500, which can significantly reduce the vertical orientation layer spacing. This allows for the stacking of more memory layers without changing the overall height of the device, greatly improving the memory density.

[0033] It should be noted that a gate dielectric layer is provided between the word line electrode 400 and the active layer 300 and between the back gate electrode 500 and the active layer 300, in order to separate the word line electrode 400 from the active layer 300 and the back gate electrode 500 from the active layer 300.

[0034] Please continue to refer to Figure 5 In this embodiment, the size of the first gate control region 301 in the vertical orientation is larger than the size of the second gate control region 302 in the vertical orientation.

[0035] This configuration allows the semiconductor device to utilize the difference in size between the first gate control region 301 and the second gate control region 302 during manufacturing, enabling the simultaneous formation of word line electrodes 400 and back gate electrodes 500 in a single deposition and etching process, greatly simplifying the manufacturing process.

[0036] Furthermore, by placing the word line electrode 400 in the large-sized first gate control region 301, sufficient gate width can be ensured to provide adequate drive current to meet the high-speed read / write requirements of the semiconductor device. Meanwhile, since the back gate electrode 500 primarily provides potential regulation and charge extraction functions and does not undertake the main switching task, placing it in the small-sized second gate control region 302 allows an electric field to influence the channel body potential. This not only further reduces the size of the semiconductor device in vertical orientation, allowing more memory cells to be stacked within the same height, but also minimizes parasitic capacitance, preventing interference with the operation of the word line electrode 400.

[0037] Please continue to refer to Figure 5 In this embodiment, the first gate control region 301 is provided with two word line electrodes 400. The two word line electrodes 400 are separated by a first dielectric layer 410 in vertical orientation and by a second dielectric layer 420 in horizontal orientation. The material of the first dielectric layer 410 is oxide and the material of the second dielectric layer 420 is nitride.

[0038] By integrating the word line electrodes 400 of the stacked transistors into a single first gate control region 301, the space occupied by the semiconductor device in vertical orientation can be significantly reduced. Furthermore, the two word line electrodes 400 can be formed in the same deposition process, resulting in good process consistency.

[0039] Specifically, by using an oxide-formed first dielectric layer 410 to vertically align the two word line electrodes 400, the parasitic capacitance between adjacent transistor layers can be significantly reduced, crosstalk can be decreased, and signal integrity can be improved. By using a nitride-formed second dielectric layer 420 to horizontally align the two word line electrodes 400, a better supporting effect can be provided in the first gate control region 301 to ensure the structural robustness of the semiconductor device.

[0040] In this embodiment, the material of the back gate electrode is titanium nitride.

[0041] By using titanium nitride as the material for the back gate electrode, a suitable work function can be ensured, enabling precise regulation of the transistor threshold voltage and optimizing its switching characteristics. Furthermore, the chemical stability and structural integrity of the back gate electrode 500 at high temperatures can be guaranteed, ensuring the reliability of the semiconductor device during long-term operation.

[0042] This embodiment also provides a storage device; please refer to the following: Figure 5 The memory device includes a vertically oriented bit line 100, a data storage unit 200 horizontally oriented away from the bit line 100, and the aforementioned semiconductor device. A first isolation layer 510 is provided between the back gate electrode 500 and the bit line 100, and a second isolation layer 520 is provided between the back gate electrode 500 and the data storage unit 200.

[0043] By incorporating the aforementioned semiconductor device into the storage device, the storage device thereby possesses all the advantages of the aforementioned semiconductor device, which will not be elaborated upon here.

[0044] In the aforementioned storage device, the first isolation layer 510 can be an oxide nitride, and the second isolation layer 520 can be a nitride. The first isolation layer 510 is formed by first depositing a thinner nitride layer and then depositing a thicker oxide layer.

[0045] By setting a highly dense nitride on the side of the back gate electrode 500 close to the data storage unit 200, etching stop protection can be provided for subsequent processes to avoid etching damage to the data storage unit 200.

[0046] In this embodiment, the storage device can be 3D DRAM.

[0047] like Figure 6 As shown, this embodiment also provides a method for manufacturing a semiconductor device, used to manufacture the aforementioned semiconductor device. The method for manufacturing the semiconductor device includes: Step S100: As Figure 1As shown, a substrate is provided, the substrate including a substrate 610 and a plurality of stacked structures 620 disposed on the substrate 610, the stacked structures 620 including sacrificial layers and channel layers that are alternately stacked in sequence along a direction away from the substrate 610.

[0048] In this embodiment, the substrate 610 can be a single-crystal silicon substrate. Using vapor deposition or epitaxy, multiple stacked structures 620, consisting of alternating sacrificial layers and channel layers, can be sequentially formed on the substrate 610. The multiple channel layers have different thicknesses. Specifically, each stacked structure 620 includes a first sacrificial layer 621, a first channel layer 622, a second sacrificial layer 623, a second channel layer 624, a third sacrificial layer 625, and a third channel layer 626, sequentially stacked along a direction away from the substrate 610. The thickness of the first channel layer 622 is greater than the thickness of the second channel layer 624, and the thickness of the third channel layer 626 is greater than the thickness of the second channel layer 624.

[0049] By setting the thickness of both the first channel layer 622 and the third channel layer 626 to be greater than the thickness of the second channel layer 624, a wider longitudinal gap can be formed at the location of the second channel layer 624 and a narrower longitudinal gap can be formed at the top and bottom ends of the second channel layer 624 after subsequent isotropic etching. This self-aligns and forms a wide trench region for filling the word line electrode 400 and a narrow trench region for filling the back gate electrode 500, simplifying the process flow. Furthermore, after subsequent isotropic etching, a thicker support structure can be formed at the edges of both the first channel layer 622 and the third channel layer 626, which helps to improve the structural stability of the semiconductor device.

[0050] In this embodiment, the materials of the first sacrificial layer 621, the second sacrificial layer 623, and the third sacrificial layer 625 can be germanium silicon (SiGe), and the materials of the first channel layer 622, the second channel layer 624, and the third channel layer 626 can be silicon (Si). The thickness of the first channel layer 622 and the third channel layer 626 can be 35 nm, and the thickness of the first sacrificial layer 621, the second sacrificial layer 623, the third sacrificial layer 625, and the second channel layer 624 can be 10 nm.

[0051] Please continue to refer to Figure 1 In this embodiment, three stacked structures 620 are stacked on the substrate 610. It is understood that the number of stacked structures 620 can be adjusted according to actual needs. This embodiment is only used as an example with three stacked structures 620.

[0052] Please continue to refer to Figure 1 In this embodiment, a hard mask layer is also deposited on the uppermost stacked structure 620. Figure 1In the example, the hard mask layer may include an oxide layer 650 and a nitride layer 660. Using the nitride layer 660 as the main etching mask improves the etching selectivity, ensuring that the nitride layer 660 can withstand a longer etching time in subsequent deep trench etching processes without being completely consumed. Using the oxide layer 650 as a buffer layer, after the pattern transfer of the nitride layer 660 is complete, the oxide layer 650 continues etching as a mask, protecting the nitride layer 660 from being etched too quickly at the pattern edges, thereby ensuring the sidewall perpendicularity of the etched deep trench and improving pattern transfer accuracy.

[0053] Step S200: As Figure 2 As shown, multiple stacked structures 620 are vertically etched to form a first deep trench 630. Laterally etched within the first deep trench 630, a first gate control region 301 and a second gate control region 302 are formed, alternating in a vertical orientation. This also creates an active layer 300 with gradually increasing thickness in a portion of the channel layer. The vertically oriented size of the first gate control region 301 is larger than that of the second gate control region 302. Simultaneously, a second deep trench 640 is formed, which is horizontally spaced from the first deep trench 630.

[0054] In this step, a first deep trench 630 is formed by vertical etching. Subsequently, lateral etching of the sacrificial layer and isotropic etching of the channel layer are performed sequentially in the first deep trench 630 to form a first gate control region 301 and a second gate control region 302. During this process, isotropic etching of the channel layer can be used to naturally form a "thin on one side and thick on the other" morphology of the channel layer cross-section. At this time, a wider lateral gap is naturally left at the position of the thinner second channel layer 624 to form the first gate control region 301, while a narrower lateral gap is naturally left at the positions of the thicker first channel layer 622 and third channel layer 626 away from the second channel layer 624 to form the second gate control region 302. That is, this step defines the first gate control region 301 as the main gate region and the second gate control region 302 as the back gate region with only one isotropic etching, and the height of the first gate control region 301 is greater than the height of the second gate control region 302.

[0055] In addition, a second deep trench 640, which is horizontally spaced from the first deep trench 630, can be formed on one side of the drain region 320 through a single etching process, so as to fabricate a capacitor in the second deep trench 640.

[0056] S300: such as Figure 4 As shown, a word line electrode 400 is formed in the first gate control region 301; and a back gate electrode 500 is formed in the second gate control region 302.

[0057] After forming the first gate control region 301 and the second gate control region 302 through step S200, as Figure 3As shown, a nitride layer 710 can be deposited in the first deep trench 630 so that the first gate control region 301 is partially filled with the nitride layer 710 in the vertical orientation, and the second gate control region 302 is completely filled with the nitride layer 710 in the vertical orientation. At this time, the upper and lower walls of the first gate control region 301 are both deposited with the nitride layer 710, and a gap is formed in the middle part of the first gate control region 301. Before depositing the nitride layer 710 in the first deep trench 630, a thin oxide layer can be deposited in the first deep trench 630 as a gate oxide layer (the gate oxide layer is not shown in the figure).

[0058] Subsequently, a first dielectric layer 410 can be deposited in the area of ​​the first gate control region 301 that is not filled with the nitride layer 710, exposing the nitride layers 710 of the first gate control region 301 and the second gate control region 302. The first dielectric layer 410 provides vertical isolation for the two word line electrodes 400 subsequently formed in the first gate control region 301. Furthermore, by exposing the nitride layers 710 of both the first gate control region 301 and the second gate control region 302 after depositing the first dielectric layer 410, the surfaces of the first gate control region 301 and the second gate control region 302 facing the first deep trench 630 are ensured to be uniform, thereby ensuring consistency in etching depth and etching profile in subsequent etching processes.

[0059] Then, as Figure 5 As shown, the first deep trench 630 can be etched laterally to remove part of the nitride layer 710 in the first gate control region 301 and the second gate control region 302, and expose the active layer 300.

[0060] By laterally etching in the first deep trench 630, a portion of the nitride layer 710 in the first gate control region 301 and the second gate control region 302 can be removed simultaneously in a single etching process, saving process time. Specifically, by controlling the etching time, the nitride layer 710 can be etched to the required thickness, and the remaining nitride layer 710 in the second gate control region 302 is used to form the second isolation layer 520. A portion of the nitride layer 710 also remains in the first gate control region 301, serving as an isolation layer for the two word line electrodes 400 on one side of the data storage unit 200.

[0061] After that, as Figure 5 As shown, conductive material layers are deposited in the first gate control region 301 and the second gate control region 302 to form two word line electrodes 400 separated by the first dielectric layer 410 in vertical orientation in the first gate control region 301, and a back gate electrode 500 is formed in the second gate control region 302. Through a single deposition, the word line electrodes 400 in the first gate control region 301 and the back gate electrode 500 in the second gate control region 302 can be obtained simultaneously, further saving process time.

[0062] It should be noted that after removing part of the nitride layer 710, the gate oxide layer is exposed. A dense oxide layer can be formed by in-situ steam generation (ISSG) to improve the quality of the gate oxide layer. Then, a conductive material layer is deposited to form the word line electrode 400 in the first gate control region 301 and the back gate electrode 500 in the second gate control region 302.

[0063] The conductive material layer can be made of titanium nitride. After the conductive material layer is deposited in the first gate control region 301 and the second gate control region 302, the titanium nitride between the layers can be disconnected by etching back the conductive material layer. At this time, the conductive material layer in the first gate control region 301 is divided into upper and lower parts by the first dielectric layer 410, serving as the two word line electrodes 400 of the first gate control region 301. Meanwhile, the conductive material layer in the second gate control region 302 serves as the back gate electrode 500.

[0064] It should be noted that during the etching process of the nitride layer 710 of the first gate control region 301 and the second gate control region 302, the etching amount can be controlled so that the nitride layer 710 close to the wall of the active layer 300 is retained. This nitride layer 710 is used as the gate dielectric layer between the word line electrode 400 and the active layer 300 and between the back gate electrode 500 and the active layer 300, thereby achieving isolation between the word line electrode 400 and the active layer 300 and between the back gate electrode 500 and the active layer 300.

[0065] Then, as Figure 5 As shown, a nitrogen-oxygen isolation layer 720 is deposited in the first gate control region 301. The nitrogen-oxygen isolation layer 720 is formed by first depositing a thin nitride layer and then depositing a thicker oxide layer. At this time, one side of the word line electrode 400 is the nitride layer 710 left over from the aforementioned etching process, and the other side of the word line electrode 400 is the nitrogen-oxygen isolation layer 720 formed by this deposition process. The nitride layer 710 and the nitrogen-oxygen isolation layer 720 together serve as the second dielectric layer 420, realizing the horizontal orientation isolation of the two word line electrodes 400 in the first gate control region 301.

[0066] This method of using a nitride layer 710 and a nitrogen-oxygen isolation layer 720 as the second dielectric layer 420 can improve the structural strength of semiconductor devices.

[0067] Please continue to refer to Figure 5 After the above steps, an oxide layer 130 can be deposited in the first deep trench 630, such that any two adjacent active layers 300 in the vertical orientation are separated by the oxide layer 130, and the active layers 300 are exposed.

[0068] This configuration enables isolation between any two adjacent active layers 300 in the vertical orientation, preventing leakage or crosstalk. Simultaneously, the oxide layer 130 provides support between the two active layers 300, enhancing the overall structural strength of the semiconductor device and preventing bending, breakage, or collapse of the active layers 300 during subsequent processes.

[0069] Please continue to refer to Figure 5 In the manufacturing method of the semiconductor device, by doping the active layer 300, a source region 310 and a drain region 320 can be formed at both ends of the active layer 300 along the horizontal orientation.

[0070] The source region 310 may include a source 311, a bit line node contact 312, and a bit line ohmic contact layer 313 arranged sequentially from the data storage unit 200 toward the first deep trench 630, and the drain region 320 may include a drain 321, a storage node contact 322, and a storage ohmic contact layer 323 arranged sequentially from the first deep trench 630 toward the data storage unit 200.

[0071] Please continue to refer to Figure 5 A data storage unit 200 can be formed in the drain region 320. The step of forming the data storage unit 200 includes: sequentially depositing a bottom electrode 210, a high dielectric constant dielectric layer 220, a top electrode 230 and a filling layer 240 in the second deep trench 640.

[0072] By fabricating a capacitor within a second deep trench 640 formed on one side of the drain region 320, sufficient storage capacitance can be obtained within a finite unit area, while simultaneously achieving functional separation between the source and drain sides.

[0073] Specifically, the filling layer 240 can be made of germanium-silicon. The high dielectric layer 220 can be made of a material with a dielectric constant greater than that of silicon dioxide.

[0074] In this semiconductor device manufacturing method, a word line electrode 400 is formed in the first gate control region 301, and a back gate electrode 500 is formed in the second gate control region 302. Compared to a fully all-around gate transistor, the single-sided back gate structure obtained by this manufacturing method occupies less vertical space, thereby allowing more memory layers to be stacked within the same height space to increase the memory capacity per unit area. Furthermore, this manufacturing method only requires adding the back gate electrode 500 formation step, without introducing entirely new and complex process modules or overhauling existing production lines, thus reducing the risk and cost of technology iteration.

[0075] In addition, such as Figure 7 As shown, this embodiment also provides a method for manufacturing a storage device, used to manufacture the aforementioned storage device. The method for manufacturing the storage device includes: Semiconductor devices are manufactured using steps S100-S300.

[0076] S400: A first isolation layer 510, a back gate electrode 500, and a second isolation layer 520 are formed in the second gate control region 302 in a horizontal orientation, wherein the first isolation layer 510 is formed by deposition in the second gate control region 302, and the second isolation layer 520 is formed by removing part of the nitride layer 710 in the second gate control region 302.

[0077] This configuration achieves physical isolation between the back gate electrode 500 and the word line electrode 400, effectively preventing mutual interference between them during operation. Furthermore, in the manufacturing method of this memory device, a single etching process not only fully exposes the active layer 300 in the first gate control region 301 and the second gate control region 302, but also forms a second isolation layer 520 of the required thickness in the second gate control region 302.

[0078] S500: Bit lines 100 are formed in the first deep trench 630 and electrically connected to each active layer 300.

[0079] This step allows for the creation of a vertically penetrating multilayer bit line 100 interconnect using the first deep trench 630, providing a shared data transmission path for each layer of transistors, thereby increasing integration density and reducing additional interconnect area.

[0080] Please continue to refer to Figure 5 In this embodiment, bit line 100 is epitaxially grown outside source region 310.

[0081] Specifically, after forming the oxide layer 130, a first conductive layer 110 can be deposited in the first deep trench 630, followed by the deposition of a second conductive layer 120. In this case, the second conductive layer 120 is surrounded by the first conductive layer 110, and the two together form the bit line 100. The material of the first conductive layer 110 can be titanium nitride, and the material of the second conductive layer 120 can be tungsten.

[0082] While this application discloses the above information, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application shall be determined by the scope defined in the claims.

[0083] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0084] In the above embodiments, descriptions of directions such as "up" and "down" are based on the accompanying drawings.

[0085] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application.

[0086] Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor device, characterized in that, include: The horizontally oriented active layer (300) has a source region (310) and a drain region (320); the active layer (300) forms a first gate control region (301) and a second gate control region (302) at both ends of the vertical orientation, and the first gate control region (301) and the second gate control region (302) are arranged alternately in the vertical orientation; Word line electrode (400) is disposed in the first gate control region (301) and supports the active layer (300). as well as A back gate electrode (500) is disposed in the second gate control region (302) and supports the active layer (300), and the back gate electrode (500) is electrically isolated from the word line electrode (400).

2. The semiconductor device according to claim 1, characterized in that, The size of the first gate control region (301) in the vertical orientation is larger than the size of the second gate control region (302) in the vertical orientation.

3. The semiconductor device according to claim 1, characterized in that, The first gate control region (301) is provided with two word line electrodes (400). The two word line electrodes (400) are separated by a first dielectric layer (410) in the vertical orientation and by a second dielectric layer (420) in the horizontal orientation. The material of the first dielectric layer (410) is oxide and the material of the second dielectric layer (420) is nitride.

4. The semiconductor device according to claim 1, characterized in that, The material of the back gate electrode (500) is titanium nitride.

5. A storage device, characterized in that, The device includes a vertically oriented bit line (100), a data storage cell (200) separated from the bit line (100) by the horizontal orientation, and a semiconductor device according to any one of claims 1-4, wherein a first isolation layer (510) is disposed between the back gate electrode (500) and the bit line (100); and a second isolation layer (520) is disposed between the back gate electrode (500) and the data storage cell (200).

6. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided, the substrate including a substrate (610) and a plurality of stacked structures (620) disposed on the substrate (610), the stacked structures (620) including sacrificial layers and channel layers alternately stacked in sequence along a direction away from the substrate (610); The plurality of stacked structures (620) are longitudinally etched to form a first deep trench (630). The first deep trench (630) is laterally etched to form a first gate control region (301) and a second gate control region (302) arranged alternately in the vertical orientation, and a portion of the channel layer is formed into an active layer (300) with gradually increasing thickness. A word line electrode (400) is formed in the first gate control region (301); a back gate electrode (500) is formed in the second gate control region (302), so that the back gate electrode (500) is electrically isolated from the word line electrode (400).

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The step of forming word line electrodes (400) in the first gate control region (301) includes: forming two word line electrodes (400) in the first gate control region (301) that are vertically separated by a first dielectric layer (410) and horizontally separated by a second dielectric layer (420).

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The steps of forming two word line electrodes (400) in the first gate control region (301) and separated by a first dielectric layer (410) in a vertical orientation and by a second dielectric layer (420) in a horizontal orientation, and forming a back gate electrode (500) in the second gate control region (302), include: A nitride layer (710) is deposited in the first deep trench (630) so that the first gate control region (301) is partially filled with the nitride layer (710) in the vertical orientation, and the second gate control region (302) is completely filled with the nitride layer (710) in the vertical orientation; A first dielectric layer (410) is deposited in the area of ​​the first gate control region (301) that is not filled by the nitride layer (710), and the nitride layer (710) of the first gate control region (301) and the second gate control region (302) is exposed. Laterally etch the first deep trench (630) to remove part of the nitride layer (710) in the first gate control region (301) and the second gate control region (302) and expose the active layer (300). Conductive material layers are deposited in the first gate control region (301) and the second gate control region (302) to form two word line electrodes (400) in the first gate control region (301) that are vertically separated by the first dielectric layer (410), and to form a back gate electrode (500) in the second gate control region (302). A nitrogen-oxygen isolation layer (720) is deposited in the first gate control region (301), and the nitrogen-oxygen isolation layer (720) and the nitride layer (710) of the first gate control region (301) together form the second dielectric layer (420).

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, Also includes: An oxide layer (130) is deposited in the first deep trench (630) such that any two adjacent active layers (300) in the vertical orientation are separated by the oxide layer (130) and the active layers (300) are exposed.

10. The method for manufacturing a semiconductor device according to claim 8, characterized in that, Also includes: The active layer (300) is doped to form a source region (310) and a drain region (320) at both ends of the active layer (300) along the horizontal orientation. The data storage unit (200) is formed in the drain region (320), wherein the step of forming the data storage unit (200) includes: longitudinally etching the plurality of stacked structures (620) to form a second deep trench (640), the second deep trench (640) being spaced apart from the first deep trench (630) in the horizontal orientation, and sequentially depositing a bottom electrode (210), a high dielectric constant dielectric layer (220), a top electrode (230), and a filling layer (240) in the second deep trench (640).

11. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The stacked structure (620) includes a first sacrificial layer (621), a first channel layer (622), a second sacrificial layer (623), a second channel layer (624), a third sacrificial layer (625), and a third channel layer (626) stacked sequentially in a direction away from the substrate (610). The thickness of the first channel layer (622) is greater than the thickness of the second channel layer (624), and the thickness of the third channel layer (626) is greater than the thickness of the second channel layer (624).

12. A method for manufacturing a storage device, comprising: A semiconductor device is manufactured using the manufacturing method of any one of claims 6-11; A first isolation layer (510), a back gate electrode (500), and a second isolation layer (520) are formed in the second gate control region (302) in a horizontal orientation, wherein the first isolation layer (510) is formed by deposition in the second gate control region (302), and the second isolation layer (520) is formed by removing part of the nitride layer (710) in the second gate control region (302); Bit lines (100) electrically connected to each of the active layers (300) are formed in the first deep trench (630).

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