Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a preparation method thereof. A bit line structure is located on a substrate. A first sidewall is located on a sidewall of the bit line structure and directly contacts the bit line structure. The first sidewall comprises an upper half sidewall and a lower half sidewall. The upper half sidewall and the lower half sidewall are separated from each other. A second sidewall is located on the first sidewall and the sidewall of the bit line structure. The second sidewall directly contacts the sidewall and the bottom surface of the upper half sidewall, the sidewall of the bit line, and the sidewall and the top surface of the lower half sidewall. In the application, the first sidewall serves as an oxidation-resistant layer for preparing the second sidewall. The first sidewall can prevent the oxygen plasma in an oxidation process from oxidizing part of the bit line structure, so as to avoid the sidewall of the bit line structure from being concave, thereby ensuring the structural integrity of the bit line structure and improving the reliability of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] In the fabrication process of semiconductor devices, especially memory devices, after forming a bit line structure on a substrate, sidewalls are formed on the sidewalls of the bit line structure. The bit line structure includes a bit line semiconductor layer, which is made of silicon. When forming the sidewalls, a deposition process is first used to form sidewalls made of oxygen. The oxygen plasma in the deposition process oxidizes the bit line semiconductor layer, causing the sidewalls of the bit line semiconductor layer to become concave, thereby affecting the reliability of the semiconductor device. Summary of the Invention

[0003] The purpose of this invention is to provide a semiconductor device and a method for fabricating the same, thereby improving the reliability of the semiconductor device.

[0004] To achieve the above objectives, the present invention provides a semiconductor device comprising:

[0005] Substrate;

[0006] Bitline structures are located on the substrate;

[0007] The first sidewall is located on the sidewall of the bit line structure and is in direct contact with the bit line structure. The first sidewall includes an upper half sidewall and a lower half sidewall, which are separated from each other.

[0008] The second sidewall is located on the first sidewall and the sidewall of the bit line structure. The second sidewall is in direct contact with the sidewall and bottom surface of the upper half sidewall, the sidewall of the bit line structure, and the sidewall and top surface of the lower half sidewall.

[0009] Optionally, the bit line structure includes a bit line semiconductor layer, a bit line metal layer, and a bit line capping layer stacked sequentially from bottom to top, with the upper half sidewall located on the sidewall of the bit line capping layer and the lower half sidewall located on the sidewall of the bit line semiconductor layer.

[0010] Optionally, the second sidewall is in direct contact with the sidewall of the bit line metal layer.

[0011] Optionally, the second sidewall has a recess that is recessed into the bit line metal layer.

[0012] Optionally, the thickness of the second sidewall located on the first sidewall is greater than the thickness of the second sidewall located on the sidewall of the bit line structure.

[0013] Optionally, it also includes the third sidewall, which covers the second sidewall.

[0014] Optionally, the third sidewall has a recess that is recessed into the bit line metal layer.

[0015] Optionally, it may also include a memory node contact structure located between adjacent bit line structures and extending into the substrate.

[0016] Optionally, the storage node contact structure has a protrusion facing the bit line metal layer.

[0017] Optionally, the material of the first sidewall includes silicon nitride, and the material of the second sidewall includes silicon oxide and / or silicon oxynitride.

[0018] This invention also provides a method for fabricating a semiconductor device, comprising:

[0019] Provide substrate;

[0020] The bit line structure is formed on the substrate;

[0021] A first sidewall is formed on the sidewall of the bit line structure and in direct contact with the bit line structure, and a second sidewall is formed on the first sidewall and the sidewall of the bit line structure;

[0022] The first sidewall includes an upper sidewall and a lower sidewall, which are separated from each other. The second sidewall is in direct contact with the sidewall and bottom surface of the upper sidewall, the sidewall of the bit line structure, and the sidewall and top surface of the lower sidewall.

[0023] Optionally, the bit line structure includes a bit line semiconductor layer, a bit line metal layer, and a bit line capping layer stacked sequentially from bottom to top, and the steps of forming the first sidewall and the second sidewall include:

[0024] A first sidewall material layer is formed to conformally cover the bit line structure, wherein the thickness of the first sidewall material layer of the bit line metal layer sidewall is less than the thickness of the first sidewall material layer of the bit line semiconductor layer and the bit line capping layer sidewall.

[0025] The first sidewall material layer is oxidized to form the second sidewall. The first sidewall material layer of the bit line metal layer sidewall is completely oxidized, and the first sidewall material layers of the bit line semiconductor layer and the bit line capping layer sidewall are partially oxidized. The remaining first sidewall material layer serves as the first sidewall.

[0026] Optionally, the thickness of the second sidewall located on the first sidewall is greater than the thickness of the second sidewall located on the sidewall of the bit line structure.

[0027] Optionally, the material of the first sidewall includes silicon nitride, and the material of the second sidewall includes silicon oxide and / or silicon oxynitride.

[0028] Optionally, after forming the second sidewall, a third sidewall is formed to conformally cover the second sidewall.

[0029] Optionally, the third sidewall has a recess that is recessed into the bit line metal layer.

[0030] Optionally, after forming the third sidewall, the method further includes forming a memory node contact structure located between adjacent bit line structures and extending into the substrate.

[0031] Optionally, the storage node contact structure has a protrusion facing the bit line metal layer.

[0032] In the semiconductor device and its fabrication method provided by this invention, the bit line structure is located on a substrate. A first sidewall is located on the sidewall of the bit line structure and is in direct contact with it. The first sidewall includes an upper half sidewall and a lower half sidewall, which are separated from each other. A second sidewall is located on the first sidewall and the sidewall of the bit line structure, and is in direct contact with the sidewall and bottom surface of the upper half sidewall, the sidewall of the bit line, and the sidewall and top surface of the lower half sidewall. In this invention, the first sidewall is located on the sidewall of the bit line structure, and the upper half sidewall and the lower half sidewall are separated from each other. The first sidewall serves as an antioxidant layer for fabricating the second sidewall. The first sidewall can prevent oxygen plasma in the oxidation process from oxidizing part of the bit line structure, thereby avoiding concavity in the sidewall of the bit line structure, ensuring the structural integrity of the bit line structure, and improving the reliability of the semiconductor device. Attached Figure Description

[0033] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of the present invention.

[0034] Figure 2 for Figure 1 Enlarged view of the area within the dashed frame.

[0035] Figures 3-6 This is a cross-sectional schematic diagram of a corresponding step in a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0036] The attached figures are labeled as follows:

[0037] 100 - Substrate; 120 - Trench isolation structure; 131 - First isolation material layer; 132 - Second isolation material layer; 133 - Third isolation material layer; 200 - Bit line structure; 210 - Bit line semiconductor layer; 220 - Bit line metal layer; 221 - First bit line metal layer; 222 - Second bit line metal layer; 230 - Bit line capping layer; 300 - First sidewall; 300a - Upper half sidewall; 300b - Lower half sidewall; 310 - First sidewall material layer; 400 - Second sidewall; 500 - Third sidewall; 600 - Storage node contact structure; 710 - Barrier layer; 720 - First metal layer; 730 - Second metal layer; 800 - Insulating structure. Detailed Implementation

[0038] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0039] Please refer to Figure 1 and Figure 2 This embodiment provides a semiconductor device, including: a substrate 100, a bit line structure 200, a first sidewall 300 and a second sidewall 400, wherein the substrate 100 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, a fully depleted silicon-on-insulator substrate, or not limited thereto; a plurality of trench isolation structures 120 are provided in the substrate 100, and adjacent trench isolation structures 120 are active regions, and the material of the trench isolation structures 120 includes one or more of silicon oxide, silicon nitride, and silicon carbonitride, or not limited thereto.

[0040] The bit line structure 200 is located on the substrate 100. The bit line structure 200 includes a first bit line structure and a second bit line structure. The bottom surface of the first bit line structure is lower than the bottom surface of the second bit line structure. The first bit line structure is in direct contact with the substrate 100. A first isolation material layer 131, a second isolation material layer 132, and a third isolation material layer 133 are disposed between the second bit line structure and the substrate 100, stacked sequentially from bottom to top. The second bit line structure is in direct contact with the third isolation material layer 133. The first isolation material layer 131, the second isolation material layer 132, and the third isolation material layer 133 can be a stacked structure composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. The bit line structure 200 includes a bit line semiconductor layer 210, a bit line metal layer 220, and a bit line capping layer 230 stacked sequentially from bottom to top. The bit line metal layer 220 includes a first bit line metal layer 221 and a second bit line metal layer 222 stacked sequentially from bottom to top. The first bit line metal layer 221 is in direct contact with the bit line semiconductor layer 210, and the second bit line metal layer 222 is in direct contact with the bit line capping layer 230. The material of the bit line semiconductor layer 210 is preferably polycrystalline silicon (and doped polycrystalline silicon). The materials of the first bit line metal layer 221 and the second bit line metal layer 222 are different. The material of the first bit line metal layer 221 can be tungsten, and the material of the second bit line metal layer 222 can be titanium nitride. The material of the bit line capping layer 230 can be an insulating material, such as silicon nitride.

[0041] The first sidewall 300 is located on the sidewall of the bit line structure 200 and is in direct contact with the bit line structure 200. The first sidewall 300 includes an upper half sidewall 300a and a lower half sidewall 300b, which are separated from each other. The material of the first sidewall 300 includes silicon nitride. Specifically, the upper half sidewall 300a is located on the sidewall of the bit line capping layer 230, and the lower half sidewall 300b is located on the sidewall of the bit line semiconductor layer 210. The lower half sidewall 300b also has a groove portion that contacts the substrate 100 (e.g., Figure 2 As shown in the rectangular dashed frame), the groove portion also contacts the groove isolation structure 120.

[0042] The second sidewall 400 is located on the first sidewall 300 and the sidewall of the bit line structure 200. The second sidewall 400 is in direct contact with the sidewall and bottom surface of the upper half sidewall 300a, the sidewall of the bit line structure 200, and the sidewall and top surface of the lower half sidewall 300b. The material of the second sidewall 400 includes silicon oxide and / or silicon oxynitride. Specifically, the second sidewall 400 is in direct contact with the sidewall of the bit line metal layer 200, that is, the second sidewall 400 is in direct contact with the sidewall of the first bit line metal layer 221 and the second bit line metal layer 222. The second sidewall 400 has a recessed portion (e.g., recessed into the bit line metal layer 220) Figure 2(As shown in the elliptical dashed frame). In one embodiment, the thickness W2 of the second sidewall 400 located on the first sidewall 300 is equal to the thickness W1 of the second sidewall 400 located on the sidewall of the bit line structure 200 (bit line metal layer 220). In another embodiment, the thickness W2 of the second sidewall 400 located on the first sidewall 300 is greater than the thickness W1 of the second sidewall 400 located on the sidewall of the bit line structure 200 (bit line metal layer 220).

[0043] Furthermore, it also includes a third sidewall 500 that covers the second sidewall 400. The third sidewall 500 has a recessed portion of the recessed bit line metal layer 220. The material of the third sidewall 500 includes silicon oxide, silicon oxynitride, or silicon nitride.

[0044] Furthermore, it also includes a memory node contact structure 600, which is located between adjacent bit line structures 200 and extends into the substrate 100. The memory node contact structure 600 has a protrusion toward the bit line metal layer 220, and the protrusion of the memory node contact structure 600 toward the bit line metal layer 220 is located in the recess of the third sidewall 500 toward the bit line metal layer 220.

[0045] Furthermore, it also includes a barrier layer 710, a first metal layer 720, a second metal layer 730, and an insulating structure 800, wherein the barrier layer 710 is located on the storage node contact structure 600, the first metal layer 720 conformally covers the barrier layer 710, the third sidewall 500, and the bit line cap 230, the second metal layer 730 covers the first metal layer 720, and the insulating structure 800 penetrates the second metal layer 730 and the first metal layer 720 and extends into the sidewall structure (first sidewall 300, second sidewall 400, and third sidewall 500).

[0046] In this embodiment, the first sidewall 300 is located on the sidewall of the bit line structure 200. This is mainly because the first sidewall 300 is located on the sidewall of the bit line semiconductor layer 210. When the second sidewall 400 is prepared, the first sidewall 300 serves as an anti-oxidation layer for preparing the second sidewall 400. The first sidewall 300 can prevent the oxygen plasma in the oxidation process from oxidizing part of the bit line structure (bit line semiconductor layer 210), so as to avoid the sidewall of the bit line structure (bit line semiconductor layer 210) from becoming concave, thereby ensuring the structural integrity of the bit line structure and improving the reliability of the semiconductor device.

[0047] This embodiment also provides a method for fabricating a semiconductor device, used to fabricate the above-mentioned bulk semiconductor device, comprising:

[0048] Step S1: Provide a substrate;

[0049] Step S2: Form a bit line structure on the substrate;

[0050] Step S3: Form a first sidewall located on the sidewall of the bit line structure and in direct contact with the bit line structure, and form a second sidewall located on the first sidewall and the sidewall of the bit line structure.

[0051] The following is combined with Figures 1-6 The method for fabricating the semiconductor device provided in this embodiment will be described in detail.

[0052] Please refer to Figure 3 Step S1: Provide a substrate 100, which can be a silicon substrate, gallium arsenide substrate, germanium substrate, germanium silicon substrate, or fully depleted silicon-on-insulator substrate, and is not limited thereto; a plurality of trench isolation structures 120 are provided in the substrate 100, and adjacent trench isolation structures 120 are active regions, and the material of the trench isolation structure 120 includes one or more of silicon oxide, silicon nitride, and silicon carbonitride, and is not limited thereto.

[0053] Please continue to refer to this. Figure 3 Step S2: A bit line structure 200 is formed on the substrate 100. The bit line structure 200 includes a first bit line structure and a second bit line structure. The bottom surface of the first bit line structure is lower than the bottom surface of the second bit line structure. The first bit line structure is in direct contact with the substrate 100. A first isolation material layer 131, a second isolation material layer 132, and a third isolation material layer 133 are stacked sequentially from bottom to top between the second bit line structure and the substrate 100. The second bit line structure is in direct contact with the third isolation material layer 133. The first isolation material layer 131, the second isolation material layer 132, and the third isolation material layer 133 can be a stacked structure composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. The bit line structure 200 includes a bit line semiconductor layer 210, a bit line metal layer 220, and a bit line capping layer 230 stacked sequentially from bottom to top. The bit line metal layer 220 includes a first bit line metal layer 221 and a second bit line metal layer 222 stacked sequentially from bottom to top. The first bit line metal layer 221 is in direct contact with the bit line semiconductor layer 210, and the second bit line metal layer 222 is in direct contact with the bit line capping layer 230. The material of the bit line semiconductor layer 210 is preferably polycrystalline silicon (and doped polycrystalline silicon). The materials of the first bit line metal layer 221 and the second bit line metal layer 222 are different. The material of the first bit line metal layer 221 can be tungsten, and the material of the second bit line metal layer 222 can be titanium nitride. The material of the bit line capping layer 230 can be an insulating material, such as silicon nitride.

[0054] Please continue to refer to this. Figure 3 and reference Figure 4Step S3 is executed: a first sidewall 300 is formed on the sidewall of the bitline structure 200 and in direct contact with the bitline structure 200, and a second sidewall 400 is formed on the first sidewall 300 and on the sidewall of the bitline structure 200. Specifically, a deposition process is used to form a first sidewall material layer 310 that conformally covers the bitline structure 200 (covering the sidewall and top surface of the bitline structure 200) and a third isolation material layer 133. The material of the first sidewall material layer 310 includes silicon nitride. Since the bit line structure 200 includes a bit line semiconductor layer 210, a bit line metal layer 220, and a bit line capping layer 230, and the materials of the bit line semiconductor layer 210, bit line metal layer 220, and bit line capping layer 230 are different, the growth rate of silicon nitride is different for different materials. The growth rate of silicon nitride (first sidewall material layer 310) on the bit line metal layer 220 is less than the growth rate of silicon nitride (first sidewall material layer 310) on the bit line semiconductor layer 210 and the bit line capping layer 230, so that the thickness of the first sidewall material layer 310 on the sidewall of the bit line metal layer 220 is less than the thickness of the first sidewall material layer 310 on the sidewall of the bit line semiconductor layer 210 and the bit line capping layer 230. Then, the first sidewall material layer 310 is oxidized using an oxidation process to form the second sidewall 400. The first sidewall material layer 310 of the bit line metal layer 220 sidewall is completely oxidized to form the second sidewall 400, so that the second sidewall 400 is in direct contact with the bit line metal layer 220. The first sidewall material layer 310 of the bit line semiconductor layer 210 and the bit line capping layer 230 sidewall is partially oxidized. The partially oxidized first sidewall material layer 310 forms the second sidewall 400, and the remaining first sidewall material layer 310 serves as the first sidewall 300.

[0055] When oxidizing the first sidewall material layer 310, since the thickness of the first sidewall material layer 310 on the sidewall of the bit line metal layer 220 is less than the thickness of the first sidewall material layer 310 on the sidewall of the bit line semiconductor layer 210 and the bit line capping layer 230, after the first sidewall material layer 310 on the sidewall of the bit line metal layer 220 is completely oxidized, there is still a remaining first sidewall material layer 310 on the sidewalls of the bit line semiconductor layer 210 and the bit line capping layer 230. The first sidewall material layer 310 serves as an antioxidant layer for preparing the second sidewall 400. The first sidewall material layer 310 can prevent the oxygen plasma in the oxidation process from oxidizing part of the bit line structure (bit line semiconductor layer 210), so as to avoid the sidewall of the bit line structure from becoming concave, thereby ensuring the structural integrity of the bit line structure and improving the reliability of the semiconductor device.

[0056] Combination Figure 2The first sidewall 300 includes an upper sidewall 300a and a lower sidewall 300b, which are separated from each other. The upper sidewall 300a is located on the sidewall of the bit line capping layer 230, and the lower sidewall 300b is located on the sidewall of the bit line semiconductor layer 210. The lower sidewall 300b also has a groove portion that contacts the substrate 100 (e.g., Figure 2 As shown in the rectangular dashed frame), the groove portion also contacts the trench isolation structure 120. The second sidewall 400 is in direct contact with the sidewall and bottom surface of the upper half sidewall 300a, the sidewall of the bit line structure 200, and the sidewall and top surface of the lower half sidewall 300b. The material of the second sidewall 400 includes silicon oxide and / or silicon oxynitride. Specifically, the second sidewall 400 is in direct contact with the sidewall of the bit line metal layer 200, that is, the second sidewall 400 is in direct contact with the sidewall of the first bit line metal layer 221 and the second bit line metal layer 222. The second sidewall 400 has a recessed portion that is concave towards the bit line metal layer 220 (e.g., Figure 2 (As shown in the elliptical dashed frame).

[0057] In one embodiment, the oxidation process ends when the first sidewall material layer 310 of the bit line metal layer 220 is completely oxidized, such that the thickness W2 of the second sidewall 400 on the first sidewall 300 is equal to the thickness W1 of the second sidewall 400 on the sidewall of the bit line structure 200 (bit line metal layer 220). In another embodiment, after the first sidewall material layer 310 of the bit line metal layer 220 is completely oxidized, a portion of the first sidewall material layer 310 on the sidewalls of the bit line semiconductor layer 210 and the bit line capping layer 230 can continue to be oxidized, such that the thickness W2 of the second sidewall 400 on the first sidewall 300 is greater than the thickness W1 of the second sidewall 400 on the sidewall of the bit line structure 200 (bit line metal layer 220), but a portion of the first sidewall material layer 310 remains on the sidewalls of the bit line semiconductor layer 210 and the bit line capping layer 230 as the first sidewall 300.

[0058] Please refer to Figure 5 Furthermore, it also includes forming a third sidewall 500 covering the second sidewall 400, the third sidewall 500 having a recessed portion of the recessed bit line metal layer 220, and the material of the third sidewall 500 including silicon oxide, silicon oxynitride or silicon nitride.

[0059] Please refer to Figure 6 Furthermore, it also includes forming a memory node contact structure 600 located between adjacent bit line structures 200 and extending into the substrate 100. The memory node contact structure 600 has a protrusion facing the bit line metal layer 220, and the protrusion of the memory node contact structure 600 facing the bit line metal layer 220 is located in a recess of the third sidewall 500 into the bit line metal layer 220. Additionally, parts of the bit line capping layer 230 and the sidewall structure are etched to reduce the height of the bit line capping layer 230.

[0060] Please continue to refer to this. Figure 1 Furthermore, it also includes forming a barrier layer 710 on the storage node contact structure 600, forming a first metal layer 720 conformally covering the barrier layer 710, the third sidewall 500 and the bit line capping layer 230, forming a second metal layer 730 covering the first metal layer 720, and forming an insulating structure 800 penetrating the second metal layer 730 and the first metal layer 720 and extending into the sidewall structure (first sidewall 300, second sidewall 400 and third sidewall 500).

[0061] In summary, in the semiconductor device and its fabrication method provided by this invention, the bit line structure is located on the substrate, and the first sidewall is located on the sidewall of the bit line structure and is in direct contact with the bit line structure. The first sidewall includes an upper half sidewall and a lower half sidewall, which are separated from each other. The second sidewall is located on the first sidewall and the sidewall of the bit line structure, and the second sidewall is in direct contact with the sidewall and bottom surface of the upper half sidewall, the sidewall of the bit line, the sidewall of the lower half sidewall, and the top surface. In this invention, the first sidewall is located on the sidewall of the bit line structure, and the upper half sidewall and the lower half sidewall are separated from each other. The first sidewall serves as an antioxidant layer for fabricating the second sidewall. The first sidewall can prevent oxygen plasma in the oxidation process from oxidizing part of the bit line structure, thereby avoiding concavity in the sidewall of the bit line structure, ensuring the structural integrity of the bit line structure, and improving the reliability of the semiconductor device.

[0062] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Substrate; Bitline structures are located on the substrate; The first sidewall is located on the sidewall of the bit line structure and is in direct contact with the bit line structure. The first sidewall includes an upper half sidewall and a lower half sidewall, which are separated from each other. The second sidewall is located on the first sidewall and the sidewall of the bit line structure. The second sidewall is in direct contact with the sidewall and bottom surface of the upper half sidewall, the sidewall of the bit line structure, and the sidewall and top surface of the lower half sidewall.

2. The semiconductor device as claimed in claim 1, characterized in that, The bit line structure includes a bit line semiconductor layer, a bit line metal layer, and a bit line capping layer stacked sequentially from bottom to top. The upper half sidewall is located on the sidewall of the bit line capping layer, and the lower half sidewall is located on the sidewall of the bit line semiconductor layer.

3. The semiconductor device as described in claim 2, characterized in that, The second sidewall is in direct contact with the sidewall of the bit line metal layer.

4. The semiconductor device as described in claim 2, characterized in that, The second sidewall has a recess that is recessed into the bit line metal layer.

5. The semiconductor device as claimed in claim 1, characterized in that, The thickness of the second sidewall located on the first sidewall is greater than the thickness of the second sidewall located on the sidewall of the bit line structure.

6. The semiconductor device as claimed in claim 2, characterized in that, It also includes the third sidewall, which covers the second sidewall.

7. The semiconductor device as claimed in claim 6, characterized in that, The third sidewall has a recess that is concave towards the bit line metal layer.

8. The semiconductor device as claimed in claim 2, characterized in that, It also includes a memory node contact structure located between adjacent bit line structures and extending into the substrate.

9. The semiconductor device as claimed in claim 8, characterized in that, The storage node contact structure has a protrusion facing the bit line metal layer.

10. The semiconductor device as claimed in claim 1, characterized in that, The first sidewall is made of silicon nitride, and the second sidewall is made of silicon oxide and / or silicon oxynitride.

11. A method for fabricating a semiconductor device, characterized in that, include: Provide substrate; The bit line structure is formed on the substrate; A first sidewall is formed on the sidewall of the bit line structure and in direct contact with the bit line structure, and a second sidewall is formed on the first sidewall and the sidewall of the bit line structure; The first sidewall includes an upper sidewall and a lower sidewall, which are separated from each other. The second sidewall is in direct contact with the sidewall and bottom surface of the upper sidewall, the sidewall of the bit line structure, and the sidewall and top surface of the lower sidewall.

12. The method for fabricating a semiconductor device as described in claim 11, characterized in that, The bit line structure includes a bit line semiconductor layer, a bit line metal layer, and a bit line capping layer stacked sequentially from bottom to top. The steps of forming the first sidewall and the second sidewall include: A first sidewall material layer is formed to conformally cover the bit line structure, wherein the thickness of the first sidewall material layer of the bit line metal layer sidewall is less than the thickness of the first sidewall material layer of the bit line semiconductor layer and the bit line capping layer sidewall. The first sidewall material layer is oxidized to form the second sidewall. The first sidewall material layer of the bit line metal layer sidewall is completely oxidized, and the first sidewall material layers of the bit line semiconductor layer and the bit line capping layer sidewall are partially oxidized. The remaining first sidewall material layer serves as the first sidewall.

13. The method for fabricating a semiconductor device as described in claim 11, characterized in that, The thickness of the second sidewall located on the first sidewall is greater than the thickness of the second sidewall located on the sidewall of the bit line structure.

14. The method for fabricating a semiconductor device as described in claim 11, characterized in that, The first sidewall is made of silicon nitride, and the second sidewall is made of silicon oxide and / or silicon oxynitride.

15. The method for fabricating a semiconductor device as described in claim 12, characterized in that, After forming the second sidewall, the process also includes forming a third sidewall that conformally covers the second sidewall.

16. The method for fabricating a semiconductor device as described in claim 15, characterized in that, The third sidewall has a recess that is concave towards the bit line metal layer.

17. The method for fabricating a semiconductor device as described in claim 15, characterized in that, After forming the third sidewall, the method further includes forming a memory node contact structure located between adjacent bit line structures and extending into the substrate.

18. The method for fabricating a semiconductor device as described in claim 17, characterized in that, The storage node contact structure has a protrusion facing the bit line metal layer.

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