Semiconductor structure and method of forming the same

Abstract

A semiconductor structure includes a capacitor in a substrate, a passageway connected to the capacitor, a gate dielectric layer around the passageway, and a word line on the substrate. The passageway and the gate dielectric layer extend through the word line. The semiconductor structure further includes a landing pad on the passageway and a bit line on the landing pad. A bottom surface of the bit line is lower than a top surface of the landing pad, and a bottom width of the bit line is less than a top width of the bit line. The semiconductor structure further includes a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer and the bit line. Methods of forming the semiconductor structure are also disclosed. The present invention can reduce the possibility of electrical short between the bit line and the landing pad. Furthermore, the bit line can have a uniform arrangement and better connection with the landing pad.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for forming the same. Background Technology

[0002] As the semiconductor industry continues to advance towards advanced technology nodes in pursuit of higher device performance and density, the precision of photolithography has also significantly improved. To further reduce device size, component dimensions and the distance between components must be reduced accordingly. However, with the reduction in component dimensions and the distance between components, precisely controlling these dimensions and distances has become a new challenge. Summary of the Invention

[0003] This invention provides a semiconductor structure including a capacitor in a substrate, a channel connecting the capacitor, a gate dielectric layer surrounding the channel, and a word line on the substrate. The channel and the gate dielectric layer extend through the word line. The semiconductor structure includes a landing pad on the channel and a bit line on the landing pad. The bottom surface of the bit line is lower than the top surface of the landing pad, and the bottom width of the bit line is smaller than the top width of the bit line. The semiconductor structure includes a first dielectric layer on the substrate and a second dielectric layer on the first dielectric layer and the bit line. The channel, the gate dielectric layer, the word line, the landing pad, and the bit line are in the first dielectric layer.

[0004] In some embodiments, the bottom width of the bitline is defined at the level of the top surface of the landing pad, and the top width of the bitline is defined at the level of the top surface of the bitline.

[0005] In some embodiments, a depth is defined from the bottom surface of the bit line to the top surface of the landing pad, and the depth is half the height of the landing pad.

[0006] In some embodiments, the bit line directly contacts the landing pad.

[0007] In some embodiments, the channel comprises indium gallium zinc oxide.

[0008] In some embodiments, the bit is electrically connected to the capacitor.

[0009] In some embodiments, the bit line has a height in the range of 18 nm to 22 nm.

[0010] In some embodiments, the bit lines are composed of tungsten.

[0011] In some embodiments, the landing pad surrounds the bottom portion of the bit line.

[0012] In some embodiments, the second dielectric layer directly contacts the top surface of the bit line and the top surface of the first dielectric layer.

[0013] This invention provides a method for forming a semiconductor structure, comprising providing a substrate, a capacitor disposed in the substrate, a channel connecting the capacitor, a gate dielectric layer surrounding the channel, a landing pad on the channel, a word line on the substrate, wherein the channel and the gate dielectric layer extend through the word line, and a dielectric material on the substrate. The method includes forming trenches in the dielectric material and the landing pad, depositing a conductive material on the dielectric material and filling the trenches, and planarizing the conductive material and the dielectric material to form a bit line and a first dielectric layer. The bottom width of the bit line is smaller than the top width of the bit line. The method includes forming a second dielectric layer on the first dielectric layer and the bit line.

[0014] In some embodiments, forming a trench in the dielectric material and the landing pad includes: depositing a hard mask on the dielectric material, etching through the hard mask and the dielectric material and into the landing pad, and removing the hard mask.

[0015] In some embodiments, etching through the hard mask and dielectric material and into the landing pad includes: etching through a portion of the hard mask and dielectric material to expose a portion of the landing pad, and removing a portion of the landing pad.

[0016] In some embodiments, a first etchant is used to etch the hard mask and dielectric material, and a second etchant, different from the first etchant, is used to etch portions of the landing pad.

[0017] In some embodiments, the first etchant includes carbon tetrafluoride (CF4) and difluoromethane (CH2F2), and the second etchant includes sulfur hexafluoride (SF6), oxygen (O2), argon (Ar), and chlorine (Cl2).

[0018] In some embodiments, etching through the hard shield and dielectric material and into the landing pad is performed in a chamber.

[0019] In some embodiments, forming a trench in the dielectric material and landing pad includes: recessing the landing pad depth from the top surface of the landing pad.

[0020] In some embodiments, the depth is half the height of the landing pad.

[0021] In some embodiments, the top surface of the bit line is coplanar with the top surface of the first dielectric layer.

[0022] In some embodiments, the conductive material completely fills the trench.

[0023] It should be understood that the foregoing general description and the following detailed description are by way of example and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0024] A more complete understanding of the present invention can be obtained by reading the following embodiments and the detailed description in conjunction with the accompanying drawings: Figures 1 to 7 These are cross-sectional views of the formation of a semiconductor structure at different stages according to some embodiments of the present invention. Detailed Implementation

[0025] Embodiments of the invention will now be described in detail, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar parts.

[0026] See Figure 1 , Figure 1 This is a cross-sectional view of the formation of a semiconductor structure at different stages according to some embodiments of the present invention. The method for forming the semiconductor structure begins with step S10. A substrate 102 is provided. A plurality of capacitors 104 are disposed on top of the substrate 102 and spaced apart from each other. The substrate 102 may be a semiconductor substrate on which a plurality of dielectric layers are deposited, and these dielectric layers may be, for example, a silicon oxide (SiO2) layer and a silicon nitride (SiN) layer on the silicon oxide layer. Each capacitor 104 includes a semiconductor layer 106, a conductive layer 108 on the semiconductor layer 106, an upper electrode layer 110 on the sidewalls of the semiconductor layer 106 and the conductive layer 108, an insulating layer 112 on the upper electrode layer 110, and a lower electrode layer (not shown) surrounding the bottom of the insulating layer 112. In some embodiments, the material of the semiconductor layer 106 may include polysilicon, the material of the conductive layer 108 may include indium tin oxide (ITO), and the material of the insulating layer 112 may include a high dielectric constant dielectric material.

[0027] Multiple channels 114 are disposed on capacitor 104. Specifically, channels 114 connect to conductive layer 108 of capacitor 104. Gate dielectric layer 116 is located around channels 114. Word lines 118 are disposed on substrate 102 and extend along a first direction (e.g., x-axis), with gate dielectric layer 116 and channels 114 extending through word lines 118. In other words, word lines 118 surround gate dielectric layer 116 and channels 114 and contact gate dielectric layer 116. In some embodiments, the material of channels 114 may include indium gallium zinc oxide (IGZO), or any suitable material having low-leakage properties. A first dielectric material 120 is disposed on substrate 102 and around word lines 118, gate dielectric layer 116, and channels 114. In some embodiments, the top surface of the first dielectric material 120 is coplanar with the top surfaces of gate dielectric layer 116 and channels 114.

[0028] Multiple landing pads 124 are disposed on the channel 114. Specifically, a conductive layer 122 is disposed on the channel 114, and the landing pads 124 are disposed on the conductive layer 122. In some embodiments, the material of the landing pads 124 may include tungsten (W), or any suitable conductive material. In some embodiments, the material of the conductive layer 122 may include a transparent conductive oxide (TCO) material, such as indium tin oxide (ITO) and zinc oxide (ZnO).

[0029] Landing pad 124 may be formed by the following steps. First, material of conductive layer 122 is deposited on capacitor 104, and material of landing pad 124 is then deposited on the material of conductive layer 122. Subsequently, the materials of conductive layer 122 and landing pad 124 are patterned, followed by overfilling with dielectric material. The remaining portion of material of conductive layer 122 may be referred to as conductive layer 122. Finally, a planarization process is performed to form landing pad 124 separated from each other by a second dielectric material 126. The second dielectric material 126 is disposed around landing pad 124 and conductive layer 122. In some embodiments, the top surface of landing pad 124 and the top surface of second dielectric material 126 are coplanar.

[0030] A third dielectric material 128 is disposed on the landing pad 124 and the second dielectric material 126. The first dielectric material 120, the second dielectric material 126, and the third dielectric material 128 can be collectively referred to as dielectric material 130. In other words, the channel 114, the gate dielectric layer 116, the word line 118, the conductive layer 122, and the landing pad 124 are disposed within dielectric material 130. In some embodiments, the materials of the first dielectric material 120, the second dielectric material 126, and the third dielectric material 128 can be different or the same. In some embodiments, the material of dielectric material 130 may include oxides or other suitable dielectric materials.

[0031] See Figure 2 , Figure 2This is a cross-sectional view of the formation of a semiconductor structure at different stages according to some embodiments of the present invention. The method for forming the semiconductor structure proceeds to step S20. A hard mask layer 132 is formed on the dielectric material 130. The hard mask layer 132 is used to protect the structure beneath the hard mask layer 132 from etching in subsequent processes. The hard mask layer 132 can be formed by any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electron beam evaporation, etc. In some embodiments, the material of the hard mask layer 132 may include nitrides, such as silicon nitride (SiN).

[0032] See Figure 3 , Figure 3 This is a cross-sectional view of the formation of a semiconductor structure at different stages according to some embodiments of the present invention. The method for forming the semiconductor structure proceeds to step S30. A plurality of trenches 134 are formed. Specifically, trenches 134 are formed by passing through the hard mask layer 132 and the dielectric material 130 and into the landing pad 124. The trenches 134 extend along a second direction (e.g., the y-axis) and are spaced apart from each other in a first direction (e.g., the x-axis), wherein the second direction is perpendicular to the first direction.

[0033] Trench 134 can be formed by reactive ion etching (RIE) or any suitable etching process. A first etchant is used to remove the hard mask layer 132 and dielectric material 130, and a second etchant, different from the first etchant, is used to remove the landing pad 124. The first etchant has high etch selectivity between the landing pad 124 and the hard mask layer 132 and dielectric material 130. In other words, the etching process removes the hard mask layer 132 and dielectric material 130 with almost no etching of the landing pad 124. The second etchant has low etch selectivity between the landing pad 124 and the hard mask layer 132 and dielectric material 130. In other words, the etching process removes the landing pad 124, the hard mask layer 132, and the dielectric material 130 together. The etching process can be performed by the following steps. First, a portion of the hard mask layer 132 and dielectric material 130 is removed using a first etchant, exposing a portion of the landing pad 124. This exposed portion of the landing pad 124 is then removed using a second etchant. In some embodiments, an additional cleaning operation may be included in the etching process to remove residues generated during the etching process. In some embodiments, etching through the hard mask layer 132 and dielectric material 130 and into the landing pad 124 is performed in a chamber. In some embodiments, the first etchant may include CF4, CH2F2, etc. In some embodiments, the second etchant includes SF6, O2, Ar, Cl2, etc.

[0034] See Figure 4 , Figure 4 This is a cross-sectional view of the formation of a semiconductor structure at different stages according to some embodiments of the present invention. The method of forming the semiconductor structure proceeds to step S40. The hard mask layer 132 is removed. After forming the trench 134, the landing pad 124 may be recessed to a depth D1. In some embodiments, the depth D1 may be approximately half the height H1 of the landing pad 124. When the depth D1 is within this range, bit lines (subsequently formed in the trench 134, for example...) Figure 6 The bit lines 140 in the dielectric material 130 have a uniform arrangement and better connection with the landing pad 124. The trench 134 may be formed to have a top width W1 and a bottom width W2. The top width W1 is defined at the level of the top surface of the dielectric material 130, and the bottom width W2 is defined at the level of the top surface of the landing pad 124. In some embodiments, the bottom width W2 is smaller than the top width W1.

[0035] See Figure 5 , Figure 5 These are cross-sectional views of the formation of a semiconductor structure at different stages according to some embodiments of the present invention. The method for forming the semiconductor structure proceeds to step S50. Conductive material 136 is formed on dielectric material 130 and overfilled into trench 134 (e.g., Figure 4(as shown in the diagram). In some embodiments, conductive material 136 fills trench 134 and directly contacts landing pad 124. Conductive material 136 can be formed by any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electron beam evaporation, etc. In some embodiments, the material of conductive material 136 may include tungsten (W), or any suitable conductive material.

[0036] See Figure 6 , Figure 6 This is a cross-sectional view of the formation of a semiconductor structure at different stages according to some embodiments of the present invention. The method for forming the semiconductor structure proceeds to step S60. A plurality of bit lines 140 are formed on the landing pad 124. The bit lines 140 can be formed by planarizing the conductive material 136 and the dielectric material 130. The reserved portion of the conductive material 136 can be referred to as the bit line 140, and the reserved portion of the dielectric material 130 can be referred to as the first dielectric layer 138. Therefore, the top surface of the bit line 140 is coplanar with the top surface of the first dielectric layer 138. In some embodiments, the channel 114, the gate dielectric layer 116, the word line 118, the conductive layer 122, the landing pad 124, and the bit line 140 are disposed in the first dielectric layer 138.

[0037] In some embodiments, bit lines 140 are formed of tungsten (W). To prevent conductive material 136 from remaining on dielectric material 130, a certain amount of both conductive material 136 and dielectric material 130 may be removed. In some embodiments, bit lines 140 may be formed to have a height H2 in the range of 18 nm to 22 nm, for example, 18, 19, 20, 21, or 22 nm. When the height H2 of bit lines 140 is within this range, this prevents electrical short circuits between bit lines 140.

[0038] Specifically, bit line 140 is formed in trench 134 (e.g. Figure 4As shown in the diagram, the landing pad 124 is recessed to form a groove 134. Therefore, the bottom surface of the bit line 140 is lower than the top surface of the landing pad 124. In some embodiments, the landing pad 124 surrounds a portion of the bottom of the bit line 140. In some embodiments, a depth D2 (i.e., substantially the same as depth D1) is defined from the bottom surface of the bit line 140 to the top surface of the landing pad 124, and the depth D2 is half the height H1 of the landing pad 124. Furthermore, the bit line 140 is formed to have a top width W3 and a bottom width W4, with the bottom width W4 being smaller than the top width W3. In some embodiments, the top width W3 is defined at the level of the top surface of the bit line 140, and the bottom width W4 is defined at the level of the top surface of the landing pad 124. The bit lines 140 extend along a second direction (e.g., the y-axis) and are spaced apart from each other in a first direction (e.g., the x-axis). In some embodiments, the bit lines 140 directly contact the landing pad 124 and the first dielectric layer 138. In some embodiments, bit line 140 is electrically connected to capacitor 104.

[0039] This invention discloses a bit line 140, which is formed through the following steps. First, a trench 134 is formed through the dielectric material 130 and into the landing pad 124. A conductive material 136 is deposited to fill the trench 134. Then, a planarization process is performed on the conductive material 136 and the dielectric material 130. The formed bit lines 140 are separated from each other by a first dielectric layer 138 to reduce the possibility of electrical short circuits between the bit lines 140.

[0040] See Figure 7 , Figure 7 This is a cross-sectional view of the formation of a semiconductor structure at different stages according to some embodiments of the present invention. The method for forming the semiconductor structure proceeds to step S70. A semiconductor structure 100 is formed. A second dielectric layer 142 is formed on the first dielectric layer 138 and the bit line 140. Specifically, the second dielectric layer 142 directly contacts the top surface of the bit line 140 and the top surface of the first dielectric layer 138. In some embodiments, the bit line 140 is composed of tungsten (W) and directly contacts the second dielectric layer 142. In some embodiments, the second dielectric layer 142 may be formed by any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electron beam evaporation, etc.

[0041] In some embodiments, bit line 140 is formed of tungsten (W) without a metal layer and dielectric layer (e.g., capping layer). When channel 114 contains indium gallium zinc oxide (IGZO), the structure of bit line 140 without a capping layer can protect the integrity of channel 114 in semiconductor structure 100.

[0042] In summary, trenches are first formed in the landing pad and dielectric material, and then bit lines are formed within these trenches. The resulting bit lines have a bottom width smaller than their top width, which reduces the likelihood of electrical short circuits between the bit lines and the landing pad. Furthermore, the bottom surface of the bit lines is lower than the top surface of the landing pad, and the depth between the bottom surface of the bit lines and the top surface of the landing pad is half the height of the landing pad. This allows for a uniform arrangement of the bit lines and better connection with the landing pad.

[0043] Although the invention has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments included herein.

[0044] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover modifications and variations of the invention falling within the appended claims.

[0045] [Symbol Explanation] 100: Semiconductor Structure 102: Substrate 104: Capacitor 106: Semiconductor layer 108: Conductive layer 110: Upper electrode layer 112: Insulation layer 114: Channel 116: Gate dielectric layer 118: Character Line 120: First dielectric material 122: Conductive layer 124: Landing mat 126: Second dielectric material 128: Third dielectric material 130: Dielectric materials 132: Hard mask layer 134: Trench 136: Conductive materials 138: First dielectric layer 140: Bit line 142: Second dielectric layer D1: Depth D2: Depth H1: Height H2: Height S10: Steps S20: Steps S30: Steps S40: Steps S50: Steps S60: Steps S70: Steps W1: Top width W2: Bottom width W3: Top width W4: Bottom width X: Axis Y: axis Z: Axis.

Claims

1. A semiconductor structure, characterized in that, include: Capacitor, in the substrate; Channel, connected to the capacitor; Gate dielectric layer, surrounding the channel; A character line on the substrate, wherein the channel and the gate dielectric layer extend through the character line; Landing mats, on the passageway; A bit line on the landing pad, wherein the bottom surface of the bit line is lower than the top surface of the landing pad, and the bottom width of the bit line is smaller than the top width of the bit line; A first dielectric layer is formed on the substrate, wherein the channel, the gate dielectric layer, the word line, the landing pad, and the bit line are contained within the first dielectric layer; and The second dielectric layer is on the first dielectric layer and on the bit line.

2. The semiconductor structure of claim 1, wherein the bottom width of the bit line is defined at the level of the top surface of the landing pad, and the top width of the bit line is defined at the level of the top surface of the bit line.

3. The semiconductor structure of claim 1, wherein a depth is defined from the bottom surface of the bit line to the top surface of the landing pad, the depth being half the height of the landing pad.

4. The semiconductor structure of claim 1, wherein the bit line is in direct contact with the landing pad.

5. The semiconductor structure of claim 1, wherein the channel comprises indium gallium zinc oxide.

6. The semiconductor structure of claim 1, wherein the bit is linearly connected to the capacitor.

7. The semiconductor structure of claim 1, wherein the bit line has a height in the range of 18 nm to 22 nm.

8. The semiconductor structure according to claim 1, wherein the bit line is composed of tungsten.

9. The semiconductor structure of claim 1, wherein the landing pad surrounds a portion of the bottom of the bit line.

10. The semiconductor structure of claim 1, wherein the second dielectric layer directly contacts the top surface of the bit line and the top surface of the first dielectric layer.

11. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, a capacitor disposed in the substrate, a channel connecting the capacitor, a gate dielectric layer surrounding the channel, a landing pad on the channel, a word line on the substrate, wherein the channel and the gate dielectric layer extend through the word line and a dielectric material on the substrate. Grooves are formed in the dielectric material and the landing pad; A conductive material is deposited on the dielectric material and the trench is overfilled; The conductive material and the dielectric material are planarized to form a bit line and a first dielectric layer, wherein the bottom width of the bit line is smaller than the top width of the bit line; and A second dielectric layer is formed on the first dielectric layer and on the bit line.

12. The method of claim 11, wherein forming the trench in the dielectric material and the landing pad comprises: A hard mask is deposited on the dielectric material; The etching penetrates the hard shield and the dielectric material and enters the landing pad; and Remove the hard mask.

13. The method of claim 12, wherein etching through the hard shield and the dielectric material and into the landing pad comprises: The etching penetrates the hard shield and the dielectric material, exposing a portion of the landing pad; and Remove that portion of the landing pad.

14. The method of claim 13, wherein the hard mask and the dielectric material are etched using a first etchant, and the portion of the landing pad is etched using a second etchant, the second etchant being different from the first etchant.

15. The method of claim 14, wherein the first etchant comprises carbon tetrafluoride and difluoromethane, and the second etchant comprises sulfur hexafluoride, oxygen, argon, and chlorine.

16. The method of claim 12, wherein the etching through the hard shield and the dielectric material and into the landing pad is performed in a chamber.

17. The method of claim 11, wherein forming the trench in the dielectric material and the landing pad comprises: The top surface of the landing pad is recessed to the depth of the landing pad.

18. The method of claim 17, wherein the depth is half the height of the landing pad.

19. The method of claim 11, wherein the top surface of the bit line is coplanar with the top surface of the first dielectric layer.

20. The method of claim 11, wherein the conductive material completely fills the trench.

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