Semiconductor memory device

Abstract

A semiconductor memory device includes a substrate including an NMOS region and a PMOS region, a first gate pattern on the NMOS region, and a second gate pattern on the PMOS region. The first gate pattern includes a first gate insulating layer, an N-type work function pattern, a first conductive pattern, and a first gate electrode stacked on the substrate. The second gate pattern includes a second gate insulating layer, a high-k layer, a second conductive pattern, and a second gate electrode stacked on the substrate. The first gate electrode includes a first lower electrode including polysilicon and a first upper electrode including tungsten on the first lower electrode. The second gate electrode includes a second lower electrode including polysilicon and a second upper electrode including tungsten on the second lower electrode. The first conductive pattern and the second conductive pattern each include titanium nitride. The N-type work function pattern includes a metal oxide including lanthanum and is in contact with the first conductive pattern. The high-k layer includes hafnium oxide and is in contact with the second gate insulating layer and the second conductive pattern.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202210920453.0, entitled "Semiconductor Memory Device," filed with the State Intellectual Property Office on August 2, 2022. Technical Field

[0002] Some example embodiments relate to a semiconductor memory device. Background Technology

[0003] Semiconductor memory devices include multiple transistors. The transistors integrated into the semiconductor memory device are formed in various structures according to required performance characteristics, such as operating voltage and / or drive current. For example, there are complementary mode (e.g., CMOS) device structures in which NMOS and PMOS elements have metal gate electrodes with different conductivity types. Optionally or additionally, the thickness of the gate insulating layer included in these elements can vary depending on the applied voltage. Summary of the Invention

[0004] Some example embodiments provide a semiconductor memory device with improved reliability.

[0005] However, the various aspects of the exemplary embodiments are not limited to the one aspect set forth herein. The above and other aspects of the inventive concept will become more apparent to those skilled in the art upon which the inventive concept pertains by referring to the following detailed description of the inventive concept.

[0006] According to some example embodiments, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate including an NMOS region and a PMOS region; a first gate pattern located on the NMOS region of the substrate; and a second gate pattern located on the PMOS region of the substrate. The first gate pattern includes a first high-k layer, a diffusion mitigation pattern, an N-type work function pattern, and a first gate electrode sequentially stacked on the substrate. The second gate pattern includes a second high-k layer and a second gate electrode sequentially stacked on the substrate. The diffusion mitigation pattern is in contact with the first high-k layer. The stacking structure of the first gate electrode is the same as the stacking structure of the second gate electrode, and the second gate pattern does not include the N-type work function pattern.

[0007] According to some example embodiments, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate including a first peripheral region, a second peripheral region, a third peripheral region, and a fourth peripheral region; a first peripheral insulating layer, a second peripheral insulating layer, a third peripheral insulating layer, and a fourth peripheral insulating layer respectively located on the first peripheral region, the second peripheral region, the third peripheral region, and the fourth peripheral region of the substrate, wherein the first peripheral insulating layer is thicker than the second peripheral insulating layer, and the third peripheral insulating layer is thicker than the fourth peripheral insulating layer; a first peripheral gate pattern, a second peripheral gate pattern, and a third peripheral gate pattern respectively located on the first peripheral insulating layer, the second peripheral insulating layer, and the third peripheral insulating layer; a channel layer disposed between the substrate and the fourth peripheral insulating layer in the fourth peripheral region, the channel layer comprising silicon germanium; and a fourth peripheral gate pattern located on the channel layer. The first peripheral gate pattern includes a first peripheral high-k layer, a first peripheral diffusion mitigation pattern, a first peripheral N-type work function pattern, and a first peripheral gate electrode, sequentially stacked on a substrate. The second peripheral gate pattern includes a second peripheral high-k layer, a second peripheral diffusion mitigation pattern, a second peripheral N-type work function pattern, and a second peripheral gate electrode, sequentially stacked on a substrate. The third peripheral gate pattern includes a third peripheral high-k layer and a third peripheral gate electrode, sequentially stacked on a substrate. The fourth peripheral gate pattern includes a fourth peripheral high-k layer and a fourth peripheral gate electrode, sequentially stacked on a channel layer. The first peripheral diffusion mitigation pattern is in contact with the first peripheral high-k layer, and the second peripheral diffusion mitigation pattern is in contact with the second peripheral high-k layer. The first, second, third, and fourth peripheral gate electrodes have the same stacking structure, and the third and fourth peripheral gate patterns do not include the first and second peripheral N-type work function patterns.

[0008] According to some example embodiments, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate including a cell array region, a first peripheral region, and a second peripheral region; a bit line intersecting the substrate in the cell array region; a buffer layer disposed between the bit line and the substrate; a first peripheral gate pattern located on the first peripheral region of the substrate; and a second peripheral gate pattern located on the second peripheral region of the substrate. The first peripheral gate pattern includes a first high-k layer, a diffusion mitigation pattern, an N-type work function pattern, and a first gate electrode sequentially stacked on the substrate. The second peripheral gate pattern includes a second high-k layer and a second gate electrode sequentially stacked on the substrate. The diffusion mitigation pattern contacts the first high-k layer. The first gate electrode, the second gate electrode, and the bit line have the same stacking structure, and the second peripheral gate pattern does not include the N-type work function pattern.

[0009] According to some example embodiments, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate including an NMOS region and a PMOS region; a first gate pattern located on the NMOS region of the substrate; and a second gate pattern located on the PMOS region of the substrate, wherein the first gate pattern includes a first gate insulating layer, an N-type work function pattern, a first conductive pattern, and a first gate electrode stacked on the substrate, the second gate pattern includes a second gate insulating layer, a high-k layer, a second conductive pattern, and a second gate electrode stacked on the substrate, the first gate electrode includes a first lower electrode and a first upper electrode, the first lower electrode includes polysilicon, the first upper electrode is located on the first lower electrode and includes tungsten (W), the second gate electrode includes a second lower electrode and a second upper electrode, the second lower electrode includes polysilicon, the second upper electrode is located on the second lower electrode and includes tungsten (W), the first conductive pattern and the second conductive pattern both include titanium nitride (TiN), the N-type work function pattern includes a metal oxide containing lanthanum (La) and is in contact with the first conductive pattern, and the high-k layer includes hafnium oxide and is in contact with the second gate insulating layer and the second conductive pattern.

[0010] According to some example embodiments, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate including an NMOS region and a PMOS region; a first gate pattern located on the NMOS region of the substrate; and a second gate pattern located on the PMOS region of the substrate, wherein the first gate pattern includes a first gate insulating layer, an N-type work function pattern, a first conductive pattern, and a first gate electrode stacked on the substrate, the second gate pattern includes a second gate insulating layer, a high-k layer, a second conductive pattern, and a second gate electrode stacked on the substrate, the first gate electrode includes a first lower electrode and a first upper electrode, the first lower electrode includes polysilicon, the first upper electrode is located on the first lower electrode and includes tungsten (W), and the second gate electrode includes a second lower electrode and a second upper electrode. The electrode comprises a second lower electrode comprising polycrystalline silicon, a second upper electrode located on the second lower electrode and comprising tungsten (W), a first gate insulating layer and a second gate insulating layer both comprising silicon oxynitride, a first conductive pattern and a second conductive pattern both comprising titanium nitride (TiN), the vertical lengths of the first conductive pattern and the second conductive pattern being equal to each other, the first lower electrode contacting the first conductive pattern, the second lower electrode contacting the second conductive pattern, the vertical lengths of the first lower electrode and the second lower electrode being equal to each other, the vertical lengths of the first upper electrode and the second upper electrode being equal to each other, an N-type work function pattern comprising a metal oxide comprising lanthanum (La) and contacting the first conductive pattern, and a high k layer comprising hafnium oxide and contacting the second gate insulating layer and the second conductive pattern.

[0011] According to some example embodiments, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate including a first peripheral region, a second peripheral region, a third peripheral region, and a fourth peripheral region; a first peripheral gate pattern, a second peripheral gate pattern, a third peripheral gate pattern, and a fourth peripheral gate pattern, respectively located on the substrate of the first peripheral region, the second peripheral region, the third peripheral region, and the fourth peripheral region; a channel layer located between the substrate of the fourth peripheral region and the fourth peripheral gate pattern, and comprising silicon germanium, wherein the first peripheral gate pattern includes a first peripheral insulating layer, a first peripheral N-type work function pattern, and a first peripheral conductive pattern stacked on the substrate. The first peripheral gate pattern includes a second peripheral insulating layer, a second peripheral N-type work function pattern, a second peripheral conductive pattern, and a second peripheral gate electrode stacked on a substrate, wherein the first peripheral insulating layer is thicker than the second peripheral insulating layer. The third peripheral gate pattern includes a third peripheral insulating layer, a first peripheral high-k layer, a third peripheral conductive pattern, and a third peripheral gate electrode stacked on a substrate. The fourth peripheral gate pattern includes a fourth peripheral insulating layer, a second peripheral high-k layer, a fourth peripheral conductive pattern, and a fourth peripheral gate electrode stacked on a channel layer, wherein the third peripheral insulating layer is thicker than the fourth peripheral insulating layer. The first peripheral gate electrode includes a first peripheral lower electrode and a first peripheral lower electrode. The peripheral upper electrode includes a first peripheral lower electrode comprising polycrystalline silicon, the first peripheral upper electrode being located on the first peripheral lower electrode and comprising tungsten (W); the second peripheral gate electrode includes a second peripheral lower electrode and a second peripheral upper electrode, the second peripheral lower electrode comprising polycrystalline silicon, the second peripheral upper electrode being located on the second peripheral lower electrode and comprising tungsten (W); the third peripheral gate electrode includes a third peripheral lower electrode and a third peripheral upper electrode, the third peripheral lower electrode comprising polycrystalline silicon, the third peripheral upper electrode being located on the third peripheral lower electrode and comprising tungsten (W); the fourth peripheral gate electrode includes a fourth peripheral lower electrode and a fourth peripheral upper electrode, the fourth peripheral lower electrode comprising polycrystalline silicon, the fourth peripheral upper electrode being located on the fourth peripheral lower electrode. The lower electrode includes tungsten (W), and the first, second, third, and fourth peripheral conductive patterns all include titanium nitride (TiN). The first and second peripheral N-type work function patterns both include metal oxides containing lanthanum (La). The first peripheral N-type work function pattern is in contact with the first peripheral conductive pattern, and the second peripheral N-type work function pattern is in contact with the second peripheral conductive pattern. The first and second peripheral high-k layers both include hafnium oxide. The first peripheral high-k layer is in contact with the third peripheral insulating layer and the third peripheral conductive pattern, and the second peripheral high-k layer is in contact with the fourth peripheral insulating layer and the fourth peripheral conductive pattern. Attached Figure Description

[0012] The above and other aspects and features of the inventive concept will become clearer by describing in detail some exemplary embodiments of the inventive concept with reference to the accompanying drawings.

[0013] Figure 1 This is an example cross-sectional view of a semiconductor memory device according to some example embodiments.

[0014] Figure 2 yes Figure 1 Enlarged views of regions P and Q.

[0015] Figures 3 to 8 This is a cross-sectional view showing a semiconductor memory device according to some example embodiments.

[0016] Figures 9 to 16 It sequentially shows the manufacturing or production of having Figure 1 A cross-sectional view of the process of a semiconductor memory device.

[0017] Figure 17 This is a plan view of a semiconductor memory device according to some example embodiments.

[0018] Figure 18 It is along Figure 17 A sectional view taken from lines AA, BB, CC, DD, and EE.

[0019] Figures 19 to 34 It shows the manufacturing process in sequence. Figure 18 A cross-sectional view of the process of a semiconductor memory device. Detailed Implementation

[0020] In the following description, for the purpose of describing the inventive concept in more detail, reference will be made to the accompanying drawings of some exemplary embodiments based on the inventive concept.

[0021] Figure 1 This is an example cross-sectional view of a semiconductor memory device according to some example embodiments. Figure 2 yes Figure 1 Enlarged views of regions P and Q.

[0022] The accompanying drawings of a semiconductor memory device according to some example embodiments show dynamic random access memory (DRAM) as an example, but the inventive concept is not limited thereto.

[0023] Reference Figure 1 and Figure 2 A substrate 1 including NMOS and PMOS regions is provided.

[0024] The substrate 1 may be, or may include, for example, a silicon single crystal substrate or a silicon-on-insulator (SOI) substrate, and may be doped or undoped. Optionally or additionally, the substrate 1 may include, but is not limited to, one or more of silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, and gallium antimonide.

[0025] A first trench 2a can be formed in the substrate 1 of the NMOS region. A second trench 2b can be formed in the substrate 1 of the PMOS region. A third trench 2c can be formed in the substrate 1 at the boundary between the NMOS region and the PMOS region. A first element isolation layer 9a can be disposed in the first trench 2a. A second element isolation layer 9b can be disposed in the second trench 2b. A third element isolation layer 9c can be disposed in the third trench 2c.

[0026] The first element isolation layer 9a may include a first liner 3a that covers or conformally covers the inner sidewall and bottom surface of the first trench 2a, a first buried insulating layer 7a that fills the first trench 2a, and a second liner 5a disposed between the first liner 3a and the first buried insulating layer 7a.

[0027] The second element isolation layer 9b may include a third liner 3b that covers or conformally covers the inner sidewall and bottom surface of the second trench 2b, a second buried insulation layer 7b that fills the second trench 2b, and a fourth liner 5b disposed between the third liner 3b and the second buried insulation layer 7b.

[0028] The third element isolation layer 9c may include a fifth liner 3c that covers or conformally covers the inner sidewall and bottom surface of the third trench 2c, a third buried insulation layer 7c that fills the third trench 2c, and a sixth liner 5c disposed between the fifth liner 3c and the third buried insulation layer 7c.

[0029] The first liner 3a, the third liner 3b, and the fifth liner 3c may comprise the same material, for example, they may be made of the same material. For example, each of the first liner 3a, the third liner 3b, and the fifth liner 3c may comprise silicon oxide. The second liner 5a, the fourth liner 5b, and the sixth liner 5c may comprise the same material, for example, they may be made of the same material. For example, the second liner 5a, the fourth liner 5b, and the sixth liner 5c may all comprise silicon nitride. The first buried insulating layer 7a, the second buried insulating layer 7b, and the third buried insulating layer 7c may comprise the same material, for example, they may be made of the same material. For example, each of the first buried insulating layer 7a, the second buried insulating layer 7b, and the third buried insulating layer 7c may comprise silicon oxide.

[0030] The first gate pattern GP1 can be disposed on the substrate 1 in the NMOS region. Although not shown, the source and drain can be disposed on both sides of the first gate pattern GP1 in the substrate 1. The source and drain of the NMOS region can be doped with, for example, N-type impurities (such as at least one of phosphorus and arsenic).

[0031] A channel layer 11 can be disposed on the substrate 1 in the PMOS region. The lattice constant of the channel layer 11 can be greater than the lattice constant of the substrate 1. For example, the channel layer 11 can be formed of silicon-germanium, while the substrate 1 can be formed of silicon. The channel layer 11 may include silicon-germanium, for example, only in the PMOS region. The channel layer 11 can improve the hole mobility in the PMOS transistor. Strain can be present on the channel layer 11. In addition, the channel layer 11 can be used to reduce work function. A second gate pattern GP2 can be disposed on the channel layer 11. Although not shown, the source and drain can be disposed on both sides of the second gate pattern GP2 in the channel layer 11 and the substrate 1. The source and drain in the PMOS region can be doped with P-type impurities (such as boron).

[0032] A dummy gate pattern GPc can be disposed at the boundary between the NMOS and PMOS regions. Although the dummy gate pattern GPc is not actually operational or electrically floating, it can be formed to maintain or help maintain constant etching process conditions at all locations and prevent loading effects. Optionally or additionally, the dummy gate pattern GPc can be formed to prevent dishing during subsequent chemical mechanical polishing (CMP) processes used to form the interlayer insulating layer.

[0033] The first gate pattern GP1 may include a first gate insulating layer 13a, a first high-dielectric (high-k) layer 15a, a diffusion mitigation pattern or diffusion prevention pattern 17a, an N-type work function pattern 19a, a first conductive pattern 21a, and a first gate electrode GEa, which are sequentially stacked. A first gate overlay pattern 31a may be disposed on the first gate pattern GP1. The first gate overlay pattern 31a may be disposed on the first gate electrode GEa. The diffusion prevention pattern 17a may be in contact with the first high-k layer 15a. The first high-k layer 15a may have a dielectric constant greater than that of silicon oxide (SiO2).

[0034] The second gate pattern GP2 may include a second gate insulating layer 13b, a second high-dielectric (high-k) layer 15b, a second conductive pattern 21b, and a second gate electrode GEb, which are sequentially stacked. A second gate overlay pattern 31b may be disposed on the second gate pattern GP2. The second gate overlay pattern 31b may be disposed on the second gate electrode GEb. The second gate pattern GP2 may not include any or both of the diffusion mitigation pattern or diffusion prevention pattern 17a and the N-type work function pattern 19a. The second high-k layer 15b may be in contact with the second conductive pattern 21b. The second high-k layer 15b may have a dielectric constant greater than that of silicon oxide (SiO2), and may or may not have the same dielectric constant as the first high-k layer 15a.

[0035] The vertical length of the first gate pattern GP1 can be greater than the vertical length of the second gate pattern GP2; however, the example embodiment is not limited thereto. For example, since the first gate pattern GP1 includes a diffusion prevention pattern 17a and an N-type work function pattern 19a, and the second gate pattern GP2 does not include the diffusion prevention pattern 17a and the N-type work function pattern 19a, the vertical length of the first gate pattern GP1 can be greater than the vertical length of the second gate pattern GP2.

[0036] A dummy gate overlay pattern 31c can be disposed on a dummy gate pattern GPc. The dummy gate pattern GPc can include a first portion C1 adjacent to the NMOS region and a second portion C2 adjacent to the PMOS region. The bottom surface of the first portion C1 of the dummy gate pattern GPc can be at a higher level than the bottom surface of the second portion C2 of the dummy gate pattern GPc.

[0037] The first part C1 of the dummy gate pattern GPc may include a dummy high k layer 15c, a dummy diffusion mitigation pattern or a dummy diffusion prevention pattern 17c, a dummy N-type work function pattern 19c, a dummy conductive pattern 21c, and a dummy gate electrode GEc, which are stacked sequentially.

[0038] The second portion C2 of the dummy gate pattern GPc does not include the dummy diffusion prevention pattern 17c and the dummy N-type work function pattern 19c. In the second portion C2 of the dummy gate pattern GP2, the dummy conductive pattern 21c may contact the dummy high-k layer 15c. In the second portion C2, a portion of the top surface of the dummy gate electrode GEc and a portion of the top surface of the dummy gate overlay pattern 31c may be recessed.

[0039] The first gate insulating layer 13a and the second gate insulating layer 13b may comprise, for example, silicon oxide, silicon oxynitride, or combinations thereof, and may comprise the same or different materials. The first high-k layer 15a, the second high-k layer 15b, and the dummy high-k layer 15c may comprise materials having a dielectric constant higher than that of silicon oxide. The first high-k layer 15a, the second high-k layer 15b, and the dummy high-k layer 15c may comprise, for example, at least one of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0040] The diffusion prevention pattern 17a and the dummy diffusion prevention pattern 17c may include, for example, titanium nitride, tungsten nitride, or tantalum nitride. Preferably, the diffusion prevention pattern 17a and the dummy diffusion prevention pattern 17c include titanium nitride (TiN). The diffusion prevention pattern 17a and the dummy diffusion prevention pattern 17c may at least partially mitigate or reduce or prevent the diffusion of elements (e.g., lanthanum (La)) included in the N-type work function pattern 19a. The diffusion prevention pattern 17a may be in contact with the first high-k layer 15a. The dummy diffusion prevention pattern 17c may be in contact with the dummy high-k layer 15c.

[0041] The N-type work function pattern 19a and the dummy N-type work function pattern 19c may include at least one of, for example, lanthanum (La), lanthanum oxide (LaO), magnesium (Mg), magnesium oxide (MgO), tantalum (Ta), tantalum nitride (TaN), and niobium (Nb).

[0042] The first gate electrode GEa may include a first lower electrode 23a, a first intermediate electrode 25a, and a first upper electrode 27a. The first lower electrode 23a, the first intermediate electrode 25a, and the first upper electrode 27a may be stacked sequentially. The second gate electrode GEb may include a second lower electrode 23b, a second intermediate electrode 25b, and a second upper electrode 27b. The second lower electrode 23b, the second intermediate electrode 25b, and the second upper electrode 27b may be stacked sequentially. The dummy gate electrode GEc may include a dummy lower electrode 23c, a dummy intermediate electrode 25c, and a dummy upper electrode 27c. The dummy lower electrode 23c, the dummy intermediate electrode 25c, and the dummy upper electrode 27c may be stacked sequentially. The first gate electrode GEa, the second gate electrode GEb, and the dummy gate electrode GEc may all have the same stacking structure, for example, they may all have the same elements and / or layers of the same thickness arranged and / or connected to each other in the same way.

[0043] Each of the first lower electrode 23a, the second lower electrode 23b, and the dummy lower electrode 23c may comprise polycrystalline silicon doped with impurities. The conductivity type of the impurity doped in the first lower electrode 23a may differ from the conductivity type of the impurity doped in the second lower electrode 23b. For example, the first lower electrode 23a may be doped with an N-type impurity (such as one or more of phosphorus and arsenic), and the second lower electrode 23b may be doped with a P-type impurity (such as boron). Each of the first intermediate electrode 25a, the second intermediate electrode 25b, and the dummy intermediate electrode 25c may comprise TiSiN. Each of the first upper electrode 27a, the second upper electrode 27b, and the dummy upper electrode 27c may comprise tungsten (W). However, the spirit of the inventive concept is not limited thereto.

[0044] Each of the first gate cover pattern 31a, the second gate cover pattern 31b, and the dummy gate cover pattern 31c may include, but is not limited to, silicon nitride.

[0045] In the second element isolation layer 9b, the upper portion of the fourth liner 5b may protrude further than the upper portion of the third liner 3b and the upper portion of the second buried insulating layer 7b. A first recess R1 may be formed on the third liner 3b. A second recess R2 may be formed on the second buried insulating layer 7b. The vertical depth from the bottom surface of the second gate pattern GP2 to the lowest point of the first recess R1 may be less than the vertical depth from the bottom surface of the second gate pattern GP2 to the lowest point of the second recess R2. The depth of the second recess R2 may be greater than the depth of the first recess R1. For example, the second buried insulating layer 7b may be recessed further than the third liner 3b.

[0046] In the third element isolation layer 9c, the upper portion of the sixth liner 5c may protrude further than the upper portions of the fifth liner 3c and the third buried insulating layer 7c. The third recess R3 may be formed on the fifth liner 3c adjacent to the second portion C2 of the dummy gate pattern GPc. The fourth recess R4 may be formed on the third buried insulating layer 7c adjacent to the second portion C2 of the dummy gate pattern GPc. The vertical depth from the bottom surface of the second gate pattern GP2 to the lowest point of the third recess R3 may be the same as the vertical depth from the bottom surface of the second gate pattern GP2 to the lowest point of the first recess R1. The vertical depth from the bottom surface of the second gate pattern GP2 to the lowest point of the fourth recess R4 may be the same as the vertical depth from the bottom surface of the second gate pattern GP2 to the lowest point of the second recess R2.

[0047] In the first element isolation layer 9a, the upper portion of the second liner 5a may protrude further than the upper portions of the first liner 3a and the first buried insulating layer 7a. A fifth recess R5 may be formed on the first liner 3a. A sixth recess R6 may be formed on the first buried insulating layer 7a. The vertical depth from the bottom surface of the first gate pattern GP1 to the lowest point of the fifth recess R5 may be less than the vertical depth from the bottom surface of the first gate pattern GP1 to the lowest point of the sixth recess R6.

[0048] The vertical depth of the first recess R1 can be greater than (deeper than) the vertical depth of the fifth recess R5. The vertical depth of the second recess R2 can be greater than (deeper than) the vertical depth of the sixth recess R6.

[0049] The seventh recess R7 can be formed on the fifth liner 3c adjacent to the first portion C1 of the dummy gate pattern GPc. The eighth recess R8 can be formed on the third buried insulating layer 7c adjacent to the first portion C1 of the dummy gate pattern GPc. The vertical depth from the bottom surface of the first gate pattern GP1 to the lowest point of the seventh recess R7 can be the same as the vertical depth from the bottom surface of the first gate pattern GP1 to the lowest point of the fifth recess R5. The vertical depth from the bottom surface of the first gate pattern GP1 to the low point (e.g., the lowest point) of the eighth recess R8 can be the same as the vertical depth from the bottom surface of the first gate pattern GP1 to the lowest point of the sixth recess R6.

[0050] exist Figure 2 In this configuration, the bottom surface GP1_BS of the first gate pattern GP1 can be lower than the bottom surface GP2_BS of the second gate pattern GP2. The first gate pattern GP1 can contact the substrate 1. The second gate pattern GP2 can contact the channel layer 11. The top surface of the substrate 1 can be positioned lower than the top surface of the channel layer 11. Therefore, the bottom surface GP1_BS of the first gate pattern GP1 can be positioned lower than the bottom surface GP2_BS of the second gate pattern GP2.

[0051] The first gate insulating layer 13a can contact the substrate 1. The bottom surface of the first gate insulating layer 13a can contact the top surface of the substrate 1. The second gate insulating layer 13b can contact the channel layer 11. The bottom surface of the second gate insulating layer 13b can contact the top surface of the channel layer 11.

[0052] The first high-k layer 15a can contact the first gate insulating layer 13a. The second high-k layer 15b can contact the second gate insulating layer 13b. The diffusion prevention pattern 17a can contact the first high-k layer 15a. The bottom surface of the diffusion prevention pattern 17a can contact the top surface of the first high-k layer 15a. The diffusion prevention pattern 17a can contact the N-type work function pattern 19a. The top surface of the diffusion prevention pattern 17a can contact the bottom surface of the N-type work function pattern 19a.

[0053] In some example embodiments, the diffusion prevention pattern 17a may be a monolayer comprising titanium nitride (TiN), but the example embodiments are not limited thereto.

[0054] The first gate pattern GP1 may include a first conductive pattern 21a on the N-type work function pattern 19a. The first conductive pattern 21a may be in contact with the N-type work function pattern 19a. The second gate pattern GP2 may include a second conductive pattern 21b on the second high-k layer 15b. The second conductive pattern 21b may be in contact with the second high-k layer 15b.

[0055] In some example embodiments, the vertical length H1 of the first conductive pattern 21a can be the same as the vertical length H2 of the second conductive pattern 21b. The first conductive pattern 21a and the second conductive pattern 21b can be formed (e.g., simultaneously) using the same process. Therefore, the vertical length of the first conductive pattern 21a can be the same as the vertical length of the second conductive pattern 21b.

[0056] Each of the first conductive pattern 21a and the second conductive pattern 21b may include titanium nitride (TiN). Each of the first conductive pattern 21a and the second conductive pattern 21b may be a single layer, but is not limited thereto.

[0057] In some example embodiments, the stacked structures of the first gate electrode GEa and the second gate electrode GEb can be identical, for example, they can have the same elements arranged in the same manner. The vertical length of the first gate electrode GEa is the same as the vertical length of the second gate electrode GEb. Furthermore, the vertical length of the first lower electrode 23a is the same as the vertical length of the second lower electrode 23b. The vertical length of the first intermediate electrode 25a is the same as the vertical length of the second intermediate electrode 25b. The vertical length of the first upper electrode 27a is the same as the vertical length of the second upper electrode 27b. The first gate electrode GEa and the second gate electrode GEb can be formed (e.g., simultaneously) using the same process.

[0058] The vertical length of the first gate cover pattern 31a can be the same as the vertical length of the second gate cover pattern 31b. The first gate cover pattern 31a and the second gate cover pattern 31b can be formed (e.g., simultaneously) using the same process.

[0059] In some example embodiments, the top surface 31a_US of the first gate cover pattern 31a may not be on the same plane as the top surface 31b_US of the second gate cover pattern 31b. Although it is shown that the top surface 31a_US of the first gate cover pattern 31a is higher than the top surface 31b_US of the second gate cover pattern 31b, this is only for simplicity and is not a limitation. The top surface 31a_US of the first gate cover pattern 31a may be formed to be lower than the top surface 31b_US of the second gate cover pattern 31b.

[0060] Figures 3 to 8 This is a cross-sectional view illustrating a semiconductor memory device according to various example embodiments. For reference, Figures 3 to 8 This can be an enlarged view of the first gate pattern GP1 and the second gate pattern GP2. Referring to the following... Figures 3 to 8 This describes a semiconductor memory device according to various example embodiments. For the sake of simplicity, the following description will focus on references to... Figure 1 and Figure 2 The differences in the descriptions.

[0061] Reference Figure 3 The first gate pattern GP1 may also include a first boundary pattern 18a and a second boundary pattern 20a.

[0062] The first boundary pattern 18a may be formed at the boundary between the diffusion prevention pattern 17a and the N-type work function pattern 19a. The first boundary pattern 18a may include a compound that is oxidized from the diffusion prevention pattern 17a and the N-type work function pattern 19a, or a compound contained in the diffusion prevention pattern 17a and the N-type work function pattern 19a. For example, the first boundary pattern 18a may include at least one of lanthanum titanium nitride (LaTiN) and lanthanum titanium oxynitride (LaTiNO), but is not limited thereto.

[0063] When the first boundary pattern 18a is formed, the vertical length of the diffusion prevention pattern 17a can be reduced. Furthermore, when the first boundary pattern 18a is formed, the vertical length of the N-type work function pattern 19a can be reduced. The first boundary pattern 18a can be formed when the diffusion prevention pattern 17a and the N-type work function pattern 19a are oxidized at the boundary between the diffusion prevention pattern 17a and the N-type work function pattern 19a (e.g., spontaneous oxidation and / or oxidation in a controlled process).

[0064] The second boundary pattern 20a may be formed at the boundary between the N-type work function pattern 19a and the first conductive pattern 21a. The second boundary pattern 20a may include compounds of the oxidized N-type work function pattern 19a and the first conductive pattern 21a, and / or compounds contained in the N-type work function pattern 19a and the first conductive pattern 21a. For example, the second boundary pattern 20a may include at least one of lanthanum titanium nitride (LaTiN) and lanthanum titanium oxynitride (LaTiNO), but is not limited thereto.

[0065] When the second boundary pattern 20a is formed, the vertical length of the N-type work function pattern 19a can be reduced. Furthermore, when the second boundary pattern 20a is formed, the vertical length of the first conductive pattern 21a can be reduced. For example, when the second boundary pattern 20a is formed, the vertical length H1 of the first conductive pattern 21a can be less than the vertical length H2 of the second conductive pattern 21b. In other words, the second boundary pattern 20a can be formed when the N-type work function pattern 19a and the first conductive pattern 21a are oxidized at the boundary between them.

[0066] Reference Figure 4The vertical length H1 of the first conductive pattern 21a can be less than the vertical length H2 of the second conductive pattern 21b. For example, the second conductive pattern 21b can be a single layer and can share a portion of the first conductive pattern 21a. For example, the second conductive pattern 21b can be formed by the same process as that used to form the first conductive pattern 21a (e.g., simultaneously with the process used to form the first conductive pattern 21a).

[0067] When diffusion prevention pattern 17a and N-type work function pattern 19a are formed Figure 12 diffusion prevention layer 17 and Figure 12 The N-type active power layer 19 is also formed in the PMOS region. Subsequently, the diffusion prevention layer and the N-type active power layer can be removed in the PMOS region, for example, while remaining in the NMOS region. In the process of removing the diffusion prevention layer and the N-type active power layer, a portion of the diffusion prevention layer may not be removed. Therefore, a diffusion prevention pattern with a certain thickness (such as a variable and determined thickness (or optionally, a predetermined thickness)) can be retained on the second high-k layer 15b.

[0068] The material forming the second conductive pattern 21b is the same as the material forming the diffusion prevention pattern 17a. Therefore, when the second conductive pattern 21b is formed on the diffusion prevention layer on the second high-k layer 15b that has not been removed and remains in the PMOS region, the vertical length H2 of the second conductive pattern 21b can be greater than the length when the entire diffusion prevention layer formed on the second high-k layer 15b is removed. Therefore, the vertical length H2 of the second conductive pattern 21b can be greater than the vertical length H1 of the first conductive pattern 21a.

[0069] In addition, Figure 4 In this configuration, the top surface 31a_US of the first gate covering pattern 31a can be located on the same plane as the top surface 31b_US of the second gate covering pattern 31b. When the thickness of the second conductive pattern 21b increases, the top surface 31b_US of the second gate covering pattern 31b can also be larger than... Figure 2 The top surface 31b_US of the second gate covering pattern 31b is higher. However, the technical spirit of the inventive concept is not limited thereto.

[0070] Reference Figure 5 It is possible to avoid forming the first conductive pattern 21a and the second conductive pattern 21b.

[0071] In the NMOS region, the first gate electrode GEa can be formed on the diffusion prevention pattern 17a and the N-type work function pattern 19a, for example, directly on the diffusion prevention pattern 17a and the N-type work function pattern 19a. In an embodiment, in the NMOS region, the first gate electrode GEa can be formed on the N-type work function pattern 19a, for example, directly on the N-type work function pattern 19a. In the PMOS region, the second gate electrode GEb can be formed on the second high-k layer 15b, for example, directly on the second high-k layer 15b.

[0072] In the NMOS region, the N-type work function pattern 19a can contact the first lower electrode 23a. In the PMOS region, the second high-k layer 15b can contact the second lower electrode 23b.

[0073] Reference Figure 6 The first conductive pattern 21a and the second conductive pattern 21b can be composed of multiple layers.

[0074] For example, the first conductive pattern 21a may include a first lower conductive pattern 21a_1, a first P-type work function pattern 21a_2, and a first upper conductive pattern 21a_3. The second conductive pattern 21b may include a second lower conductive pattern 21b_1, a second P-type work function pattern 21b_2, and a second upper conductive pattern 21b_3.

[0075] The first conductive pattern 21a and the second conductive pattern 21b can have the same stacking structure, such as the same layers arranged in the same way with the same thickness. The vertical length H1 of the first conductive pattern 21a can be the same as the vertical length H2 of the second conductive pattern 21b.

[0076] The thickness of the first lower conductive pattern 21a_1 and the thickness of the second lower conductive pattern 21b_1 can be the same. The thickness of the first P-type work function pattern 21a_2 and the thickness of the second P-type work function pattern 21b_2 can be the same. The thickness of the first upper conductive pattern 21a_3 and the thickness of the second upper conductive pattern 21b_3 can be the same.

[0077] Each of the first lower conductive pattern 21a_1 and the second lower conductive pattern 21b_1 may include titanium nitride (TiN). Each of the first p-type work function pattern 21a_2 and the second p-type work function pattern 21b_2 may include aluminum (Al). Each of the first upper conductive pattern 21a_3 and the second upper conductive pattern 21b_3 may include titanium nitride (TiN). However, the technical spirit of the inventive concept is not limited thereto.

[0078] Reference Figure 7 The first conductive pattern 21a may not be formed in the NMOS region and / or may be removed from the NMOS region.

[0079] The second conductive pattern 21b may be formed only in the PMOS region. The second conductive pattern 21b may be multiple layers including the second P-type work function pattern 21b_2. The first gate pattern GP1 in the NMOS region may not include the P-type work function pattern.

[0080] After forming conductive layers in both the NMOS and PMOS regions, the conductive layer in the NMOS region can be removed only. Therefore, the second conductive pattern 21b can be retained only in the PMOS region.

[0081] Reference Figure 8 The first conductive pattern 21a may not be formed in the NMOS region, and the second conductive pattern 21b in the PMOS region may be a single layer.

[0082] For example, in both the NMOS and PMOS regions, it is possible to form Figure 12 diffusion prevention layer 17 and Figure 12 The N-type active power layer 19 in the PMOS region, and in the process of removing the diffusion prevention layer and the N-type active power layer in the PMOS region, a portion of the diffusion prevention layer in the PMOS region may not be removed.

[0083] The diffusion prevention layer that is not removed can be transformed into a second conductive pattern 21b. The second conductive pattern 21b can be a monolayer comprising titanium nitride (TiN).

[0084] Figures 9 to 16 It sequentially shows the manufacturing or production of having Figure 1 A cross-sectional view of the semiconductor memory device process. In the following text, reference will be made to... Figures 9 to 16 Description of manufacturing with Figure 1 A method for constructing a semiconductor memory device with a cross-section.

[0085] Reference Figure 9 Prepare a substrate 1 that includes NMOS and PMOS regions.

[0086] The substrate 1 is etched to form a first trench 2a, a second trench 2b, and a third trench 2c. A first liner layer and a second liner layer are conformally formed (e.g., deposited using a process such as chemical vapor deposition (CVD)) on the front surface of the substrate 1. A buried insulating layer is formed to fill the first trench 2a, the second trench 2b, and the third trench 2c. A planarization process, such as CMP and / or etch-back processes, is performed to form a first element isolation layer 9a, a second element isolation layer 9b, and a third element isolation layer 9c in the first trench 2a, the second trench 2b, and the third trench 2c.

[0087] The first element isolation layer 9a may include a first liner 3a conformally covering the inner wall and bottom surface of the first trench 2a, a first buried insulating layer 7a filling the first trench 2a, and a second liner 5a disposed between the first liner 3a and the first buried insulating layer 7a. The second element isolation layer 9b may include a third liner 3b conformally covering the inner wall and bottom surface of the second trench 2b, a second buried insulating layer 7b filling the second trench 2b, and a fourth liner 5b disposed between the third liner 3b and the second buried insulating layer 7b. The third element isolation layer 9c may include a fifth liner 3c conformally covering the inner wall and bottom surface of the third trench 2c, a third buried insulating layer 7c filling the third trench 2c, and a sixth liner 5c disposed between the fifth liner 3c and the third buried insulating layer 7c.

[0088] Reference Figure 10 A first mask layer, MASK1, is formed that covers the NMOS region and exposes the PMOS region.

[0089] For example, the first mask layer MASK1 can be formed of a silicon oxide layer. The first mask layer MASK1 can cover a portion of the third element isolation layer 9c and expose another portion of the third element isolation layer 9c. A channel layer 11 is formed on the top surface of the substrate 1 exposed in the PMOS region by using the first mask layer MASK1 as an epitaxial barrier. The channel layer 11 can be formed by, for example, selective epitaxial growth (SEG). The channel layer 11 can include silicon germanium, for example, the channel layer 11 can be epitaxial silicon germanium (eSiGe). The channel layer 11 is not formed on the first element isolation layer 9a, the second element isolation layer 9b, and the third element isolation layer 9c.

[0090] Reference Figure 11 The first mask layer MASK1 can be removed. For example, the first mask layer MASK1 can be removed by a wet etching process including but not limited to buffered oxide etching (BOE).

[0091] When the first mask layer MASK1 is formed of a silicon oxide layer, hydrofluoric acid can be used as an etchant in a wet etching process. When the first mask layer MASK1 is removed, a portion of the second element isolation layer 9b and a portion of the third element isolation layer 9c exposed in the PMOS region can be etched in the same manner as the first mask layer MASK1.

[0092] For example, the upper portions of the third liner 3b, the second buried insulating layer 7b, the fifth liner 3c, and the third buried insulating layer 7c, which are made of the same material as the first mask layer MASK1, can be partially etched. Therefore, a first recess R1 can be formed on the third liner 3b. A second recess R2 can be formed on the second buried insulating layer 7b. A third recess R3 can be formed on the fifth liner 3c. A fourth recess R4 can be formed on the third buried insulating layer 7c.

[0093] The third liner 3b and the fifth liner 3c have relatively narrow widths. Therefore, etchant penetration can be relatively difficult. On the other hand, since the second buried insulating layer 7b and the third buried insulating layer 7c have large exposed areas, etchant penetration can be performed more easily. Therefore, the depths of the first recess R1 and the third recess R3 can be less than the depths of the second recess R2 and the fourth recess R4.

[0094] The fourth liner 5b and the sixth liner 5c, which are made of materials different from those of the first mask layer MASK1, are not etched like the first mask layer MASK1. Therefore, the upper parts of the fourth liner 5b and the sixth liner 5c can protrude from the third liner 3b, the second buried insulating layer 7b, the fifth liner 3c, and the third buried insulating layer 7c.

[0095] Reference Figure 12 A first gate insulating layer 13a can be formed on the substrate 1 in the NMOS region. A second gate insulating layer 13b can be formed on the channel layer 11 in the PMOS region.

[0096] The first gate insulating layer 13a and the second gate insulating layer 13b can be formed simultaneously by thermal oxidation and / or deposition processes. The first gate insulating layer 13a and the second gate insulating layer 13b can be formed from, for example, a silicon oxide layer. Although not shown, a cleaning process can be performed on the surface of the substrate 1 before forming the first gate insulating layer 13a and the second gate insulating layer 13b. The cleaning process can also be used to partially etch the surfaces of the first element isolation layer 9a, the second element isolation layer 9b, and the third element isolation layer 9c.

[0097] Subsequently, a pre-high k layer 15 can be formed on the substrate 1. A diffusion prevention layer 17 can be formed on the pre-high k layer 15. An N-type active power layer 19 can be formed on the diffusion prevention layer 17. The diffusion prevention layer 17 and the N-type active power layer 19 may be difficult to conformally deposit in the first depression R1 and the third depression R3, and therefore have relatively thin thicknesses.

[0098] The pre-high k layer 15 may include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0099] The diffusion prevention layer 17 may include, for example, titanium nitride (TiN). The N-type work function layer 19 may include at least one of, for example, lanthanum (La), lanthanum oxide (LaO), magnesium (Mg), magnesium oxide (MgO), tantalum (Ta), tantalum nitride (TaN), and niobium (Nb). However, the technical spirit of the inventive concept is not limited thereto.

[0100] Reference Figure 13 A second mask layer MASK2 can be formed on the N-type power efflux layer 19, covering the NMOS region and exposing the PMOS region.

[0101] The second mask layer MASK2 can be formed from at least one of a photoresist layer, an amorphous carbon layer (ACL), a spin-on hard mask (SOH), a spin-on carbon (SOC), and a silicon nitride layer.

[0102] The pre-high-k layer 15 is exposed by etching the N-type active power layer 19 and the diffusion prevention layer 17 in the PMOS region using a second mask layer MASK2 as an etching mask. A wet etching process can be used to remove the N-type active power layer 19 and the diffusion prevention layer 17 in the PMOS region. For example, an etchant containing sulfuric acid can be used to perform the wet etching process. Compared to a dry etching process, a wet etching process can significantly reduce etch damage to the pre-high-k layer 15.

[0103] Although the N-type work function layer 19 and diffusion prevention layer 17 of the PMOS region are shown to be completely removed to expose the pre-high k layer 15, the inventive concept is not limited thereto. The diffusion prevention layer 17 of the PMOS region may be partially removed or not removed at all. In this case, the pre-high k layer 15 of the PMOS region may not be exposed.

[0104] Reference Figure 14 Remove the second mask layer MASK2. Sequentially stack a conductive layer 21, a lower electrode layer 23, an intermediate electrode layer 25, an upper electrode layer 27, and a gate capping layer 31 on the front surface of the substrate 1.

[0105] The conductive layer 21 may include titanium nitride (TiN). The lower electrode layer 23 may include polysilicon doped with impurities. After depositing the polysilicon layer, N-type impurities may be doped into the lower electrode layer 23 of the NMOS region, and P-type impurities may be doped into the lower electrode layer 23 of the PMOS region. The lower electrode layer 23 may be doped with the same type of impurities in both the NMOS and PMOS regions. For example, both the NMOS and PMOS regions may be doped with N-type impurities (such as phosphorus and / or arsenic). As another example, both the NMOS and PMOS regions may be doped with P-type impurities (such as boron). The intermediate electrode layer 25 may include TiSiN. The upper electrode layer 27 may include tungsten (W). The gate capping layer 31 may include silicon nitride (SiN).

[0106] Reference Figure 15 A third mask layer MASK3 can be formed on the gate capping layer 31. The width of the third mask layer MASK3 can be the same as the width of the first gate pattern GP1, the second gate pattern GP2, and the dummy gate pattern GPc, which will be formed later. The third mask layer MASK3 can be formed from one or more of a photoresist layer, an amorphous carbon layer (ACL), a spin-on hard mask (SOH), and a spin-on carbon (SOC).

[0107] Reference Figure 16 In the NMOS region, the third mask layer MASK3 can be used as an etching mask to continuously etch the gate cover layer 31, the upper electrode layer 27, the middle electrode layer 25, the lower electrode layer 23, the conductive layer 21, the N-type work function layer 19, the diffusion prevention layer 17, and the pre-high k layer 15 (e.g., and the first gate insulating layer 13a) to form the first gate cover pattern 31a and the first gate pattern GP1.

[0108] In the PMOS region, the third mask layer MASK3 can be used as an etching mask to continuously etch the gate cover layer 31, the upper electrode layer 27, the middle electrode layer 25, the lower electrode layer 23, the conductive layer 21, and the pre-high k layer 15 (e.g., and the second gate insulating layer 13b) to form the second gate cover pattern 31b and the second gate pattern GP2.

[0109] At the boundary between the NMOS and PMOS regions, a third mask layer MASK3 can be used as an etching mask to continuously etch the gate cover layer 31, the upper electrode layer 27, the middle electrode layer 25, the lower electrode layer 23, the conductive layer 21, the N-type power loss layer 19, the diffusion prevention layer 17, and the pre-high k layer 15 to form a dummy gate cover pattern 31c and a dummy gate pattern GPc.

[0110] The first gate pattern GP1, the second gate pattern GP2, and the dummy gate pattern GPc can be formed simultaneously or synchronously.

[0111] Because the first depression R1 and the third depression R3 are relatively narrow and relatively deep, it may be difficult to achieve optimal performance when the thickness of the layer present in the first depression R1 and the third depression R3 increases. Figure 16 The etching process removes the layers present in the first recess R1 and the third recess R3. When the process of removing the diffusion prevention layer 17 and the N-type active power layer 19 of the PMOS region is not performed, the diffusion prevention layer 17 and the N-type active power layer 19 can exist in the first recess R1 and the third recess R3 of the PMOS region.

[0112] In this case, excessive etching may be required to remove the diffusion prevention layer 17 and the N-type active power layer 19 in the first recess R1 and the third recess R3 in the PMOS region. When excessive etching is required, the substrate 1 may also be damaged.

[0113] However, when using the method for manufacturing a semiconductor memory device according to some example embodiments of the inventive concept, in Figure 13 In the etching process, the diffusion prevention layer 17 and the N-type power transition layer 19 in the PMOS region are removed in advance by a wet etching process, so that in the subsequent... Figure 16 In the etching process, the process burden can be reduced. Optionally or additionally, the possibility of residue remaining in the first recess R1 and the third recess R3 can be reduced. Therefore, a semiconductor memory device with improved reliability can be realized.

[0114] Figure 17 This is a plan view of a semiconductor memory device according to some example embodiments. Figure 18 It is along Figure 17 The sectional views are taken from lines AA, BB, CC, DD, and EE. Referring to these views below... Figure 17 and Figure 18 This describes a semiconductor memory device according to some example embodiments.

[0115] Reference Figure 17 and Figure 18 A substrate 1 is provided, comprising a cell array region CA, a first peripheral region PA1, a second peripheral region PA2, a third peripheral region PA3, and a fourth peripheral region PA4.

[0116] The first peripheral region PA1, the second peripheral region PA2, the third peripheral region PA3, and the fourth peripheral region PA4 can be disposed around the cell array region CA. Peripheral circuitry for driving the word line WL and bit line BL disposed in the cell array region CA can be disposed in the first peripheral region PA1, the second peripheral region PA2, the third peripheral region PA3, and the fourth peripheral region PA4. For example, an NMOS high-voltage transistor can be disposed in the first peripheral region PA1. An NMOS low-voltage transistor can be disposed in the second peripheral region PA2. A PMOS high-voltage transistor can be disposed in the third peripheral region PA3. A PMOS low-voltage transistor can be disposed in the fourth peripheral region PA4. The first peripheral region PA1, the second peripheral region PA2, the third peripheral region PA3, and the fourth peripheral region PA4 can be disposed sequentially, but the example embodiment is not limited thereto.

[0117] Cell element isolation layer 105 can be disposed in substrate 1 of cell array region CA. Cell element isolation layer 105 can define cell active region ACTC. Due to the reduced design rules of semiconductor memory devices, cell active region ACTC can be provided in a diagonal and / or slanted bar shape as shown. For example, cell active region ACTC can extend in the third direction D3.

[0118] The active cell regions ACTC can be arranged parallel to each other in the first direction D1. The end of one active cell region ACTC can be arranged adjacent to the center of another adjacent active cell region ACTC. Here, the first direction D1 and the second direction D2 can be perpendicular to each other. The third direction D3 can be any direction between the first direction D1 and the second direction D2.

[0119] Substrate 1 can be a monocrystalline silicon or polycrystalline silicon substrate, or an SOI substrate. (See reference...) Figure 1 As described, the unit element isolation layer 105 may include an oxide liner, a nitride liner, and a buried insulation layer.

[0120] Semiconductor memory devices according to some example embodiments may include various contact arrangements formed on the cell active region ACTC. These various contact arrangements may include, for example, digital line contacts or direct contacts (DC, or “bit line contacts”), buried contacts (BC), bonding pads (LP, or “landing pads”), etc.

[0121] Here, the direct contact DC can refer to the contact that electrically connects the cell active region ACTC to the bit line BL. The buried contact BC can refer to the contact that connects the cell active region ACTC to the lower electrode 181 of the capacitor. Due to the configuration, the contact area between the buried contact BC and the cell active region ACTC may be small. Therefore, a conductive bonding pad LP can be introduced to increase the contact area with the lower electrode 181 of the capacitor, in addition to increasing the contact area with the cell active region ACTC.

[0122] The bonding pad LP can be disposed between the cell active region ACTC and the buried contact BC, or it can be disposed between the buried contact BC and the lower electrode 181 of the capacitor. In a semiconductor memory device according to some example embodiments, the bonding pad LP can be disposed between the buried contact BC and the lower electrode 181 of the capacitor. By introducing the bonding pad LP to increase the contact area, the contact resistance between the cell active region ACTC and the lower electrode 181 of the capacitor can be reduced.

[0123] Word lines WL may be buried in or within substrate 1. Word lines WL may intersect with cell active regions ACTC. Word lines WL may extend in a first direction D1. Word lines WL may be spaced apart from each other in a second direction D2. Word lines WL may be buried in substrate 1 and extend in the first direction D1. Although not shown, doped regions may be formed in the cell active regions ACTC between word lines WL. Doped regions may be doped with N-type impurities (such as at least one of arsenic and phosphorus).

[0124] A buffer layer 110 may be disposed on a substrate 1 of the cell array region CA. The buffer layer 110 may include a first cell insulating layer 111, a second cell insulating layer 112, and a third cell insulating layer 113 stacked sequentially. The second cell insulating layer 112 may include a material that is etch-selective for the first cell insulating layer 111 and the third cell insulating layer 113. For example, the second cell insulating layer 112 may include silicon nitride and may not include silicon oxide. The first cell insulating layer 111 and the third cell insulating layer 113 may include silicon oxide and may not include silicon nitride.

[0125] Bit line BL can be set on buffer layer 110. Bit line BL can intersect with substrate 1 and word line WL. For example... Figure 17 As shown, bit lines BL can extend in the second direction D2. Bit lines BL can be spaced apart from each other in the first direction D1.

[0126] Bit line BL may include a bit line lower electrode 130t, a bit line intermediate electrode 132t, and a bit line upper electrode 134t stacked sequentially. The bit line lower electrode 130t may include polycrystalline silicon doped with impurities. The bit line intermediate electrode 132t may include TiSiN. The bit line upper electrode 134t may include tungsten (W). However, the spirit of the inventive concept is not limited thereto.

[0127] Bit line overlay pattern 140 may be disposed on bit line BL. Bit line overlay pattern 140 may include a first bit line overlay pattern 142t and a second bit line overlay pattern 148t stacked sequentially. Each of the first bit line overlay pattern 142t and the second bit line overlay pattern 148t may include silicon nitride.

[0128] Bit line spacers 150 can be disposed on the sidewalls of bit line BL and bit line overlay pattern 140. Bit line spacers 150 can be disposed on the substrate 1 and unit element isolation layer 105 in the portion of bit line BL where direct contact elements DC are formed. However, in the portion where direct contact elements DC are not formed, bit line spacers 150 can be disposed on buffer layer 110.

[0129] Bit line spacer 150 may be a single layer, but as shown, bit line spacer 150 may be a multilayer including first bit line spacer 151 and second bit line spacer 152. For example, first bit line spacer 151 and second bit line spacer 152 may include, but are not limited to, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride (SiON) layer, a silicon carbonitride (SiOCN) layer, air (such as clean, dry air), and combinations thereof.

[0130] The buffer layer 110 can be placed between the bit line BL and the cell element isolation layer 105, and between the bit line spacer 150 and the substrate 1.

[0131] Bit line BL can be electrically connected to the doped region of the cell active region ACTC via direct contact DC. Direct contact DC can be formed of, for example, polysilicon doped with impurities.

[0132] Buried contacts BC can be disposed between a pair of adjacent bit lines BL. Buried contacts BC can be spaced apart from each other. Buried contacts BC can comprise at least one of doped polysilicon, conductive silicide compounds, conductive metal nitrides, and metals. Buried contacts BC can have the shape of islands spaced apart from each other in a planar view. Buried contacts BC can penetrate the buffer layer 110 to contact the doped region of the cell active region ACTC.

[0133] Bonding pad LP may be formed on buried contact BC. Bonding pad LP may be electrically connected to buried contact BC. Bonding pad LP may be stacked with a portion of the top surface of bit line BL. Bonding pad LP may include at least one of, for example, a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, and a metal alloy.

[0134] A pad separation insulating layer 160 can be formed on the bonding pad LP and the bit line BL. For example, the pad separation insulating layer 160 can be disposed on the bit line cover pattern 140. The pad separation insulating layer 160 can define the area of ​​the bonding pad LP that forms multiple separation regions. In addition, the pad separation insulating layer 160 may not cover the top surface of the bonding pad LP.

[0135] The pad separation insulating layer 160 may include an insulating material to electrically separate the plurality of bonding pads LP from each other. For example, the pad separation insulating layer 160 may include at least one of, for example, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon carbonitride layer, and a silicon carbonitride layer.

[0136] An etch stop layer 170 may be disposed on the pad separation insulating layer 160 and the bonding pad LP. The etch stop layer 170 may include at least one of a silicon nitride layer, a silicon carbonitride layer, a silicon boron nitride (SiBN) layer, a silicon oxynitride layer, and a silicon oxycarbonate layer.

[0137] Memory components such as memristors and / or capacitors 180 may be disposed on bonding pads LP. Capacitors 180 may be electrically connected to bonding pads LP. A portion of capacitors 180 may be disposed in etch stop layer 170. Capacitors 180 include a lower electrode 181, a dielectric layer 182, and an upper electrode 183.

[0138] The lower electrode 181 of the capacitor can be disposed on the bonding pad LP. The lower electrode 181 is shown as having a cylindrical shape, but is not limited thereto. Of course, the lower electrode 181 can also have a cylindrical shape. A capacitor dielectric layer 182 is formed on the lower electrode 181. The capacitor dielectric layer 182 can be formed along the contour of the lower electrode 181. An upper electrode 183 of the capacitor is formed on the capacitor dielectric layer 182. The upper electrode 183 can surround the outer wall of the lower electrode 181.

[0139] As an example, the capacitor dielectric layer 182 may be disposed at a portion vertically stacked with the upper electrode 183 of the capacitor. Alternatively, unlike as shown in the figures, the capacitor dielectric layer 182 may include a first portion vertically stacked with the upper electrode 183 of the capacitor and a second portion not vertically stacked with the upper electrode 183 of the capacitor. For example, the second portion of the capacitor dielectric layer 182 is the portion not covered by the upper electrode 183 of the capacitor.

[0140] Each of the lower electrode 181 and the upper electrode 183 of the capacitor may include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, tungsten nitride, etc.), a metal (e.g., ruthenium, iridium, titanium, tantalum, etc.), a conductive metal oxide (e.g., iridium oxide, niobium oxide, etc.), etc., but the inventive concept is not limited thereto.

[0141] The capacitor dielectric layer 182 may include, but is not limited to, at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, high-k materials, and combinations thereof. In a semiconductor memory device according to some example embodiments, the capacitor dielectric layer 182 may include a stacked structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked. In a semiconductor memory device according to some example embodiments, the capacitor dielectric layer 182 may include a dielectric layer containing hafnium (Hf). In a semiconductor memory device according to some example embodiments, the capacitor dielectric layer 182 may have a stacked structure including a ferroelectric material layer and a paraelectric material layer.

[0142] Although not shown, in the first peripheral region PA1, the first peripheral active region ACT1 may be defined by a peripheral element isolation layer. A first peripheral gate pattern PGP1 is disposed on the substrate 1 in the first peripheral region PA1. The first peripheral gate pattern PGP1 may include a first peripheral insulating layer 118a, a first peripheral high-k layer 122a, a first peripheral diffusion prevention pattern 124a, a first peripheral N-type work function pattern 126a, a first peripheral conductive pattern 128a, and a first peripheral gate electrode GE1, sequentially stacked on the substrate 1. A first peripheral gate overlay pattern 142a may be disposed on the first peripheral gate pattern PGP1.

[0143] Although not shown, in the second peripheral region PA2, the second peripheral active region ACT2 may be defined by a peripheral element isolation layer. A second peripheral gate pattern PGP2 is disposed on the substrate 1 in the second peripheral region PA2. The second peripheral gate pattern PGP2 may include a second peripheral insulating layer 120b, a second peripheral high-k layer 122b, a second peripheral diffusion prevention pattern 124b, a second peripheral N-type work function pattern 126b, a second peripheral conductive pattern 128b, and a second peripheral gate electrode GE2, sequentially stacked on the substrate 1. A second peripheral gate overlay pattern 142b may be disposed on the second peripheral gate pattern PGP2.

[0144] Although not shown, in the third peripheral region PA3, the third peripheral active region ACT3 may be defined by a peripheral element isolation layer. A third peripheral gate pattern PGP3 is disposed on the substrate 1 of the third peripheral region PA3. The third peripheral gate pattern PGP3 may include a third peripheral insulating layer 118c, a third peripheral high-k layer 122c, a third peripheral conductive pattern 128c, and a third peripheral gate electrode GE3 sequentially stacked on the substrate 1. A third peripheral gate overlay pattern 142c may be disposed on the third peripheral gate pattern PGP3. The third peripheral gate pattern PGP3 may not include a diffusion prevention pattern and an N-type work function pattern.

[0145] Although not shown, in the fourth peripheral region PA4, the fourth peripheral active region ACT4 may be defined by a peripheral element isolation layer. A channel layer 116 may be disposed on the substrate 1 in the fourth peripheral region PA4. The lattice constant of the channel layer 116 may be greater than the lattice constant of the substrate 1. The channel layer 116 may include, for example, silicon-germanium, while the substrate 1 may include monocrystalline silicon. A fourth peripheral gate pattern PGP4 is disposed on the channel layer 116.

[0146] The fourth peripheral gate pattern PGP4 may include a fourth peripheral insulating layer 120d, a fourth peripheral high-k layer 122d, a fourth peripheral conductive pattern 128d, and a fourth peripheral gate electrode GE4, sequentially stacked on the channel layer 116. A fourth peripheral gate overlay pattern 142d may be disposed on the fourth peripheral gate pattern PGP4. The fourth peripheral gate pattern PGP4 may not include a diffusion prevention pattern and an N-type work function pattern.

[0147] exist Figure 17 In this configuration, the width W1 of the first peripheral gate pattern PGP1 can be greater than the width W2 of the second peripheral gate pattern PGP2. The width of the third peripheral gate pattern PGP3 can be the same as the width W1 of the first peripheral gate pattern PGP1. The width of the fourth peripheral gate pattern PGP4 can be the same as the width W2 of the second peripheral gate pattern PGP2. For example, the width of the third peripheral gate pattern PGP3 can be greater than the width of the fourth peripheral gate pattern PGP4.

[0148] exist Figure 18 In this configuration, the first peripheral insulating layer 118a may be thicker than the second peripheral insulating layer 120b. The third peripheral insulating layer 118c may be thicker than the fourth peripheral insulating layer 120d. High-voltage transistors may be disposed in the first peripheral region PA1 and the third peripheral region PA3, and low-voltage transistors may be disposed in the second peripheral region PA2 and the fourth peripheral region PA4. Therefore, the first peripheral insulating layer 118a of the first peripheral region PA1 and the third peripheral insulating layer 118c of the third peripheral region PA3 may be thicker than the second peripheral insulating layer 120b of the second peripheral region PA2 and the fourth peripheral insulating layer 120d of the fourth peripheral region PA4, respectively.

[0149] Each of the first peripheral insulating layer 118a, the second peripheral insulating layer 120b, the third peripheral insulating layer 118c, and the fourth peripheral insulating layer 120d may include silicon oxide.

[0150] Each of the first outer high-k layer 122a, the second outer high-k layer 122b, the third outer high-k layer 122c, and the fourth outer high-k layer 122d may include, for example, at least one of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof.

[0151] Each of the first peripheral diffusion prevention pattern 124a and the second peripheral diffusion prevention pattern 124b may include titanium nitride (TiN). Each of the first peripheral diffusion prevention pattern 124a and the second peripheral diffusion prevention pattern 124b may be a single layer, but is not limited thereto.

[0152] Although not shown, the first peripheral gate pattern PGP1 may further include a first lower peripheral boundary pattern disposed between the first peripheral diffusion prevention pattern 124a and the first peripheral N-type work function pattern 126a. The second peripheral gate pattern PGP2 may further include a second lower peripheral boundary pattern disposed between the second peripheral diffusion prevention pattern 124b and the second peripheral N-type work function pattern 126b.

[0153] Optionally or additionally, the first peripheral gate pattern PGP1 may further include a first upper peripheral boundary pattern disposed between the first peripheral N-type work function pattern 126a and the first peripheral conductive pattern 128a. The second peripheral gate pattern PGP2 may further include a second upper peripheral boundary pattern disposed between the second peripheral N-type work function pattern 126b and the second peripheral conductive pattern 128b.

[0154] Each of the first lower outer boundary pattern, the second lower outer boundary pattern, the first upper outer boundary pattern, and the second upper outer boundary pattern may include, but is not limited to, lanthanum titanium nitride (LaTiN) or lanthanum titanium oxynitride (LaTiNO).

[0155] Each of the first peripheral diffusion prevention pattern 124a and the second peripheral diffusion prevention pattern 124b can prevent or reduce the possibility and / or impact of the diffusion of elements (e.g., lanthanum (La)) included in the first peripheral N-type work function pattern 126a and the second peripheral N-type work function pattern 126b.

[0156] Each of the first peripheral N-type work function pattern 126a and the second peripheral N-type work function pattern 126b may include at least one of, for example, lanthanum (La), lanthanum oxide (LaO), magnesium (Mg), magnesium oxide (MgO), tantalum (Ta), tantalum nitride (TaN), and niobium (Nb).

[0157] Each of the first peripheral conductive pattern 128a, the second peripheral conductive pattern 128b, the third peripheral conductive pattern 128c, and the fourth peripheral conductive pattern 128d may include titanium nitride (TiN), aluminum (Al), or a combination thereof.

[0158] Each of the first peripheral gate cover pattern 142a, the second peripheral gate cover pattern 142b, the third peripheral gate cover pattern 142c, and the fourth peripheral gate cover pattern 142d may include silicon nitride.

[0159] In some exemplary embodiments, the first peripheral conductive pattern 128a, the second peripheral conductive pattern 128b, the third peripheral conductive pattern 128c, and the fourth peripheral conductive pattern 128d may all have the same thickness. However, the spirit of the inventive concept is not limited thereto. The thickness of the first peripheral conductive pattern 128a and the second peripheral conductive pattern 128b may be less than the thickness of the third peripheral conductive pattern 128c and the fourth peripheral conductive pattern 128d.

[0160] The first peripheral gate cover pattern 142a, the second peripheral gate cover pattern 142b, the third peripheral gate cover pattern 142c, and the fourth peripheral gate cover pattern 142d can have the same thickness as the first bit line cover pattern 142t. The bit line cover pattern 140 may also include a second bit line cover pattern 148t. Therefore, the thickness of the first peripheral gate cover pattern 142a, the second peripheral gate cover pattern 142b, the third peripheral gate cover pattern 142c, and the fourth peripheral gate cover pattern 142d can be less than the thickness of the bit line cover pattern 140.

[0161] The first peripheral gate electrode GE1 includes a first peripheral lower electrode 130a, a first peripheral middle electrode 132a, and a first peripheral upper electrode 134a stacked sequentially. The second peripheral gate electrode GE2 includes a second peripheral lower electrode 130b, a second peripheral middle electrode 132b, and a second peripheral upper electrode 134b stacked sequentially. The third peripheral gate electrode GE3 includes a third peripheral lower electrode 130c, a third peripheral middle electrode 132c, and a third peripheral upper electrode 134c stacked sequentially. The fourth peripheral gate electrode GE4 includes a fourth peripheral lower electrode 130d, a fourth peripheral middle electrode 132d, and a fourth peripheral upper electrode 134d stacked sequentially.

[0162] Each of the first peripheral lower electrode 130a, the second peripheral lower electrode 130b, the third peripheral lower electrode 130c, and the fourth peripheral lower electrode 130d may comprise polycrystalline silicon doped with impurities. The conductivity type of the impurities doped in the first peripheral lower electrode 130a and the second peripheral lower electrode 130b may be different from the conductivity type of the impurities doped in the third peripheral lower electrode 130c and the fourth peripheral lower electrode 130d. For example, the first peripheral lower electrode 130a and the second peripheral lower electrode 130b may be doped with N-type impurities, and the third peripheral lower electrode 130c and the fourth peripheral lower electrode 130d may be doped with P-type impurities. Each of the first peripheral intermediate electrode 132a, the second peripheral intermediate electrode 132b, the third peripheral intermediate electrode 132c, and the fourth peripheral intermediate electrode 132d may comprise TiSiN. Each of the first peripheral upper electrode 134a, the second peripheral upper electrode 134b, the third peripheral upper electrode 134c, and the fourth peripheral upper electrode 134d may comprise tungsten. However, the spirit of the inventive concept is not limited thereto.

[0163] In some example embodiments, the bit line BL, the first peripheral gate electrode GE1, the second peripheral gate electrode GE2, the third peripheral gate electrode GE3, and the fourth peripheral gate electrode GE4 may have the same stacked structure.

[0164] For example, the lower bit line electrode 130t, the first peripheral lower electrode 130a, the second peripheral lower electrode 130b, the third peripheral lower electrode 130c, and the fourth peripheral lower electrode 130d have the same thickness. Furthermore, the bit line intermediate electrode 132t, the first peripheral intermediate electrode 132a, the second peripheral intermediate electrode 132b, the third peripheral intermediate electrode 132c, and the fourth peripheral intermediate electrode 132d have the same thickness. The upper bit line electrode 134t, the first peripheral upper electrode 134a, the second peripheral upper electrode 134b, the third peripheral upper electrode 134c, and the fourth peripheral upper electrode 134d have the same thickness.

[0165] The sidewalls of the first peripheral gate pattern PGP1, the second peripheral gate pattern PGP2, the third peripheral gate pattern PGP3, and the fourth peripheral gate pattern PGP4 may be covered by peripheral spacers 144. The sidewalls of the peripheral spacers 144 and the substrate 1 may be covered by a peripheral interlayer insulating layer 146. The peripheral interlayer insulating layer 146 may include, for example, silicon oxide. A second capping layer 148 may be disposed on the peripheral interlayer insulating layer 146. The second capping layer 148 may serve as an etch stop layer. The second capping layer 148 may be formed of a material different from that of the peripheral interlayer insulating layer 146. For example, the second capping layer 148 may include silicon nitride. The thickness of the second capping layer 148 may be substantially the same as the thickness of the second bit line overlay pattern 148t.

[0166] Figures 19 to 34 It shows the manufacturing process in sequence. Figure 18 A cross-sectional view of the process of manufacturing a semiconductor memory device. Hereinafter, methods for manufacturing a semiconductor memory device according to some exemplary embodiments of the inventive concept will be described.

[0167] Reference Figure 17 and Figure 19 A substrate 1 is provided, comprising a cell array region CA, a first peripheral region PA1, a second peripheral region PA2, a third peripheral region PA3, and a fourth peripheral region PA4.

[0168] A unit element isolation layer 105 and a peripheral element isolation layer can be formed in the substrate 1 to form a unit active region ACTC, a first peripheral active region ACT1, a second peripheral active region ACT2, a third peripheral active region ACT3, and a fourth peripheral active region ACT4. The unit element isolation layer 105 and the peripheral element isolation layer can define the unit active region ACTC, the first peripheral active region ACT1, the second peripheral active region ACT2, the third peripheral active region ACT3, and the fourth peripheral active region ACT4.

[0169] Word lines WL can be formed in the cell array region CA. The word lines WL can be buried in the substrate 1 and extend in the first direction D1. An ion implantation process can be performed in the cell array region CA to form doped regions in the cell active region ACTC. During the ion implantation process, a mask can be used to cover the first peripheral region PA1, the second peripheral region PA2, the third peripheral region PA3, and the fourth peripheral region PA4.

[0170] Reference Figure 20 The first peripheral region PA1, the second peripheral region PA2, the third peripheral region PA3, and the fourth peripheral region PA4 can be covered by a mask. Subsequently, the first unit insulating layer 111, the second unit insulating layer 112, and the third unit insulating layer 113 can be sequentially stacked and patterned on the substrate 1 of the unit array region CA to form a buffer layer 110 on the unit array region CA.

[0171] Subsequently, the first peripheral region PA1, the second peripheral region PA2, the third peripheral region PA3, and the fourth peripheral region PA4 can be exposed. A fourth mask layer MASK4 can be formed on the substrate 1, covering the cell array region CA, the first peripheral region PA1, the second peripheral region PA2, and the third peripheral region PA3, and exposing the fourth peripheral region PA4. The fourth mask layer MASK4 may include, for example, silicon oxide. The fourth mask layer MASK4 may correspond to... Figure 10 The first mask layer is MASK1.

[0172] A channel layer 116 can be formed on the substrate 1 of the fourth peripheral region PA4 by using a fourth mask layer MASK4 as an epitaxial barrier. The channel layer 116 may include silicon germanium. The channel layer 116 can be formed by a selective epitaxial growth (SEG) method.

[0173] Reference Figure 21 The fourth mask layer MASK4 can be removed to expose the top surface of the buffer layer 110 of the cell array region CA, as well as the first peripheral region PA1, the second peripheral region PA2, and the third peripheral region PA3.

[0174] Subsequently, although not shown, separate masks can be used to cover the cell array region CA, the second peripheral region PA2, and the fourth peripheral region PA4. A high-voltage gate insulating layer 118 can be formed on the substrate 1, which is open in the first peripheral region PA1 and the third peripheral region PA3. The high-voltage gate insulating layer 118 can be formed of a silicon oxide layer.

[0175] Reference Figure 22 A separate mask can be used to cover the cell array region CA, the first peripheral region PA1, and the third peripheral region PA3, and a low-voltage gate insulating layer 120 can be formed on the substrate 1 of the second peripheral region PA2 and the channel layer 116 of the fourth peripheral region PA4. The low-voltage gate insulating layer 120 can be formed, for example, a silicon oxide layer. The low-voltage gate insulating layer 120 can be formed thinner than the high-voltage gate insulating layer 118.

[0176] Reference Figure 23 A pre-high k layer 122, a diffusion prevention layer 124, and an N-type work function layer 126 can be sequentially formed on the front surface of the substrate 1.

[0177] The high-k layer 122, the diffusion prevention layer 124, and the N-type work function layer 126 can respectively correspond to Figure 12 The high-k layer 15, the diffusion prevention layer 17, and the N-type work function layer 19.

[0178] The pre-high-k layer 122 can be formed by deposition processes such as chemical vapor deposition (CVD) and / or atomic layer deposition (ALD). The pre-high-k layer 122 may comprise a material having a dielectric constant higher than that of the first peripheral insulating layer 118a, the second peripheral insulating layer 120b, the third peripheral insulating layer 118c, and the fourth peripheral insulating layer 120d. For example, the pre-high-k layer 122 may comprise hafnium oxide, but is not limited thereto.

[0179] The diffusion prevention layer 124 may include, for example, titanium nitride (TiN). The N-type work function layer 126 may include at least one of, for example, lanthanum (La), lanthanum oxide (LaO), magnesium (Mg), magnesium oxide (MgO), tantalum (Ta), tantalum nitride (TaN), and niobium (Nb). However, the technical spirit of the inventive concept is not limited thereto.

[0180] Reference Figure 24 A fifth mask layer, MASK5, can be formed, which covers the first peripheral region PA1 and the second peripheral region PA2 and exposes the cell array region CA, the third peripheral region PA3, and the fourth peripheral region PA4. The fifth mask layer, MASK5, can be at least one of a photoresist layer, ACL, SOH, SOC, and a silicon nitride layer.

[0181] Subsequently, the fifth mask layer MASK5 can be used as an etching mask to perform the etching process. The etching process removes the N-type active power layer 126 and the diffusion prevention layer 124 from the cell array region CA, the third peripheral region PA3, and the fourth peripheral region PA4. The etching process can be a wet etching process using an etchant containing sulfuric acid. The N-type active power layer 126 and the diffusion prevention layer 124 can be selectively removed by performing a wet etching process. The N-type active power layer 126 and the diffusion prevention layer 124 can be selectively formed in the first peripheral region PA1 and the second peripheral region PA2.

[0182] Reference Figure 25 The fifth mask layer (MASK5) can be removed. The cell array region (CA), the first peripheral region (PA1), the second peripheral region (PA2), the third peripheral region (PA3), and the fourth peripheral region (PA4) can be exposed.

[0183] A conductive layer 128 may be formed on a substrate 1 comprising the cell array region CA, the first peripheral region PA1, the second peripheral region PA2, the third peripheral region PA3, and the fourth peripheral region PA4. The conductive layer 128 may include, for example, titanium nitride (TiN), aluminum (Al), or combinations thereof, but is not limited thereto.

[0184] Reference Figure 26 A sixth mask layer, MASK6, can be formed, which covers the first peripheral region PA1, the second peripheral region PA2, the third peripheral region PA3, and the fourth peripheral region PA4 and exposes the cell array region CA.

[0185] The conductive layer 128 and the pre-high-k layer 122 of the cell array region CA can be removed by performing an etching process using the sixth mask layer MASK6 as an etching mask. The etching process can be a wet etching process using an etchant containing sulfuric acid. By performing a wet etching process, the conductive layer 128 and the pre-high-k layer 122 can be selectively removed without damaging the buffer layer 110.

[0186] Reference Figure 27 The sixth mask layer MASK6 can be removed to expose the cell array region CA, the first peripheral region PA1, the second peripheral region PA2, the third peripheral region PA3, and the fourth peripheral region PA4.

[0187] The buffer layer 110 of the cell array region CA and the conductive layers 128 of the first peripheral region PA1, the second peripheral region PA2, the third peripheral region PA3, and the fourth peripheral region PA4 can be exposed. Subsequently, a lower electrode layer 130 can be formed on the front surface of the substrate 1. The lower electrode layer 130 can be formed from a polysilicon layer doped with impurities. For example, the polysilicon layer can be deposited integrally, and the ion implantation process can be performed multiple times. In the ion implantation process, N-type impurities can be doped into the polysilicon layers of the cell array region CA, the first peripheral region PA1, and the second peripheral region PA2, and P-type impurities can be doped into the polysilicon layers of the third peripheral region PA3 and the fourth peripheral region PA4.

[0188] Reference Figure 28 and Figure 29 A seventh mask layer, MASK7, can be formed on the lower electrode layer 130.

[0189] The seventh mask layer MASK7 may have an opening that substantially defines the location of the direct contact DC. The seventh mask layer MASK7 may be at least one of, for example, a photoresist layer, ACL, SOH, and SOC. A trench T can be formed by etching a portion of the lower electrode layer 130, buffer layer 110, and substrate 1 of the cell array region CA using the seventh mask layer MASK7 as an etching mask. In this case, the upper portion of the cell element isolation layer 105 may also be partially removed.

[0190] Reference Figure 30 The seventh mask layer MASK7 can be removed to expose the upper part of the lower electrode layer 130.

[0191] Subsequently, a polysilicon layer doped with impurities can be deposited on the front surface of substrate 1 to fill trench T. The pre-direct contact PDC can then be formed by removing the polysilicon layer on the lower electrode layer 130 through a CMP process.

[0192] Subsequently, an intermediate electrode layer 132, an upper electrode layer 134, and a first capping layer 142 can be sequentially stacked on the lower electrode layer 130 and the pre-direct contact PDC. The intermediate electrode layer 132 can be, for example, TiSiN. The upper electrode layer 134 can be, for example, tungsten. The first capping layer 142 can be, for example, silicon nitride.

[0193] Reference Figure 31The first cover layer 142 of the first peripheral region PA1, the second peripheral region PA2, the third peripheral region PA3, and the fourth peripheral region PA4 can be patterned using a mask to form the first peripheral gate cover pattern 142a, the second peripheral gate cover pattern 142b, the third peripheral gate cover pattern 142c, and the fourth peripheral gate cover pattern 142d. The upper electrode layer 134, the middle electrode layer 132, and the lower electrode layer 130 can be patterned to form the first peripheral gate electrode GE1, the second peripheral gate electrode GE2, the third peripheral gate electrode GE3, and the fourth peripheral gate electrode GE4.

[0194] The first peripheral gate pattern PGP1 can be formed by patterning the upper electrode layer 134, the middle electrode layer 132, the lower electrode layer 130, the conductive layer 128, the N-type active power layer 126, the diffusion prevention layer 124, the pre-high k layer 122, and the high voltage gate insulating layer 118.

[0195] The second peripheral gate pattern PGP2 can be formed by patterning the upper electrode layer 134, the middle electrode layer 132, the lower electrode layer 130, the conductive layer 128, the N-type active power layer 126, the diffusion prevention layer 124, the pre-high k layer 122, and the low voltage gate insulating layer 120.

[0196] The third peripheral gate pattern PGP3 can be formed by patterning the upper electrode layer 134, the middle electrode layer 132, the lower electrode layer 130, the conductive layer 128, the pre-high k layer 122, and the high voltage gate insulating layer 118.

[0197] The fourth peripheral gate pattern PGP4 can be formed by patterning the upper electrode layer 134, the middle electrode layer 132, the lower electrode layer 130, the conductive layer 128, the pre-high k layer 122, and the low voltage gate insulating layer 120.

[0198] Subsequently, although not shown, N-type impurities can be doped into the substrate 1 adjacent to the first peripheral gate pattern PGP1 and the second peripheral gate pattern PGP2. Source / drain regions can be formed around the first peripheral gate pattern PGP1 and the second peripheral gate pattern PGP2. P-type impurities can be doped into the substrate 1 adjacent to the third peripheral gate pattern PGP3 and the fourth peripheral gate pattern PGP4. Source / drain regions can be formed around the third peripheral gate pattern PGP3 and the fourth peripheral gate pattern PGP4.

[0199] Reference Figure 32 A peripheral spacer 144 can be formed along the sidewalls of the first peripheral gate pattern PGP1, the second peripheral gate pattern PGP2, the third peripheral gate pattern PGP3, and the fourth peripheral gate pattern PGP4.

[0200] First, a spacer layer can be conventionally formed in the first peripheral region PA1, the second peripheral region PA2, the third peripheral region PA3, and the fourth peripheral region PA4. The peripheral spacer 144 can be formed by etching the spacer layer.

[0201] A peripheral interlayer insulating layer 146 can be formed on the peripheral spacer 144, the first peripheral gate cover pattern 142a, the second peripheral gate cover pattern 142b, the third peripheral gate cover pattern 142c, and the fourth peripheral gate cover pattern 142d. A CMP process can be performed to expose the top surface of the first peripheral gate cover pattern 142a. Since the top surface of the first peripheral gate cover pattern 142a is located at the very top, the top surface of the first peripheral gate cover pattern 142a can be exposed. However, this is only for the sake of simplicity, and the exemplary embodiment is not limited thereto.

[0202] Subsequently, a second cover layer 148 can be formed on the front surface of the substrate 1.

[0203] Reference Figure 33 The second cover layer 148, the first cover layer 142, the upper electrode layer 134, the middle electrode layer 132 and the lower electrode layer 130 of the cell array region CA can be patterned using a mask to form the bit line cover pattern 140 and the bit line BL.

[0204] In this case, the pre-direct contact DC can also be patterned to form the direct contact DC. Part of the sidewalls and bottom surface of the trench T can be exposed. Since the buffer layer 110 has a three-layer structure including a first unit insulating layer 111, a second unit insulating layer 112 and a third unit insulating layer 113, the etching process can be easily controlled.

[0205] Bit line cover pattern 140 may include a first bit line cover pattern 142t and a second bit line cover pattern 148t. The vertical length of the bit line cover pattern 140 may be greater than the vertical length of the first peripheral gate cover pattern 142a, the second peripheral gate cover pattern 142b, the third peripheral gate cover pattern 142c, and the fourth peripheral gate cover pattern 142d. Since the vertical length of the first bit line cover pattern 142t is the same as the vertical length of the first peripheral gate cover pattern 142a, the second peripheral gate cover pattern 142b, the third peripheral gate cover pattern 142c, and the fourth peripheral gate cover pattern 142d, the vertical length of the bit line cover pattern 140 may be greater than the vertical length of the first peripheral gate cover pattern 142a, the second peripheral gate cover pattern 142b, the third peripheral gate cover pattern 142c, and the fourth peripheral gate cover pattern 142d.

[0206] Reference Figure 34Bit line spacers 150 can be formed to cover the sidewalls of the bit line overlay pattern 140 and the bit line BL. A portion of the buffer layer 110 and the substrate 1 can be removed between adjacent bit line spacers 150 by using the bit line spacers 150 and the bit line overlay pattern 140 as an etching mask. Since the buffer layer 110 has a three-layer structure including a first unit insulating layer 111, a second unit insulating layer 112, and a third unit insulating layer 113, the etching process can be easily controlled. Therefore, a semiconductor memory device with improved reliability can be realized.

[0207] Subsequently, buried contacts BC that contact the substrate 1 can be formed between the bit line spacers 150. A bonding pad LP and a pad separation insulating layer 160 can be formed on the buried contacts BC. A capacitor 180 can be formed on the bonding pad LP.

[0208] In summarizing the specific embodiments, those skilled in the art will understand that many variations and modifications can be made to the various exemplary embodiments without substantially departing from the principles of the inventive concept. Furthermore, the exemplary embodiments are not necessarily mutually exclusive. For example, some exemplary embodiments may include one or more features described with reference to one or more accompanying drawings, and may also include one or more other features described with reference to one or more other accompanying drawings. Therefore, the preferred embodiments disclosed herein are used in a general and descriptive sense only, and not for limiting purposes.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: The substrate includes NMOS and PMOS regions; The first gate pattern is located on the NMOS region of the substrate; as well as The second gate pattern is located on the PMOS region of the substrate. The first gate pattern includes a first gate insulating layer, an N-type work function pattern, a first conductive pattern, and a first gate electrode stacked on the substrate. The second gate pattern includes a second gate insulating layer, a high-k layer, a second conductive pattern, and a second gate electrode stacked on a substrate. The first gate electrode includes a first lower electrode and a first upper electrode. The first lower electrode includes polycrystalline silicon, and the first upper electrode is located on the first lower electrode and includes tungsten. The second gate electrode includes a second lower electrode and a second upper electrode. The second lower electrode includes polycrystalline silicon, and the second upper electrode is located on the second lower electrode and includes tungsten. Both the first and second conductive patterns include titanium nitride. The N-type work function pattern includes a metal oxide containing lanthanum and is in contact with the first conductive pattern. The high-k layer includes hafnium oxide and is in contact with the second gate insulating layer and the second conductive pattern.

2. The semiconductor memory device according to claim 1, wherein, The first lower electrode is in contact with the first conductive pattern, and The second lower electrode is in contact with the second conductive pattern.

3. The semiconductor memory device according to claim 1, wherein, The vertical lengths of the first conductive pattern and the second conductive pattern are equal.

4. The semiconductor memory device according to claim 1, wherein, The vertical lengths of the first lower electrode and the second lower electrode are equal.

5. The semiconductor memory device according to claim 1, wherein, The vertical lengths of the first upper electrode and the second upper electrode are equal.

6. The semiconductor memory device according to claim 1, wherein, Both the first gate insulating layer and the second gate insulating layer comprise silicon oxynitride.

7. The semiconductor memory device according to claim 1, wherein, The high-k layer does not include lanthanum.

8. The semiconductor memory device of claim 1, further comprising: The first gate overlay pattern is located on the first gate pattern; as well as The second gate overlay pattern is located on the second gate pattern. Both the first gate cover pattern and the second gate cover pattern include silicon nitride.

9. The semiconductor memory device according to claim 8, wherein, The first upper electrode is in contact with the first gate cover pattern, and The second upper electrode is in contact with the second gate cover pattern.

10. The semiconductor memory device of claim 1, further comprising: The channel layer is located between the substrate and the second gate pattern in the PMOS region. The channel layer includes silicon and germanium.

11. A semiconductor memory device, the semiconductor memory device comprising: The substrate includes NMOS and PMOS regions; The first gate pattern is located on the NMOS region of the substrate; as well as The second gate pattern is located on the PMOS region of the substrate. The first gate pattern includes a first gate insulating layer, an N-type work function pattern, a first conductive pattern, and a first gate electrode stacked on the substrate. The second gate pattern includes a second gate insulating layer, a high-k layer, a second conductive pattern, and a second gate electrode stacked on a substrate. The first gate electrode includes a first lower electrode and a first upper electrode. The first lower electrode includes polycrystalline silicon, and the first upper electrode is located on the first lower electrode and includes tungsten. The second gate electrode includes a second lower electrode and a second upper electrode. The second lower electrode includes polycrystalline silicon, and the second upper electrode is located on the second lower electrode and includes tungsten. Both the first gate insulating layer and the second gate insulating layer comprise silicon oxynitride. Both the first and second conductive patterns include titanium nitride. The vertical lengths of the first conductive pattern and the second conductive pattern are equal. The first lower electrode is in contact with the first conductive pattern. The second lower electrode is in contact with the second conductive pattern. The vertical lengths of the first lower electrode and the second lower electrode are equal. The vertical lengths of the first upper electrode and the second upper electrode are equal. The N-type work function pattern includes a metal oxide containing lanthanum and is in contact with the first conductive pattern. The high-k layer includes hafnium oxide and is in contact with the second gate insulating layer and the second conductive pattern.

12. The semiconductor memory device of claim 11, further comprising: The first gate overlay pattern is located on the first gate pattern; as well as The second gate overlay pattern is located on the second gate pattern. Both the first gate cover pattern and the second gate cover pattern include silicon nitride.

13. The semiconductor memory device according to claim 12, wherein, The first upper electrode is in contact with the first gate cover pattern, and The second upper electrode is in contact with the second gate cover pattern.

14. The semiconductor memory device of claim 11, further comprising: The channel layer is located between the substrate and the second gate pattern in the PMOS region. The channel layer includes silicon and germanium.

15. A semiconductor memory device, the semiconductor memory device comprising: The base includes a first outer region, a second outer region, a third outer region, and a fourth outer region; The first peripheral gate pattern, the second peripheral gate pattern, the third peripheral gate pattern, and the fourth peripheral gate pattern are located on the substrates of the first peripheral region, the second peripheral region, the third peripheral region, and the fourth peripheral region, respectively. A channel layer, located between the substrate and the fourth peripheral gate pattern in the fourth peripheral region, and comprising silicon germanium, The first peripheral gate pattern includes a first peripheral insulating layer, a first peripheral N-type work function pattern, a first peripheral conductive pattern, and a first peripheral gate electrode stacked on the substrate. The second peripheral gate pattern includes a second peripheral insulating layer, a second peripheral N-type work function pattern, a second peripheral conductive pattern, and a second peripheral gate electrode stacked on a substrate, wherein the first peripheral insulating layer is thicker than the second peripheral insulating layer. The third peripheral gate pattern includes a third peripheral insulating layer, a first peripheral high-k layer, a third peripheral conductive pattern, and a third peripheral gate electrode stacked on the substrate. The fourth peripheral gate pattern includes a fourth peripheral insulating layer, a second peripheral high-k layer, a fourth peripheral conductive pattern, and a fourth peripheral gate electrode stacked on the channel layer, wherein the third peripheral insulating layer is thicker than the fourth peripheral insulating layer. The first peripheral gate electrode includes a first peripheral lower electrode and a first peripheral upper electrode. The first peripheral lower electrode includes polycrystalline silicon, and the first peripheral upper electrode is located on the first peripheral lower electrode and includes tungsten. The second peripheral gate electrode includes a second peripheral lower electrode and a second peripheral upper electrode. The second peripheral lower electrode comprises polycrystalline silicon, and the second peripheral upper electrode is located on the second peripheral lower electrode and comprises tungsten. The third peripheral gate electrode includes a third peripheral lower electrode and a third peripheral upper electrode. The third peripheral lower electrode includes polycrystalline silicon, and the third peripheral upper electrode is located on the third peripheral lower electrode and includes tungsten. The fourth peripheral gate electrode includes a fourth peripheral lower electrode and a fourth peripheral upper electrode. The fourth peripheral lower electrode comprises polycrystalline silicon, and the fourth peripheral upper electrode is located on the fourth peripheral lower electrode and comprises tungsten. The first, second, third, and fourth peripheral conductive patterns all include titanium nitride. Both the first and second peripheral N-type work function patterns include metal oxides containing lanthanum. The first peripheral N-type work function pattern is in contact with the first peripheral conductive pattern. The second peripheral N-type work function pattern is in contact with the second peripheral conductive pattern. Both the first and second outer high-k layers contain hafnium oxide. The first outer high-k layer is in contact with the third outer insulating layer and the third outer conductive pattern, and The second outer high-k layer is in contact with the fourth outer insulating layer and the fourth outer conductive pattern.

16. The semiconductor memory device according to claim 15, wherein, The first peripheral lower electrode is in contact with the first peripheral conductive pattern. The second peripheral lower electrode is in contact with the second peripheral conductive pattern. The third peripheral lower electrode is in contact with the third peripheral conductive pattern, and The fourth peripheral lower electrode is in contact with the fourth peripheral conductive pattern.

17. The semiconductor memory device according to claim 15, wherein, The thicknesses of the first, second, third, and fourth outer conductive patterns are equal.

18. The semiconductor memory device according to claim 15, wherein, The thicknesses of the first, second, third, and fourth peripheral lower electrodes are all equal.

19. The semiconductor memory device according to claim 15, wherein, The thicknesses of the first, second, third, and fourth outer outer electrodes are all equal.

20. The semiconductor memory device according to claim 15, wherein, The first and second outermost high-k layers do not include lanthanum.

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