Memory device and formation, manufacturing method thereof

Abstract

Embodiments of the present disclosure provide a memory device, such as a memory device having 1T1R electronic programmable fuse (eFuse) memory cells with shared word line transistors. By sharing word line transistors, eFuse memory cells according to the present disclosure can reduce bitcell area. Compared to 2T1R eFuse memory cells, 1T1R eFuse memory cells with shared word line transistors reduce bitcell area by about 30%. In some embodiments, a memory device according to the present disclosure includes backside power lines or signal lines, such as control gate lines on the backside of eFuse memory cells. By incorporating backside signal lines or power lines that can be wider than frontside lines, embodiments of the present disclosure provide a memory device with lower resistance values, thus reducing RC delay and improving programming performance. Embodiments of the present disclosure also provide methods of manufacturing and operating a memory device.

Description

Technical Field

[0001] The embodiments of the present invention generally relate to the semiconductor field, and more specifically, to memory devices and methods of manufacturing the same. Background Technology

[0002] Throughout the development of integrated circuits (ICs), functional diversity (i.e., the number of interconnected devices per chip area) has increased, while geometric dimensions (i.e., the smallest components (or interconnects) that can be formed using manufacturing processes) have shrunk. This shrinking size increases the complexity of IC processing and manufacturing. For some memory devices, as device dimensions shrink, the size of metal lines is also forced to shrink, resulting in increased parasitic resistance and capacitance, higher process risks, and / or poor connections. Additionally, some signal lines may be placed in metal lines far from memory cells, which can reduce the speed of the memory device and increase the complexity of circuit design. Summary of the Invention

[0003] An embodiment of the present invention provides a memory device, comprising: a device layer including transistors for rows of electronically programmable fuse (eFuse) memory cells and shared word line transistors; a first interconnect structure disposed on a first side of the device layer, wherein the first interconnect structure includes: a first control gate line disposed along the rows of the eFuse memory cells, wherein the first control gate line is connected to the eFuse memory cells; and a second interconnect structure disposed on a second side of the device layer, wherein the second side is relative to the first side, and the second interconnect structure includes:

[0004] A second control gate line is disposed above the shared word line transistor, and the first control gate line and the second control gate line are connected through a conductive path.

[0005] Another embodiment of the present invention provides a method of operating a memory device, comprising: providing a memory device including: rows of electronically programmable fuse (eFuse) memory cells, wherein each eFuse memory cell includes: a control gate transistor; a fuse resistor connected to the control gate transistor; and a control gate line connected to the control gate transistor in each of the eFuse memory cells; and a shared word line transistor disposed in the row of eFuse memory cells, wherein the shared word line transistor is disposed between a power line and the control gate line; and reading or programming a first eFuse memory cell in the row of eFuse memory cells, wherein reading or programming the first eFuse memory cell in the row of eFuse memory cells includes: activating the control gate transistor of the first eFuse memory cell in the row of eFuse memory cells; and activating the shared word line transistor.

[0006] Another embodiment of the present invention provides a method for forming a memory device, comprising: forming a device layer on a first side of a substrate, wherein the device layer includes transistors for rows of electronically programmable fuse (eFuse) memory cells and shared word line transistors, the shared word line transistors being aligned with the eFuse memory cell rows along a first direction; forming a front-side interconnect structure over the device layer, wherein the front-side interconnect structure includes a front-side control gate line; and forming a back-side interconnect structure on the device layer, wherein the back-side interconnect structure includes a back-side control gate line. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 This is a cell diagram of a storage device according to an embodiment of the present disclosure;

[0009] Figure 2A This is a schematic diagram illustrating a portion of a storage device of an eFuse memory cell according to an embodiment of the present disclosure;

[0010] Figures 2B to 2E This is a schematic diagram illustrating various operations of the eFuse memory cell according to embodiments of the present disclosure;

[0011] Figure 3A This is a circuit diagram of a storage device according to an embodiment of the present disclosure;

[0012] Figures 3B to 3EThis is a partial layout diagram of a storage device according to an embodiment of the present disclosure.

[0013] Figure 3F This is a schematic top view of the fuse resistor of the eFuse memory cell according to an embodiment of the present disclosure;

[0014] Figure 3G to Figure 3K yes Figure 3E A schematic cross-sectional view;

[0015] Figure 4A This is a schematic layout diagram showing the storage devices of the tap unit located next to the first eFuse memory cell in the cell area;

[0016] Figure 4B This shows a partial layout diagram of the tap unit;

[0017] Figure 4C yes Figure 4B Cross-sectional view of the tap unit in the diagram;

[0018] Figure 4D It is a cross-sectional view of a tap unit with FTV;

[0019] Figure 5A This is a schematic layout diagram of memory devices showing word line transistor regions located adjacent to tap units;

[0020] Figure 5B This is a memory device that shows the word line transistor area and the tap unit;

[0021] Figure 5C yes Figure 5B Cross-sectional view of the tap unit in the diagram;

[0022] Figure 5D yes Figure 5B Cross-sectional view of the tap unit in the diagram;

[0023] Figure 6A This is a schematic layout diagram of a storage device according to an embodiment of the present disclosure;

[0024] Figure 6B yes Figure 6A A cross-sectional view of the layout of the storage devices;

[0025] Figure 7A This is a circuit diagram of a storage device according to an embodiment of the present disclosure;

[0026] Figure 7B This is a partial layout diagram of the eFuse memory cell that implements the storage device;

[0027] Figure 7C yes Figure 7B Partial cross-sectional view of the layout in the image;

[0028] Figure 8 This is a circuit diagram of a storage device according to an embodiment of the present disclosure;

[0029] Figure 9 This is a flowchart of an exemplary method for forming a storage device according to embodiments of the present disclosure. Detailed Implementation

[0030] This invention provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0031] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0032] The foregoing outlines some aspects of the embodiments described in this disclosure. While some embodiments described herein are based on nanosheet field-effect transistors (FETs), embodiments of some aspects of this disclosure can be used in other processes and / or other devices, such as planar FETs, fin FETs, gate-all-around (GAA) FETs (e.g., horizontal GAA (HGAA) FETs and vertical GAA (VGAA) FETs), and other suitable devices. Those skilled in the art will understand that the scope of this disclosure covers other possible modifications. Furthermore, although method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than those described herein. The source / drain region may refer to the source or drain, independently or jointly, depending on the context.

[0033] Embodiments of this disclosure relate to non-volatile memory (NVM) devices, such as one-time programmable (OTP) memory devices. Memory devices according to this disclosure include cell bits having shared word line transistors. In some embodiments, embodiments of this disclosure include electronically programmable fuse (eFuse) memory cells having shared word line transistors. Specifically, embodiments of this disclosure provide a one-transistor-one-resistor (1T1R) eFuse memory cell, including a resistor and a control gate (CG) transistor. Two or more 1T1R eFuse memory cells share a routing line connected to the word line transistor. In some embodiments, the shared word line transistor is a footer switch provided between the routing line and a potential supply line Vss. In some embodiments, the shared routing line is disposed on the back side of the substrate device. In some embodiments, the memory device according to this disclosure includes a back-side power rail. The 1T1R eFuse memory cell design according to this disclosure reduces the overall bit cell area.

[0034] Figure 1 This is a cell diagram of a storage device 100 according to an embodiment of the present disclosure. Figure 1 As shown, the storage device 100 includes a memory cell array 102, a row decoder 104, a column decoder 106, input / output circuitry 108, and control logic circuitry 112. Although not shown in... Figure 1 All elements of storage device 100 can be coupled to each other and to control logic circuit 112. Although, in Figure 1 In the illustrated embodiments, each element is represented by a separate unit for clarity, but in some other embodiments, Figure 1 One or all of the components shown can be integrated together.

[0035] The memory cell array 102 is a hardware element for storing data. In some embodiments, the memory cell array 102 is implemented as a semiconductor memory device. The memory cell array 102 includes a plurality of memory cells 103 (or storage cells). The memory cell array 102 includes rows (rows R1, R2, R3... RM) each extending along a first direction (X direction), and columns (columns C1, C2, C3... CN) each extending along a second direction (Y direction). Each column and each row may include one or more conductive (e.g., metallic) structures that function as access lines. Each memory cell 103 is located at the intersection of a corresponding column and a corresponding row and can be operated according to the voltage or current passing through the corresponding conductive structures of the row and column. For example, each row may include a corresponding word line (WL), and each column may include a corresponding bit line (BL) and a plurality of corresponding control gate (CG) lines.

[0036] In some embodiments, each memory cell 103 is implemented as an eFuse memory cell that may include a fuse resistor, a control / cascode gate (CG) / selector / transistor, and a word line selector / transistor. The fuse resistor, control gate transistor, and word line transistor are coupled to each other in series. Additionally, corresponding word lines may be connected to the corresponding gates of one or more word line transistors, corresponding bit lines may be connected to the corresponding terminals of the fuse resistor, and corresponding control gate lines may be connected to the gates of the control gate transistors.

[0037] Although, in various embodiments of this disclosure, memory cell 103 is implemented as an eFuse memory cell including a number of fuse resistors, each of which is formed on a metal track in a corresponding metallization layer, the fuse resistors of memory cell 103 can be implemented according to other electrical processor-based memory configurations. For example, memory cell 103 can be configured as a resistive random access memory (RRAM), a phase-change random access memory (PCRAM or PRAM), or a magnetoresistive random access memory (MRAM). In some embodiments, the fuse resistors of memory cell 103 can be implemented according to a via structure or a polysilicon structure. Additionally, in some other embodiments, memory cell 103 can be implemented as an eFuse memory cell including a number of fuse capacitors, each of which can be formed as a metal-insulator-metal (MIM) capacitor or a metal-oxide-metal (MOM) capacitor.

[0038] Row decoder 104 is a hardware element capable of receiving row addresses of memory cell array 102 and asserting conductive structures (e.g., word lines) of said row addresses. Column decoder 106 is a hardware element capable of receiving column addresses of memory cell array 102 and asserting conductive structures (e.g., bit lines and one or more control gate lines) of said column addresses. Input / output circuitry 108 is a hardware element capable of accessing (e.g., reading, programming) each memory cell 103 accessed via row decoder 104 and column decoder 106. Control logic circuitry 112 is a hardware element capable of controlling coupled elements (e.g., memory cell array to input / output circuitry 108).

[0039] Figure 2A This includes a schematic diagram showing a storage device 100 of an eFuse memory cell 103 according to the present disclosure. Figure 2A The diagram shows eFuse memory cells 103A to 103H (collectively referred to as memory cells 103) of a memory cell array 102, and each of eFuse memory cells 103A to 103H includes a fuse resistor. Although eight eFuse memory cells 103A to 103H are shown, it should be understood that within the scope of this disclosure, the memory cell array can have any number of similar eFuse memory cells.

[0040] The eFuse memory cells 103 can be arranged in an array. Memory cells 103A, 103B, 103C, and 103D can be located in the same row but in different columns; while memory cells 103E, 103F, 103G, and 103H can be located in the same row but in different columns. For example, memory cells 103A, 103B, 103C, and 103D can be located in row R0 but in columns C0, C1, C2, and C3 respectively; while memory cells 103E, 103F, 103G, and 103H can be located in row R1 but in columns C0, C1, C2, and C3 respectively. With this configuration, each memory cell can be operatively coupled to the access lines in the corresponding column and row. In some embodiments, along each row, some eFuse memory cells 103 are coupled to corresponding word lines; and along each column, some eFuse memory cells 103 are coupled to corresponding bit lines and corresponding control gate lines. For example, eFuse memory cells 103A, 103B, 103C, and 103D are coupled to word lines WL0 disposed in row R0, and respectively coupled to bit lines BL0 and control gate lines CG0 disposed in column C0, bit lines BL1 and control gate lines CG1 disposed in column C1, bit lines BL2 and control gate lines CG2 disposed in column C2, and bit lines BL3 and control gate lines CG3 disposed in column C3. The eFuse memory cells 103E, 103F, 103G, and 103H are coupled to the word line WL1 in the horizontal row R1, and are respectively coupled to the bit line BL0 and control gate line CG0 in the vertical row C0, the bit line BL1 and control gate line CG1 in the vertical row C1, the bit line BL2 and control gate line CG2 in the vertical row C2, and the bit line BL3 and control gate line CG3 in the vertical row C3.

[0041] In some embodiments, the eFuse memory cell 103 includes a fuse resistor 210 and a control gate transistor 230. The fuse resistor 210 and the control gate transistor 230 are connected in series between each other, between the bit line BL0 and the routing line 240. The routing line 240 may extend along a row of eFuse memory cells 103. The control gate transistor 230 of this row of eFuse memory cells 103 has a source / drain region coupled to the routing line 240. In some embodiments, the memory cell array 102 includes a word line transistor 250 for each row of eFuse memory cells 103. Figure 2A As shown, word line transistor 250 is connected between routing line 240 and electrical ground. Word line WL is connected to the gate of word line transistor 250. Figure 2A The design of the eFuse memory cell 103 shown is sometimes referred to as a 1-transistor-1-resistor (1T1R) configuration, featuring a shared word line transistor. Figure 2A In this embodiment, the control gate transistor 230 and the word line transistor 250 are each implemented as N-type transistors. However, it should be understood that within the scope of this disclosure, each of these transistors may also be implemented as a P-type transistor.

[0042] Using eFuse memory cell 103A as a representative example, fuse resistor 210 has a first terminal connected to bit line BL0 and a second terminal connected to the first source / drain region of the corresponding control gate transistor 230. Control gate transistor 230 has a gate terminal connected to control gate line CG0. Control gate transistor 230 has a second source / drain terminal connected to routing line 240. Routing line 240 is connected to the first source / drain region of word line transistor 250. The second source / drain region of word line transistor 250 is connected to ground. Word line transistor 250 has a gate terminal connected to word line WL0. eFuse memory cell 103A can be programmed and read by selecting bit line BL0, activating the CG line by control gate line CG0, and activating the shared word line transistor 250 by word line WL0.

[0043] Other eFuse memory cells, such as eFuse memory cells 103B, 103C, and 103D, are located in the same row R0 and share the same word line transistor 250 as eFuse memory cell 103A. They remain unselected during the programming and reading of eFuse memory cell 103A. Figures 2B to 2E This is a schematic diagram of various operations of the eFuse memory cell 103 according to embodiments of the present disclosure. Table 1 shows exemplary bias conditions at different nodes of the eFuse memory cell 103 under different states. Each bias condition includes the signal magnitudes corresponding to the word line (WL), bit line (BL), control gate line (CGL), source / drain contact via (VD), and node VC when the eFuse memory cell 103 is being written to, read from, or in standby mode. When only one eFuse memory cell's word line or bit line is selected, it means that a second memory cell located in the same column or row is being written to or read from. When the second memory cells are located in the same row, it is assumed that the memory cells share the same word line transistor 250. The term X represents a value of X or substantially close to X, where X is a number.

[0044] Table 1

[0045]

[0046] Figure 2B , Figure 2C , Figure 2D , Figure 2E This includes four eFuse memory cells: 103A, 103B, 103E, and 103F. During programming or reading operations on eFuse memory cell 103A, eFuse memory cell 103A represents the selected cell in Table 1, with both its word line and bit line selected. eFuse memory cell 103B represents the cell in Table 1 where the WL (Start Character Line) is not selected, or the cell where the start character line is not selected; its word line is selected, but its bit line is not selected. eFuse memory cell 103E represents the cell in Table 1 where the BL (Start Character Line) is not selected, or the cell where the start bit line is not selected; its bit line is selected, but its word line is not selected. eFuse memory cell 103F represents the standby cell in Table 1, with neither its word line nor its bit line selected.

[0047] To program eFuse memory cell 103, the word line transistors shared in the corresponding row and the control gate transistors in eFuse memory cell 103 are first activated. In an example where these transistors are each implemented as N-type transistors, the word line transistors and control gate transistors are activated (e.g., turned on) by applying a logic high-level state signal to each of the word line and control gate line. Then, a programming signal (e.g., voltage) is applied to the bit line. Figure 2B As shown, to write the logic value 1 to eFuse memory cell 103A, a high-level programming voltage can be applied through bit line BL0. With word line transistor 250 and control gate transistor 230 turned on, the high-level programming voltage can be applied across the fuse resistor, causing current to flow and eventually burning out the fuse resistor. When the fuse resistor burns out, eFuse memory cell 103A becomes an open circuit, and eFuse memory cell 103A is programmed with the logic value 1.

[0048] like Figure 2C As shown, to write the logic value 0 to eFuse memory cell 103, a low-level programming voltage can be applied through the bit line. Even if the word line transistor and the control gate transistor are turned on, the low-level programming voltage cannot cause current to flow through the fuse resistor. When the programming cycle ends, the fuse resistor remains connected, and eFuse memory cell 103 is programmed with the logic value 0.

[0049] To read eFuse memory cell 103, the shared word line transistor and control gate transistor are first activated. In some embodiments, the selection of which control gate transistor to activate is fixed throughout the memory array. For example, in all columns of the memory array, one control gate line is activated during the read process. Then, a read signal (e.g., voltage) is applied to the bit line. If the fuse resistor has been programmed or blown, such as... Figure 2D As shown, there is no conductive path that can be established from the bit line, through the burned-out fuse resistor and the selected or activated control gate transistor and word line transistor, to ground. If the fuse resistor is not programmed or is burned out, a conductive path can be established from the bit line, through the fuse resistor, the control gate transistor and word line transistor, to ground, as shown. Figure 2E As shown. In some embodiments, if no conductive path is established (i.e., the fuse resistor connected to the selected control gate transistor is burned out), the eFuse memory cell 103 is identified as a first logic state (e.g., logic value 1); if a conductive path exists (i.e., the fuse resistor connected to the selected control gate transistor is not burned out), the eFuse memory cell 103 is identified as a second logic state (e.g., logic value 0).

[0050] Figure 3A This is a circuit diagram of a storage device 300 according to an embodiment of the present disclosure. Figure 3A The memory device 300 comprises a row of 1T1R eFuse memory cells sharing a word line transistor. The transistors and resistors of the memory device 300 are formed on the front side of the substrate. In some embodiments, the row of eFuse memory cells is connected to control gate routing lines formed on the back side of the substrate. In some embodiments, tap units are formed between the row of eFuse memory cells and the word line transistors. The tap units are configured to provide a conductive path between the front and back sides of the substrate to connect the back-side control gate routing lines to the source / drain regions of the shared word line transistors on the front side. In some embodiments, the memory device 300 also includes electrical rails formed on the back side of the substrate. For example, a line Vss may be formed on the back side of the substrate. The word line transistors are connected to the back-side electrical rails. Because the width of the lines on the back side of the substrate (i.e., the back-side interconnect structure) is wider than the width of the conductors on the front side, the back-side conductors have a lower resistance value. By placing the control gate routing lines and / or power lines on the back side of the substrate, the memory device according to this disclosure improves performance by reducing signal delay with lower resistance values.

[0051] Figure 3A This includes eFuse memory cells 1030, 1031, 1032, and 1033, which are located in a single row. For example... Figure 3AAs shown, eFuse memory cells 1030, 1031, 1032, and 1033 in this row are arranged along the X direction. Bit lines BL0, BL1, BL2, and BL3 extend along the Y direction with control gate lines CG0, CG1, CG2, and CG3. eFuse memory cells 1030, 1031, 1032, and 1033 in this row are connected to the same word line WL0 via a shared word line transistor 250. Even Figure 3A This illustrates four memory cells sharing a single word line transistor. The number of eFuse memory cells sharing the word line transistor can range from 2 to 32. Memory device 300 includes multiple rows of eFuse memory cells to form a memory cell array, for example... Figure 1 The memory cell array 102 in the memory.

[0052] In some embodiments, the memory device 300 includes a control gate route 240 extending through each row of memory cells. The eFuse memory cells 1030, 1031, 1032, and 1033 in this row are connected to the control gate route 240. A tap unit 270 is disposed between a shared word line transistor 250 and the eFuse memory cells 1030, 1031, 1032, and 1033 in this row. In some embodiments, the shared word line transistor 250, the tap unit 270, and the eFuse memory cells 1030, 1031, 1032, and 1033 in this row form a line along the X direction. A control gate routing line 240 extends from eFuse memory cells 1030, 1031, 1032, and 1033 in this row to a tap unit 270. In some embodiments, the memory device 300 includes a control gate termination line 242 extending between the tap unit 270 and a shared word line transistor 250. In some embodiments, the gate structure of the word line transistor 250 is connected to the word line WL0. One source / drain region of the word line transistor 250 is connected to the control gate termination line 242. Another source / drain region of the word line transistor 250 is connected to the power supply VSS. In some embodiments, the control gate termination line 242 is disposed on the front side of the substrate, while the power supply VSS is disposed on the back side of the substrate. The tap unit 270 includes a conductive path 272 electrically coupling the control gate routing line 240 formed on the back side of the substrate to the control gate termination line 242 formed on the front side of the substrate. In some embodiments, the conductive path 272 includes conductors formed on layers VB, SD, MD, and VD. In some embodiments, additional tap units may be provided along eFuse memory units 1030, 1031, 1032, and 1033 of this row to provide additional conductive paths for power lines or signal lines between the front and back sides.

[0053] Figures 3B to 3E This is a partial layout diagram of a storage device 300 according to an embodiment of the present disclosure. Figures 3B to 3E The layout diagram includes views of different layers to show the layout. Figures 3B to 3E The layout in the middle achieves Figure 3A The circuit diagram of the storage device 300 shows an eFuse memory cell 103. The eFuse memory cell 103 can be implemented with other layout designs. The eFuse memory cell 103 is based on... Figure 2A and Figure 3A The circuit design shown is implemented using a 1T1R configuration.

[0054] In some embodiments, the active region and gate structure are located along the main front surface of the substrate 402 (sometimes referred to as part of the front-end-of-line (FEOL) process / network). In some embodiments, the active region and gate structure may be referred to as device layer 430. After device layer 430 is formed, front-side interconnect structure 432 is formed on device layer 430 in a back-end-of-line (BEOL) process. In some embodiments, after front-side interconnect structure 432 is formed, back-side interconnect structure 434 may be formed on the back side of substrate 402. Front-side interconnect structure 432 and back-side interconnect structure 434 include wires and conductive vias to provide power lines and signal lines to transistors in device layer 430.

[0055] The front interconnect structure 432 may include formable metallization layers (e.g., layer M0, layer M1, layer M2, layer M3, etc.), which include metal rails or metal lines embedded in the corresponding dielectric material (e.g., inter-metal dielectric (IMD) / inter-layer dielectric (ILD)). The back interconnect structure 434 may include formable metallization layers (e.g., layer BM0, layer BM1, etc.), which include metal rails or metal lines embedded in the corresponding dielectric material (e.g., IMD / ILD). Figure 3B This includes the metal layer BM0, the device layer, and the fuse resistor 210 in layer M2. Figure 3C Including metal layer M0 and Figure 3B The layers in the middle. Figure 3D Including metal layer M1 and Figure 3C The layers in the middle. Figure 3E Including metal layer M3 and Figure 3D The layers in the middle. Figure 3F This is a schematic top view of the fuse resistor of the eFuse memory cell 103 according to an embodiment of the present disclosure. Figure 3G to Figure 3K They are along Figure 3E Cross-sectional views of line segments A-A', B-B', C-C', D-D', and E-E'.

[0056] exist Figure 3B For clarity, only the active region, gate structure, back-side interconnect layer, and fuse resistor of eFuse memory cell 103 are shown. Figure 3BAs shown, the eFuse memory cell 103 includes patterns each configured to form active regions (hereinafter referred to as active regions 412, 414, 416, and 418), and patterns each configured to form gate structures (hereinafter referred to as control gate structure 408 and pseudo gate structure 410, respectively). Active regions 412, 414, 416, and 418 may each extend along a first lateral direction (e.g., the X direction), while gate structures 408 and 410 may each extend along a different second lateral direction (e.g., the Y direction). Active regions 412, 414, 416, and 418, together with gate structure 408, form one or more control gate transistors.

[0057] The transistor can be a planar transistor, a FinFET transistor, a multi-channel transistor, a GAA transistor, or any other suitable type of transistor. In some embodiments, active regions 412, 414, 416, and 418 include channel regions formed in and / or on the substrate 402, and epitaxially grown source / drain regions connected to the channel regions. Active regions 412, 414, 416, and 418 are isolated by an isolation region 404 (e.g., Figure 3G to Figure 3K (As shown) and separated from each other, for example, by shallow trench isolation.

[0058] In some embodiments, such as Figure 3G to Figure 3K As shown, active regions 412, 414, 416, and 418 include channels formed from doped regions in the substrate, and source / drain regions formed adjacent to the channels. In other embodiments, active regions 412, 414, 416, and 418 each form a fin structure protruding from the main surface of substrate 402 to form a FinFET or GAA transistor. The fin structure may comprise a single layer of semiconductor material or may comprise semiconductor nanostructures (e.g., nanosheets) extending along the X-direction and perpendicularly spaced from each other. Portions of the semiconductor material in the doped regions, or in the fin structures covered by gate structures 408 and 410, are retained, while other portions are replaced by epitaxial structures. The portion of the semiconductor structure that is retained can be configured as the channel of the corresponding transistor, while the epitaxial structure coupled to both sides (or both ends) of the portion of the semiconductor structure that is retained can be configured as the source / drain region of the transistor, and the portion of the gate structure that covers (e.g., straddle) the portion of the semiconductor structure that is retained can be configured as the gate of the transistor.

[0059] like Figure 3BIn a representative example, the portions of active regions 412, 414, 416, and 418 covered by the controlled gate structure 408 can serve as the channel of the controlled gate transistor 230. Figure 3B In the illustrated embodiment, eight control gate structures 408 intersect with four active regions 412, 414, 416, and 418, forming 32 control gate transistors 230. These 32 control gate transistors 230 are connected in parallel and function as a single control gate transistor. Depending on performance requirements, the eFuse memory cell 103 may include more parallel-connected control gate transistors, or as few as a single control gate transistor.

[0060] In transistor regions 420 and 422, the group of control gate structures 408 intersects with active regions 412, 414, 416, and 418. Active regions 412, 414, 416, and 418 extend along the X-direction beyond both ends of transistor regions 420 and 422. Outside transistor regions 420 and 422, dummy gate structures 410 are formed above active regions 412, 414, 416, and 418. Dummy gate structures 410 are disposed along the X-direction on both sides of transistor regions 420 and 422. The position of the dummy gate structures 410 is used to maintain the pattern density of the CG gate structure 408 near the edge and improve process uniformity.

[0061] The eFuse memory cell 103 also includes source / drain contact components formed on the source / drain regions in active regions 412, 414, 416, and 418. These source / drain contact components are sometimes referred to as middle-end interconnect structures (MD). The source / drain contact components can connect the corresponding source / drain regions to the upper interconnect structure via middle-end conductive vias (i.e., source / drain contact vias VD). Additionally, the gate structure can be coupled to the upper interconnect structure via middle-end conductive vias (i.e., gate contact vias VG).

[0062] In some embodiments, substrate 402, active regions 412, 414, 416, and 418, gate structure 408, gate structure 410, source / drain contact components, source / drain contact conductive vias, and gate contact conductive vias can be collectively referred to as device layer 430, such as... Figure 3G As shown. Reference Figure 3BThe eFuse memory cell 103 includes source / drain contact components 428 and 429, respectively formed above the source / drain regions of the control gate transistor 230. Source / drain contact component 428 is formed above the source / drain regions of the control gate transistor 230 to connect to the fuse resistor 210. Source / drain contact component 429 is formed above the source / drain regions of the control gate transistor 230 to connect to the control gate routing line 240.

[0063] In some embodiments, the control gate route 240 is formed on the back-side interconnect structure 434. Therefore, the control gate route 240 is connected to the source / drain region of the control gate transistor 230 via a back-side conductive via and a source / drain contact 429. The source / drain contact 429 is a dummy contact and is not further connected to signal or power lines formed after the front-side interconnect structure 432. In this case, the source / drain contact 429 can be formed to maintain pattern density, thus promoting process uniformity. In other embodiments, the source / drain contact 429 may be omitted.

[0064] In an alternative embodiment, the eFuse memory cell 103 may include a control gate route formed in the front-side interconnect structure 432. Source / drain contact 429 is connected to the front-side control gate route 240. In some embodiments, the eFuse memory cell 103 includes both a front-side control gate route and a back-side control gate route.

[0065] In some embodiments, the eFuse memory cell 103 further includes a back-side source / drain contact via 438 formed from the back side of the substrate 402. The back-side source / drain contact via 438 provides electrical connections to the connection lines in the back-side interconnect structure 434, ultimately connecting the source / drain region of the control gate transistor 230 to the control gate routing line. In some embodiments, a source / drain contact member 429 may be connected to a source / drain contact via 436 to connect to the wires formed in the front-side interconnect structure 432, ultimately connecting the source / drain contact member 429 and the source / drain region of the control gate transistor 230 to the front-side control gate routing line. In some embodiments, the eFuse memory cell 103 includes both the source / drain contact via 436 and the back-side source / drain contact via 438 to connect the source / drain region to a power source with less resistance.

[0066] In some embodiments, the source / drain contact portions 426 and 428 of adjacent active regions 412 / 414 and 416 / 418 may be formed as continuous lines and then separated by cut contact portions 427 (also referred to as CMDs). The cut contact portions 427 are formed with an insulating material to provide independent electrical connections to the transistors formed in the active regions 412 / 414 and 416 / 418. In some embodiments, the device layer 430 of the eFuse memory cell 103 includes a gate conductive via 448 connecting the gate structure 408 to the control gate transistor 230.

[0067] In some embodiments, such as Figures 3B to 3H As shown, the eFuse memory cell 103 includes a control gate route 445 formed in the back-side interconnect structure 434. In some embodiments, the control gate route 445 is formed in the metal layer BMO of the back-side interconnect structure 434. In some embodiments, the control gate route 445 extends along the X direction or parallel to the active regions 412, 414, 416, and 418. The control gate route 445 extends through the eFuse memory cell 103 and other eFuse memory cells 103 in the same row. In some embodiments, the eFuse memory cell 103 includes four control gate routes 445, aligned with the active regions 412, 414, 416, and 418, respectively. A source / drain conductive via 438 electrically connects the control gate route 445 to the source / drain regions of the control gate transistor 230.

[0068] Figure 3C It is eFuse memory cell 103, in Figure 3B The layout diagram includes a layout diagram of metal layer M0. In some embodiments, metal layer M0 is the first layer directly adjacent to the device layer in the front interconnect structure 432. Metal layer M0 includes various metal lines extending along the X direction (or parallel to the direction of active regions 412, 414, 416, and 418).

[0069] like Figure 3C and Figure 3KAs shown, the metal layer M0 includes a control gate landing pad 440 configured to be connected to the gate structure 408 of the control gate transistor 230 via a gate conductive via 448. The control gate landing pad 440 is configured to provide a control gate signal to the gate of the control gate transistor 230. In some embodiments, the landing pad 440 may be disposed along the X direction and extend through the gate structure 408. In some embodiments, the control gate landing pad 440 may be disposed at the boundary of the eFuse memory cell 103 and shared with adjacent eFuse memory cells 103 in adjacent rows.

[0070] The metal layer M0 also includes a landing pad 444, which is connected to the source / drain contact portion 428 of the control gate transistor 230 via a source / drain contact conductive via 437. For example... Figure 3C , Figure 3G and Figure 3H As shown, landing pad 444 is configured to connect to fuse resistor 210 formed in the overlying metal layer. In some embodiments, landing pad 444 may be positioned along the X direction, extending through source / drain contact portion 428. In some embodiments, eFuse memory cell 103 may include a plurality of landing pads 444. For example, landing pad 444 may be positioned above each of active regions 412, 414, 416, and 418, as shown. Figure 3H As shown, the source / drain contact component 428 is connected above the corresponding active region.

[0071] In some embodiments, such as Figures 3B to 3E and Figures 3H to 3K As shown, the fuse resistor 210 can be formed at an offset location from the active regions 412, 414, 416, and 418, so that the heat generated during programming (e.g., melting of the fuse resistor 210) will not affect the transistor wires and conductive vias. In some embodiments, the fuse resistor 210 is formed between transistor regions 420 and 422 to have a substantially symmetrical layout.

[0072] In some embodiments, the fuse resistor 210 includes an elongated wire extending along the X direction. Figure 3FThis is a schematic enlarged view of a portion of the fuse resistor 210 of the eFuse memory cell 103 according to an embodiment of the present disclosure. The fuse resistor 210 may include an elongated conductor 454 extending along the X direction. In some embodiments, the elongated conductor 454 may extend along the long side of transistor region 420 and transistor region 422. In some embodiments, the elongated conductor 454 has a length 454x along the X direction and a width 454y along the Y direction. The length 454x is much larger than the width 454y. The fuse resistor 210 has a first end 454bl configured to connect to a bit line and a second end 454cg configured to connect to the source / drain region of a control gate transistor 230. The fuse resistor 210 is designed to melt when a programming voltage is applied from the bit line, breaking the connection between the first end 454bl and the second end 454cg.

[0073] In some embodiments, the fuse resistor 210 further includes a dummy conductor 456 disposed adjacent to the first end 454bl and the second end 454cg of the elongated conductor 454. The dummy conductor 456 may be disposed parallel to both sides of the elongated conductor 454. The dummy conductor 456 may serve as a heat dissipation path between the first end 454bl and the second end 454cg, thereby promoting heat accumulation in the central portion of the elongated conductor 454 to facilitate melting during programming. In some embodiments, the dummy conductor 456 may be a rectangular conductive pad having a length 456x along the X direction and a width 456y along the Y direction. In some embodiments, the ratio of the length 456x of the dummy conductor 456 to the length 454x of the elongated conductor 454 is in the range of 0.1 to 0.33. In some embodiments, the width 456y of the dummy conductor 456 is substantially similar to the width 454y of the elongated conductor 454. In some embodiments, the width 456y of the dummy conductor 456 is greater than the width 454y of the elongated conductor 454. For example, the ratio of width 456y to width 454y is in the range of 1.0 to 5.0. In some embodiments, the dummy conductor 456 is electrically connected to the elongated conductor 454 at a corresponding point in the first end 454bl and the second end 454cg.

[0074] like Figure 3H and Figure 3KAs shown, the second end 454cg of the elongated conductor 454 is connected to the source / drain region of the control gate transistor 230 via the source / drain contact member 428, the source / drain contact conductive via 437, the landing pad 444 in layer M0, the conductive via 458 connected to the landing pad 444, the landing pad 460 in layer M1, and the conductive via 462 connecting the landing pad 460 and the second end 454cg of the elongated conductor 454. The landing pad 460 in layer M1 may be a wire extending along the Y direction. In some embodiments, the eFuse memory cell 103 includes a number of landing pads 460 disposed along the Y direction. These landing pads 460 may extend along the length of the second end 454cg, for example, a length similar to the length 456x of the pseudo conductor 456, to connect the elongated conductor 454 having a plurality of conductive vias 462. These landing pads 460 provide multiple parallel conductive paths between the word line transistor 250 and the fuse resistor 210, thereby reducing the resistance value. In some embodiments, the dummy conductor 456 is electrically connected to the landing pad 460 at the second end 454cg via a conductive via 462.

[0075] like Figure 3I and Figure 3K As shown, the first end 454bl of the elongated conductor 454 is connected to one or more bit lines 466 formed in layer M3. In some embodiments, the one or more bit lines 466 implement Figure 3A The eFuse memory cell 103 includes bit lines BL0, BL1, BL2, and BL3. The eFuse memory cell includes conductive vias 464 connecting bit lines 466 in layer M3 to elongated conductors 454 in layer M2. In some embodiments, the eFuse memory cell 103 includes a number of bit lines 466 arranged along the Y direction. These bit lines 466 may extend along the length of the first end 454bl, for example, similar to the length 456x of the dummy conductor 456, to connect the elongated conductor 454 having multiple conductive vias 464. These bit lines 466 provide multiple parallel conductive paths to the bit line signals of the fuse resistor 210, thereby reducing the resistance value and improving performance. In some embodiments, the dummy conductor 456 is electrically connected to the bit lines 466 through the conductive vias 464 at the first end 454bl.

[0076] In some embodiments, the eFuse memory cell 103 includes one or more control gate lines 467 in layer M3. For example... Figure 3E , Figure 3H and Figure 3J As shown, the eFuse memory cell 103 includes one or more control gate lines 467 extending along the Y direction in layer M3. In some embodiments, these one or more control gate lines 467 implement... Figure 3AThe control gate lines CG0, CG1, CG2, and CG3 are specified. In some embodiments, one or more control gate lines 467 may be disposed above the second end 454cg of the elongated conductor 454. By placing one or more control gate lines 467 and bit lines 466 above the second end 454cg and the first end 454b1, respectively, heat generated in the elongated conductor 454 during the programming operation can be avoided.

[0077] These one or more control gate lines 467 can be connected to the gate structure 408 via conductive paths formed in the front interconnect structure 432. For example... Figure 3J As shown, one or more control gate lines 467 can be electrically coupled to the gate structure 408 via conductive paths. These conductive paths include conductive vias 448 in layer V0, control gate landing pads 440 in layer M0, one or more conductive vias in layer V0, landing pads 461 and 463 in layer M1, landing pads 457 and 465 in layer V2. In some embodiments, the landing pad 457 can be a wire extending along the X direction. Landing pads 457 and 461 can be disposed at the boundaries of eFuse memory cells 103 and shared with adjacent eFuse memory cells 103 in adjacent rows.

[0078] In some embodiments, the storage device includes a tap unit 470 arranged side-by-side next to a cell area 411, which includes a row of eFuse memory cells 103. Figure 4A This is a schematic layout diagram showing the storage device 300 of the tap unit 470 located next to the first eFuse memory cell 103 in the cell area 411. Figure 4B This shows a partial layout diagram of tap unit 470. Figure 4C yes Figure 4B The cross-sectional view of tap unit 470 along line segment F-F'.

[0079] Tap unit 470 can be arranged along the direction of active regions 412, 414, 416, and 418, for example, at the edge of transistor regions 420 and 422. Figure 4A As shown. Tap unit 470 includes conductive paths to facilitate additional power lines and / or signal lines. In some embodiments, tap unit 470 is configured to provide conductive paths to connect control gate routing line 445 to front-side interconnect structure 432, the control gate routing line 445 being disposed in back-side interconnect structure 434.

[0080] like Figure 4B and Figure 4C As shown, in device layer 430, tap unit 470 may include an active region 476 extending along the directions of active regions 412, 414, 416, and 418, but electrically isolated from them. Active region 476 is a pseudo-region. In some embodiments, active region 476 is formed along the same line as active regions 412, 414, 416, and 418 but is separated by an isolation structure. Pseudo-gate structure 472 and pseudo-source / drain contact components 474 are formed above active region 476. In some embodiments, control gate routing line 445 in layer BMO extends from eFuse memory cell 103 to tap unit 470. Control gate routing line 445 in layer BMO extends along the X direction through tap unit 470 and transistor regions 420 / 422.

[0081] Tap unit 470 includes a front-side control gate routing rail 442 in layer M0. The front-side control gate routing rail 442 also extends through tap unit 470 and into a word line transistor 250 adjacent to tap unit 470. Control gate routing line 445 and the front-side control gate routing rail 442 can be electrically connected to each other via conductive paths formed in tap unit 470. In some embodiments, the conductive paths may include source / drain contact vias 436, source / drain contact members 474, active regions 476, and back-side source / drain contact members 438. Other conductive structures, such as vias through the device layer, may be formed at the locations of the back-side source / drain contact vias 438 and active regions 476. The conductive paths in tap unit 470 allow control gate routing line 445 to connect to the front-side control gate routing rail 442, which in turn connects to the word line transistor 250.

[0082] In some embodiments, the conductive path in the tap unit 470 may include a feed through via (FTV) 439, replacing the conductive via 438 and the active region 476. Figure 4D This is a cross-sectional view of a tap unit 470 with a feedthrough via 439. The feedthrough via 439 can be formed in a back-side process by forming a conductive via opening from the back side and filling it with a conductive material (e.g., metal). The feedthrough via 439 contacts the source / drain contact component 474, forming a conductive path between the metals, thereby reducing the resistance value.

[0083] In some embodiments, the storage device 300 includes a word line transistor region 450 disposed next to the tap unit 470. Figure 5AThis is a schematic layout diagram showing a memory device 300 located adjacent to a word line transistor region 450 disposed at a tap unit 470. The transistor region 450 and the cell region 411 are located on opposite sides of the tap unit 470. Figure 5B Figure 5B This shows a memory device 300 with word line transistor area 450 and tap unit 470. Figure 5C yes Figure 5B The cross-sectional view of tap unit 470 along line segment G-G'. Figure 5D yes Figure 5B The cross-sectional view of tap unit 470 along line segment H-H'.

[0084] The word line transistor region 450 includes an active region 480 extending along the X direction on a substrate 402, and a word line gate structure 406 extending along the Y direction. The portion of the active region 480 covered by the word line gate structure 406 can serve as the channel of the word line transistor 250. Figure 5B In the illustrated embodiment, eight word line gate structures 406 intersect with four active regions 480, thus forming 32 word line transistors 250. These 32 word line transistors 250 are connected in parallel and function as a single word line transistor. The word line transistor region 450 may include more word line transistors connected in parallel, or as few as a single word line transistor, depending on performance requirements. Source / drain contact portions 424 and 426 are formed in the source / drain regions of the active regions 480. The source / drain contact portion 424 is formed above the source / drain regions of the word line transistors 250, which will be connected to the power supply Vss. The source / drain contact portion 426 is formed above the source / drain regions of the word line transistors 250, which will be connected to the control gate transistor 230 in the eFuse memory cell 103 of this row.

[0085] In some embodiments, such as Figure 5B As shown, the word line transistor region 450 includes a word line rail 446 in layer M0. The word line rail 446 is connected to the gate structure 406 via a gate conductive via 448. In some embodiments, a front-side control gate rail 442 extends from the tap unit 470 to the word line transistor region 450. A source / drain contact 426 is formed above the source / drain region of the word line transistor 250, which is connected to the control gate route line 240 via the tap unit 470. The source / drain contact 426 is connected to the front-side control gate rail 442 via a contact conductive via 482, as shown. Figure 5B and Figure 5C As shown.

[0086] In some embodiments, the word line transistor region 450 includes a front-side Vss rail 486 formed in layer M0. The front-side Vss rail 486 may be parallel to the front-side control gate rail 442 and the word line rail 446. The front-side Vss rail 486 can be connected to the source / drain contact member 424 via a contact conductive via 484, such as... Figure 5D As shown.

[0087] In some embodiments, the word line transistor region 450 may include a back-side Vss rail 478 formed in the back-side interconnect structure 434. In some embodiments, the back-side Vss rail 478 may be disposed in layer BMO. For example, the back-side Vss rail 478 may be aligned with the control gate route line 445 in the tap unit 470 and gate structure 410, but electrically isolated from the control gate route line 445. The source / drain regions of the word line transistor 250 are connected to the back-side Vss rail 478 through conductive vias 435. Figure 5C As shown, the source / drain regions of the word line transistor 250 are powered by the back-side Vss rail 478 and the front-side Vss rail 486. The dual Vss power lines improve the performance stability of the memory device 300.

[0088] In some embodiments, the control gate routing line 445 in the gate structure 410 and the tap unit 470 can be widened to cover one or more active regions in order to reduce the resistance value and improve performance. Figure 6A and Figure 6B The layout of a memory device 300 with a widened control gate routing line 445 is shown. In particular, the control gate routing line 445 has a width along the Y direction that covers two or more active regions 412, 414, 416, and 418.

[0089] In some embodiments, the memory device according to this disclosure may include a front-side control gate route line in addition to the control gate route line 445 to improve performance. Figure 7A This is a circuit diagram of a storage device 300a according to an embodiment of the present disclosure. The storage device 300a and... Figure 3A The memory device 300 is similar, except that memory device 300a includes a front-side control gate route 241. The front-side control gate route 241 may extend along a row of eFuse memory cells 103. The control gate transistors 230 of this row of eFuse memory cells 103 have source / drain terminals coupled to the route 241.

[0090] Figure 7B This is a partial layout diagram of the eFuse memory cell 103 that implements the storage device 300a. Figure 7C yes Figure 7B The layout is a partial cross-sectional view along line segment C-C'. For example... Figure 7Aand Figure 7B As shown, routing line 241 can be implemented as a front control gate rail 442a disposed above eFuse memory cell 103. The front control gate rail 442a is connected to source / drain contact member 429 via contact conductive via 436. The front control gate rail 442a extends along the X direction through the eFuse memory cell 103 in this row. In some embodiments, the front control gate rail 442a may extend through tap unit 470 and word line transistor region 450 to or connect to the front control gate rail 442.

[0091] In the memory devices described above, a single word line transistor is connected to a word line and is shared by an entire row of memory cells. In some embodiments, two or more shared word line transistors are connected to a word line, and each shared word line transistor is shared by two or more memory cells in a row. Figure 8 This is a circuit diagram of a memory device 300b according to an embodiment of the present disclosure. The memory device 300b includes memory cells arranged in columns and rows. Each row of memory cells can be divided into two or more cell groups 110. Each cell group 110 includes a shared word line transistor. Figure 8 As shown, the word line WL can extend along the memory cells in this row. The word line WL is connected to the gate structure of the shared word line transistor. By dividing a row of memory cells into two or more groups, the memory device 300b can share the word line transistor and avoid excessive performance degradation.

[0092] Figure 9 This is a flowchart of an exemplary method 500 for forming a storage device according to an embodiment of the present disclosure. Method 500 can be used to manufacture storage devices, such as storage devices 100, 300, and 300b according to the present disclosure.

[0093] In operation 502 of method 500, a device layer comprising transistors of multiple memory cells can be formed on a substrate. For example, device layer 430 is formed on substrate 402, such as... Figures 3B to 3KAs shown. In some embodiments, device layer 430 may include transistors for a plurality of memory cells, such as eFuse memory cell 103 according to an embodiment of the present disclosure. Device layer 430 may include a cell region and a word line transistor region, the cell region including a row of memory cells, and the word line transistor region being disposed adjacent to one end of the cell region. The word line transistor region includes character transistors shared by the row of memory cells. In some embodiments, device layer 430 may include a tap unit, such as tap unit 470, disposed between the cell region and the shared word line transistor region. In some embodiments, device layer also includes circuit elements of logic circuitry, such as row decoder 104, column decoder 106, input / output circuitry 108, and control logic circuitry 112.

[0094] In operation 504, a front interconnect structure (e.g., front interconnect structure 432) is formed over the device layer. In some embodiments, the front interconnect structure 432 may include paths for signal and power lines to connect to transistors in the device layer for memory cells and overlay units. In some embodiments, the front interconnect structure 432 includes a front control gate line connecting the memory cells in this row to shared word line transistors. In some embodiments, the control gate line extends through word line transistor regions and tap units. In other embodiments, the front control gate line extends through word line transistors, tap units, and memory cells in this row.

[0095] In operation 506, the carrier wafer can be attached over the front-side interconnect structure of the substrate. Then, the carrier wafer and substrate can be flipped to be processed from the back side of the substrate. In some embodiments, the substrate can be ground down prior to the back-side processing.

[0096] In operation 508, back-side contact components, such as source / drain contact vias 438, may be formed on the back side of the substrate. These back-side contact components may be formed to connect memory cells to the transistors of the encapsulation cells. In some embodiments, conductive vias (through-device vias) may be formed to provide a conductive path from the front side of the substrate to the back side of the substrate.

[0097] In operation 510, a back-side interconnect structure, such as back-side interconnect structure 434, is formed on the back side of the substrate. In some embodiments, back-side interconnect structure 434 may include paths for signal lines and power lines to connect to transistors in the device layer for memory cells, tap units, and word line transistors. In some embodiments, back-side interconnect structure 434 includes a back-side control gate line. The back-side control gate line may be directly connected to the control gate transistor in the memory cell. In some embodiments, the back-side control gate line may be electrically coupled to a front-side control gate line via a conductive path in the tap unit. In some embodiments, back-side interconnect structure 434 may include back-side electrical rails. In some embodiments, back-side electrical rails may be formed in the word line transistor region.

[0098] The various embodiments or examples described herein offer numerous advantages over the prior art. Embodiments of this disclosure provide memory devices (e.g., memory devices with 1T1R eFuse memory cells having shared word line transistors). By sharing word line transistors, the eFuse memory cells according to this disclosure have a reduced bit cell area. Compared to 2T1R eFuse memory cells, the bit cell area of ​​a 1T1R eFuse memory cell with shared word line transistors is reduced by approximately 30%. In some embodiments, the memory device according to this disclosure includes back-side power lines or signal lines, such as control gate lines on the back side of the eFuse memory cell. By incorporating back-side signal lines or power lines that can be wider than front-side lines, embodiments of this disclosure provide memory devices with lower resistance values, thereby reducing RC delay and improving programming performance.

[0099] It should be understood that not all advantages need to be described here, and all embodiments and examples do not necessarily provide any specific advantages; other embodiments or examples may provide different advantages.

[0100] In some aspects, the technology described herein relates to a semiconductor device comprising: a device layer including transistors of a row of eFuse memory cells and a shared word line transistor; a first interconnect structure disposed on a first side of the device layer, wherein the first interconnect structure includes: a first control gate line disposed along the row of eFuse memory cells, wherein the first control gate line is connected to the eFuse memory cells; and a second interconnect structure disposed on a second side of the device layer, wherein the second side is relative to the first side, the second interconnect structure including a second control gate line disposed above the shared word line transistor, and the first control gate line and the second control gate line are connected via a conductive path.

[0101] In some embodiments, the device layer further includes a tap unit disposed between the eFuse memory cells and the shared word line transistor in this row. In some embodiments, each of the eFuse memory cells includes: a control gate transistor having a first source / drain region and a second source / drain region; and a fuse resistor connected to the first source / drain region. In some embodiments, a first control gate line is electrically connected to the second source / drain region of the control gate transistor. In some embodiments, the fuse resistor is formed in the second interconnect structure. In some embodiments, the semiconductor device further includes a third control gate line disposed along the eFuse memory cells in this row and disposed in the second interconnect structure. In some embodiments, the third control gate line is connected to the second control gate line. In some embodiments, the first control gate line extends into the tap unit. In some embodiments, the first interconnect structure further includes: a back-side power line disposed along the shared word line transistor. In some embodiments, the back-side power line and the first control gate line are disposed in the same layer of the first interconnect structure.

[0102] In some aspects, the technology described herein relates to a method of operating a memory device, comprising: providing a memory device including: a row of eFuse memory cells, wherein the row of eFuse memory cells includes a control gate transistor and a fuse resistor connected to the control gate transistor, and a control gate line connected to the control gate transistor in each of the row of eFuse memory cells; and a shared word line transistor disposed in the row of eFuse memory cells, wherein the shared word line transistor is disposed between a power line and a control gate line; and reading or programming a first eFuse memory cell in the row of memory cells, wherein reading or programming the first eFuse memory cell in the row of memory cells includes: activating the control gate transistor of the first eFuse memory cell in the row of memory cells; and activating the shared word line transistor.

[0103] In some embodiments, the method of operating the memory device further includes reading or programming a second eFuse memory cell in the eFuse memory cell of this row, wherein the operation of reading or programming the second eFuse memory cell in the eFuse memory cell of this row includes: activating the control gate transistor of the second eFuse memory cell in the eFuse memory cell of this row; and activating the shared word line transistor.

[0104] In some aspects, the technology described herein relates to a method of forming a memory device, comprising: forming a device layer on a first side of a substrate, wherein the device layer includes transistors for a row of eFuse memory cells and a shared word line transistor aligned with the row of eFuse memory cells along a first direction; forming a front-side interconnect structure over the device layer, wherein the front-side interconnect structure includes a front-side control gate line; and forming a back-side interconnect structure on the device layer, wherein the back-side interconnect structure includes a back-side control gate line.

[0105] In some embodiments, forming a device layer includes: forming a plurality of active regions along a first direction; and forming a plurality of gate structures along a second direction perpendicular to the first direction, wherein the eFuse memory cells in this row are arranged along the first direction. In some embodiments, a front-side control gate line is electrically connected to a back-side control gate line. In some embodiments, the device layer further includes a tap unit disposed between a shared word line transistor and the eFuse memory cells in this row. In some embodiments, each of the eFuse memory cells includes: a control gate transistor having a first source / drain region and a second source / drain region; and a fuse resistor connected to the first source / drain region. In some embodiments, a back-side control gate line is disposed along the eFuse memory cells in this row and connected to the second source / drain region of each of the eFuse memory cells in this row. In some embodiments, a front-side control gate line is disposed above the shared word line transistor. In some embodiments, a front-side control gate line is disposed above the shared word line transistor and the tap unit.

[0106] As used herein, “about” and “approximately” generally refer to the value of a given quantity that varies depending on the specific process node associated with the semiconductor device in question. Based on a specific process node, “about” can indicate that the value of a given quantity varies within, for example, 10% to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0107] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them without departing from the spirit and scope of this disclosure.

Claims

1. A storage device, comprising: The device layer includes transistors for rows of electronically programmable fuse (eFuse) memory cells and shared word line transistors; A first interconnect structure is disposed on a first side of the device layer, wherein the first interconnect structure includes: A first control gate line is disposed along a row of the eFuse memory cell, wherein the first control gate line is connected to the eFuse memory cell; and A second interconnect structure is disposed on a second side of the device layer, wherein the second side is relative to the first side, and the second interconnect structure includes: A second control gate line is disposed above the shared word line transistor, and the first control gate line and the second control gate line are connected through a conductive path.

2. The memory device of claim 1, wherein the device layer further comprises a tap unit disposed between a row of the eFuse memory cell and the shared word line transistor.

3. The storage device of claim 2, wherein each of the eFuse memory cells comprises: A control gate transistor having a first source / drain region and a second source / drain region; as well as A fuse resistor is connected to the first source / drain region.

4. The memory device of claim 3, wherein the first control gate line is electrically connected to the second source / drain region of the control gate transistor.

5. The memory device of claim 3, wherein the fuse resistor is formed in the second interconnect structure.

6. A method of operating a storage device, comprising: A memory device is provided, the memory device comprising rows of electronically programmable fuse (eFuse) memory cells and shared word line transistors, wherein the eFuse memory cell includes: a control gate transistor; a fuse resistor connected to the control gate transistor; and a control gate line connected to the control gate transistor in each of the eFuse memory cells; and the shared word line transistor disposed in a row of the eFuse memory cell, wherein the shared word line transistor is disposed between a power line and the control gate line; and Read or program the first eFuse memory cell in the row of the eFuse memory cells. The operation of reading or programming the first eFuse memory cell in the row of eFuse memory cells includes: The control gate transistor of the first eFuse memory cell in the row of the eFuse memory cell is activated; and Start the shared word line transistor.

7. The method of operating the storage device according to claim 6, further comprising reading or programming a second eFuse memory cell in the row of the eFuse memory cells. The operation of reading or programming the second eFuse memory cell in the row of eFuse memory cells includes: The control gate transistor of the second eFuse memory cell in the row of the eFuse memory cell is activated; as well as Start the shared word line transistor.

8. A method of forming a storage device, comprising: A device layer is formed on a first side of a substrate, wherein the device layer includes transistors for rows of electronically programmable fuse (eFuse) memory cells and shared word line transistors, the shared word line transistors being aligned with the rows of eFuse memory cells along a first direction; A front-side interconnect structure is formed above the device layer, wherein the front-side interconnect structure includes a front-side control gate line; as well as A back-side interconnect structure is formed in the device layer, wherein the back-side interconnect structure includes a back-side control gate line.

9. The method of forming a memory device according to claim 9, wherein the operation of forming the device layer includes: Multiple active regions are formed along the first direction; as well as Multiple gate structures are formed along a second direction perpendicular to the first direction, wherein rows of eFuse memory cells are arranged along the first direction.

10. The method of forming a memory device according to claim 9, wherein the front-side control gate line is electrically connected to the back-side control gate line.

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