Semiconductor structure and method of manufacturing the same, storage system

Abstract

The present disclosure provides a semiconductor structure, a manufacturing method thereof, and a storage system. The semiconductor structure includes a first bonding layer. The first bonding layer includes a first gap structure and a plurality of first bonding structures. The first gap structure is located between adjacent first bonding structures. The first gap structure includes an air gap.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to semiconductor structures, methods of manufacturing semiconductor structures, and memory systems. Background Technology

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices and cloud storage, the requirements for the performance and processes of semiconductor structures such as three-dimensional semiconductor storage devices are becoming increasingly stringent. Summary of the Invention

[0003] This disclosure provides a semiconductor structure. The semiconductor structure includes a first bonding layer. The first bonding layer includes a first gap structure and a plurality of first bonding structures. The first gap structure is located between adjacent first bonding structures. The first gap structure includes an air gap.

[0004] In one embodiment, the semiconductor structure further includes a second bonding layer. The second bonding layer is located on one side of the first bonding layer in the first direction and includes a second bonding structure and a second gap structure. The second bonding structure is connected to the first bonding structure. The second gap structure includes an air gap.

[0005] In one embodiment, the first gap structure is spaced apart from or in contact with the second gap structure.

[0006] In one embodiment, a plurality of first bonding structures are arranged in an array along a second direction and / or a third direction. First gap structures are located between adjacent first bonding structures along the second direction. The second direction and the third direction intersect.

[0007] In one embodiment, a plurality of first bonding structures are arranged in an array facing the second direction and / or the third direction. First gap structures are located between adjacent first bonding structures facing the second direction and / or the third direction. The second direction and the third direction intersect.

[0008] In one embodiment, the first gap structure is spaced apart from or in contact with the first bonding structure.

[0009] In one embodiment, the first gap structure includes a strip-shaped structure and / or a curved structure.

[0010] In one embodiment, the first gap structure and the second gap structure have the same structure.

[0011] In one embodiment, the semiconductor structure further includes a sealing ring surrounding the first bonding layer. A first gap structure contacts the sealing ring.

[0012] In one embodiment, the first bonding layer further includes a first dielectric layer. The second bonding layer further includes a second dielectric layer connected to the first dielectric layer. At least a portion of the first bonding structure and the first gap structure are located within the first dielectric layer, and at least a portion of the second bonding structure and the second gap structure are located within the second dielectric layer.

[0013] In one embodiment, at least one of the first dielectric layer and the second dielectric layer comprises a multilayer structure.

[0014] In one embodiment, the semiconductor structure further includes a first semiconductor component and a second semiconductor component. The first semiconductor component is located on a side of the first bonding layer opposite to the second bonding layer in a first direction. The second semiconductor component is located on a side of the second bonding layer opposite to the first bonding layer in a first direction. The first semiconductor component includes a first memory cell array and / or a first peripheral circuit. The second semiconductor component includes a second memory cell array and / or a second peripheral circuit.

[0015] This disclosure also provides a method for manufacturing a semiconductor structure. The method includes: forming a first bonding layer, the first bonding layer including a first gap structure and a plurality of first bonding structures. The first gap structures are located between adjacent first bonding structures and include air gaps.

[0016] In one embodiment, the method further includes: forming a second bonding layer, the second bonding layer including a second bonding structure; and bonding the first bonding layer and the second bonding layer.

[0017] In one embodiment, forming a first bonding layer includes: forming a first dielectric layer and a first bonding structure penetrating the first dielectric layer in a first direction; and forming a first gap structure penetrating the first dielectric layer in the first direction. A plurality of first bonding structures are arranged in an array in a second direction and / or a third direction. The first gap structures are located between adjacent first bonding structures in the second direction and / or between adjacent first bonding structures in the third direction. The first direction, the second direction, and the third direction intersect each other.

[0018] In one embodiment, forming a second bonding layer includes: forming a second dielectric layer and a second bonding structure penetrating the second dielectric layer in a first direction; and forming a second gap structure in the second bonding layer penetrating the second dielectric layer in the first direction. A plurality of second bonding structures are arranged in an array in the second direction and / or a third direction. The second gap structures are located between adjacent second bonding structures in the second direction and / or between adjacent second bonding structures in the third direction.

[0019] In one embodiment, forming the first bonding layer includes: forming a first dielectric layer and a first bonding structure penetrating the first dielectric layer in a first direction; forming a gap penetrating the first dielectric layer in the first direction; and forming a first gap structure within the gap and a dielectric material surrounding the first gap structure. A plurality of first bonding structures are arranged in an array in a second direction and / or a third direction. The first gap structures are located between adjacent first bonding structures in the second direction and / or between adjacent first bonding structures in the third direction. The first direction, the second direction, and the third direction intersect each other.

[0020] In one embodiment, bonding the first bonding layer and the second bonding layer includes: bonding the second bonding structure to the first bonding structure. The second gap structure is spaced apart from or in contact with the first gap structure.

[0021] In one embodiment, the method further includes: forming a first interconnect layer, wherein a first bonding layer is located on one side of the first interconnect layer in a first direction and is connected to the first interconnect layer; and forming a second interconnect layer, wherein a second bonding layer is located on one side of the second interconnect layer in the first direction and is connected to the second interconnect layer. A first gap structure penetrates the first dielectric layer and extends to the first interconnect layer. A second gap structure penetrates the second dielectric layer and extends to the second interconnect layer.

[0022] In one embodiment, the method further includes: forming a first semiconductor component, wherein a first interconnect layer is located on one side of the first semiconductor component in a first direction; and forming a second semiconductor component, wherein a second interconnect layer is located on one side of the second semiconductor component in the first direction. The first semiconductor component includes a first memory cell array and / or a first peripheral circuit. The second semiconductor component includes a second memory cell array and / or a second peripheral circuit.

[0023] This disclosure also provides a storage system. The storage system includes a semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the semiconductor structure to store data. Attached Figure Description

[0024] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0025] Figure 1 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment of the present disclosure;

[0026] Figure 2 This is a partially enlarged schematic diagram of a semiconductor structure according to an exemplary embodiment of the present disclosure;

[0027] Figure 3This is a schematic diagram of the structure of a first gap structure according to an exemplary embodiment of the present disclosure;

[0028] Figure 4 This is a schematic diagram of the second gap structure according to an exemplary embodiment of the present disclosure;

[0029] Figure 5 This is a schematic diagram of the first gap structure according to another exemplary embodiment of the present disclosure;

[0030] Figure 6 This is a schematic diagram of a semiconductor structure according to another exemplary embodiment of the present disclosure;

[0031] Figure 7 This is a schematic diagram of a semiconductor structure according to yet another exemplary embodiment of the present disclosure;

[0032] Figure 8 This is a schematic diagram of a semiconductor structure according to yet another exemplary embodiment of the present disclosure;

[0033] Figure 9 yes Figure 8 A partially enlarged schematic diagram of the semiconductor structure in the image;

[0034] Figure 10 This is a schematic diagram of a semiconductor structure according to yet another exemplary embodiment of the present disclosure;

[0035] Figure 11 This is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure;

[0036] Figure 12 This is a schematic diagram of the structure forming a first bonding layer, a first interconnect layer, and a first semiconductor component according to an exemplary embodiment of the present disclosure;

[0037] Figure 13 This is a partially enlarged schematic diagram of the first bonding layer and the first interconnect layer;

[0038] Figure 14 This is a schematic diagram of the structure forming a second bonding layer, a second interconnect layer, and a second semiconductor component according to an exemplary embodiment of the present disclosure;

[0039] Figure 15 This is a partially enlarged schematic diagram of the second bonding layer and the second interconnect layer;

[0040] Figure 16 This is a schematic diagram of the structure forming a first bonding layer, a first interconnect layer, and a first semiconductor component according to another exemplary embodiment of this disclosure;

[0041] Figure 17This is a partially enlarged schematic diagram of the first bonding layer and the first interconnect layer;

[0042] Figure 18 This is a schematic diagram of the structure forming a second bonding layer, a second interconnect layer, and a second semiconductor component according to another exemplary embodiment of this disclosure;

[0043] Figure 19 This is a partially enlarged schematic diagram of the second bonding layer and the second interconnect layer;

[0044] Figure 20 This is an exemplary block diagram of a system having a storage system according to exemplary embodiments of the present disclosure; and

[0045] Figure 21A and Figure 21B This is a schematic diagram of a storage system according to an exemplary embodiment of the present disclosure.

[0046] Explanation of reference numerals in the attached figures:

[0047] Z, First direction; X, Second direction; Y, Third direction; 1000, 2000, 3000, 4000, 5000, Semiconductor structure; 1100, First bonding layer; 1110, First gap structure; 1120, First bonding structure; 1130, First dielectric layer; 1131, First sub-dielectric layer; 1132, Second sub-dielectric layer; 1140, First dielectric material; 1200, Second bonding layer; 1210, Second gap structure; 1220, Second bonding structure; 1230, Second dielectric layer; 1231, Third sub-dielectric layer; 1232, Fourth sub-dielectric layer; 1240, Second dielectric material; 1310, First sealing ring; 1320, Second sealing ring; 1400, First semiconductor component; 1500, Second semiconductor component; 1600, First interconnect layer; 1700, Second interconnect layer; 1610, 1710, Dielectric layers; 1620, 1720, Interconnect structure. Detailed Implementation

[0048] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way.

[0049] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this disclosure, the first bonding layer discussed herein may also be referred to as the second bonding layer, the first direction may also be referred to as the second direction, and vice versa.

[0050] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0051] Furthermore, in this text, when describing a part as being "on" another part, such as "on," "above," and "above," the meaning should be interpreted in the broadest possible sense, such that "on" not only means "directly on" something, but also includes the meaning of "on" something with intermediate features or layers in between. Moreover, "above" or "above" does not absolutely mean being above something with respect to the direction of gravity, nor does it only mean "on" something or "above" something, but can also include the meaning of "on" something or "above" something without intermediate features or layers in between (i.e., directly on) something.

[0052] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplarily" is intended to refer to an example or illustration.

[0053] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0054] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0055] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer can be a region of a homogeneous or non-homogeneous continuous structure, the height of which is less than the height of the continuous structure. For example, a layer can be located at or between the top and bottom surfaces of a continuous structure and any set of horizontal planes therebetween. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it.

[0056] Furthermore, in this disclosure, the use of “contact,” “connection,” or “linkage” may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0057] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0058] It should be noted that the first direction Z, the second direction X, and the third direction Y mentioned below may intersect each other (e.g., be perpendicular). The second direction X and the third direction Y may be two directions that intersect each other (e.g., be perpendicular) on a plane that intersects (e.g., are perpendicular to) the first direction Z.

[0059] Figure 1 This is a schematic diagram of the structure of a semiconductor structure 1000 according to an exemplary embodiment of the present disclosure.

[0060] like Figure 1 As shown, the semiconductor structure 1000 may include a first bonding layer 1100. The first bonding layer 1100 may include a first gap structure 1110 and a plurality of first bonding structures 1120. The first gap structure 1110 may be located between adjacent first bonding structures 1120. The first gap structure 1110 may include an air gap.

[0061] In this disclosure, the first bonding layer 1100 can be used to bond with other bonding layers (such as the second bonding layer 1200, which will be described in detail below). With the development of semiconductor technology, semiconductor structures are gradually becoming smaller, and their dimensions are decreasing. This disclosure, by including a first gap structure 1110 in the first bonding layer 1100, helps to reduce the parasitic capacitance between adjacent first bonding structures 1120.

[0062] Furthermore, as semiconductor structure performance improves and size shrinks, its process complexity may increase, and the density of multiple components, such as the first bonding structure 1120, may increase. Based on this, this disclosure, by providing a first gap structure 1110 between adjacent first bonding structures 1120, helps reduce the stress around the first bonding structure 1120, thereby reducing phenomena such as bonding misalignment caused by high stress. In addition, by providing the first gap structure 1110, this disclosure also facilitates the dissipation of heat from the first bonding layer 1100 through the first gap structure 1110, achieving heat dissipation and other purposes.

[0063] For example, such as Figure 1 As shown, the semiconductor structure 1000 may further include a second bonding layer 1200. The second bonding layer 1200 may be located on one side of the first bonding layer 1100 in the first direction Z, and may include a second bonding structure 1220 and a second gap structure 1210. The second bonding structure 1220 may be connected to the first bonding structure 1120. For example, the second bonding structure 1220 and the first bonding structure 1120 may be bonded together by a bonding process. The second gap structure 1210 may include an air gap.

[0064] It should be noted that the second gap structure 1210 may have the same or similar functions as the first gap structure 1110. To avoid redundancy, the functions of the second gap structure 1210 will not be described in detail here.

[0065] Figure 2 This is a partially enlarged schematic diagram of a semiconductor structure 1000 according to an exemplary embodiment of the present disclosure. Figure 3 This is a schematic diagram of the structure of the first gap structure 1110 according to an exemplary embodiment of the present disclosure. Figure 4 This is a schematic diagram of the structure of the second gap structure 1210 according to an exemplary embodiment of the present disclosure.

[0066] For example, such as Figure 1 or Figure 2 As shown, the first gap structure 1110 can contact the second gap structure 1210. In other words, the first gap structure 1110 and the second gap structure 1210 can be connected.

[0067] It should be noted that, Figure 1 and Figure 2The shown contact between the first gap structure 1110 and the second gap structure 1210 is merely an example and not a specific limitation. In actual processes, the structures of the first gap structure 1110 and the second gap structure 1210 can be reasonably configured according to actual conditions, so that the first gap structure 1110 and the second gap structure 1210 have at least one of the functions of reducing parasitic capacitance, reducing stress, and heat dissipation. For example, in another embodiment of this disclosure, the first gap structure 1110 may be spaced apart from the second gap structure 1210.

[0068] Exemplarily, a plurality of first bonding structures 1120 may be arrayed in the second direction X and / or the third direction Y. A first gap structure 1110 may be located between adjacent first bonding structures 1120 in the second direction X and / or the third direction Y. For example, in one embodiment of this disclosure, a plurality of first bonding structures 1120 may be arrayed in the second direction X. A first gap structure 1110 may be located between adjacent first bonding structures 1120 in the second direction X. In another embodiment of this disclosure, a plurality of first bonding structures 1120 may be arrayed in the third direction Y. A first gap structure 1110 may be located between adjacent first bonding structures 1120 in the third direction Y. In yet another embodiment of this disclosure, a plurality of first bonding structures 1120 may be arrayed in both the second direction X and the third direction Y. A first gap structure 1110 may be located between adjacent first bonding structures 1120 in the second direction X and / or the third direction Y. For example, as... Figure 3 As shown, a plurality of first bonding structures 1120 may be arranged in an array in the second direction X and the third direction Y. A first gap structure 1110 may be located between adjacent first bonding structures 1120 in the second direction X and between adjacent first bonding structures 1120 in the third direction Y.

[0069] Exemplarily, a plurality of second bonding structures 1220 may be arrayed in the second direction X and / or the third direction Y. A second gap structure 1210 may be located between adjacent second bonding structures 1220 in the second direction X and / or the third direction Y. For example, in one embodiment of this disclosure, a plurality of second bonding structures 1220 may be arrayed in the second direction X. A second gap structure 1210 may be located between adjacent second bonding structures 1220 in the second direction X. In another embodiment of this disclosure, a plurality of second bonding structures 1220 may be arrayed in the third direction Y. A second gap structure 1210 may be located between adjacent second bonding structures 1220 in the third direction Y. In yet another embodiment of this disclosure, a plurality of second bonding structures 1220 may be arrayed in both the second direction X and the third direction Y. A second gap structure 1210 may be located between adjacent second bonding structures 1220 in the second direction X and / or the third direction Y. For example, as... Figure 4As shown, a plurality of second bonding structures 1220 may be arranged in an array in the second direction X and the third direction Y. The second gap structure 1210 may be located between adjacent second bonding structures 1220 in the second direction X and between adjacent second bonding structures 1220 in the third direction Y.

[0070] Exemplarily, at least one of the first bonding structure 1120 and the second bonding structure 1220 may include a conductive material. For example, both the first bonding structure 1120 and the second bonding structure 1220 may include a conductive material. This conductive material includes, but is not limited to, tantalum, tantalum nitride, copper, tungsten, titanium, titanium nitride, aluminum, doped silicon, silicide, or any combination thereof. For example, both the first bonding structure 1120 and the second bonding structure 1220 may include copper and tantalum nitride surrounding the copper.

[0071] Exemplarily, at least one of the first bonding structure 1120 and the second bonding structure 1220 may include a damask structure. For example, at least one of the first bonding structure 1120 and the second bonding structure 1220 may include a single damask structure or a double damask structure. For example, as Figure 2 As shown, both the first bonding structure 1120 and the second bonding structure 1220 can include a double damask structure. It should be understood that the structures of the first bonding structure 1120 and the second bonding structure 1220 shown in this disclosure are merely examples and not specific limitations.

[0072] For example, such as Figure 3 and Figure 4 As shown, the first gap structure 1110 may have the same structure as the second gap structure 1210. For example, the first gap structure 1110 and the second gap structure 1210 may be symmetrically arranged in the first direction Z.

[0073] It should be noted that the phrase "the first gap structure 1110 and the second gap structure 1210 have the same structure" as defined in this disclosure refers to the characteristics of the first gap structure 1110 and the second gap structure 1210 set during the product or process design stage. It should be understood that, due to limitations in actual manufacturing processes, the structure of the first gap structure 1110 and the structure of the second gap structure 1210 in actual manufacturing may deviate from the design value to a certain extent. This error range may be due to minor variations in manufacturing processes or tolerances, and therefore, this error range is also within the protection scope of this disclosure. For example, this error range may vary within 10% to 30% (e.g., ±10%, ±20%, or ±30%).

[0074] Figure 5 This is a schematic diagram of the structure of a first gap structure 1110 according to another exemplary embodiment of the present disclosure. Exemplarily, the first gap structure 1110 may include a strip-shaped structure and / or a curved structure. For example, such as... Figure 3As shown, the first gap structure 1110 may include a strip-shaped structure. For example... Figure 5 As shown, the first gap structure 1110 may include a curved structure. It should be understood that the second gap structure 1210 may also include a strip structure and / or a curved structure.

[0075] It should be noted that, Figure 3 and Figure 5 The structure of the first gap structure 1110 shown is merely an example and not a specific limitation. In actual manufacturing processes, the structure of the first gap structure 1110 can be reasonably configured according to actual conditions so that the first gap structure 1110 has at least one of the functions of reducing parasitic capacitance, reducing stress, and heat dissipation. Similarly, this disclosure does not specifically limit the structure of the second gap structure 1210.

[0076] For example, the first gap structure 1110 may be spaced apart from or in contact with the first bonding structure 1120. For instance, as... Figure 3 As shown, the first gap structure 1110 can be spaced apart from the first bonding structure 1120. For example... Figure 5 As shown, the first gap structure 1110 can contact the first bonding structure 1120. In other words, the first gap structure 1110 can expose a portion of the first bonding structure 1120. For example, as... Figure 3 or Figure 5 As shown, the first gap structure 1110 can be a continuous structure, such as a continuous channel, to carry away heat from the first bonding layer 1100 and improve heat dissipation. Similarly, the second gap structure 1210 can be spaced apart from or in contact with the second bonding structure 1220.

[0077] For example, such as Figure 1 and Figure 2 As shown, the first bonding layer 1100 may further include a first dielectric layer 1130. The second bonding layer 1200 may further include a second dielectric layer 1230 connected to the first dielectric layer 1130. For example, the first dielectric layer 1130 and the second dielectric layer 1230 can be bonded together by a bonding process. Exemplarily, at least a portion of the first bonding structure 1120 and the first gap structure 1110 may be located within the first dielectric layer 1130. At least a portion of the second bonding structure 1220 and the second gap structure 1210 may be located within the second dielectric layer 1230.

[0078] For example, such as Figure 2As shown, the first bonding structure 1120 extends through the first dielectric layer 1130 in the first direction Z and extends into the interconnect structure 1620 in the first interconnect layer 1600 (described in detail below). The first gap structure 1110 extends through the first dielectric layer 1130 in the first direction Z and extends into the dielectric layer 1610 in the first interconnect layer 1600. The second bonding structure 1220 extends through the second dielectric layer 1230 in the first direction Z and extends into the interconnect structure 1720 in the second interconnect layer 1700 (described in detail below). The second gap structure 1210 extends through the second dielectric layer 1230 in the first direction Z and extends into the dielectric layer 1710 in the second interconnect layer 1700.

[0079] Exemplarily, at least one of the first dielectric layer 1130 and the second dielectric layer 1230 includes a multilayer structure. For example, both the first dielectric layer 1130 and the second dielectric layer 1230 may include a multilayer structure. For example, the first dielectric layer 1130 may include a first sub-dielectric layer 1131 and a second sub-dielectric layer 1132 arranged sequentially in the first direction Z. The second dielectric layer 1230 may include a third sub-dielectric layer 1231 and a fourth sub-dielectric layer 1232 arranged sequentially in the first direction Z. The second sub-dielectric layer 1132 may be connected to the fourth sub-dielectric layer 1232. In other words, the first sub-dielectric layer 1131 may be located on the side opposite to the second sub-dielectric layer 1132. The third sub-dielectric layer 1231 may be located on the side of the fourth sub-dielectric layer 1232 opposite to the second sub-dielectric layer 1132.

[0080] Exemplarily, the first sub-dielectric layer 1131 and the third sub-dielectric layer 1231 may include an insulating material such as silicon oxide to space the plurality of first bonding structures 1120 and / or the plurality of second bonding structures 1220. The second sub-dielectric layer 1132 and the fourth sub-dielectric layer 1232 may include carbon-containing silicides. For example, both the second sub-dielectric layer 1132 and the fourth sub-dielectric layer 1232 may include carbon-containing silicides such as carbon-containing silicon nitride to block metal diffusion in the first bonding structure 1120 and the second bonding structure 1220, thereby improving the stability of the semiconductor structure and extending the electromigration lifetime of the semiconductor structure.

[0081] For example, such as Figure 1As shown, the semiconductor structure 1000 may further include a first semiconductor component 1400 and a second semiconductor component 1500. The first semiconductor component 1400 may be located on the side of the first bonding layer 1100 facing away from the second bonding layer 1200 in the first direction Z. The second semiconductor component 1500 may be located on the side of the second bonding layer 1200 facing away from the first bonding layer 1100 in the first direction Z. The second semiconductor component 1500 can be connected to the first semiconductor component 1400 through the second bonding layer 1200 and the first bonding layer 1100. Exemplarily, the first semiconductor component 1400 may include a first memory cell array and / or a first peripheral circuit. The second semiconductor component 1500 may include a second memory cell array and / or a second peripheral circuit.

[0082] The first and second memory cell arrays may include any suitable memory cell with storage function, such as NAND flash memory string cells, embedded DRAM memory cells (including transistors and capacitors), etc. A NAND flash memory string cell may include a source, a drain, and multiple memory cells at intersections with multiple memory layers and between the source and drain. A DRAM memory cell may include a capacitor for storing data bits as positive or negative charges and one or more transistors (also called transfer transistors) for controlling (e.g., switching and selecting) access to the memory cell.

[0083] The first and second peripheral circuits may be referred to as control and sensing circuits and may include any suitable digital, analog, and / or mixed-signal circuitry used to facilitate the operation of the memory cell array. For example, the peripheral circuitry may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., peripheral transistors, diodes, resistors, or capacitors).

[0084] In one embodiment of this disclosure, the first semiconductor component 1400 may include a first memory cell array. The second semiconductor component 1500 may include a second memory cell array. The first memory cell array and the second memory cell array can be connected through a second bonding layer 1200 and a first bonding layer 1100. In another embodiment of this disclosure, the first semiconductor component 1400 may include a first memory cell array. The second semiconductor component 1500 may include a second peripheral circuit. The first memory cell array and the second peripheral circuit can be connected through a second bonding layer 1200 and a first bonding layer 1100. In yet another embodiment of this disclosure, the first semiconductor component 1400 may include a first peripheral circuit. The second semiconductor component 1500 may include a second memory cell array. The first peripheral circuit and the second memory cell array can be connected through a second bonding layer 1200 and a first bonding layer 1100. In yet another embodiment of this disclosure, the first semiconductor component 1400 may include a first peripheral circuit. The second semiconductor component 1500 may include a second peripheral circuit. The first peripheral circuit and the second peripheral circuit can be connected through a second bonding layer 1200 and a first bonding layer 1100. In another embodiment of this disclosure, the first semiconductor component 1400 may include a first memory cell array and a first peripheral circuit. The second semiconductor component 1500 may include a second memory cell array and a second peripheral circuit. For example, the first semiconductor component 1400 may be a die comprising a memory cell array and peripheral circuitry coupled to the memory cell array; similarly, the second semiconductor component 1500 may be a die. Different dies may be connected via a second bonding layer 1200 and a first bonding layer 1100.

[0085] For example, such as Figure 1 and Figure 2As shown, the semiconductor structure 1000 may further include a first interconnect layer 1600 and a second interconnect layer 1700. The first interconnect layer 1600 may be located between the first semiconductor component 1400 and the first bonding layer 1100. The second interconnect layer 1700 may be located between the second semiconductor component 1500 and the second bonding layer 1200. The first interconnect layer 1600 may include a plurality of dielectric layers such as dielectric layer 1610, and interconnect structures (also referred to as "contact structures," such as interconnect structure 1620) in the plurality of dielectric layers such as dielectric layer 1610, wherein the interconnect structures may include lateral interconnects and interconnect contacts. The second interconnect layer 1700 may include a plurality of dielectric layers such as dielectric layer 1710, and interconnect structures (also referred to as "contact structures," such as interconnect structure 1720) in the plurality of dielectric layers such as dielectric layer 1710, wherein the interconnect structures may include lateral interconnects and interconnect contacts. Exemplarily, the first bonding structure 1120 may be connected to the interconnect structure 1620 in the first interconnect layer 1600. The first gap structure 1110 can extend into the dielectric layer 1610 in the first interconnect layer 1600. The second bonding structure 1220 can be connected to the interconnect structure 1720 in the second interconnect layer 1700. The second gap structure 1210 can extend into the dielectric layer 1710 in the second interconnect layer 1700.

[0086] For example, the materials of interconnect structures such as interconnect structure 1620 and interconnect structure 1720 in the first interconnect layer 1600 and the second interconnect layer 1700 may include conductive materials, such as, but not limited to, tungsten, copper, aluminum, doped silicon, silicide, or any combination thereof. The materials of dielectric layers such as dielectric layer 1610 and dielectric layer 1710 in the first interconnect layer 1600 and the second interconnect layer 1700 may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant material layers, or any combination thereof.

[0087] For example, such as Figure 3 or Figure 4 As shown, the semiconductor structure 1000 may further include a sealing ring, such as a first sealing ring 1310, surrounding the first bonding layer 1100. The semiconductor structure 1000 may also include a sealing ring, such as a second sealing ring 1320, surrounding the second bonding layer 1200.

[0088] In semiconductor device layout design, a sealing ring (SR) is typically placed around the device area of ​​the semiconductor structure. The sealing ring is spaced at a certain distance from the semiconductor device to effectively separate the edges of the semiconductor device, reducing mechanical damage from dicing processes and moisture intrusion. For example, in this disclosure, the first sealing ring 1310 may circumferentially surround the first bonding layer 1100, the first interconnect layer 1600, and the first semiconductor component 1400. The second sealing ring 1320 may circumferentially surround the second bonding layer 1200, the second interconnect layer 1700, and the second semiconductor component 1500.

[0089] It should be noted that the first sealing ring 1310 surrounding the first bonding layer 1100, the first interconnect layer 1600, and the first semiconductor component 1400 in this disclosure refers to surrounding the sides of the first bonding layer 1100, the first interconnect layer 1600, and the first semiconductor component 1400, and does not involve covering the top surface of the first bonding layer 1100, the first interconnect layer 1600, and the first semiconductor component 1400. The first sealing ring 1310 may not be in direct contact with the first bonding layer 1100, the first interconnect layer 1600, and the first semiconductor component 1400. Similarly, the second sealing ring 1320 surrounding the second bonding layer 1200, the second interconnect layer 1700, and the second semiconductor component 1500 refers to surrounding the sides of the second bonding layer 1200, the second interconnect layer 1700, and the second semiconductor component 1500, and does not involve covering the top surfaces of the second bonding layer 1200, the second interconnect layer 1700, and the second semiconductor component 1500. The second sealing ring 1320 may not be in direct contact with the second bonding layer 1200, the second interconnect layer 1700, and the second semiconductor component 1500.

[0090] Exemplarily, the shapes of the first sealing ring 1310 and the second sealing ring 1320 may include at least one of annular groove and annular column. The first sealing ring 1310 and the second sealing ring 1320 may be made of conductive materials including, but not limited to, copper, aluminum, nickel, tungsten, silver, gold, and titanium. In an exemplary embodiment of this disclosure, as... Figure 3 and Figure 4 As shown, both the first sealing ring 1310 and the second sealing ring 1320 can include an annular groove shape, meaning both the first sealing ring 1310 and the second sealing ring 1320 can include a metal wall. In another exemplary embodiment of this disclosure, the first sealing ring 1310 and the second sealing ring 1320 can include an annular column shape, meaning both the first sealing ring 1310 and the second sealing ring 1320 can include a metal column. It should be understood that, compared to a metal column, a metal wall can provide improved reinforcement strength and improved protection against moisture and mobile ion contaminants.

[0091] For example, such as Figure 3 or Figure 5 As shown, the first gap structure 1110 may contact a sealing ring, such as the first sealing ring 1310. For example, the first gap structure 1110 may extend along a second direction X or a third direction Y to the first sealing ring 1310, so that heat in the first bonding layer 1100 can diffuse to the outside via the first gap structure 1110 and the first sealing ring 1310. Exemplarily, as... Figure 4 As shown, the second gap structure 1210 may contact the second sealing ring 1320. For example, the second gap structure 1210 may extend to the second sealing ring 1320 along the second direction X or the third direction Y, so that heat in the second bonding layer 1200 can be diffused to the outside through the second gap structure 1210 and the second sealing ring 1320.

[0092] Figure 6 This is a schematic diagram of a semiconductor structure 2000 according to another exemplary embodiment of the present disclosure. In this embodiment, for the sake of brevity, the omitted parts are... Figures 1 to 5 The embodiments shown are described similarly.

[0093] like Figure 6 As shown, the semiconductor structure 2000 may include a first bonding layer 1100 and a second bonding layer 1200 bonded together. The first bonding layer 1100 may include a first gap structure 1110. The first gap structure 1110 may include an air gap. In this embodiment, the first bonding layer 1100 may have an air gap, while the second bonding layer 1200 may not have an air gap.

[0094] Figure 7 This is a schematic diagram of a semiconductor structure 3000 according to yet another exemplary embodiment of the present disclosure. In this embodiment, for the sake of brevity, omitted parts are... Figures 1 to 5 The embodiments shown are described similarly.

[0095] like Figure 7 As shown, the semiconductor structure 3000 may include a first bonding layer 1100 and a second bonding layer 1200 bonded together. The first bonding layer 1100 may include a first gap structure 1110. The second bonding layer 1200 may include a second gap structure 1210. Both the first gap structure 1110 and the second gap structure 1210 may include an air gap.

[0096] For example, such as Figure 7 As shown, the first gap structure 1110 and the second gap structure 1210 may have different structures. For example, the first gap structure 1110 and the second gap structure 1210 may be asymmetrical in the first direction Z.

[0097] It should be noted that the structural limitations of the first gap structure 1110 and the second gap structure 1210 in this disclosure are merely examples and not specific limitations. In actual processes, the structures of the first gap structure 1110 and the second gap structure 1210 can be reasonably configured according to specific circumstances to meet actual requirements. For example, the first gap structure 1110 and the second gap structure 1210 can be configured to have the same structure, or they can be configured to have different structures. This disclosure does not impose specific limitations in this regard.

[0098] Figure 8 This is a schematic diagram of a semiconductor structure 4000 according to yet another exemplary embodiment of the present disclosure. Figure 9 yes Figure 8 A partially enlarged schematic diagram of the semiconductor structure 4000 is shown. In this embodiment, for simplicity, the omitted parts are... Figures 1 to 5 The embodiments shown are described similarly.

[0099] like Figure 8 or Figure 9 As shown, the first bonding layer 1100 may further include a dielectric material, such as a first dielectric material 1140, surrounding the first gap structure 1110. The second bonding layer 1200 may further include a dielectric material, such as a second dielectric material 1240, surrounding the second gap structure 1210. The first gap structure 1110 and the second gap structure 1210 may be spaced apart by the first dielectric material 1140 and the second dielectric material 1240.

[0100] The first dielectric material 1140 and the second dielectric material 1240 may be bonded together by a bonding process. The first dielectric material 1140 and the second dielectric material 1240 may comprise the same material. For example, the first dielectric material 1140 and the second dielectric material 1240 may comprise an insulating material such as silicon oxide.

[0101] Figure 10 This is a schematic diagram of a semiconductor structure 5000 according to yet another exemplary embodiment of the present disclosure. In this embodiment, for the sake of brevity, omitted parts are... Figure 9 The embodiments shown are described similarly.

[0102] like Figure 10 As shown, the first bonding layer 1100 may include a first gap structure 1110 and a dielectric material, such as a first dielectric material 1140, surrounding the first gap structure 1110. The first gap structure 1110 may include an air gap. In this embodiment, the first bonding layer 1100 may have an air gap, and the second bonding layer 1200 may not have a second dielectric material 1240 and a second gap structure 1210, such as an air gap.

[0103] Figure 11 This is a flowchart of a method 6000 for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0104] like Figure 11 As shown, the method 6000 for manufacturing a semiconductor structure may include: S6100, forming a first bonding layer, the first bonding layer including a first gap structure and a plurality of first bonding structures; and S6200, performing a bonding process on the first bonding layer. Steps S6100 and S6200 will be described in detail below.

[0105] Figure 12 This is a schematic diagram of the structure forming a first bonding layer 1100, a first interconnect layer 1600 and a first semiconductor component 1400 according to an exemplary embodiment of the present disclosure. Figure 13 This is a partially enlarged schematic diagram of the first bonding layer 1100 and the first interconnect layer 1600. Figure 14 This is a schematic diagram of the structure forming a second bonding layer 1200, a second interconnect layer 1700, and a second semiconductor component 1500 according to an exemplary embodiment of the present disclosure. Figure 15 This is a partially enlarged schematic diagram of the second bonding layer 1200 and the second interconnect layer 1700.

[0106] For example, such as Figure 12 As shown, a first bonding layer 1100 may be formed. For example, a first semiconductor component 1400 may be formed; a first interconnect layer 1600 may be formed on one side of the first semiconductor component 1400 along the first direction Z; and the first bonding layer 1100 may be formed on the side of the first interconnect layer 1600 opposite to the first semiconductor component 1400. In other words, the first interconnect layer 1600 may be located on one side of the first semiconductor component 1400 along the first direction Z and may be connected to the first semiconductor component 1400. The first bonding layer 1100 may be located on one side of the first interconnect layer 1600 along the first direction Z and may be connected to the first interconnect layer 1600. The first semiconductor component 1400 may include a first memory cell array or a first peripheral circuit.

[0107] like Figure 12 and Figure 13 As shown, the first bonding layer 1100 may include a first gap structure 1110 and a plurality of first bonding structures 1120. The first gap structure 1110 may be located between adjacent first bonding structures 1120. The first gap structure 1110 may include an air gap.

[0108] In this disclosure, the first bonding layer 1100 can be used to bond with other bonding layers (such as the second bonding layer 1200, which will be described in detail below). With the development of semiconductor technology, semiconductor structures are gradually becoming smaller, and their dimensions are decreasing. This disclosure, by including a first gap structure 1110 in the first bonding layer 1100, helps to reduce the parasitic capacitance between adjacent first bonding structures 1120.

[0109] Furthermore, as semiconductor structure performance improves and size shrinks, its process complexity may increase, and the density of multiple components, such as the first bonding structure 1120, may increase. Based on this, this disclosure, by providing a first gap structure 1110 between adjacent first bonding structures 1120, helps reduce the stress around the first bonding structure 1120, thereby reducing phenomena such as bonding misalignment caused by high stress. In addition, by providing the first gap structure 1110, this disclosure also facilitates the dissipation of heat from the first bonding layer 1100 through the first gap structure 1110, achieving heat dissipation and other purposes.

[0110] For example, such as Figure 14 As shown, a second bonding layer 1200 may be formed. For example, a second semiconductor component 1500 may be formed; a second interconnect layer 1700 may be formed on one side of the second semiconductor component 1500 along the first direction Z; and the second bonding layer 1200 may be formed on the side of the second interconnect layer 1700 opposite to the second semiconductor component 1500. In other words, the second interconnect layer 1700 may be located on one side of the second semiconductor component 1500 along the first direction Z and may be connected to the second semiconductor component 1500. The second bonding layer 1200 may be located on one side of the second interconnect layer 1700 along the first direction Z and may be connected to the second interconnect layer 1700. The second semiconductor component 1500 includes a second memory cell array or a second peripheral circuit.

[0111] like Figure 14 and Figure 15 As shown, the second bonding layer 1200 may include a second gap structure 1210 and a plurality of second bonding structures 1220. The second gap structure 1210 may be located between adjacent second bonding structures 1220. The second gap structure 1210 may include an air gap. The second bonding layer 1200 may be used to bond with other bonding layers (such as the first bonding layer 1100).

[0112] It should be noted that the second gap structure 1210 may have the same or similar functions as the first gap structure 1110. To avoid redundancy, the functions of the second gap structure 1210 will not be described in detail here.

[0113] The first and second memory cell arrays may include any suitable memory cell with storage function, such as NAND flash memory string cells, embedded DRAM memory cells (including transistors and capacitors), etc. A NAND flash memory string cell may include a source, a drain, and multiple memory cells at intersections with multiple memory layers and between the source and drain. A DRAM memory cell may include a capacitor for storing data bits as positive or negative charges and one or more transistors (also called transfer transistors) for controlling (e.g., switching and selecting) access to the memory cell.

[0114] The first and second peripheral circuits may be referred to as control and sensing circuits and may include any suitable digital, analog, and / or mixed-signal circuitry used to facilitate the operation of the memory cell array. For example, the peripheral circuitry may include one or more of the following: page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion (e.g., sub-circuits) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., peripheral transistors, diodes, resistors, or capacitors).

[0115] In one embodiment of this disclosure, the first semiconductor component 1400 may include a first memory cell array. The second semiconductor component 1500 may include a second memory cell array. After subsequent bonding of the second bonding layer 1200 and the first bonding layer 1100, the first memory cell array and the second memory cell array can be connected through the second bonding layer 1200 and the first bonding layer 1100. In another embodiment of this disclosure, the first semiconductor component 1400 may include a first memory cell array. The second semiconductor component 1500 may include a second peripheral circuit. After subsequent bonding of the second bonding layer 1200 and the first bonding layer 1100, the first memory cell array and the second peripheral circuit can be connected through the second bonding layer 1200 and the first bonding layer 1100. In yet another embodiment of this disclosure, the first semiconductor component 1400 may include a first peripheral circuit. The second semiconductor component 1500 may include a second memory cell array. After subsequent bonding of the second bonding layer 1200 and the first bonding layer 1100, the first peripheral circuit and the second memory cell array can be connected through the second bonding layer 1200 and the first bonding layer 1100. In another embodiment of this disclosure, the first semiconductor component 1400 may include a first peripheral circuit. The second semiconductor component 1500 may include a second peripheral circuit. After subsequent bonding of the second bonding layer 1200 and the first bonding layer 1100, the first peripheral circuit and the second peripheral circuit can be connected through the second bonding layer 1200 and the first bonding layer 1100. In yet another embodiment of this disclosure, the first semiconductor component 1400 may include a first memory cell array and a first peripheral circuit. The second semiconductor component 1500 may include a second memory cell array and a second peripheral circuit. For example, the first semiconductor component 1400 may be a die, which includes a memory cell array and peripheral circuits coupled to the memory cell array; similarly, the second semiconductor component 1500 may be a die. Different dies can be connected through the second bonding layer 1200 and the first bonding layer 1100.

[0116] The first interconnect layer 1600 may include multiple dielectric layers such as dielectric layer 1610, and interconnect structures (also referred to as "contact structures," such as interconnect structure 1620) in the multiple dielectric layers such as dielectric layer 1610, wherein the interconnect structures may include lateral interconnects and interconnect contacts. The second interconnect layer 1700 may include multiple dielectric layers such as dielectric layer 1710, and interconnect structures (also referred to as "contact structures," such as interconnect structure 1720) in the multiple dielectric layers such as dielectric layer 1710, wherein the interconnect structures may include lateral interconnects and interconnect contacts. Exemplarily, a first bonding structure 1120 may be connected to the interconnect structure 1620 in the first interconnect layer 1600. A first gap structure 1110 may extend into the dielectric layer 1610 in the first interconnect layer 1600. A second bonding structure 1220 may be connected to the interconnect structure 1720 in the second interconnect layer 1700. A second gap structure 1210 may extend into the dielectric layer 1710 in the second interconnect layer 1700.

[0117] For example, the materials of interconnect structures such as interconnect structure 1620 and interconnect structure 1720 in the first interconnect layer 1600 and the second interconnect layer 1700 may include conductive materials, such as, but not limited to, tungsten, copper, aluminum, doped silicon, silicide, or any combination thereof. The materials of dielectric layers such as dielectric layer 1610 and dielectric layer 1710 in the first interconnect layer 1600 and the second interconnect layer 1700 may include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant material layers, or any combination thereof.

[0118] For example, such as Figure 12 and Figure 13 As shown, forming the first bonding layer 1100 may include: forming a first dielectric layer 1130 on one side of the first interconnect layer 1600 along the first direction Z; forming a first bonding structure 1120 that penetrates the first dielectric layer 1130 and extends into the first interconnect layer 1600 in the first direction Z; and forming a first gap structure 1110 that penetrates the first dielectric layer 1130 and extends into the first interconnect layer 1600 in the first direction Z.

[0119] For example, forming the first bonding structure 1120 may include: forming a via (not shown) that penetrates the first dielectric layer 1130 and extends into the interconnect structure 1620 in the first interconnect layer 1600 in the first direction Z; and forming the first bonding structure 1120 within the via. For example, the via may be formed using a dry etching process, a wet etching process, or a combination of dry and wet etching processes. The first bonding structure 1120 may be formed using one or more thin film deposition processes.

[0120] For example, the first bonding structure 1120 can be formed using a damascus process. Figure 12 or Figure 13 As shown, the first bonding structure 1120 formed using the damascus process can have a structure that is wider at the top and narrower at the bottom. For example, a smaller bottom via and a larger top via (not shown) can be formed using two photomasks and two photolithography and etching processes; and the first bonding structure 1120 can be formed within the bottom via and the top via.

[0121] Exemplarily, the first bonding structure 1120 may include a conductive material. For example, the first bonding structure 1120 may include a conductive material. This conductive material includes, but is not limited to, tantalum, tantalum nitride, copper, tungsten, titanium, titanium nitride, aluminum, doped silicon, silicide, or any combination thereof. For example, the first bonding structure 1120 may include copper and tantalum nitride surrounding the copper.

[0122] For example, the first dielectric layer 1130 may include a multilayer structure. For instance, the first dielectric layer 1130 may include a first sub-dielectric layer 1131 and a second sub-dielectric layer 1132 arranged sequentially in the first direction Z. The second sub-dielectric layer 1132 may be located on the side of the first sub-dielectric layer 1131 opposite to the first interconnect layer 1600.

[0123] Exemplarily, the first sub-dielectric layer 1131 may include an insulating material such as silicon oxide to space the plurality of first bonding structures 1120. The second sub-dielectric layer 1132 may include a carbon-containing silicide. For example, the second sub-dielectric layer 1132 may include a carbon-containing silicide such as carbon-containing silicon nitride to block metal diffusion in the first bonding structures 1120, improve the stability of the semiconductor structure, and extend the electromigration lifetime of the semiconductor structure.

[0124] Exemplarily, the first sub-dielectric layer 1131 may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Exemplarily, the second sub-dielectric layer 1132 may be formed by one or more thin film deposition processes and / or doping processes.

[0125] Exemplarily, a plurality of first bonding structures 1120 may be arrayed in the second direction X and / or the third direction Y. A first gap structure 1110 may be located between adjacent first bonding structures 1120 in the second direction X and / or the third direction Y. For example, in one embodiment of this disclosure, a plurality of first bonding structures 1120 may be arrayed in the second direction X. A first gap structure 1110 may be located between adjacent first bonding structures 1120 in the second direction X. In another embodiment of this disclosure, a plurality of first bonding structures 1120 may be arrayed in the third direction Y. A first gap structure 1110 may be located between adjacent first bonding structures 1120 in the third direction Y. In yet another embodiment of this disclosure, a plurality of first bonding structures 1120 may be arrayed in both the second direction X and the third direction Y. A first gap structure 1110 may be located between adjacent first bonding structures 1120 in the second direction X and / or the third direction Y. For example, as... Figure 3 As shown, a plurality of first bonding structures 1120 may be arranged in an array in the second direction X and the third direction Y. A first gap structure 1110 may be located between adjacent first bonding structures 1120 in the second direction X and between adjacent first bonding structures 1120 in the third direction Y.

[0126] Exemplarily, the first gap structure 1110 may include a strip-shaped structure and / or a curved structure. For example, such as... Figure 3 As shown, the first gap structure 1110 may include a strip-shaped structure. For example... Figure 5 As shown, the first gap structure 1110 may include a curved structure.

[0127] It should be noted that, Figure 3 and Figure 5 The structure of the first gap structure 1110 shown is merely an example and not a specific limitation. In actual processes, the structure of the first gap structure 1110 can be reasonably set according to the actual situation so that the first gap structure 1110 has at least one of the functions of reducing parasitic capacitance, reducing stress, and heat dissipation.

[0128] For example, the first gap structure 1110 may be spaced apart from or in contact with the first bonding structure 1120. For instance, as... Figure 3 As shown, the first gap structure 1110 can be spaced apart from the first bonding structure 1120. For example... Figure 5 As shown, the first gap structure 1110 can contact the first bonding structure 1120. In other words, the first gap structure 1110 can expose a portion of the first bonding structure 1120. For example, as... Figure 3 or Figure 5 As shown, the first gap structure 1110 can be a continuous structure, such as a continuous channel, to carry away the heat in the first bonding layer 1100 and improve the heat dissipation effect.

[0129] For example, such as Figure 14 and Figure 15 As shown, forming the second bonding layer 1200 may include: forming a second dielectric layer 1230 on one side of the second interconnect layer 1700 along the first direction Z; forming a second bonding structure 1220 that penetrates the second dielectric layer 1230 in the first direction Z and extends into the interconnect structure 1720 in the second interconnect layer 1700; and forming a second gap structure 1210 that penetrates the second dielectric layer 1230 in the first direction Z and extends into the dielectric layer 1710 in the second interconnect layer 1700.

[0130] It should be noted that the material and forming process of the second bonding structure 1220 are similar to those of the first bonding structure 1120. To avoid redundancy, these will not be described in detail here. The structure and forming process of the second gap structure 1210 are similar to those of the first gap structure 1110. To avoid redundancy, these will not be described in detail here.

[0131] Furthermore, the materials and formation processes of the second dielectric layer 1230 are similar to those of the first dielectric layer 1130, and to avoid redundancy, they will not be described in detail here. For example, the second dielectric layer 1230 may include a multilayer structure. For example, the second dielectric layer 1230 may include a third sub-dielectric layer 1231 and a fourth sub-dielectric layer 1232 arranged sequentially in the first direction Z. The fourth sub-dielectric layer 1232 may be located on the side of the third sub-dielectric layer 1231 opposite to the second interconnect layer 1700.

[0132] Exemplarily, a plurality of second bonding structures 1220 may be arrayed in the second direction X and / or the third direction Y. A second gap structure 1210 may be located between adjacent second bonding structures 1220 in the second direction X and / or the third direction Y. For example, in one embodiment of this disclosure, a plurality of second bonding structures 1220 may be arrayed in the second direction X. A second gap structure 1210 may be located between adjacent second bonding structures 1220 in the second direction X. In another embodiment of this disclosure, a plurality of second bonding structures 1220 may be arrayed in the third direction Y. A second gap structure 1210 may be located between adjacent second bonding structures 1220 in the third direction Y. In yet another embodiment of this disclosure, a plurality of second bonding structures 1220 may be arrayed in both the second direction X and the third direction Y. A second gap structure 1210 may be located between adjacent second bonding structures 1220 in the second direction X and / or the third direction Y. For example, as... Figure 4 As shown, a plurality of second bonding structures 1220 may be arranged in an array in the second direction X and the third direction Y. The second gap structure 1210 may be located between adjacent second bonding structures 1220 in the second direction X and between adjacent second bonding structures 1220 in the third direction Y.

[0133] Exemplarily, at least one of the first bonding structure 1120 and the second bonding structure 1220 may include a damask structure. For example, at least one of the first bonding structure 1120 and the second bonding structure 1220 may include a single damask structure or a double damask structure. For example, as Figure 2 As shown, both the first bonding structure 1120 and the second bonding structure 1220 can include a double damask structure. It should be understood that the structures of the first bonding structure 1120 and the second bonding structure 1220 shown in this disclosure are merely examples and not specific limitations.

[0134] For example, such as Figure 3 or Figure 5 As shown, a sealing ring such as a first sealing ring 1310 may also be formed around the first bonding layer 1100; and a sealing ring such as a second sealing ring 1320 may be formed around the second bonding layer 1200.

[0135] In semiconductor device layout design, a sealing ring (SR) is typically placed around the device area of ​​the semiconductor structure. The sealing ring is spaced at a certain distance from the semiconductor device to effectively separate the edges of the semiconductor device, reducing mechanical damage from dicing processes and moisture intrusion. For example, in this disclosure, the first sealing ring 1310 may circumferentially surround the first bonding layer 1100, the first interconnect layer 1600, and the first semiconductor component 1400. The second sealing ring 1320 may circumferentially surround the second bonding layer 1200, the second interconnect layer 1700, and the second semiconductor component 1500.

[0136] It should be noted that the first sealing ring 1310 surrounding the first bonding layer 1100, the first interconnect layer 1600, and the first semiconductor component 1400 in this disclosure refers to surrounding the sides of the first bonding layer 1100, the first interconnect layer 1600, and the first semiconductor component 1400, and does not involve covering the top surface of the first bonding layer 1100, the first interconnect layer 1600, and the first semiconductor component 1400. The first sealing ring 1310 may not be in direct contact with the first bonding layer 1100, the first interconnect layer 1600, and the first semiconductor component 1400. Similarly, the second sealing ring 1320 surrounding the second bonding layer 1200, the second interconnect layer 1700, and the second semiconductor component 1500 refers to surrounding the sides of the second bonding layer 1200, the second interconnect layer 1700, and the second semiconductor component 1500, and does not involve covering the top surfaces of the second bonding layer 1200, the second interconnect layer 1700, and the second semiconductor component 1500. The second sealing ring 1320 may not be in direct contact with the second bonding layer 1200, the second interconnect layer 1700, and the second semiconductor component 1500.

[0137] Exemplarily, the shapes of the first sealing ring 1310 and the second sealing ring 1320 may include at least one of annular groove and annular column. The first sealing ring 1310 and the second sealing ring 1320 may be made of conductive materials including, but not limited to, copper, aluminum, nickel, tungsten, silver, gold, and titanium. In an exemplary embodiment of this disclosure, as... Figure 3 and Figure 4 As shown, both the first sealing ring 1310 and the second sealing ring 1320 can include an annular groove shape, meaning both the first sealing ring 1310 and the second sealing ring 1320 can include a metal wall. In another exemplary embodiment of this disclosure, the first sealing ring 1310 and the second sealing ring 1320 can include an annular column shape, meaning both the first sealing ring 1310 and the second sealing ring 1320 can include a metal column. It should be understood that, compared to a metal column, a metal wall can provide improved reinforcement strength and improved protection against moisture and mobile ion contaminants.

[0138] For example, such as Figure 3 or Figure 5 As shown, the first gap structure 1110 may contact a sealing ring, such as the first sealing ring 1310. For example, the first gap structure 1110 may extend along a second direction X or a third direction Y to the first sealing ring 1310, so that heat in the first bonding layer 1100 can be diffused to the outside via the first gap structure 1110 and the first sealing ring 1310. Exemplarily, as... Figure 4 As shown, the second gap structure 1210 may contact the second sealing ring 1320. For example, the second gap structure 1210 may extend to the second sealing ring 1320 along the second direction X or the third direction Y, so that heat in the second bonding layer 1200 can be diffused to the outside through the second gap structure 1210 and the second sealing ring 1320.

[0139] For example, the first bonding layer 1100 and the second bonding layer 1200 may be bonded to form Figure 1 The semiconductor structure 1000 is shown. For example, the first bonding layer 1100 and the second bonding layer 1200 can be bonded face-to-face along the first direction Z to form... Figure 1 The structure shown includes a first bonding structure 1120 connected to a second bonding structure 1220. Exemplarily, a hybrid bonding method can be used to bond the first bonding layer 1100 and the second bonding layer 1200. A first dielectric layer 1130 can be connected to a second dielectric layer 1230. The first bonding structure 1120 can be connected to the second bonding structure 1220.

[0140] For example, such as Figure 1 or Figure 2As shown, after the first bonding layer 1100 and the second bonding layer 1200 are bonded, the first gap structure 1110 can contact the second gap structure 1210. In other words, the first gap structure 1110 and the second gap structure 1210 can be connected.

[0141] It should be noted that, Figure 1 and Figure 2 The shown contact between the first gap structure 1110 and the second gap structure 1210 is merely an example and not a specific limitation. In actual processes, the structures of the first gap structure 1110 and the second gap structure 1210 can be reasonably configured according to actual conditions, so that the first gap structure 1110 and the second gap structure 1210 have at least one of the functions of reducing parasitic capacitance, reducing stress, and heat dissipation. For example, in another embodiment of this disclosure, the first gap structure 1110 may be spaced apart from the second gap structure 1210.

[0142] For example, such as Figure 3 and Figure 4 As shown, the first gap structure 1110 may have the same structure as the second gap structure 1210. For example, after bonding the first bonding layer 1100 and the second bonding layer 1200, the first gap structure 1110 and the second gap structure 1210 may be symmetrically arranged in the first direction Z.

[0143] It should be noted that the phrase "the first gap structure 1110 and the second gap structure 1210 have the same structure" as defined in this disclosure refers to the characteristics of the first gap structure 1110 and the second gap structure 1210 set during the product or process design stage. It should be understood that, due to limitations in actual manufacturing processes, the structure of the first gap structure 1110 and the structure of the second gap structure 1210 in actual manufacturing may deviate from the design value to a certain extent. This error range may be due to minor variations in manufacturing processes or tolerances, and therefore, this error range is also within the protection scope of this disclosure. For example, this error range may vary within 10% to 30% (e.g., ±10%, ±20%, or ±30%).

[0144] Figure 16 This is a schematic diagram of the structure forming a first bonding layer 1100, a first interconnect layer 1600 and a first semiconductor component 1400 according to another exemplary embodiment of this disclosure. Figure 17 This is a partially enlarged schematic diagram of the first bonding layer 1100 and the first interconnect layer 1600. Figure 18 This is a schematic diagram of the structure forming a second bonding layer 1200, a second interconnect layer 1700, and a second semiconductor component 1500 according to another exemplary embodiment of this disclosure. Figure 19 This is a partially enlarged schematic diagram of the second bonding layer 1200 and the second interconnect layer 1700.

[0145] In this embodiment, for the sake of brevity, the omitted parts are... Figures 12 to 15 The embodiments shown are described similarly.

[0146] For example, such as Figure 16 and Figure 17 As shown, a first bonding layer 1100 may be formed. For example, a first dielectric layer 1130 may be formed on one side of the first interconnect layer 1600 along the first direction Z; a first bonding structure 1120 may be formed through the first dielectric layer 1130 in the first direction Z; a gap may be formed in a dielectric layer 1610 that extends through the first dielectric layer 1130 in the first direction Z and into the first interconnect layer 1600; and a first gap structure 1110 and a dielectric material such as a first dielectric material 1140 may be formed within the gap.

[0147] Exemplarily, the gap can be formed by one or more etching processes. The first dielectric material 1140 can be formed by one or more thin film deposition processes. Exemplarily, the first gap structure 1110, such as an air gap, can be formed within the gap by controlling the process conditions for forming the first dielectric material 1140, such as process speed and time.

[0148] For example, such as Figure 18 and Figure 19 As shown, a second bonding layer 1200 may be formed. For example, a second dielectric layer 1230 may be formed on one side of the second interconnect layer 1700 along the first direction Z; a second bonding structure 1220 may be formed penetrating the second dielectric layer 1230 in the first direction Z; a gap may be formed in a dielectric layer 1710 penetrating the second dielectric layer 1230 in the first direction Z and extending into the second interconnect layer 1700; and a second gap structure 1210 and a dielectric material such as a second dielectric material 1240 may be formed within the gap.

[0149] Exemplarily, a second gap structure 1210, such as an air gap, can be formed within the gap by controlling the process conditions, such as process speed and time, in forming the second medium material 1240.

[0150] For example, the first dielectric material 1140 and the second dielectric material 1240 may comprise the same material. For instance, the first dielectric material 1140 and the second dielectric material 1240 may comprise an insulating material such as silicon oxide.

[0151] For example, the first bonding layer 1100 and the second bonding layer 1200 may be bonded to form Figure 8 The semiconductor structure 4000 is shown. For example, the first bonding layer 1100 and the second bonding layer 1200 can be face-to-face bonded along the first direction Z to form... Figure 8The structure shown includes a first dielectric material 1140 and a second dielectric material 1240 connected. Exemplarily, a hybrid bonding method can be used to bond the first bonding layer 1100 and the second bonding layer 1200. The first dielectric layer 1130 can be connected to the second dielectric layer 1230. The first dielectric material 1140 and the second dielectric material 1240 are connected. The first bonding structure 1120 can be connected to the second bonding structure 1220.

[0152] Since the contents and structures involved in the semiconductor structures 1000, 2000, 3000, 4000, and 5000 described above are wholly or partially applicable to the method of manufacturing semiconductor structures 6000 described herein, related or similar contents will not be repeated here.

[0153] Although exemplary structures and fabrication methods of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the fabrication methods of the semiconductor structure. Furthermore, the layers and materials described are merely exemplary.

[0154] Figure 20 This is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of this disclosure.

[0155] System 10 can be a mobile phone, desktop computer, laptop, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage system 12 located therein). Figure 20 As shown, system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memories 14.

[0156] The three-dimensional memory 14 may include the semiconductor structure described in any embodiment of this disclosure. According to some embodiments, a controller 16 is coupled to the three-dimensional memory 14 and the host 18 and is configured to control the three-dimensional memory 14. The controller 16 may manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in a mobile device, such as a smartphone, tablet, laptop, etc. The controller 16 may be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the 3D memory 14, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction codes (ECCs) related to data read from or written to the 3D memory 14. The controller 16 may also perform any other appropriate functions, such as formatting the 3D memory 14. The controller 16 may communicate with external devices (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0157] The controller 16 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. Figure 21AIn one example shown, the controller 16 and a single three-dimensional memory 14 may be integrated into the memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a connection between the memory card 22 and a host (e.g., Figure 20 The host 18) is coupled to the memory card connector 24. Figure 21B In another example shown, the controller 16 and multiple 3D memories 14 may be integrated into the SSD 26. The SSD 26 may further include a connection between the SSD 26 and a host (e.g., Figure 20 The SSD connector 28 is coupled to the host 18. In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than that of the memory card 22.

[0158] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A semiconductor structure, comprising: The first bonding layer includes a first gap structure and multiple first bonding structures. The first gap structure is located between adjacent first bonding structures, and the first gap structure includes an air gap.

2. The semiconductor structure according to claim 1, wherein, The semiconductor structure also includes: The second bonding layer is located on one side of the first bonding layer in the first direction, and includes a second bonding structure and a second gap structure, wherein the second bonding structure is connected to the first bonding structure. The second gap structure includes an air gap.

3. The semiconductor structure according to claim 2, wherein, The first gap structure is spaced apart from or in contact with the second gap structure.

4. The semiconductor structure according to claim 1, wherein, Multiple first bonding structures are arranged in the second direction. The first gap structure is located between adjacent first bonding structures in the second direction.

5. The semiconductor structure according to claim 1, wherein, Multiple first bonding structures are arranged upwards in a third-party manner. The first gap structure is located between the first bonding structures that are adjacent to the third party in the upward direction.

6. The semiconductor structure according to claim 1, wherein, Multiple first bonding structures are arranged in an array facing upwards in the second and third directions. Wherein, the first gap structure is located between the first bonding structures adjacent to each other in the second direction and / or the third direction upward. The second direction intersects with the third direction.

7. The semiconductor structure according to claim 1, wherein, The first gap structure is spaced apart from or in contact with the first bonding structure.

8. The semiconductor structure according to claim 1, wherein, The first gap structure includes a strip-shaped structure and / or a curved structure.

9. The semiconductor structure according to claim 2, wherein, The first gap structure and the second gap structure have the same structure.

10. The semiconductor structure according to any one of claims 1-9, wherein, The semiconductor structure also includes a sealing ring surrounding the first bonding layer. The first gap structure is in contact with the sealing ring.

11. The semiconductor structure according to claim 2, wherein, The first bonding layer further includes a first dielectric layer, and the second bonding layer further includes a second dielectric layer connected to the first dielectric layer. Wherein, at least a portion of the first bonding structure and the first gap structure are located within the first dielectric layer, and at least a portion of the second bonding structure and the second gap structure are located within the second dielectric layer.

12. The semiconductor structure according to claim 11, wherein, At least one of the first dielectric layer and the second dielectric layer comprises a multilayer structure.

13. The semiconductor structure according to claim 11, wherein, The semiconductor structure also includes: A first semiconductor component is located on the side of the first bonding layer opposite to the second bonding layer in the first direction; and The second semiconductor component is located on the side of the second bonding layer that is opposite to the first bonding layer in the first direction; Wherein, the first semiconductor component includes a first memory cell array and / or a first peripheral circuit; and The second semiconductor component includes a second memory cell array and / or a second peripheral circuit.

14. A method for manufacturing a semiconductor structure, comprising: A first bonding layer is formed, the first bonding layer including a first gap structure and a plurality of first bonding structures. The first gap structure is located between adjacent first bonding structures, and the first gap structure includes an air gap.

15. The method according to claim 14, wherein, The method further includes: Forming a second bonding layer, the second bonding layer including a second bonding structure; and The first bonding layer and the second bonding layer are bonded together.

16. The method according to claim 15, wherein, The formation of the first bonding layer includes: Forming a first dielectric layer and a first bonding structure penetrating the first dielectric layer in a first direction; and The first gap structure is formed in the first direction, penetrating the first dielectric layer. In this configuration, a plurality of the first bonding structures are arranged in an array facing upwards in the second direction and / or the third direction, and the first gap structures are located between adjacent first bonding structures in the second direction and / or between adjacent first bonding structures facing upwards in the third direction. The first direction, the second direction, and the third direction intersect each other.

17. The method according to claim 16, wherein, The formation of the second bonding layer includes: Forming a second dielectric layer and a second bonding structure penetrating the second dielectric layer in the first direction; and A second gap structure is formed in the second bonding layer that penetrates the second dielectric layer in the first direction. The plurality of second bonding structures are arranged in an array in the second direction and / or the third direction upward, and the second gap structure is located between adjacent second bonding structures in the second direction and / or between adjacent second bonding structures in the third direction upward.

18. The method according to claim 14, wherein, The formation of the first bonding layer includes: A first dielectric layer and a first bonding structure extending through the first dielectric layer in a first direction are formed; A gap is formed in the first direction that penetrates the first dielectric layer; and The first gap structure and the medium material surrounding the first gap structure are formed within the gap. In this configuration, a plurality of the first bonding structures are arranged in an array facing upwards in the second direction and / or the third direction, and the first gap structures are located between adjacent first bonding structures in the second direction and / or between adjacent first bonding structures facing upwards in the third direction. The first direction, the second direction, and the third direction intersect each other.

19. The method of claim 17, wherein, Bonding the first bonding layer and the second bonding layer includes: Bond the second bonding structure to the first bonding structure. The second gap structure is spaced apart from or in contact with the first gap structure.

20. The method of claim 17, wherein, The method further includes: A first interconnect layer is formed, wherein the first bonding layer is located on one side of the first interconnect layer in the first direction and is connected to the first interconnect layer; and A second interconnect layer is formed, wherein the second bonding layer is located on one side of the second interconnect layer in the first direction and is connected to the second interconnect layer; The first gap structure penetrates the first dielectric layer and extends to the first interconnect layer, and the second gap structure penetrates the second dielectric layer and extends to the second interconnect layer.

21. The method according to claim 20, wherein, The method further includes: A first semiconductor component is formed, wherein the first interconnect layer is located on one side of the first semiconductor component in the first direction; and A second semiconductor component is formed, wherein the second interconnect layer is located on one side of the second semiconductor component in the first direction; Wherein, the first semiconductor component includes a first memory cell array and / or a first peripheral circuit; and The second semiconductor component includes a second memory cell array and / or a second peripheral circuit.

22. A storage system, comprising: The semiconductor structure as described in any one of claims 1 to 13; as well as A controller, coupled to the semiconductor structure, is used to control the semiconductor structure to store data.

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