Memory device, method of manufacturing memory device, and memory system

Abstract

The application discloses a memory device, a manufacturing method of the memory device, and a storage system. The memory device comprises a semiconductor layer, a stack structure, and a channel structure. The stack structure comprises a plurality of dielectric layers and a plurality of conductive layers which are alternately stacked along a first direction on the semiconductor layer. The channel structure penetrates the stack structure along the first direction, and comprises a channel layer. The channel layer comprises a first end portion and a second end portion which are oppositely arranged along the first direction, and an intermediate portion between the first end portion and the second end portion. The first end portion extends to the semiconductor layer. An interface between the first end portion and the intermediate portion is a hetero-interface. The application can improve the problem that the off-state leakage current and the erasing efficiency are difficult to balance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a memory device, a method for manufacturing the memory device, and a memory system. Background Technology

[0002] In related technologies, gate-induced drain leakage (GIDL) erasure mechanisms are used to perform erase operations on memory devices. A longer source junction depth results in a higher GIDL current, thereby improving erase efficiency. However, increasing the source junction depth leads to a higher off-state leakage current, making it difficult to balance off-state leakage current with erase efficiency. Summary of the Invention

[0003] This application provides a storage device, a method for manufacturing the storage device, and a storage system to improve the problem of balancing off-state leakage current and erase efficiency.

[0004] According to one aspect of this application, a memory device is provided, including a semiconductor layer, a stacked structure, and a channel structure. The stacked structure includes a plurality of dielectric layers and a plurality of conductive layers alternately stacked on the semiconductor layer along a first direction. The channel structure extends through the stacked structure along the first direction and includes a channel layer. The channel layer includes a first end and a second end disposed opposite to each other along the first direction, and an intermediate portion located between the first end and the second end. The first end extends to the semiconductor layer. The junction between the first end and the intermediate portion has a heterogeneous interface.

[0005] In some embodiments, both the first end and the second end are provided with a first doped material, and the first end is provided with a second doped material of a different type than the first doped material.

[0006] In some embodiments, the band gap of the portion of the channel layer doped with the second doped material is lower than the band gap of the portion not doped with the second doped material.

[0007] In some embodiments, the first doping material includes an N-type dopant; the second doping material includes at least one of germanium, carbon, and nitrogen.

[0008] In some embodiments, the doping ratio of the second doped material is less than or equal to 50%.

[0009] In some embodiments, the first end portion contacts the end face of the middle portion facing the semiconductor layer; the heterojunction is located in the region where the first end portion contacts the middle portion.

[0010] In some embodiments, the channel structure further includes a tunneling layer, a storage layer, and a barrier layer arranged sequentially from the channel layer outwards; the first end portion contacts the end face of the middle portion facing the semiconductor layer, and the first end portion contacts the inner surface of the tunneling layer.

[0011] In some embodiments, the channel structure further includes a tunneling layer, a storage layer, and a barrier layer arranged sequentially from the channel layer outwards; the first end is in contact with the end face of the middle portion facing the semiconductor layer, the end face of the tunneling layer facing the semiconductor layer, the end face of the storage layer facing the semiconductor layer, and the end face of the barrier layer facing the semiconductor layer, and the first end is in contact with the inner surface of the tunneling layer.

[0012] In some embodiments, the heterogeneous interface is also present at the junction of the second end and the middle portion.

[0013] According to another aspect of this application, a method for manufacturing a storage device is provided, comprising the following steps:

[0014] A stacked structure is provided, the stacked structure comprising a plurality of dielectric layers and a plurality of conductive layers alternately stacked along a first direction;

[0015] A channel structure is formed on the stacked structure along the first direction through the stacked structure. The channel structure includes a channel layer, the channel layer includes a first end and a second end disposed opposite to each other along the first direction, and an intermediate portion located between the first end and the second end. The first end extends to the semiconductor layer, wherein a heterogeneous interface is present at the junction of the first end and the intermediate portion.

[0016] In some embodiments, forming a channel structure on the stacked structure that extends through the stacked structure along the first direction includes:

[0017] An initial channel structure is formed on the stacked structure, extending through the stacked structure along the first direction;

[0018] Remove a portion of the material at one end of the initial channel structure along the first direction to form the middle part of the channel layer;

[0019] An initial first end portion is formed at one end of the middle portion;

[0020] The initial first end is doped with a second doping material to form the first end of the channel layer.

[0021] According to another aspect of this application, a storage system is provided, including at least one storage device as described above and a controller, the controller being coupled to the storage device and used to control the storage device to store data.

[0022] According to at least one embodiment of the present application, the memory device, the method of manufacturing the memory device, and the memory system include a semiconductor layer, a stacked structure stacked on the semiconductor layer, and a channel structure penetrating the stacked structure along a first direction. The channel structure includes a channel layer, which includes a first end, a second end, and an intermediate portion located between the first end and the second end, wherein the first end extends to the semiconductor layer, and a heterogeneous interface is provided at the junction of the first end and the intermediate portion, thereby increasing the erase current at the junction of the first end and the intermediate portion, thereby improving the erase efficiency and balancing the off-state leakage current and the erase efficiency. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic diagram of a storage device according to an embodiment of this application is shown.

[0025] Figure 2 A cross-sectional view of a storage string is shown in one embodiment of this application.

[0026] Figure 3 A cross-sectional view of the storage string is shown in another embodiment of this application.

[0027] Figure 4 A cross-sectional view of the storage string is shown in another embodiment of this application.

[0028] Figure 5 A cross-sectional view of the storage string is shown in another embodiment of this application.

[0029] Figures 6a-6j The diagram illustrates the steps of a method for manufacturing a storage device according to an embodiment of this application.

[0030] Figures 7a-7h A schematic diagram of the steps in a method for manufacturing a storage device according to another embodiment of this application is shown.

[0031] Figures 8a-8f A schematic diagram of the steps in a method for manufacturing a storage device according to another embodiment of this application is shown.

[0032] Figure 9 A schematic diagram of a storage system according to an embodiment of this application is shown.

[0033] Explanation of reference numerals in the attached figures:

[0034] 10000, Electronic devices;

[0035] 1000, Storage system; 100, Storage device; 200, Controller; 2000, Host;

[0036] 100a, Storage array; 100b, Storage string; 100c, Storage cell;

[0037] 10. Semiconductor layer;

[0038] 20. Stacked structure; 21. Dielectric layer; 22. Conductive layer; 221. Bottom select gate; 222. Top select gate; 223. Gate; 224. Dummy layer; 225. Word line;

[0039] 30. Trench structure; 31. Trench layer; 311. First end; 312. Second end; 313. Middle section; 314. Heterogeneous interface; 32. Tunneling layer; 33. Storage layer; 34. Barrier layer; 35. Filling layer;

[0040] 30a, Initial trench structure; 30a1, Initial barrier layer; 30a2, Initial storage layer; 30a21, Intermediate storage layer; 30a3, Initial tunneling layer; 30a31, Intermediate tunneling layer; 30a4, Initial trench layer; 30a41, Intermediate trench layer; 30a42, Initial first end; 30a43, Intermediate first end; 30a44, Intermediate second end; 30a45, Initial second end; 30a5, Initial filler layer; 30a51, Intermediate filler layer;

[0041] 30b, channel hole;

[0042] 40. Substrate; 41. First substrate layer; 42. Second substrate layer; 43. Third substrate layer;

[0043] 50. Bit line;

[0044] 60; Sacrificial layer;

[0045] D1, First Direction; D2, Second Direction; D3, Third Direction. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0047] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0048] See Figure 1 Some embodiments of this application provide a storage device 100.

[0049] The storage device 100 includes a storage array 100a, which includes a plurality of storage strings 100b arranged in an array. Specifically, the plurality of storage strings 100b are arranged in rows along a second direction D2 and in columns along a third direction D3, wherein the second direction D2 and the third direction D3 intersect, for example, perpendicularly.

[0050] Combination Figure 1 and Figure 2 The storage string 100b includes a semiconductor layer 10, a stacked structure 20, and a channel structure 30. The stacked structure 20 includes a plurality of dielectric layers 21 and a plurality of conductive layers 22 alternately stacked on the semiconductor layer 10 along a first direction D1. The channel structure 30 penetrates the stacked structure 20 along the first direction D1. The first direction D1 is, for example, perpendicular to the second direction D2 and the third direction D3, respectively.

[0051] The material of the semiconductor layer 10 includes, for example, at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0052] The material of the dielectric layer 21 includes, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and organic insulating materials.

[0053] The material of the conductive layer 22 includes, for example, at least one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicide.

[0054] In the stacked structure 20, the conductive layer 22 serves as the gate electrode, and the dielectric layer 21 serves as the interlayer insulating layer between adjacent gate electrodes. The thicknesses of the multiple dielectric layers 21 and the multiple conductive layers 22 may be the same or different, depending on the process requirements. The stacked structure 20 can have 8, 16, 32, 64, 96, or 128 layers, etc. The more layers the stacked structure 20 has, the more memory cells 100c it forms. The number of stacked layers in the stacked structure 20 can be designed according to actual storage needs; this embodiment does not impose specific limitations.

[0055] The channel structure 30 includes a channel layer 31, which includes a first end 311, a second end 312, and a middle portion 313. The first end 311 and the second end 312 are disposed opposite to each other along a first direction D1, and the middle portion 313 is located between the first end 311 and the second end 312. The first end 311 extends to the semiconductor layer 10.

[0056] The material of the channel layer 31 includes, for example, at least one of single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The first end 311 and the second end 312 may be formed into an N-doped well region by, for example, N-type heavy doping, with the first end 311 serving as the source and the second end 312 serving as the drain.

[0057] In the channel layer 31, a heterogeneous interface 314 is formed at the junction of the first end 311 and the middle portion 313. The heterogeneous interface 314 is formed by, for example, bandgap adjustment. For example, by adjusting the band structure of the material of the first end 311, a difference can be created between the band structure of the first end 311 and the band structure of the middle portion 313, thereby forming a heterogeneous interface 314 at the junction of the first end 311 and the middle portion 313. Structurally, the heterogeneous interface 314 formed by bandgap adjustment can be manifested such that when the storage device 100 is sliced ​​along the stacking direction of the stacked structure 20, a boundary line exists between the first end 311 and the middle portion 313.

[0058] In some other embodiments, no heterogeneous interface is formed at the junction of the first end and the middle part. In its schematic diagram, in order to divide the channel layer into different regions, different filling regions are usually used to refer to the doped region and the undoped region respectively. However, in its actual structure, if the memory device is sliced, there is no boundary between the doped region formed by N-type doping or P-type doping and the undoped region, that is, there is no heterogeneous interface 314 in this embodiment.

[0059] Furthermore, in such embodiments where no heterogeneous interface is formed, a deeper source-drain junction is typically required to increase the gate-induced drain leakage (GIDL) to improve erase efficiency, which leads to a higher off-state leakage current.

[0060] The storage device 100 provided in this embodiment changes its internal structure by forming a heterogeneous interface 314 at the junction of the first end 311 and the middle part 313, thereby increasing the erase current at the junction of the first end 311 and the middle part 313. This achieves higher erase efficiency with a shorter source-drain junction, thus balancing the off-state leakage current and erase efficiency.

[0061] Continue reading Figure 1 and Figure 2In the stacked structure 20, multiple conductive layers 22 include a bottom select gate (BSG) 221, a gate 223, and a top select gate (TSG) 222. The bottom select gate 221 and the top select gate 222 are located at opposite ends of the stacked structure 20, with the bottom select gate 221 located closer to the semiconductor layer 10, and the gate 223 located between the bottom select gate 221 and the top select gate 222. The bottom select gate 221 and the top select gate 222 are used to activate a selected memory string 100b during, for example, an erase operation.

[0062] Optionally, the plurality of conductive layers 22 of the stacked structure 20 may also include a dummy layer 224 located between the bottom select gate 221 and the gate 223, and between the top select gate 222 and the gate 223.

[0063] The storage device 100 also includes a word line (WL) 225, which is coupled to each gate 223 in the same row of the storage array 100a.

[0064] The memory device 100 also includes a bit line (BL) 50, which is coupled to the end of the channel structure 30 away from the semiconductor layer 10.

[0065] In some embodiments, both the first end 311 and the second end 312 are provided with a first doped material, so that the first end 311 and the second end 312 form a doped well region. For example, the first end 311 serves as the source and the second end 312 serves as the drain. The dopants of the first end 311 and the second end 312 may be the same or different, and the doping ratios may be the same or different. This application does not limit this.

[0066] Optionally, the first end 311 and the second end 312 are doped with an N-type dopant, which includes any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb).

[0067] Optionally, the first end 311 and the second end 312 are doped with a P-type dopant, which includes any one or a combination of boron (B), gallium (Ga), and indium (In).

[0068] In some embodiments, the first end 311 is provided with a second doped material, and the doping type of the second doped material is different from that of the first doped material.

[0069] Optionally, the band gap of the portion of the channel layer 31 doped with the second doped material is lower than the band gap of the portion not doped with the second doped material. For example, the band gap of the first end 311 is lower than the band gap of the middle portion 313. In other words, by doping the first end 311 with the second doped material, the band gap of the first end 311 is adjusted so that the band gap of the first end 311 is lower than the band gap of the middle portion 313, thereby forming a heterogeneous interface 314 between the first end 311 and the middle portion 313, thereby improving the erasure efficiency.

[0070] Optionally, the first doping material includes an N-type dopant, such as at least one of phosphorus (P), arsenic (As), and antimony (Sb). The second doping material includes at least one of germanium (Ge), carbon (C), and nitrogen (N). By using the second doping material, the energy band of the first end 311 is adjusted, reducing its band gap, thereby increasing the erasure current of the heterojunction interface 314 and improving the erasure efficiency.

[0071] Optionally, the doping ratio of the second doped material is less than or equal to 50%. For example, the doping ratio of the second doped material is 20%, 30%, or 40%.

[0072] Continue reading Figure 2 In some embodiments, the first end 311 contacts the end face of the middle portion 313 facing the semiconductor layer 10, and the heterogeneous interface 314 is formed in the area where the first end 311 contacts the middle portion 313, thereby improving the erasure efficiency.

[0073] Combination Figure 1 and Figure 2 In some embodiments, the channel structure 30 further includes a tunneling layer 32, a storage layer 33, and a barrier layer 34 arranged sequentially from the channel layer 31 outwards. The gate 223 in the stacked structure 20, together with the corresponding barrier layer 34, storage layer 33, and tunneling layer 32, forms a memory cell 100c.

[0074] Optionally, the material of the tunneling layer 32 includes silicon oxide, silicon oxynitride, or a combination thereof.

[0075] Optionally, the material of the storage layer 33 includes silicon nitride, silicon oxynitride, or a combination thereof.

[0076] Optionally, the material of the barrier layer 34 includes silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or a combination thereof.

[0077] Optionally, see Figure 2 The first end 311 contacts the end face of the middle portion 313 facing the semiconductor layer 10, and the first end 311 contacts the inner surface of the tunneling layer 32, or, see [reference] Figure 3The first end portion 311 contacts the end face of the middle portion 313 facing the semiconductor layer 10, the end face of the tunneling layer 32 facing the semiconductor layer 10, the end face of the storage layer 33 facing the semiconductor layer 10, and the end face of the barrier layer 34 facing the semiconductor layer 10, and the first end portion 311 contacts the inner surface of the tunneling layer 32. In this way, the area of ​​the heterojunction 314 is increased.

[0078] See Figure 4 and Figure 5 In some embodiments, a heterogeneous interface 314 is also provided at the junction of the second end 312 and the middle portion 313. The structural features of the heterogeneous interface 314 of the second end 312 are the same as or different from the structural features of the heterogeneous interface 314 of the first end 311, and the formation method of the heterogeneous interface 314 of the second end 312 is the same as or different from the formation method of the heterogeneous interface 314 of the first end 311. Based on this, in addition to providing a heterogeneous interface 314 at the junction of the first end 311 and the middle portion 313, providing a heterogeneous interface 314 at the junction of the second end 312 and the middle portion 313 can further improve the erasing efficiency.

[0079] Based on the same inventive concept, some embodiments of this application also provide a method for manufacturing a storage device, the method comprising the following steps:

[0080] Step S1: Provide a stacked structure, the stacked structure including a plurality of dielectric layers and a plurality of conductive layers alternately stacked along a first direction;

[0081] Step S2: Form a channel structure that extends through the stacked structure along a first direction on the stacked structure. The channel structure includes a channel layer, which includes a first end and a second end disposed opposite to each other along the first direction, and an intermediate portion located between the first end and the second end. The first end extends to the semiconductor layer, wherein a heterogeneous interface is present at the junction of the first end and the intermediate portion.

[0082] Furthermore, forming a channel structure that penetrates the stacked structure along a first direction on the stacked structure includes:

[0083] Step S21: Form an initial channel structure that penetrates the stacked structure along a first direction on the stacked structure;

[0084] Step S22: Remove part of the material at one end of the initial channel structure along the first direction to form the middle part of the channel layer;

[0085] Step S23: Form an initial first end portion at one end of the middle portion;

[0086] Step S24: Doping the initial first end with a second doped material to form the first end of the channel layer.

[0087] The following will combine Figure 2 , Figures 6a-6j The above-described preparation method is described in detail for preparing a storage device 100 having a heterogeneous interface 314 at the junction of the first end 311 and the middle portion 313. The specific process of each step in one embodiment is described.

[0088] Combination Figure 2 , Figure 6a Step S1, the method for forming the stacked structure 20 includes, for example, depositing a plurality of alternating dielectric layers 21 and a plurality of conductive layers 22 on one side of the substrate 40 along the first direction D1 to form an initial stacked structure located on one side of the substrate 40 along the first direction D1.

[0089] Specifically, the material of the substrate 40 includes at least one of the following III-V compounds: single-crystal silicon (Si), single-crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide (GaAs).

[0090] In one embodiment of this application, the substrate 40 is, for example, a composite substrate for supporting a device structure thereon. The substrate 40 is formed by sequentially depositing multiple layers made of different materials using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0091] Alternatively, the substrate 40 includes a first substrate layer 41, a second substrate layer 42, and a third substrate layer 43 disposed sequentially, wherein the first substrate 40 is a silicon layer, the second substrate layer 42 is a silicon oxide layer, and the third substrate layer 43 is a silicon nitride layer.

[0092] Specifically, the initial stacked structure is formed through multiple thin film deposition processes, including, for example, chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0093] In one embodiment of this application, a dielectric layer 21 is first deposited on the side of the third substrate layer 43 away from the second substrate layer 42, such as at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and organic insulating materials; then a conductive layer 22 is deposited on the side of the dielectric layer 21 away from the substrate 40, such as at least one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicide; then multiple dielectric layers 21 and multiple conductive layers 22 are deposited alternately in the same manner to form an initial stacked structure.

[0094] Combination Figure 6a and Figure 6b Step S21, the method of forming an initial channel structure 30a that penetrates the stacked structure 20 along the first direction D1 on the stacked structure 20 includes, for example: removing a portion of the material of the initial stacked structure from the side away from the substrate 40 to form a stacked structure 20 having a channel hole 30b (CH), the channel hole 30b penetrating the stacked structure 20 along the first direction D1 and extending to the substrate 40; sequentially depositing an initial barrier layer 30a1, an initial storage layer 30a2, an initial tunneling layer 30a3, an initial channel layer 30a4 and an initial fill layer 30a5 in the channel hole 30b, the initial barrier layer 30a1, the initial storage layer 30a2, the initial tunneling layer 30a3, the initial channel layer 30a4 and the initial fill layer 30a5 forming the initial channel structure 30a.

[0095] Specifically, the process of removing a portion of the material from the initial stacked structure to form a stacked structure 20 with channel holes 30b includes, for example, wet etching and dry etching, with dry etching specifically including plasma etching, ion milling etching and reactive ion etching.

[0096] After forming the stacked structure 20 with the channel hole 30b, an initial barrier layer 30a1, an initial storage layer 30a2, an initial tunneling layer 30a3, an initial channel layer 30a4, and an initial fill layer 30a5 are sequentially deposited within the channel hole 30b using a thin film deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof, to fill the channel hole 30b. Specifically, the initial barrier layer 30a1 covers the sidewalls and bottom wall of the channel hole 30b, forming a first groove with a shape similar to or close to that of the channel hole 30b; the initial storage layer 30a2 covers the sidewalls and bottom wall of the first groove, forming a second groove; the initial tunneling layer 30a3 covers the sidewalls and bottom wall of the second groove, forming a third groove; the initial channel layer 30a4 covers the sidewalls and bottom wall of the third groove, forming a fourth groove; and the initial fill layer 30a5 fills the fourth groove. Among them, the initial barrier layer 30a1, the initial storage layer 30a2, and the initial tunneling layer 30a3 extend to the substrate 40, while the initial channel layer 30a4 does not extend to the substrate 40.

[0097] Alternatively, a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, a polysilicon layer, and a silicon oxide layer are sequentially deposited within the channel via 30b to form an initial channel structure 30a.

[0098] Combination Figures 6b to 6f Step S22, the method of removing a portion of the material at one end of the initial channel structure 30a along the first direction D1 to form the middle portion 313 of the channel layer 31, includes, for example:

[0099] Partial material of the first substrate layer 41 and the initial barrier layer 30a1 is removed to expose the second substrate layer 42 and one end of the initial channel structure 30a. The exposed end of the initial channel structure 30a extends beyond the second substrate layer 42, thereby exposing the side and end face of the initial storage layer 30a2 at that end.

[0100] A portion of the material of the second substrate layer 42 is removed to expose the third substrate layer 43; and a portion of the material of the initial channel structure 30a is removed, such as a portion of the initial barrier layer 30a1, the initial storage layer 30a2, and the initial tunneling layer 30a3, to form an intermediate storage layer 30a21 and an intermediate tunneling layer 30a31 flush with the third substrate layer 43, and to expose the side and end face of the initial channel layer 30a4 at that end.

[0101] The third substrate layer 43 is removed to expose the dielectric layer 21 of the stacked structure 20; and one end of the initial channel layer 30a4 is removed to form an intermediate channel layer 30a41 that is flush with the intermediate storage layer 30a21 and the intermediate tunneling layer 30a31.

[0102] A portion of the intermediate channel layer 30a41 is removed to form the middle portion 313 of the channel layer 31, which is lower than the intermediate storage layer 30a21 and the intermediate tunneling layer 30a31, and the end face and part of the side face of the initial filling layer 30a5 are exposed to form the filling layer 35.

[0103] Specifically, a portion of the first substrate layer 41, the second substrate layer 42, the third substrate layer 43, and the initial channel structure 30a are removed by, for example, dry etching, wet etching, a combination of dry etching and wet etching, or a patterning process including photolithography, cleaning, and chemical mechanical polishing.

[0104] Combination Figure 6f and Figure 6g Step S23, the method of forming an initial first end 30a42 at one end of the intermediate portion 313 includes, for example, depositing a semiconductor material at the end of the intermediate portion 313 and the filling layer 35, such as depositing at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor material, II-VI compound semiconductor material and other suitable semiconductor materials, to form an initial first end 30a42 that is flush with and stacked with the intermediate storage layer 30a21 and the intermediate tunneling layer 30a31.

[0105] Specifically, the initial first end 30a42 is formed by a thin film deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0106] Combination Figure 6g and Figure 6jStep S24, the method for doping the initial first end 30a42 with a second doped material to form the first end 311 of the channel layer 31, includes, for example:

[0107] The initial first end 30a42 is doped with a second doping material, such as germanium (Ge), to form the intermediate first end.

[0108] The first end is doped with a first doping material, such as an N-type dopant, to form the first end 311.

[0109] Specifically, the intermediate first end is doped using, for example, an ion implantation process.

[0110] After forming the first end 311, the portions of the intermediate storage layer 30a21 and the intermediate tunneling layer 30a31 that extend beyond the dielectric layer 21 of the stacked structure 20 are removed to form a tunneling layer 32 and a storage layer 33 that are flush with the dielectric layer 21 of the stacked structure 20. The first end 311 extends beyond the dielectric layer 21 of the stacked structure 20.

[0111] Semiconductor material is deposited on the exposed side of the dielectric layer 21 of the stacked structure 20, such as at least one of single-crystal silicon, polycrystalline silicon, single-crystal germanium, group III-V compound semiconductor material, group II-VI compound semiconductor material, and other suitable semiconductor materials, to form a semiconductor layer 10 covering the first end 311, the tunneling layer 32, and the storage layer 33. Based on this, a memory device 100 with a heterogeneous interface 314 at the junction of the first end 311 and the middle portion 313 can be formed.

[0112] The following will combine Figure 3 , Figures 7a-7h The above-described preparation method is described in detail for preparing a storage device 100 having a heterogeneous interface 314 at the junction of the first end 311 and the middle portion 313. The specific process of each step in one embodiment is described.

[0113] The substrate, stacked structure 20, and initial channel structure 30a are formed using the same method as in other embodiments of this application or other methods.

[0114] Combination Figure 3 , Figures 7a-7f Step S22, the method of removing a portion of the material at one end of the initial channel structure 30a along the first direction D1 to form the middle portion 313 of the channel layer 31, includes, for example:

[0115] Partial material of the first substrate layer 41 and the initial barrier layer 30a1 is removed to expose the second substrate layer 42 and one end of the initial channel structure 30a. The exposed end of the initial channel structure 30a extends beyond the second substrate layer 42, thereby exposing the side and end face of the initial storage layer 30a2 at that end.

[0116] Remove a portion of the material from one end of the initial channel structure 30a that extends beyond the second substrate layer 42, for example, remove one end of the initial storage layer 30a2 and the initial tunneling layer 30a3 that extend beyond the second substrate layer 42, to form an intermediate storage layer 30a21 and an intermediate tunneling layer 30a31 that are flush with the second substrate layer 42, and expose the side and end face of the initial channel layer 30a4 at that end.

[0117] Remove the portions of the initial channel layer 30a4 and the initial fill layer 30a5 that extend beyond the second substrate layer 42 to form an intermediate channel layer 30a41 and an intermediate fill layer 30a51 that are flush with the second substrate layer 42.

[0118] A material such as silicon dioxide is deposited on the exposed side of the second substrate layer 42 to form a sacrificial layer 60 covering the second substrate layer 42, the intermediate storage layer 30a21, the intermediate tunneling layer 30a31, the intermediate channel layer 30a41, and the intermediate fill layer 30a51.

[0119] The sacrificial layer 60 and the second substrate layer 42 are removed to expose the third substrate layer 43; and a portion of the intermediate storage layer 30a21 and the intermediate tunneling layer 30a31 are removed to form a storage layer 33 and a tunneling layer 32 below the third substrate layer 43; and a portion of the intermediate fill layer 30a51 is removed to form a fill layer 35 below the third substrate layer 43.

[0120] A portion of the intermediate channel layer 30a41 is removed to form the middle section 313 of the channel layer, which is lower than the storage layer 33 and the tunneling layer 32.

[0121] Specifically, a portion of the first substrate layer 41, the second substrate layer 42, and the initial channel structure 30a is removed by, for example, dry etching, wet etching, a combination of dry etching and wet etching, or a patterning process including photolithography, cleaning, and chemical mechanical polishing.

[0122] Combination Figures 7f-7h Step S23, the method of forming an initial first end 30a42 at one end of the intermediate portion 313 includes, for example, depositing a semiconductor material at the end of the intermediate portion 313 of the channel layer 31, the tunnel layer 32, the storage layer 33, and the barrier layer 34, such as depositing at least one of single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor material, II-VI compound semiconductor material, and other suitable semiconductor materials to form an initial first end 30a42 flush with the third substrate layer 43.

[0123] Specifically, the initial first end 30a42 is formed by a thin film deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0124] Step S24, the method for doping the initial first end 30a42 with a second doped material to form the first end 311 of the channel layer 31, includes, for example:

[0125] The initial first end 30a42 is doped with a second doping material, such as germanium (Ge), to form the intermediate first end.

[0126] The first end is doped with a first doping material, such as an N-type dopant, to form the first end 311.

[0127] Specifically, the intermediate first end is doped using, for example, an ion implantation process.

[0128] After forming the first end portion 311, a semiconductor material is deposited on the exposed side of the third substrate layer 43, such as at least one of single-crystal silicon, polycrystalline silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials, to form a semiconductor layer 10 covering the first end portion 311 and the third substrate layer 43. Based on this, a memory device 100 with a heterogeneous interface 314 at the junction of the first end portion 311 and the middle portion 313 can be formed.

[0129] Based on the same inventive concept, some embodiments of this application also provide a method for manufacturing a storage device, the method comprising the following steps:

[0130] Step S1': Provide a stacked structure, the stacked structure including a plurality of dielectric layers and a plurality of conductive layers alternately stacked along a first direction;

[0131] Step S2': Form a channel structure that extends through the stacked structure along a first direction on the stacked structure. The channel structure includes a channel layer, which includes a first end and a second end disposed opposite to each other along the first direction, and an intermediate portion located between the first end and the second end. The first end extends to the semiconductor layer, and the junction of the second end and the intermediate portion has a heterogeneous interface.

[0132] Furthermore, forming a channel structure that penetrates the stacked structure along a first direction on the stacked structure includes:

[0133] Step S21': Form an initial channel structure that penetrates the stacked structure along the first direction on the stacked structure;

[0134] Step S22': Remove part of the material at one end of the initial channel structure along the first direction to form the middle part of the channel layer;

[0135] Step S23': Form an initial second end at one end of the middle section;

[0136] Step S24': Doping the initial second end with a second doped material to form the second end of the channel layer.

[0137] The following will combine Figure 4 , Figures 8a-8f The above-described preparation method is described in detail for preparing a storage device 100 having a heterogeneous interface 314 at the junction of the second end 312 and the middle portion 313. The specific process of each step in one embodiment is described.

[0138] Combination Figure 4 , Figure 8a In steps S1' and S21', the stacked structure 20 and the initial channel structure 30a are formed using the same method as in other embodiments of this application or other methods.

[0139] The initial barrier layer 30a1 covers the sidewalls and bottomwalls of the channel hole 30b, forming a first groove with the same or similar shape as the channel hole 30b; the initial storage layer 30a2 covers the sidewalls and bottomwalls of the first groove, and the initial storage layer 30a2 covers the end face of the initial barrier layer 30a1, forming a second groove; the initial tunneling layer 30a3 covers the sidewalls and bottomwalls of the second groove, and the initial storage layer 30a3 covers the end face of the initial barrier layer 30a2, forming a third groove; the initial channel layer 30a4 covers the sidewalls and bottomwalls of the third groove, and the initial tunneling layer 30a4 covers the end face of the initial storage layer 30a3, forming a fourth groove; the initial filling layer 30a5 fills the fourth groove, and the initial filling layer 30a5 covers the end face of the initial channel layer 30a4.

[0140] Combination Figures 8a-8d Step S22', the method of removing a portion of the material at one end of the initial channel structure 30a along the first direction D1 to form the middle portion 313 of the channel layer 31, includes, for example:

[0141] The portion of the initial fill layer 30a5 covering the initial channel layer 30a4 is removed, and the portion of the initial fill layer 30a5 located in the fourth groove is removed, forming a fill layer 35 lower than the stacked structure 20.

[0142] The portion of the initial channel layer 30a4 covering the initial storage layer 30a3 is removed, and the portion of the initial channel layer 30a4 located in the third groove is removed, forming the middle portion 313 of the channel layer 31 below the filling layer 35.

[0143] The portion of the initial tunneling layer 30a3 covering the initial storage layer 30a2, the portion of the initial tunneling layer 30a3 located in the second groove, and the portion of the initial storage layer 30a2 covering the initial barrier layer 30a1, and the portion of the initial storage layer 30a2 located in the first groove are removed to form a storage layer 33 and a tunneling layer 32 lower than the stacked structure 20, and the end of the initial barrier layer 30a1 is exposed to form a barrier layer 34.

[0144] Specifically, a portion of the initial channel structure 30a is removed by, for example, dry etching, wet etching, a combination of dry and wet etching, or a patterning process including photolithography, cleaning, and chemical mechanical polishing.

[0145] Combination Figures 8d-8f Step S23', the method of forming an initial second end at one end of the intermediate portion 313 includes, for example, depositing a semiconductor material at the end of the filling layer 35, the intermediate portion 313, the tunneling layer 32, and the storage layer 33, such as depositing at least one of single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor material, II-VI compound semiconductor material, and other suitable semiconductor materials to form an initial second end 30a45 flush with the stacked structure 20.

[0146] Specifically, the initial second end 30a45 is formed by a thin film deposition process, such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or any combination thereof.

[0147] Step S24', the method for doping the initial second end 30a45 with a second doped material to form the second end 312 of the channel layer 31, includes, for example:

[0148] The initial second end is doped with a second doping material, such as germanium (Ge), to form an intermediate second end.

[0149] The second end of the middle layer is doped with a first doping material, such as an N-type dopant, to form the second end 312 of the channel layer 31.

[0150] Specifically, the intermediate second end is doped using, for example, an ion implantation process. Based on this, a memory device 100 with a heterogeneous interface 314 at the junction of the second end 312 and the intermediate portion 313 can be formed.

[0151] See Figure 9 Based on the same inventive concept, some embodiments of this application also provide a storage system 1000. The storage system 1000 includes a controller 200 and at least one storage device 100 of the above embodiments. The controller 200 is coupled to the storage device 100 and is used to control the storage device 100 to store data.

[0152] Optionally, the controller 200 and the individual storage device 100 are integrated into the memory card. Memory cards include Personal Computer Memory Card International Association (PCMCIA or PC), Compact Flash (CF), Smart Media (SM), Memory Stick, Multimedia Card (MMC), Secure Digital Memory Card (SD), Universal Flash Storage (UFS), etc.

[0153] Optionally, the controller 200 and multiple storage devices 100 are integrated into a solid state drive (SSD).

[0154] In some embodiments, the storage system 1000 is used for mobile phones, desktop computers, laptops, tablets, in-vehicle computers, game consoles, printers, positioning devices, wearable electronic devices 10000, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or other electronic devices 10000 having storage components located therein.

[0155] Optionally, the electronic device 10000 includes a host 2000 and a storage system 1000 having one or more storage devices 100 and a controller 200. The host 2000 may be a processor of the electronic device 10000, such as a central processing unit (CPU) or a system-on-chip (SoC). The host 2000 is configured to send data to or receive data from the storage device 100.

[0156] Optionally, the controller 200 is coupled to the storage device 100 and the processor, and the controller 200 is configured to manage data stored in the storage device 100 and communicate with the processor.

[0157] Optionally, the controller 200 is configured to control the operation of the storage device 100, such as read, erase, and program operations.

[0158] Optionally, the controller 200 is configured to manage various functions related to data stored in or to be stored in the storage device 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0159] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances. Furthermore, in the description of this application, unless otherwise stated, "multiple" means at least two, for example, two, three, four, etc. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0160] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A storage device, characterized in that, include: Semiconductor layer; A stacked structure, comprising a plurality of dielectric layers and a plurality of conductive layers alternately stacked along a first direction on the semiconductor layer; A channel structure extending through the stacked structure along the first direction, the channel structure including a channel layer, the channel layer including a first end and a second end disposed opposite to each other along the first direction, and an intermediate portion located between the first end and the second end, the first end extending to the semiconductor layer; The junction between the first end and the middle part has a heterogeneous interface.

2. The storage device according to claim 1, characterized in that, Both the first end and the second end are provided with a first doped material, and the first end is provided with a second doped material of a different type than the first doped material.

3. The storage device according to claim 2, characterized in that, The band gap of the portion of the channel layer doped with the second doped material is lower than the band gap of the portion not doped with the second doped material.

4. The storage device according to claim 2, characterized in that, The first doped material includes an N-type dopant; The second doped material includes at least one of germanium, carbon, and nitrogen.

5. The storage device according to claim 2, characterized in that, The doping ratio of the second doped material is less than or equal to 50%.

6. The storage device according to claim 1, characterized in that, The first end portion contacts the end face of the middle portion facing the semiconductor layer; The heterogeneous interface is located in the region where the first end contacts the middle part.

7. The storage device according to claim 1, characterized in that, The trench structure also includes a tunneling layer, a storage layer, and a barrier layer arranged sequentially from the trench layer outwards; The first end portion contacts the end face of the middle portion facing the semiconductor layer, and the first end portion contacts the inner side surface of the tunneling layer.

8. The storage device according to claim 1, characterized in that, The trench structure also includes a tunneling layer, a storage layer, and a barrier layer arranged sequentially from the trench layer outwards; The first end is in contact with the end face of the middle portion facing the semiconductor layer, the end face of the tunneling layer facing the semiconductor layer, the end face of the storage layer facing the semiconductor layer, and the end face of the barrier layer facing the semiconductor layer, and the first end is in contact with the inner side of the tunneling layer.

9. The storage device according to claim 1, characterized in that, The heterogeneous interface is also present at the junction of the second end and the middle part.

10. A method for manufacturing a storage device, characterized in that, Includes the following steps: A stacked structure is provided, the stacked structure comprising a plurality of dielectric layers and a plurality of conductive layers alternately stacked along a first direction; A channel structure is formed on the stacked structure along the first direction through the stacked structure. The channel structure includes a channel layer, the channel layer includes a first end and a second end disposed opposite to each other along the first direction, and an intermediate portion located between the first end and the second end. The first end extends to the semiconductor layer, wherein a heterogeneous interface is present at the junction of the first end and the intermediate portion.

11. The method for manufacturing a storage device according to claim 10, characterized in that, The method of forming a channel structure that penetrates the stacked structure along the first direction on the stacked structure includes: An initial channel structure is formed on the stacked structure, extending through the stacked structure along the first direction; Remove a portion of the material at one end of the initial channel structure along the first direction to form the middle part of the channel layer; An initial first end portion is formed at one end of the middle portion; The initial first end is doped with a second doping material to form the first end of the channel layer.

12. A storage system, characterized in that, include: At least one storage device as described in any one of claims 1-9; A controller, coupled to the storage device, is used to control the storage device to store data.

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