Semiconductor device

Abstract

The present application relates to semiconductor devices. A semiconductor device is provided that includes a first source layer, a second source layer, a first insulating passivation layer partially interposed between the first source layer and the second source layer, and a gate structure on the second source layer. The semiconductor device also includes a source contact structure through the gate structure, the second source layer, and the first insulating passivation layer. The source contact structure is coupled to the first source layer.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202110842761.1 (application date: July 26, 2021, invention title: semiconductor device and method of manufacturing thereof). Technical Field

[0002] Various embodiments of this disclosure generally relate to electronic devices, and more specifically, to a semiconductor device and a method of manufacturing the semiconductor device. Background Technology

[0003] The integration of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as improvements in the integration of semiconductor devices comprising memory cells formed as a single layer on a substrate have become limited, three-dimensional semiconductor devices comprising memory cells stacked on a substrate have been proposed. Furthermore, various structures and manufacturing methods have been developed to improve the operational reliability of these semiconductor devices. Summary of the Invention

[0004] Various embodiments of this disclosure relate to a semiconductor device having a stable structure and improved properties, and a method for manufacturing the same.

[0005] Embodiments of this disclosure provide a semiconductor device including a first source layer, a second source layer, a first insulating passivation layer partially interposed between the first and second source layers, and a gate structure located on the second source layer. The semiconductor device also includes a source contact structure passing through the gate structure, the second source layer, and the first insulating passivation layer. The source contact structure is connected to the first source layer.

[0006] Embodiments of this disclosure provide a semiconductor device including a source structure, a gate structure, and an interlayer insulating layer disposed between the source structure and the gate structure. The semiconductor device also includes a source contact structure passing through the gate structure and the interlayer insulating layer, the source contact structure being coupled to the source structure. The source contact structure may include a first portion passing through the gate structure, a second portion passing through the interlayer insulating layer, and a third portion passing through the source structure, wherein the third portion is wider than the first portion and includes a gap.

[0007] Embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising the steps of: forming a first source layer; forming a first insulating passivation layer on the first source layer; and forming a sacrificial structure on the first insulating passivation layer. The method further comprises the step of: forming a stack on the sacrificial structure, the stack comprising alternatingly stacked first and second material layers. The method further comprises the steps of: forming a first opening through the stack; forming a second opening coupled to the first opening by removing the sacrificial structure; forming a third opening through the first insulating passivation layer and exposing the first source layer; forming a second source layer in the second and third openings; and replacing the first material layer with the third material layer through the first opening. Attached Figure Description

[0008] Figure 1A and Figure 1B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2A and Figure 2B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3A and Figure 3B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4A , Figure 4B , Figure 5A , Figure 5B as well as Figures 6 to 16 This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0012] Figures 17A to 17E This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0013] Figures 18A to 18F This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 19 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0015] Figure 20 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0016] Figure 21 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0017] Figure 22 This is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0018] Figure 23 This is a diagram illustrating a memory system according to an embodiment of the present disclosure. Detailed Implementation

[0019] The specific structural or functional descriptions of the embodiments of this disclosure presented in this specification or application are for the purpose of describing the embodiments only. This description should not be construed as limiting the scope to the embodiments described in the specification or application.

[0020] Figure 1A and Figure 1B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure.

[0021] Reference Figure 1A and Figure 1B The semiconductor device may include a source structure S, a gate structure GST, and a source contact structure SCT. The semiconductor device may also include an interlayer insulating layer 16, a second insulating passivation layer 22, or a channel structure CH, and may also include combinations thereof.

[0022] The source structure S may include a first source layer S1 and a second source layer S2, and may also include a first insulating passivation layer 21. The first source layer S1 may include a first layer 11. The first layer 11 may be a polysilicon layer or a metal layer such as tungsten or molybdenum. The second source layer S2 may include a second layer 12, a third layer 13, or a fourth layer 14, or a combination thereof. The fourth layer 14 may be interposed between the second layer 12 and the third layer 13. The second layer 12, the third layer 13, or the fourth layer 14 may be a polysilicon layer or a metal layer such as tungsten or molybdenum.

[0023] The first source layer S1 or the second source layer S2 may include dopants. Dopants may include N-type or P-type impurities. The dopant concentration of the first source layer S1 and the dopant concentration of the second source layer S2 may be substantially equal to or different from each other. The dopant concentrations of the second layers 12 to the fourth layers 14 may be substantially equal to or different from each other.

[0024] The first insulating passivation layer 21 may be partially interposed between the first source layer S1 and the second source layer S2. The first insulating passivation layer 21 may be used to protect the first source layer S1 during the manufacturing process. The first insulating passivation layer 21 may comprise an insulating material such as an oxide or a nitride.

[0025] The first insulating passivation layer 21 may be spaced apart from the sidewalls of the channel structure CH. Around the periphery of the source contact structure SCT, the first insulating passivation layer 21 may be inserted between the first source layer S1 and the second source layer S2. Around the periphery of the channel structure CH, the first insulating passivation layer 21 may not be inserted between the first source layer S1 and the second source layer S2. Around the periphery of the channel structure CH, the second source layer S2 may pass through the first insulating passivation layer 21 to be electrically connected to the first source layer.

[0026] The gate structure GST may be located on the source structure S. The gate structure GST may include alternating layers of conductive layers 17 and insulating layers 18. The bottom layer of the gate structure GST may be either the insulating layer 18 (as shown) or the conductive layer 17. The conductive layer 17 may be the gate electrode, such as a memory cell or a selection transistor. The conductive layer 17 may include a conductive material such as polysilicon, tungsten, molybdenum, or metal. The insulating layer 18 is used to insulate the stacked conductive layers 17 from each other. The insulating layer 18 may include an insulating material such as oxide, nitride, or air gap.

[0027] An interlayer insulating layer 16 may be interposed between the source structure S and the gate structure GST. In one embodiment, the interlayer insulating layer 16 may be interposed between the second source layer S2 and the gate structure GST. The interlayer insulating layer 16 may comprise an insulating material such as an oxide or a nitride. In another embodiment, the interlayer insulating layer 16 may comprise a silicon oxide layer.

[0028] The channel structure CH can pass through the gate structure GST, the interlayer insulating layer 16, the second source layer S2, and the first insulating passivation layer 21, and can extend to the first source layer S1. The channel structure CH may include a channel layer 24, and the channel layer 24 can pass through the gate structure GST, the interlayer insulating layer 16, the second source layer S2, and the first insulating passivation layer 21. The second source layer S2 can pass through the memory layer 23 of the channel structure CH and is directly connected to the channel layer 24. The channel layer 24 may include semiconductor materials such as silicon, germanium, or nanostructures.

[0029] The channel structure CH may also include a memory layer 23 or an insulating core 25, or a combination thereof. The memory layer 23 may be interposed between the channel layer 24 and the conductive layer 17. In one embodiment, the memory layer 23 may be formed as a sidewall surrounding the channel layer 24. The memory layer 23 may include a tunnel insulating layer, a data storage layer, or a barrier layer, or a combination thereof. The data storage layer may include a floating gate, a charge trapping material, polysilicon, a nitride, a variable resistance material, a phase change material, etc., or a combination thereof. The insulating core 25 may be formed in the channel layer 24. The insulating core 25 may include an insulating material such as an oxide, a nitride, or an air gap.

[0030] The source contact structure SCT can pass through the gate structure GST, the interlayer insulating layer 16, the second source layer S2, and the first insulating passivation layer 21. The source contact structure SCT can be connected to the first source layer S1. The source contact structure SCT may include a conductive material, an insulating material, or a combination thereof.

[0031] The second insulating passivation layer 22 may be inserted between the source contact structure SCT and the source structure S. In one embodiment, the second insulating passivation layer 22 may be inserted between the source contact structure SCT and the second source layer S2. In another embodiment, the second insulating passivation layer 22 may be inserted between the insulating spacer 26 and the second source layer S2, and may extend between the insulating spacer 26 and the first insulating passivation layer 21. In yet another embodiment, the second insulating passivation layer 22 may be inserted between the insulating spacer 26 and the second source layer S2, and may not be inserted between the insulating spacer 26 and the first insulating passivation layer 21. The second insulating passivation layer 22 may be spaced apart from the first source layer S1.

[0032] The second insulating passivation layer 22 can be used to protect the first source layer S1 or the second source layer S2, or both, during the manufacturing process. The second insulating passivation layer 22 may include an insulating material such as an oxide or a nitride.

[0033] Reference Figure 1A The source contact structure SCT may include a conductive source contact layer 27 and an insulating spacer 26. The conductive source contact layer 27 may pass through the second insulating passivation layer 22 and the first insulating passivation layer 21, and may be electrically connected to the first source layer S1. The insulating spacer 26 may be used to insulate the conductive source contact layer 27 and the conductive layer 17 from each other. In an embodiment, the insulating spacer 26 may be formed as a sidewall surrounding the conductive source contact layer 27.

[0034] The insulating spacer 26 may include a first portion 26_P1, a second portion 26_P2, and a third portion 26_P3. The first portion 26_P1 may be inserted between the conductive power electrode contact layer 27 and the gate structure GST. The second portion 26_P2 may be inserted between the conductive power electrode contact layer 27 and the interlayer insulating layer 16. The third portion 26_P3 may be inserted between the conductive power electrode contact layer 27 and the second source layer S2. The widths W1 of the first portion 26_P1, W2 of the second portion 26_P2, and W3 of the third portion 26_P3 may be substantially the same or different. The width W2 of the second portion 26_P2 may be wider than the width W1 of the first portion 26_P1. The width W3 of the third portion 26_P3 may be wider than the width W1 of the first portion 26_P1. The width W3 of the third portion 26_P3 may be narrower than the width W2 of the second portion 26_P2.

[0035] For reference only. Figure 1AThe conductive electrode contact layer 27 is shown to have a uniform width in the first direction I and a length in the third direction III. However, the width can be varied. Although Figure 1A The insulating spacer 26 is shown to have a first width W1 to a third width W3, but the insulating spacer 26 may have a uniform width. In an embodiment, the width of the portion of the conductive electrode contact layer 27 corresponding to the second portion 26_P2 or the third portion 26_P3 may be wider than the width of the portion corresponding to the first portion 26_P1. Furthermore, the conductive electrode contact layer 27 may include gaps located in the wider portions.

[0036] Reference Figure 1B The source contact structure SCT may be formed of an insulating material. The source contact structure SCT may include an insulating layer 28. The insulating layer 28 may include an insulating material such as an oxide, nitride, or air gap.

[0037] The insulating layer 28 may include a first portion 28_P1, a second portion 28_P2, and a third portion 28_P3, and may also include a fourth portion 28_P4. The first portion 28_P1 may be a portion passing through the gate structure GST. The second portion 28_P2 may be a portion passing through the interlayer insulating layer 16. The third portion 28_P3 may be a portion passing through the second source layer S2. The fourth portion 28_P4 may be a portion passing through the second insulating passivation layer 22 and the first insulating passivation layer 21. The fourth portion 28_P4 may be connected to the first source layer S1. In an embodiment, the insulating layer 28 may not include the fourth portion 28_P4, and the second insulating passivation layer 22 may be formed to surround the lower surface of the insulating layer 28. In this case, the insulating layer 28 may be spaced apart from the first source layer S1 and the first insulating passivation layer 21.

[0038] The widths W1' of the first portion 28_P1, W2' of the second portion 28_P2, and W3' of the third portion 28_P3 may be substantially the same or different. The width W2' of the second portion 28_P2 may be wider than the width W1' of the first portion 28_P1. The width W3' of the third portion 28_P3 may be wider than the width W1' of the first portion 28_P1. The width W3' of the third portion 28_P3 may be narrower than the width W2' of the second portion 28_P2. The width W4' of the fourth portion 28_P4 may be narrower than the widths of the first portion 28_P1, the second portion 28_P2, or the third portion 28_P3. In an embodiment, when the widths of the second portion 28_P2 and the third portion 28_P3 are wider than the widths of the first portion 28_P1 and the fourth portion 28_P4, a gap may be included in the second portion 28_P2 or the third portion 28_P3.

[0039] In the above structure, the memory cell or selection transistor may be located in the portion where the channel structure CH and the conductive layer 17 intersect. The memory cell may be stacked along the channel structure CH. Furthermore, the first source layer S1 and the second source layer S2 may be prevented from being damaged during the manufacturing process, and each of the first source layer S1 and the second source layer S2 may have a substantially flat surface.

[0040] Figure 2A and Figure 2B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Repeated descriptions will be omitted hereinafter if deemed redundant.

[0041] Reference Figure 2A and Figure 2B The semiconductor device may include a source structure S', a gate structure GST, and a source contact structure SCT. The semiconductor device may also include an interlayer insulating layer 16, a second insulating passivation layer 22, or a channel structure CH, and may also include combinations thereof.

[0042] The source structure S' may include a first source layer S1 and a second source layer S2'. The first source layer S1 may include a first layer 11. The first layer 11 may be a polysilicon layer or a metal layer such as tungsten or molybdenum. The second source layer S2' may include a third layer 13 or a fourth layer 14, or a combination thereof. The fourth layer 14 may be interposed between the first layer 11 and the third layer 13. The third layer 13 or the fourth layer 14 may be a polysilicon layer or a metal layer such as tungsten or molybdenum.

[0043] The gate structure GST may be located on the source structure S'. The gate structure GST may include alternating layers of conductive layers 17 and insulating layers 18. An interlayer insulating layer 16 may be inserted between the source structure S' and the gate structure GST.

[0044] The channel structure CH can pass through the gate structure GST, the interlayer insulating layer 16, and the second source layer S2', and can extend to the first source layer S1. The channel structure CH may include a channel layer 24. The channel structure CH may also include a memory layer 23 or an insulating core 25, or a combination thereof.

[0045] The source contact structure SCT can pass through the gate structure GST, the interlayer insulating layer 16, and the second source layer S2'. The source contact structure SCT can be connected to the first source layer S1.

[0046] The second insulating passivation layer 22 can be inserted between the source contact structure SCT and the source structure S'. In an embodiment, the second insulating passivation layer 22 can be inserted between the source contact structure SCT and the first source layer S1, and between the source contact structure SCT and the second source layer S2'. The second insulating passivation layer 22 can contact the first source layer S1.

[0047] Reference Figure 2A The source contact structure SCT may include a conductive electrode contact layer 27 and an insulating spacer 26. The conductive electrode contact layer 27 may penetrate the second insulating passivation layer 22 and may be electrically connected to the first source layer S1. The portion of the conductive electrode contact layer 27 that penetrates the interlayer insulating layer 16 or that penetrates the source structure S' may be wider than the portion that penetrates the gate structure GST. Furthermore, the conductive electrode contact layer 27 may include a void in the portion having a relatively wider width. The void V is a blank space not filled with conductive material and may be filled with air, etc.

[0048] Reference Figure 2B The source contact structure SCT may include an insulating layer 28. A portion of the insulating layer 28 that passes through the interlayer insulating layer 16 or that passes through the source structure S' may be wider than a portion that passes through the gate structure GST. Furthermore, the insulating layer 28 may include voids in a portion having a relatively wider width.

[0049] In the above structure, the memory cell or selection transistor may be located in the portion where the channel structure CH and the conductive layer 17 intersect. The memory cell may be stacked along the channel structure CH. Furthermore, the first source layer S1 and the second source layer S2' may be prevented from being damaged during the manufacturing process, and each of the first source layer S1 and the second source layer S2' may have a substantially flat surface.

[0050] Figure 3A and Figure 3B This is a diagram illustrating the structure of a semiconductor device according to an embodiment of the present disclosure. Repeated descriptions will be omitted hereinafter.

[0051] Reference Figure 3A and Figure 3B The semiconductor device may include a source structure S, a gate structure GST, and a source contact structure SCT. The semiconductor device may also include an interlayer insulating layer 16, a second insulating passivation layer 22, or a channel structure CH, and may also include combinations thereof. The source contact structure SCT may include a gap. For reference, although... Figure 3A and Figure 3B The source structure S shown includes a second layer 12 and a first insulating passivation layer 21, but this disclosure is not limited thereto. The second source layer S2 may or may not include the second layer 12. The source structure S may or may not include the first insulating passivation layer 21.

[0052] The gate structure GST' may include alternately stacked conductive layers 17 and insulating layers 18. The bottommost layer of the gate structure GST may be the conductive layer 17. The width of the bottommost conductive layer 17_L may be narrower than the width of the remaining conductive layers 17. In an embodiment, the width of the portion of the source contact structure SCT passing through the bottommost conductive layer 17_L may be wider than the width of the portion passing through the remaining conductive layers 17. Between the channel structure CH and the source contact structure SCT, the width Wa of the bottommost conductive layer 17_L may be narrower than the width Wb of the remaining conductive layers 17. The sidewalls of the bottommost conductive layer 17_L may include curved surfaces. The sidewalls of the bottommost conductive layer 17_L may include tails extending toward the source contact structure SCT.

[0053] Figure 4A , Figure 4B , Figure 5A , Figure 5B as well as Figures 6 to 16 This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 4A and Figure 5A It can be a floor plan. Figure 4B and Figure 5B It can be along Figure 4A and Figure 5A A cross-sectional view taken from line A-A'. Figures 6 to 16 This is a cross-sectional view taken along the first direction I-I'. Repeated descriptions will be omitted in the following text.

[0054] Reference Figure 4A and Figure 4B A first source layer 31 is formed. The first source layer 31 may include polysilicon. In an embodiment, the first source layer 31 may be polysilicon doped with N-type or P-type impurities.

[0055] Subsequently, a first insulating passivation layer 32 is formed on the first source layer 31. The first insulating passivation layer 32 may include an insulating material such as an oxide or a nitride. In an embodiment, the first insulating passivation layer 32 may be a silicon oxide layer.

[0056] Subsequently, a first preliminary source layer 33 may be formed on the first insulating passivation layer 32. The first preliminary source layer 33 may include a doped polysilicon layer or an undoped polysilicon layer.

[0057] Subsequently, a sacrificial structure SC is formed on the first preliminary source layer 33. The sacrificial structure SC may have a single-layer structure or a multi-layer structure. The sacrificial structure SC may include a first sacrificial layer 34, a second sacrificial layer 35, a third sacrificial layer 36, or a fourth sacrificial layer 37, or a combination thereof. In an embodiment, the first sacrificial layer 34 may be a nitride layer including silicon nitride, etc. The second sacrificial layer 35 may be a doped polysilicon layer or an undoped polysilicon layer. The third sacrificial layer 36 may be a nitride layer including silicon nitride, etc. The fourth sacrificial layer 37 may be an oxide layer including silicon oxide, etc.

[0058] Subsequently, a second preliminary source layer 38 may be formed on the sacrificial structure SC. The second preliminary source layer 38 may include a doped polysilicon layer or an undoped polysilicon layer. Subsequently, an interlayer insulating layer 39 may be formed on the second preliminary source layer 38. The interlayer insulating layer 39 may include an insulating material such as an oxide or a nitride.

[0059] Subsequently, an etch stop layer 40 may be formed. The etch stop layer 40 may penetrate the interlayer insulating layer 39. The etch stop layer 40 may further penetrate the second preliminary source layer 38, or may further penetrate the second preliminary source layer 38 and the fourth sacrificial layer 37. The etch stop layer 40 may be formed to correspond to the location where the first opening will be formed in a subsequent process. The etch stop layer 40 may include a line pattern extending in a second direction II. The line pattern may have a width in a first direction I and a length in a second direction II. The width in the first direction I may be wider than the width of the first opening to be formed in a subsequent process. The second direction II may be a direction intersecting the first direction I. In an embodiment, the second direction II may be perpendicular to the first direction I. The etch stop layer 40 may include a material with high etch selectivity relative to the first and second material layers formed in subsequent processes.

[0060] Subsequently, a stack ST is formed on the interlayer insulating layer 39. The stack ST may include alternating layers of a first material layer 41 and a second material layer 42. The first material layer 41 may include a material with high etch selectivity relative to the second material layer 42. In one embodiment, the first material layer 41 may include a sacrificial material such as a nitride, and the second material layer 42 may include an insulating material such as an oxide. In another embodiment, the first material layer 41 may include a conductive material such as polysilicon, tungsten, or molybdenum, and the second material layer 42 may include an insulating material such as an oxide. As shown, the first material layer 41 or the second material layer 42 may be deposited first on the interlayer insulating layer 39.

[0061] Subsequently, a channel structure CH is formed. The channel structure CH can be formed between the etch stop layers 40. The channel structure CH can be arranged in a matrix form or in a staggered form with a center offset. The channel structure CH can be arranged symmetrically or asymmetrically on both sides, and the etch stop layers 40 are interposed therebetween.

[0062] The channel structure CH may include a channel layer 44. The channel layer 44 may penetrate the laminate ST, the sacrificial structure SC, and the first insulating passivation layer 32. The channel layer 44 may further penetrate the interlayer insulating layer 39, the second preliminary source layer 38, and the first preliminary source layer 33. The channel layer 44 may extend to the first source layer 31. The channel structure CH may also include a memory layer 43 or an insulating core 45, or a combination thereof.

[0063] In one embodiment, an opening is formed through the laminate ST, the interlayer insulating layer 39, the second preliminary source layer 38, the sacrificial structure SC, the first preliminary source layer 33, and the first insulating passivation layer 32. This opening may be formed to the depth exposing the first source layer 31. Subsequently, a memory layer 43 is formed in the opening, a channel layer 44 is formed in the memory layer 43, and an insulating core 45 is formed in the channel layer 44.

[0064] Reference Figure 5A and Figure 5B A first opening OP1 is formed through the laminate ST. The first opening OP1 may be formed to expose the etch stop layer 40. Subsequently, the etch stop layer 40 is removed through the first opening OP1. The first opening OP1 may include a first portion OP1_P1 corresponding to the laminate ST and a second portion OP1_P2 corresponding to the interlayer insulating layer 39 and the second preliminary source layer 38. The width of the second portion OP1_P2 may be wider than the width of the first portion OP1_P1.

[0065] Reference Figures 6 to 8 A protective spacer 46_SP is formed in the first opening OP1. The protective spacer 46_SP can be used to protect the sidewalls of the laminate ST exposed through the first opening OP1. The protective spacer 46_SP can have a single-layer structure or a multi-layer structure.

[0066] First, refer to Figure 6 A passivation layer 46 is formed along the inner surface of the first opening OP1. The passivation layer 46 may include a first passivation layer 46A, a second passivation layer 46B, or a third passivation layer 46, or a combination thereof. In an embodiment, the first passivation layer 46A may be a nitride layer including silicon nitride, the second passivation layer 46B may be an oxide layer including silicon oxide, and the third passivation layer 46C may be a nitride layer including silicon nitride.

[0067] Subsequently, referring to Figure 7 A mask pattern 50 is formed. The mask pattern 50 may be formed on the stack ST and cover the top of the first opening OP1. The mask pattern 50 may be formed by depositing mask material in a manner with poor step coverage. In an embodiment, the mask pattern 50 may be formed by plasma-enhanced chemical vapor deposition (PE-CVD). The mask pattern 50 may include a carbon layer.

[0068] Subsequently, referring to Figure 8 A protective spacer 46_SP is formed by etching the passivation layer 46 using a mask pattern 50 as an etching barrier. Subsequently, at least a portion of the sacrificial structure SC is etched using the protective spacer 46_SP as an etching barrier. Thus, a first opening OP1 extends into the sacrificial structure SC and penetrates the third sacrificial layer 36. The extended first opening OP1 exposes the second sacrificial layer 35. Afterward, the mask pattern 50 is removed.

[0069] Reference Figure 9 The second opening OP2 is formed by removing the second sacrificial layer 35 exposed via the first opening OP1. The second opening OP2 can be formed by selectively etching the second sacrificial layer 35. The memory layer 43 can be exposed through the second opening OP2.

[0070] Reference Figure 10 The memory layer 43 is etched through the second opening OP2. This exposes the channel layer 44. When the memory layer 43 is etched, the first sacrificial layer 34, the third sacrificial layer 36, and the fourth sacrificial layer 37 are also etched. This exposes the first preliminary source layer 33 and the second preliminary source layer 38. When the memory layer 43 is etched, the first insulating passivation layer 32 is protected by the first preliminary source layer 33.

[0071] When memory layer 43 is etched, a portion of the protective spacer 46_SP can be etched. In this embodiment, the third passivation layer 46C and the second passivation layer 46B can be etched. The first passivation layer 46A can be retained, and the stack ST and interlayer insulating layer 39 can be protected by the remaining first passivation layer 46A.

[0072] When memory layer 43 is etched, a third opening OP3 can be formed. The third opening OP3 can penetrate the first preliminary source layer 33 and the first insulating passivation layer 32, and expose the first source layer 31. The third opening OP3 can be formed around the channel structure CH. The sidewalls of the channel layer 44 can be exposed through the third opening OP3.

[0073] Reference Figure 11 A source layer 47 is formed in the second opening OP2 and the third opening OP3. The source layer 47 may contact the first preliminary source layer 33 and the second preliminary source layer 38. The source layer 47, together with the first preliminary source layer 33 and the second preliminary source layer 38, may form a second source layer S2. The first source layer 31 and the second source layer S2 may form a source structure S.

[0074] In one embodiment, a conductive layer is deposited to fill the second opening OP2 and the third opening OP3. Subsequently, a portion of the conductive layer formed in the first opening OP1 is etched. This forms the source layer 47. During the etching process of the conductive layer, a portion B of the first preliminary source layer 33 is etched, and the first insulating passivation layer 32 is exposed.

[0075] In this embodiment, the source layer 47 can be selectively grown in the second opening OP2 and the third opening OP3. In this case, the source layer 47 can be grown from the first source layer 31, the first preliminary source layer 33, and the second preliminary source layer 38. Since the source layer 47 is not grown in the first opening OP1, an etching process is not required.

[0076] Reference Figure 12 The protective spacer 46_SP is removed. This exposes the first material layer 41 and the second material layer 42. Furthermore, the interlayer insulating layer 39 and the second preliminary source layer 38 are also exposed.

[0077] Reference Figure 13 A second insulating passivation layer 48 is formed in the first opening OP1. The second insulating passivation layer 48 may be formed on the source layer 47. In an embodiment, the second insulating passivation layer 48 may be formed using an oxidation process. The second insulating passivation layer 48 may be formed by oxidizing the surfaces of the first preliminary source layer 33, the source layer 47, and the second preliminary source layer 38. The second insulating passivation layer 48 may include an oxide layer.

[0078] For reference, when a portion B of the first preliminary source layer 33 is etched in the process of forming the source layer 47 to expose the first insulating passivation layer 32, the second insulating passivation layer 48 may not be formed on the surface of the first preliminary source layer 33.

[0079] Reference Figure 14 The first material layer 41 is replaced by a third material layer 49 through the first opening OP1. The third material layer 49 may include a conductive material such as doped polysilicon, tungsten, molybdenum, or metal. Thus, a gate structure GST in which the second material layer 42 and the third material layer 49 are alternately stacked can be formed.

[0080] For example, when the first material layer 41 comprises a sacrificial material and the second material layer 42 comprises an insulating material, the first material layer 41 is replaced with a conductive layer. First, the first material layer 41 is removed to form a fourth opening OP4. Subsequently, conductive material is deposited in the first opening OP1 and the fourth opening OP4 to fill the fourth opening OP4. Afterward, a portion of the conductive material formed in the first opening OP1 is etched to form conductive layers in the fourth opening OP4. Here, the width of the conductive layer can be determined by the width of the second material layer 42 or the interlayer insulating layer 39 located at the upper and lower parts. Since the second material layer 42 protrudes into the first opening OP1 compared to the interlayer insulating layer 39, the lowermost conductive layer can be formed to have a narrower width than the other conductive layers. Furthermore, the sidewalls of the lowermost conductive layer may include curved surfaces resulting from the etching process (see...). Figure 3A and Figure 3B For example, when the first material layer 41 comprises a conductive material and the second material layer 42 comprises an insulating material, the first material layer 41 is silicided to form a metal silicide layer. When the first material layer 41 is replaced by a third material layer 49, the first source layer 31 and the second source layer S2 can be protected by the first insulating passivation layer 32 and the second insulating passivation layer 48.

[0081] Reference Figures 15 to 16 A source contact structure SCT is formed in the first opening OP1. The source contact structure SCT can pass through the gate structure GST, the interlayer insulating layer 39, and the second source layer S2. The source contact structure SCT can further pass through the first insulating passivation layer 32 and can be connected to the first source layer 31. The source contact structure SCT may include an insulating material or a conductive material, or a combination thereof.

[0082] Reference Figure 15 The source contact structure SCT may include an insulating spacer 51 and a conductive electrode contact layer 52. In an embodiment, after forming an insulating layer for the spacer in the first opening OP1, the insulating spacer 51 is formed by etching the spacer insulating layer via an etch-back process. When the spacer insulating layer is etched, the first insulating passivation layer 32 may be etched together, and the first source layer 31 may be exposed. Subsequently, a conductive electrode contact layer 52 electrically connected to the first source layer 31 is formed in the insulating spacer 51. The conductive electrode contact layer 52 may include a void V.

[0083] Reference Figure 16 The source contact structure SCT may include an insulating layer 53. In one embodiment, the insulating layer 53 may be formed by depositing an insulating material in the first opening OP1. The insulating layer 53 may include voids V.

[0084] In the above manufacturing method, the sacrificial structure SC can be replaced by the source layer 47 through the first opening OP1. The first material layer 41 can be replaced by the third material layer 49 through the first opening OP1. Furthermore, the first insulating passivation layer 32 can be used to prevent damage to the first source layer 31 during the process of replacing the first material layer 41 with the third material layer 49.

[0085] Figures 17A to 17E This is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Repeated descriptions will be omitted below.

[0086] Figure 17A This can correspond to the above. Figure 9 . Reference Figure 17A The memory layer 43 can be exposed through the second opening OP2. The memory layer 43 may include a barrier layer 43A, a data storage layer 43B, or a tunnel insulation layer 43C, or a combination thereof. The barrier layer 43A can be exposed through the second opening OP2.

[0087] Reference Figure 17B The barrier layer 43A is etched through the second opening OP2. This exposes the data storage layer 43B. While the barrier layer 43A is being etched, the stack ST is protected by a third passivation layer 46C. While the barrier layer 43A is being etched, the first preliminary source layer 33 is protected by a first sacrificial layer 34. While the barrier layer 43A is being etched, the second preliminary source layer 38 is protected by a third sacrificial layer 36.

[0088] Reference Figure 17C The data storage layer 43B is etched through the second opening OP2. This exposes the tunnel insulation layer 43C. When the data storage layer 43B is etched, the first sacrificial layer 34 is etched, exposing the first preliminary source layer 33. When the data storage layer 43B is etched, the third sacrificial layer 36 is etched, exposing the fourth sacrificial layer 37. When the data storage layer 43B is etched, the third passivation layer 46C is etched, exposing the second passivation layer 46B.

[0089] Reference Figure 17D The tunnel insulating layer 43C is etched through the second opening OP2. This exposes the channel layer 44. When the tunnel insulating layer 34C is etched, the fourth sacrificial layer 37 is etched. This exposes the second preliminary source layer 38. When the tunnel insulating layer 34C is etched, the second passivation layer 46B is etched. This exposes the first passivation layer 46A.

[0090] When the tunnel insulating layer 34C is etched, the barrier layer 43A covering the sidewalls of the first preliminary source layer 33 and the first insulating passivation layer 32 can be etched. This forms a third opening OP3 to expose the first source layer 31. The surfaces of the barrier layer 43A, the data storage layer 43B, and the tunnel insulating layer 43C exposed through the third opening OP3 can be located at different levels. In the third direction III, the surface of the data storage layer 43B can protrude most into the third opening OP3, and the surface of the tunnel insulating layer 43C can be located between the surface of the data storage layer 43B and the surface of the barrier layer 43A.

[0091] Furthermore, when the tunnel insulating layer 43C is etched, the first insulating passivation layer 32 exposed through the third opening OP3 can also be etched. Therefore, a groove G can be formed in the sidewall of the third opening OP3. Compared to the first insulating passivation layer 32, the first preliminary source layer 33 can protrude further into the third opening OP3.

[0092] When the tunnel insulating layer 34C is etched, the barrier layer 43A covering the sidewalls of the second preliminary source layer 38 can be etched. This forms a fifth opening OP5 to expose the sidewalls of the second preliminary source layer 38. The fifth opening OP5 can expose the interlayer insulating layer 39 depending on the amount of etching of the barrier layer 43A.

[0093] The surfaces of the barrier layer 43A, the data storage layer 43B, and the tunnel insulation layer 43C, exposed through the fifth opening OP5, may be located at different levels. In the third direction III, the surface of the barrier layer 43A may protrude most into the fifth opening OP5, and the surface of the data storage layer 43B may be located between the surface of the tunnel insulation layer 43C and the surface of the barrier layer 43A.

[0094] Reference Figure 17E A source layer 47 is formed in the second opening OP2, the third opening OP3, and the fifth opening OP5. The source layer 47 may include a first portion 47_P1 and a second portion 47_P2, and may also include a third portion 47_P3. The first portion 47_P1 may be inserted between the first preliminary source layer 33 and the second preliminary source layer 38. The second portion 47_P2 may be connected to the first portion 47_P1 and may surround the sidewalls of the channel layer 44. The third portion 47_P3 may be connected to the second portion 47_P2 and may protrude from the second portion 47_P2 toward the first insulating passivation layer 32.

[0095] Although not shown in the figure, subsequent processes such as forming the source contact structure can be performed. (Refer to...) Figures 12 to 16 The manufacturing method described can be applied to subsequent processes.

[0096] Figures 18A to 18FThis is a diagram illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Repeated descriptions will be omitted below.

[0097] Reference Figure 18A A first source layer 61 and a first insulating passivation layer 62 are formed. Subsequently, a sacrificial structure SC is formed on the first insulating passivation layer 62. The sacrificial structure SC may include a first sacrificial layer 64, a second sacrificial layer 65, a third sacrificial layer 66, or a fourth sacrificial layer 67, or a combination thereof. In an embodiment, the first sacrificial layer 64 may be a nitride layer including silicon nitride, etc. The second sacrificial layer 65 may be a doped polysilicon layer or an undoped polysilicon layer. The third sacrificial layer 66 may be a nitride layer including silicon nitride, etc. The fourth sacrificial layer 67 may be an oxide layer including silicon oxide, etc.

[0098] Subsequently, a preliminary source layer 68 can be formed on the sacrificial structure SC. Then, an interlayer insulating layer 39 can be formed on the preliminary source layer 68. Afterward, an etch stop layer 70 can be formed through the interlayer insulating layer 69.

[0099] Subsequently, a stack ST is formed on the interlayer insulating layer 39. The stack ST may include alternating layers of first material 71 and second material 72. A channel structure CH is then formed through the stack ST, the interlayer insulating layer 69, the sacrificial structure SC, and the first insulating passivation layer 62, extending to the first source layer 61. The channel structure CH may include a channel layer 74. The channel structure CH may also include a memory layer 73 or an insulating core 75, or a combination thereof.

[0100] Reference Figure 18B After forming the first opening OP1 through the stack ST, the etch stop layer 40 is removed. Thereafter, a passivation layer 76 is formed in the first opening OP1. The passivation layer 76 may include a first passivation layer 76A, a second passivation layer 76B, or a third passivation layer 76, or a combination thereof. In an embodiment, the first passivation layer 76A may be a nitride layer including silicon nitride, the second passivation layer 76B may be an oxide layer including silicon oxide, and the third passivation layer 76C may be a nitride layer including silicon nitride.

[0101] Reference Figure 18C The passivation layer 76 is etched to form a protective spacer 76_SP. Subsequently, the protective spacer 76_SP is used as an etching barrier to etch the third sacrificial layer 66 to expose the second sacrificial layer 65. Afterward, the second opening OP2 is formed by removing the second sacrificial layer 65 exposed via the first opening OP1. The memory layer 73 can then be exposed through the second opening OP2.

[0102] Reference Figure 18DThe memory layer 73 is etched through the second opening OP2. This exposes the channel layer 74. When the memory layer 73 is etched, the first sacrificial layer 64, the third sacrificial layer 66, the fourth sacrificial layer 67, and the first insulating passivation layer 62 are also etched. This exposes the first source layer 61 and the initial source layer 68. When the memory layer 73 is etched, the third passivation layer 76C and the second passivation layer 76B are also etched, while the first passivation layer 76A remains.

[0103] When memory layer 73 is etched, a third opening OP3 can be formed. The third opening OP3 can be formed around the channel structure CH. The sidewalls of the first source layer 61 and the sidewalls of the channel layer 74 can be exposed through the third opening OP3.

[0104] Reference Figure 18E A source layer 77 is formed in the second opening OP2 and the third opening OP3. The source layer 77 may be in contact with the initial source layer 68. The source layer 77, together with the initial source layer 68, may serve as a second source layer S2. The second source layer S2 may be in contact with the first source layer 61. The first source layer 61 and the second source layer S2 may form a source structure S.

[0105] Subsequently, the protective spacer 76_SP is removed. Then, a second insulating passivation layer 78 is formed in the first opening OP1. The second insulating passivation layer 78 may be formed on the surface of the first source layer 61 and the surface of the source layer 47.

[0106] Reference Figure 18F The first material layer 71 is replaced by the third material layer 79 through the first opening OP1. When the first material layer 71 is replaced by the third material layer 79, the first source layer 61 and the second source layer S2 can be protected by the second insulating passivation layer 78.

[0107] Subsequently, a source contact structure SCT is formed in the first opening OP1. The source contact structure SCT can pass through the gate structure GST, the interlayer insulating layer 69, and the second source layer S2. The source contact structure SCT can be connected to the first source layer 61. In an embodiment, the source contact structure SCT may include an insulating spacer 81 and a conductive electrode contact layer 82. The conductive electrode contact layer 82 may include a void V. In an embodiment, the source contact structure SCT may include an insulating layer.

[0108] In the above manufacturing method, the sacrificial structure SC can be replaced by the source layer 77 through the first opening OP1. The first material layer 71 can be replaced by the third material layer 79 through the first opening OP1. In addition, the second insulating passivation layer 78 can be used to prevent damage to the first source layer 61 during the process of replacing the first material layer 71 with the third material layer 79.

[0109] Figure 19This is a diagram illustrating a memory system 1000 according to an embodiment of the present disclosure.

[0110] Reference Figure 19 The memory system 1000 may include a memory device 1200 configured to store data and a memory controller 1100 configured to communicate between the memory device 1200 and the host 2000.

[0111] The host 2000 can be a device or system configured to store data in or retrieve data from the memory system 1000. The host 2000 can generate requests for various operations and output these requests to the memory system 1000. Requests may include programming requests for programming operations, read requests for read operations, and erase requests for erase operations. The host 2000 can communicate with the memory system 1000 through various interfaces such as a PCIe interface, an Advanced Technology Attachment (ATA) interface, a Serial ATA (SATA) interface, a Parallel ATA (PATA) interface, a Serial Attached SCSI (SAS) interface, a High-Speed ​​Non-Volatile Memory (NVMe) interface, a Universal Serial Bus (USB) interface, a Multimedia Card (MMC) interface, an Enhanced Small Digital Disk Interface (ESDI), or an Integrated Drive Electronic Device (IDE) interface.

[0112] The host 2000 may include at least one of a computer, portable digital device, tablet PC, digital camera, digital audio player, television, wireless communication device and cellular phone, but the embodiments disclosed herein are not limited thereto.

[0113] The storage controller 1100 controls the overall operation of the storage system 1000. The storage controller 1100 can control the storage device 1200 upon request from the host 2000. The storage controller 1100 can control the storage device 1200 to perform programming operations, read operations, erase operations, etc., upon request from the host 2000. Alternatively, even without a request from the host 2000, the storage controller 1100 can perform background operations to improve the performance of the storage system 1000.

[0114] The storage controller 1100 can send control signals and data signals to the storage device 1200 to control the operation of the storage device 1200. The control signals and data signals can be sent to the storage device 1200 via different input / output lines. Data signals may include commands, addresses, or data. Control signals can be used to identify segments of input data signals.

[0115] The memory device 1200 can perform programming, reading, and erasing operations under the control of the memory controller 1100. The memory device 1200 can be formed of a volatile memory device in which data stored is lost when power is interrupted, or a non-volatile memory device in which data stored is retained even when power is interrupted. The memory device 1200 can be a reference... Figure 1A and Figure 3B The semiconductor device described herein. The memory device 1200 can be configured as described by reference to... Figures 4A to 18F A semiconductor device manufactured by the described manufacturing method. In an embodiment, the semiconductor device may include a first source layer, a second source layer, a first insulating passivation layer partially interposed between the first source layer and the second source layer, a gate structure located on the second source layer, and a source contact structure passing through the gate structure, the second source layer and the first insulating passivation layer and connected to the first source layer.

[0116] Figure 20 This is a diagram illustrating a memory system 30000 according to an embodiment of the present disclosure.

[0117] Reference Figure 20 The memory system 30000 may be implemented as a cellular phone, smartphone, tablet PC, personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 2200 and a controller 2100 configured to control the operation of the memory device 2200.

[0118] The controller 2100 can control the data access operations (e.g., programming operations, erasing operations, or reading operations) of the memory device 2200 under the control of the processor 3100.

[0119] The data programmed in the memory device 2200 can be output through the display 3200 under the control of the controller 2100.

[0120] The radio transceiver 3300 can transmit and receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert the radio signals received via the antenna ANT into signals that can be processed in the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and send the processed signals to the controller 2100 or the display 3200. The controller 2100 can send the signals processed by the processor 3100 to the memory device 2200. Furthermore, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the converted radio signals to an external device via the antenna ANT. The input device 3400 can be used to input control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 can be specifically implemented in pointing devices such as touchpads and computer mice, keypads, or keyboards. The processor 3100 can control the operation of the display 3200, so that data output from the controller 2100, data output from the radio transceiver 3300, or data output from the input device 3400 is output through the display 3200.

[0121] In an implementation, the controller 2100, which controls the operation of the memory device 2200, may be specifically implemented as part of the processor 3100 or as a separate chip from the processor 3100.

[0122] Figure 21 This is a diagram illustrating a memory system 40000 according to an embodiment of the present disclosure.

[0123] Reference Figure 21 The memory system 40000 can be implemented in personal computers (PCs), tablet PCs, netbooks, e-readers, personal digital assistants (PDAs), portable multimedia players (PMPs), MP3 players, or MP4 players.

[0124] The memory system 40000 may include a memory device 2200 and a controller 2100 configured to control data processing operations of the memory device 2200.

[0125] The processor 4100 can output data stored in the memory device 2200 via the display 4300 based on data input from the input device 4200. For example, the input device 4200 can be specifically implemented in a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard.

[0126] The processor 4100 can control the overall operation of the memory system 40000 and control the operation of the controller 2100. In an embodiment, the controller 2100, which is capable of controlling the operation of the memory device 2200, may be specifically implemented as part of the processor 4100 or provided as a separate chip from the processor 4100.

[0127] Figure 22 This is a diagram illustrating a memory system 50000 according to an embodiment of the present disclosure.

[0128] Reference Figure 22 The memory system 50000 can be specifically implemented in an image processing device (e.g., a digital camera, a mobile phone equipped with a digital camera, a smartphone equipped with a digital camera, or a tablet PC equipped with a digital camera).

[0129] The memory system 50000 may include a memory device 2200 and a controller 2100 configured to control data processing operations (e.g., programming operations, erasing operations, or read operations) of the memory device 2200.

[0130] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals. The converted digital signals can be sent to the processor 5100 or the controller 2100. Under the control of the processor 5100, the converted digital signals can be output through the display 5300 or stored in the memory device 2200 through the controller 2100. The data stored in the memory device 2200 can be output through the display 5300 under the control of the processor 5100 or the controller 2100.

[0131] In an implementation, the controller 2100, which controls the operation of the memory device 2200, may be specifically implemented as part of the processor 5100 or as a separate chip from the processor 5100.

[0132] Figure 23 This is a diagram illustrating a memory system 70000 according to an embodiment of the present disclosure.

[0133] Reference Figure 23 The memory system 70000 can be specifically implemented in a memory card or a smart card. The memory system 70000 may include a memory device 2200, a controller 2100, and a card interface 7100.

[0134] The controller 2100 controls the data exchange between the memory device 2200 and the card interface 7100. In some embodiments, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but this disclosure is not limited thereto.

[0135] Card interface 7100 can interface for data exchange between host 60000 and controller 2100 according to the protocol of host 60000. In this embodiment, card interface 7100 can support Universal Serial Bus (USB) protocol and chip-to-chip (IC) USB protocol. Here, card interface 7100 can refer to hardware, software installed in the hardware, or signal transmission method that can support the protocol used by host 60000.

[0136] When the memory system 70000 is connected to the host interface 6200 of a host 60000, such as a PC, tablet PC, digital camera, digital audio player, cellular phone, console video game hardware, or digital set-top box, the host interface 6200 can perform data communication with the memory device 2200 through the card interface 7100 and the controller 2100 under the control of the microprocessor 6100.

[0137] By stacking memory cells in a three-dimensional manner, the integration of semiconductor devices can be improved. Furthermore, a semiconductor device with a stable structure and improved reliability can be provided.

[0138] Cross-references to related applications

[0139] This application claims priority to Korean Patent Application No. 10-2020-0172681, filed with the Korean Intellectual Property Office on December 10, 2020, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: Source structure; Gate structure; An interlayer insulating layer is inserted between the source structure and the gate structure; as well as A through-structure that penetrates the gate structure and the interlayer insulating layer and extends into the source structure. The through-structure includes: A first portion, the first portion extending through the gate structure; The second portion extends through the interlayer insulating layer and into the gate structure; and The third part is disposed in the source structure. Wherein, the width of the second portion at the height corresponding to the interlayer insulation layer is greater than the width of the first portion, and The third part is wider than the first part.

2. The semiconductor device according to claim 1, wherein, The third part includes a gap.

3. The semiconductor device according to claim 2, wherein, The gap extends into the second part.

4. The semiconductor device according to claim 1, further comprising: A channel structure that passes through the gate structure and the interlayer insulating layer and extends into the source structure.

5. The semiconductor device according to claim 1, wherein, The through-structure includes: Source contact layer, the source contact layer being electrically connected to the source structure; and An insulating spacer is disposed between the source contact layer and the gate structure.

6. The semiconductor device according to claim 5, wherein, The insulating spacer extends between the source contact layer and the source structure.

7. The semiconductor device according to claim 1, wherein, The through-structure is formed of an insulating material.

8. The semiconductor device according to claim 1, wherein, The source structure includes: First source layer; Second source layer; A first insulating passivation layer is partially interposed between the first source layer and the second source layer.

9. The semiconductor device according to claim 8, wherein, The first insulating passivation layer extends between the first source layer and at least a portion of the through structure.

10. The semiconductor device of claim 1, further comprising: A second insulating passivation layer extends between the through-structure and the source structure.

11. A semiconductor device comprising: First source layer; Second source layer; A gate structure, wherein the gate structure is located above the second source layer; An interlayer insulating layer is inserted between the second source layer and the gate structure; as well as A through-structure that passes through the gate structure, the interlayer insulating layer, and the second source layer, and extends into the first source layer. The through-structure includes a first portion extending through the gate structure and a second portion extending through the interlayer insulating layer and into the gate structure. Wherein, the width of the second portion at the height corresponding to the interlayer insulation layer is greater than the width of the first portion.

12. The semiconductor device of claim 11, further comprising: A channel structure that passes through the gate structure, the interlayer insulating layer, and the second source layer.

13. The semiconductor device according to claim 11, wherein, The through-structure includes: A conductive electrode contact layer, wherein the conductive electrode contact layer is electrically connected to the first source electrode layer; and An insulating spacer surrounds the sidewall of the conductive electrode contact layer.

14. The semiconductor device according to claim 13, wherein, The insulating spacer includes: A first spacer portion, the first spacer portion passing through the gate structure; and The second spacer portion extends through the interlayer insulation layer. The second spacer portion is wider than the first portion.

15. The semiconductor device according to claim 11, wherein, The through-structure is formed of an insulating material.

16. The semiconductor device according to claim 11, wherein, The through-structure also includes a third portion that passes through the second source layer, and the third portion is wider than the first portion.

17. The semiconductor device according to claim 16, wherein, The third part is narrower than the second part.

18. The semiconductor device according to claim 11, wherein, The gate structure includes: Multiple conductive layers; and Multiple insulating layers are alternately stacked with the multiple conductive layers.

19. The semiconductor device according to claim 18, wherein, The second part is in contact with the lowest insulating layer among the plurality of insulating layers.

Images