Memory and method of making the same

Abstract

The application provides a memory and a preparation method thereof. The memory comprises a plurality of memory cells, and the memory comprises: a silicon substrate, the silicon substrate is provided with a source end, and two adjacent memory cells share one source end; a control gate, located on one side of the source end, and two adjacent memory cells share one control gate; an erase gate, located on one side of the control gate, and the erase gates of two adjacent memory cells are symmetrically arranged relative to the control gate; a floating gate, located on one side of the silicon substrate, and the floating gates of two adjacent memory cells are symmetrically arranged relative to the control gate, and a tunneling oxide layer is arranged between the floating gate and the silicon substrate; and a selection gate, located on one side of the silicon substrate and located on one side of the floating gate away from the control gate, and a first oxide layer and an oxide isolation layer are arranged between the selection gate and the floating gate. The preparation method optimizes the isolation layer structure between the floating gate and the selection gate, and significantly improves the breakdown voltage and the erasing and writing durability of the memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, specifically to a memory and its fabrication method. Background Technology

[0002] Floating-gate embedded flash memory (eflash) is increasingly widely used in the non-volatile memory field due to its advantages of low cost, low power consumption, and high-speed access. As technology nodes shrink to 40nm and below, the market demand for high density, high performance, and high reliability is becoming increasingly urgent. Endurance is a key parameter for measuring eflash reliability, characterizing the maximum number of times the memory can remain operational after multiple program / erase cycles. Deterioration of gate-to-gate isolation performance is one of the important causes of endurance failure.

[0003] A typical existing memory device structure includes two symmetrical bits that share the same common source (CS), control gate (CG), and erase gate (EP). The select gate (SG) and floating gate (FG) can be read and written independently. Programming is achieved by channel hot electron injection (CHEI) into the floating gate, and erasing is achieved by electrons tunneling through the Fowler-Nordheim (FN) tunnel at the tip of the floating gate to the erase gate. This type of memory has strict requirements for the isolation performance between the gates, and its process window is related to the thickness and uniformity of the oxide or oxynitride between the gates. In traditional manufacturing processes, an ONO (SiO2 / Si3N4 / SiO2) sandwich isolation layer structure is used between the select gate (SG) and the floating gate (FG). However, during the subsequent nitride removal process of the common source electrode, phosphoric acid, while removing the silicon nitride (SIN) sidewalls of the common source electrode, also erodes the silicon nitride sidewalls between the select gate (SG) and the floating gate (FG). This results in a reduction in silicon nitride height, forming a divot defect. This defect grows according to the shape during the subsequent polysilicon deposition of the erase gate (EP), forming a downward-pointing sharp corner. This reduces the dielectric layer thickness between the erase gate (EP), the select gate (SG), and the control gate (CG), leading to poor uniformity and the formation of leakage current channels. Ultimately, this severely restricts the endurance testing of the memory, becoming a core bottleneck restricting product reliability. Therefore, it is urgent to develop a new isolation layer structure that can improve the inter-gate breakdown voltage while eliminating process defects to meet the requirements of high-reliability applications.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] To address the problems in the prior art, the purpose of this application is to provide a memory and a method for fabricating the same, wherein the fabrication method optimizes the isolation layer structure between the floating gate and the select gate, thereby significantly improving the breakdown voltage and write endurance of the memory.

[0006] A first aspect of this application provides a memory including a plurality of memory cells, the memory comprising: A silicon substrate, wherein a source terminal is provided in the silicon substrate, and two adjacent memory cells share one source terminal; A control gate is located on one side of the source end, and two adjacent memory cells share one control gate; An erase gate is located on one side of the control gate, and the erase gates of every two memory cells are symmetrically arranged relative to the control gate; A floating gate is located on one side of the silicon substrate. The floating gates of each pair of adjacent memory cells are symmetrically arranged with respect to the control gate. A tunneling oxide layer is disposed between the floating gate and the silicon substrate. A selection gate is located on one side of the silicon substrate and on the side of the floating gate opposite to the control gate. A first oxide layer and an oxide isolation layer are disposed between the selection gate and the floating gate.

[0007] According to the first aspect of this application, any of the following conditions must be met: (1) The tunneling oxide layer is grown using an in-situ steam generation process; (2) The first oxide layer is formed by a rapid thermal oxidation process or an in-situ steam generation process; (3) The oxide isolation layer is deposited using a chemical vapor deposition process.

[0008] According to the first aspect of this application, any of the following conditions must be met: (1) The thickness of the first oxide layer is 30~60 angstroms; (2) The thickness of the oxide isolation layer is 100~200 angstroms; (3) The thickness of the tunneling oxide layer is 90~110 angstroms.

[0009] A second aspect of this application provides a method for fabricating a memory, the method comprising the following steps: A silicon substrate is provided, on which a selection gate is formed, and on top of the selection gate a hard mask layer is formed; A first oxide layer is formed on the silicon substrate between the sidewall of the selection gate and the selection gate; An oxide isolation layer is formed on the hard mask layer and the first oxide layer; Remove the oxide isolation layer and the first oxide layer on the silicon substrate between the select gates; A tunneling oxide layer is formed on the silicon substrate between the selected gates.

[0010] According to the second aspect of this application, any of the following conditions must be met: (1) The oxide isolation layer comprises silicon dioxide; (2) The thickness of the hard mask layer is 800~1000 angstroms.

[0011] According to a second aspect of this application, the process for forming the first oxide layer includes a rapid thermal oxidation process; and / or

[0012] The process for forming the oxide isolation layer includes chemical vapor deposition.

[0013] According to a second aspect of this application, the process for removing the oxide isolation layer and the second oxide layer on the silicon substrate between the select gates includes a dry etching process.

[0014] According to a second aspect of this application, the process for removing the oxide isolation layer and the second oxide layer on the silicon substrate between the select gates includes a maskless etching process, wherein the etching gas used in the maskless etching process includes at least one of CF4, CHF3 and Ar.

[0015] According to a second aspect of this application, the process for forming the tunnel oxide layer includes an in-situ steam generation process.

[0016] According to a second aspect of this application, forming the tunneling oxide layer includes the following sub-steps: The silicon substrate is oxidized by introducing hydrogen-containing gas and oxygen-containing gas. A nitrogen-oxygen compound gas is introduced to anneal the silicon substrate, forming a tunneling oxide layer.

[0017] In the memory fabrication method of this application, the isolation layer between the select gate and the floating gate adopts an oxide film structure of "bottom oxide film + isolation oxide film + high-temperature densification treatment". This isolation layer structure completely eliminates the silicon nitride film layer in the traditional ONO (silicon oxide / silicon nitride / silicon oxide) isolation layer, thus eliminating the material factors that cause divot defects at the source. After the above process optimization, the breakdown voltage between the select gate and the floating gate can be greatly improved. The improved withstand voltage level of this isolation layer means that the isolation layer can effectively resist electric field stress during high-voltage erase and write operations of the device, avoiding memory cell failure caused by local breakdown or leakage channel formation. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0019] Figure 1 This is a cross-sectional schematic diagram of a memory according to an embodiment of this application; Figure 2 This is a flowchart of a method for fabricating a memory according to an embodiment of this application; Figures 3-8 This is a schematic diagram of the fabrication process of a memory according to an embodiment of this application; Figure 9 and Figure 10 The figures show the erase / write cycle endurance test results of a prior art memory and a memory according to an embodiment of this application. Detailed Implementation

[0020] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted. The words “or” and “or” in the specification may mean “and” or “or”. Spatial relation terms such as “…above” are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, the element or feature described as “…above” will be oriented “…below” other elements or features. Therefore, the exemplary term “…above” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0021] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items. Although “first” or “second,” etc., are used in this specification to denote certain features, this is merely indicative of function and not a limitation on the number or importance of the specific features.

[0022] The memory and its preparation method of the present invention are further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments are not intended to limit the scope of protection of the present invention.

[0023] This application also provides a storage device. Figure 1 This is a cross-sectional schematic diagram of a memory according to an embodiment of this application. Specifically, the memory includes: A silicon substrate 1 is provided with a source terminal CS. Adjacent memory cells share the same source terminal CS to achieve higher integration.

[0024] The control gate (CG) is located on one side of the source terminal (CS). Two adjacent memory cells share the same control gate (CG), which is typically made of polysilicon and is used to control the switching state of the memory cells during programming or read operations.

[0025] The erase gate EP is located on one side of the control gate CG. The erase gates EP1 and EP2 of each pair of adjacent memory cells are symmetrically arranged with respect to the control gate CG. The erase gate EP is used to provide an erase voltage during the erase operation, so that the charge stored in the floating gate FG is injected into the erase gate EP through FN tunneling (Fowler-Nordheim tunneling), thereby realizing the erasure of data.

[0026] A floating gate (FG) is located on one side of the silicon substrate 1, between the control gate (CG) and the select gate. The floating gates FG1 and FG2 of every two adjacent memory cells are symmetrically arranged relative to the control gate (CG). In this embodiment, the cross-sections of the floating gates FG1 and FG2 are triangular, with the apex of the triangle facing the control gate (CG) to enhance the electric field concentration effect at the apex and improve the FN tunneling erase efficiency. A tunneling oxide layer (6) is disposed between the floating gates FG1 and FG2 and the silicon substrate 1. This tunneling oxide layer acts as a barrier layer for charge carrier tunneling, and its thickness directly affects the erase / write efficiency and data retention capability of the memory cell. In this embodiment, the tunneling oxide layer is grown using an in-situ vapor generation (ISSG) process, which can form a highly dense and uniform silicon oxide film, thereby improving the quality and reliability of the tunneling oxide layer. Preferably, the thickness of the tunneling oxide layer is 90-110 angstroms.

[0027] The select gate SG is located on one side of the silicon substrate 1 and on the side of the floating gate FG opposite to the control gate CG. Similarly, the select gates SG1 and SG2 of each pair of adjacent memory cells are symmetrically arranged with respect to the control gate CG. A first oxide layer and an oxide isolation layer are provided between the select gate SG1 and the floating gate FG1, and between the select gate SG2 and the floating gate FG2. The first oxide layer covers the sidewall of the select gate and can be formed using a rapid thermal oxidation (RTO) process or an in-situ vapor generation (ISSG) process. The thickness of the first oxide layer is between 30 and 60 angstroms. This RTO first oxide layer serves as the bottom oxide film of the isolation dielectric layer between the select gate and the floating gate. The oxide isolation layer covers the first oxide layer and can be deposited using a chemical vapor deposition process, preferably a low-pressure chemical vapor deposition (LPCVD) high-temperature oxidation (HTO) process. This oxide isolation layer serves as the main dielectric isolation film layer between the select gate and the floating gate, and its thickness is controlled between 100 and 200 angstroms, which can effectively improve the breakdown voltage between the gates.

[0028] This invention provides a method for fabricating a memory. Figure 2 This is a flowchart of a method for fabricating a memory according to an embodiment of this application. Specifically, the method for fabricating the memory includes the following steps: Step S100: A silicon substrate 1 is provided. The silicon substrate 1 may be a single-crystal silicon substrate or other silicon-based materials suitable for semiconductor device manufacturing. A plurality of discrete selection gates 2 are formed on the silicon substrate 1, and a hard mask layer 3 is formed on top of each selection gate 2.

[0029] The select gate 2 is typically made of polycrystalline silicon. In actual fabrication, a select gate material layer and a hard mask layer are deposited sequentially on a silicon substrate 1. For example, a polycrystalline silicon thin film can be deposited on the surface of the silicon substrate 1 using a low-pressure chemical vapor deposition (LPCVD) process as the subsequent select gate material layer. The thickness of this polycrystalline silicon thin film can be controlled according to the device design requirements. Subsequently, a hard mask layer 3 is formed on top of the polycrystalline silicon thin film using a chemical vapor deposition process. The material of this hard mask layer 3 is preferably silicon dioxide. Next, the hard mask layer is patterned. Specifically, a photoresist layer is spin-coated onto the surface of the hard mask layer, and the pattern of the select gate is defined on the photoresist layer using a photolithography process (including exposure, development, etc.). Then, using this patterned photoresist layer as a mask, an anisotropic dry etching process (e.g., reactive ion etching) is used to etch the exposed hard mask layer, transferring the pattern on the photoresist to the hard mask layer, forming the patterned hard mask layer 3. The remaining photoresist layer is removed using a photoresist stripping process. Subsequently, the polysilicon select gate material layer is etched using this patterned hard mask layer as a mask. This etching step preferably employs an anisotropic dry etching process (e.g., reactive ion etching) to precisely control the etching profile. The etching process continues until the surface of the silicon substrate 1 beneath the select gate material layer is exposed, thereby dividing the polysilicon thin film into multiple discrete and isolated select gates 2. The patterned hard mask layer 3 serves as a hard mask during the select gate etching process. After etching, multiple discrete select gates 2, each topped with the hard mask layer 3, are obtained on the silicon substrate 1, as shown below. Figure 3 As shown, this structure is the starting structure for subsequent processes.

[0030] After the selection gate 2 is etched and shaped, step S200 is performed, that is, a first oxide layer is formed on the sidewalls of the selection gate 2 and on the silicon substrate 1 between the selection gates 2. In this embodiment, the first oxide layer can be formed using a rapid thermal oxidation (RTO) process or an in-situ vapor generation (ISSG) process. Specifically, the first oxide layer includes a first oxide layer 41 located on the sidewalls of the selection gate 2 and a first oxide layer 42 located on the surface of the silicon substrate 1 between the selection gates 2, such as... Figure 4 As shown.

[0031] In step S200, the temperature of the rapid thermal oxidation process is preferably controlled at 1000~1100℃, the processing time is 10~60 seconds, and the thickness of the first oxide layer is between 30~60 angstroms. This step has a dual function: on the one hand, the high-temperature oxidation environment can grow a dense oxide film on the sidewalls of the select gate 2 and the exposed silicon substrate surface, serving as the bottom oxide film in the subsequent isolation dielectric layer; on the other hand, this high-temperature rapid oxidation process can effectively repair the lattice damage introduced by plasma bombardment during the select gate etching process on the silicon sidewalls and substrate surface, eliminating the defect states left by etching, which is crucial for suppressing leakage channels in the device.

[0032] Subsequently, step S300 is performed: an oxide isolation layer is deposited over the silicon substrate 1 between the hard mask layer 3 and the select gate 2. This oxide isolation layer comprises silicon dioxide, and the deposition process is preferably chemical vapor deposition (CVD), more preferably low-pressure chemical vapor deposition (LPCVD) with high-temperature oxidation (HTO). In this embodiment, the thickness of the oxide isolation layer is controlled to be 100-200 angstroms.

[0033] After deposition, the oxide isolation layer covers the entire wafer surface, specifically including: an oxide isolation layer 51 above the first oxide layer 41, an oxide isolation layer 52 above the first oxide layer 42, and an oxide isolation layer 53 above the hard mask layer 3 on top of the select gate 2, as shown below. Figure 5 As shown, the HTO oxide isolation layer serves as the primary dielectric film (main isolation oxide film) separating the sidewall of the select gate from the floating gate. Its thickness and uniformity directly affect the device's breakdown voltage characteristics. Here, an oxide film structure replaces the traditional ONO (silicon oxide / silicon nitride / silicon oxide) sandwich structure, fundamentally avoiding subsequent divot defects caused by the introduction of the silicon nitride film layer.

[0034] After the oxide isolation layer is deposited, step S400 is performed: the oxide isolation layer 52 and the first oxide layer 42 deposited on the silicon substrate 1 between the select gates 2 are removed until the surface of the silicon substrate 1 of the select gates 2 is exposed. In this embodiment, the above structure can be etched using a maskless etching process, preferably a dry etching process, using an etching gas including at least one of CF4, CHF3, and Ar, such as a CHF3 / Ar mixed gas, a CF4 / Ar mixed gas, or a CF4 / CHF3 / Ar mixed gas. Due to the anisotropic nature of dry etching, this step can vertically remove the oxide layer located on top of the select gates 2 (i.e., the oxide isolation layer 53 and part of the hard mask layer 3) and between the select gates 2 (i.e., the oxide isolation layer 52 on the surface of the silicon substrate 1 and the first oxide layer 42 below it), until the surface of the silicon substrate between the select gates 2 is exposed.

[0035] In step S400, the oxide isolation layer 51 located on the sidewall of the selection gate 2 is still retained due to the blocking effect in the sidewall direction, forming the sidewall structure of the selection gate 2, such as... Figure 6 As shown. This step does not require an additional photomask.

[0036] Step S500: A tunneling oxide layer 6 is grown on the surface of the silicon substrate 1 between the selected gates 2, such as... Figure 7As shown. The thickness of the tunneling oxide layer 6 is preferably controlled between 90 and 110 angstroms. In this embodiment, the tunneling oxide layer 6 is grown using an in-situ vapor generation (ISSG) process, which involves high-temperature densification of the silicon substrate, specifically including the following sub-steps: First, hydrogen-containing gas (such as H2) and oxygen-containing gas (such as O2) are introduced into the growth chamber. At a high temperature of 900~1100°C, the hydrogen and oxygen react directly to generate highly reactive oxygen free radicals, which strongly oxidize the exposed silicon substrate 1 surface, forming a highly dense and uniform silicon oxide film as the tunneling oxide layer 6. Because the reactivity of oxygen free radicals is much higher than that of ordinary oxygen molecules, the oxide layer grown by the ISSG process exhibits excellent thickness uniformity and high density on the wafer surface and in the trenches.

[0037] Subsequently, the gas in the growth chamber is switched to a nitrogen-oxygen compound gas (such as N2O and / or NO), and the silicon substrate is annealed at a high temperature. This annealing step can passivate the dangling bonds at the interface between the tunneling oxide layer 6 and the silicon substrate 1, reduce the interface trap density, and thus improve the device erasure efficiency. On the other hand, this high-temperature heat treatment process also densifies the formed oxide isolation layer (especially the oxide isolation layer 51 on the sidewall), improving the resistance of the isolation dielectric layer to electric field stress breakdown.

[0038] During the growth of the tunnel oxide layer 6 in the ISSG process, the high-temperature environment also densifies the already formed oxide isolation layer 51, further improving its resistance to electric field stress breakdown. It should be noted that during the ISSG process, since the sidewalls of the select gate 2 are already covered by the first oxide layer 41 formed by the RTO process and the oxide isolation layer 51 formed by the HTO process, new oxide layers will almost never grow on the sidewalls of the polysilicon select gate 2. However, optimizing the thermal treatment of the existing oxide film layer on the sidewalls under high-temperature conditions is a key step in improving device reliability.

[0039] Those skilled in the art will understand that, after the above steps are completed, the method for fabricating the memory further includes depositing a floating gate layer 7 (such as...) on the substrate after step 500. Figure 8 (as shown), and the subsequent fabrication steps for the control gate, erase gate, and source. The deposition, patterning, and etching processes for these structures can be performed according to existing process flows, and will not be elaborated here.

[0040] In the memory fabrication method of this application, the isolation layer between the select gate 2 and the floating gate adopts an oxide film structure of "bottom oxide film + main isolation oxide film + high-temperature densification treatment". This isolation layer structure completely eliminates the silicon nitride film layer in the traditional ONO (silicon oxide / silicon nitride / silicon oxide) isolation layer, thus eliminating the material factors that cause divot defects at the source. After the above process optimization, the breakdown voltage between the select gate 2 and the floating gate can be greatly improved. The improved withstand voltage level of this isolation layer means that the isolation layer can effectively resist electric field stress during high-voltage erase and write operations of the device, avoiding memory cell failure caused by local breakdown or leakage channel formation.

[0041] As those skilled in the art know, endurance testing is a core indicator for measuring the reliability of non-volatile memory. It simulates the actual lifespan of a device by repeatedly executing erase / write cycles (P / EC cycles). Endurance tests were performed on existing memory and a memory according to an embodiment of this application. The endurance testing method can refer to the JEDEC JESD22-A117E standard. Specifically, the memory sample was subjected to program / erase cycles, and the cycles were sequentially repeated to 1% (1000 times), 10% (10000 times), and 100% (100000 times) of the maximum number of cycles. After the cycle was completed, the current values ​​in the programmed and erased states were read and compared with the initial values. The degree of current degradation was determined according to the product specifications to see if it was within the allowable range. Figure 9 and Figure 10 The figures show the program-erase cycle endurance test results of a prior art memory and a memory according to an embodiment of this application. In the prior art memory, the select gate SG and the floating gate FG adopt a conventional ONO isolation layer structure. Figure 9 and Figure 10 The curves in the figure represent the device characteristic curves after the initial state, 1K, 10K, and 100K erase / write cycles, respectively. The horizontal axis represents the physical parameters of the memory cell, the vertical axis represents the voltage, and the dashed line position is the critical withstand voltage reference position.

[0042] like Figure 9As shown, the curve of existing memory technologies continuously shifts to the left with each erase / write cycle. At 100K cycles (blue curve), the withstand voltage threshold of the dashed line on the left has been significantly exceeded, the gate-to-gate breakdown voltage deteriorates, device characteristics are significantly degraded, and the device fails its durability test, failing the 100K erase / write cycle reliability assessment. It can be seen that the traditional SG-FG isolation layer structure has insufficient withstand voltage; after multiple Program / Erase cycles, the isolation layer suffers charge damage, the gate-to-gate breakdown voltage decreases, and the device performance deteriorates and fails.

[0043] The memory of one embodiment of this application, such as Figure 10 As shown, after undergoing initial, 1K, 10K, and 100K erase / write cycles, although each curve shifts to the left with increasing cycle count, the curve after 100K cycles remains to the right of the dashed voltage withstand boundary. After 100K cycles, the gate breakdown voltage (BV) remains ≥20V, and the device's electrical characteristics are fully preserved, successfully passing the 100K Program / Erase cycle durability and reliability test.

[0044] In summary, the isolation layer between the select gate and the floating gate of the memory in this application adopts an oxide film structure of "bottom oxide film + main isolation oxide film + high-temperature densification treatment". This design avoids the divot defects caused by the introduction of silicon nitride film layer in the subsequent process of traditional isolation layer structure from the material level, thereby eliminating the leakage path between the select gate and the floating gate, significantly improving the breakdown voltage between the gates (up to 20V or more), suppressing the isolation layer damage caused by repeated erase and write cycles, and enabling the erase and write cycle durability of the memory to reach more than 100K cycles, thus solving the pain point of memory endurance failure.

[0045] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A memory, characterized in that, The memory includes multiple storage units, and the memory includes: A silicon substrate, wherein a source terminal is provided in the silicon substrate, and two adjacent memory cells share one source terminal; A control gate is located on one side of the source end, and two adjacent memory cells share one control gate; An erase gate is located on one side of the control gate, and the erase gates of two adjacent memory cells are symmetrically arranged with respect to the control gate; A floating gate is located on one side of the silicon substrate, and the floating gates of two adjacent memory cells are symmetrically arranged with respect to the control gate. A tunneling oxide layer is disposed between the floating gate and the silicon substrate. A selection gate is located on one side of the silicon substrate and on the side of the floating gate opposite to the control gate. A first oxide layer and an oxide isolation layer are disposed between the selection gate and the floating gate.

2. The memory according to claim 1, characterized in that, Meet any of the following conditions: (1) The tunneling oxide layer is grown using an in-situ steam generation process; (2) The first oxide layer is formed by a rapid thermal oxidation process or an in-situ steam generation process; (3) The oxide isolation layer is deposited using a chemical vapor deposition process.

3. The memory according to claim 1, characterized in that, Meet any of the following conditions: (1) The thickness of the first oxide layer is 30~60 angstroms; (2) The thickness of the oxide isolation layer is 100~200 angstroms; (3) The thickness of the tunneling oxide layer is 90~110 angstroms.

4. A method for fabricating a memory, characterized in that, The preparation method includes the following steps: A silicon substrate is provided, on which a selection gate is formed, and on top of the selection gate a hard mask layer is formed; A first oxide layer is formed on the silicon substrate between the sidewall of the selection gate and the selection gate; An oxide isolation layer is formed on the hard mask layer and the first oxide layer; Remove the oxide isolation layer and the first oxide layer on the silicon substrate between the select gates; A tunneling oxide layer is formed on the silicon substrate between the selected gates.

5. The method for fabricating a memory according to claim 4, characterized in that, Meet any of the following conditions: (1) The oxide isolation layer comprises silicon dioxide; (2) The thickness of the hard mask layer is 800~1000 angstroms.

6. The method for fabricating a memory according to claim 4, characterized in that, The process for forming the first oxide layer includes a rapid thermal oxidation process; and / or The process for forming the oxide isolation layer includes chemical vapor deposition.

7. The method for fabricating a memory according to claim 4, characterized in that, The process for removing the oxide isolation layer and the first oxide layer on the silicon substrate between the select gates includes a dry etching process.

8. The method for fabricating a memory according to claim 4 or 7, characterized in that, The process for removing the oxide isolation layer and the first oxide layer on the silicon substrate between the select gates includes a maskless etching process, wherein the etching gas used in the maskless etching process includes at least one of CF4, CHF3 and Ar.

9. The method for fabricating a memory according to claim 4, characterized in that, The process for forming the tunnel oxide layer includes an in-situ steam generation process.

10. The method for fabricating a memory according to claim 4 or 9, characterized in that, The formation of the tunneling oxide layer includes the following sub-steps: The silicon substrate is oxidized by introducing hydrogen-containing gas and oxygen-containing gas. A nitrogen-oxygen compound gas is introduced to anneal the silicon substrate, forming a tunneling oxide layer.

Images