Method of manufacturing memory elements

Abstract

A method for fabricating a memory device includes forming a two-layer structure on a substrate, the two-layer structure including a floating gate, a control gate, and a hard mask, forming a polysilicon layer between the two-layer structure and an outer side, and performing a photolithography process to pattern the two hard masks and the polysilicon layer, thereby forming a contact opening in each of the hard masks to expose the control gate, and converting the polysilicon layer outside the two-layer structure into two word lines.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing memory devices that integrates hard mask opening and word line patterning steps. Specifically, it can be applied to high-efficiency / low-power / low-leakage logic devices, mixed-signal devices, embedded memories, BCD (Bipolar-CMOS-DMOS), high-voltage devices, and other related products and manufacturing processes using polysilicon gate / high dielectric metal gate. Background Technology

[0002] Split-gate non-volatile flash memory cells with select gates, floating gates, control gates, and erase gates are well-known existing technologies. It is also common practice to form logic elements (i.e., low-voltage and / or high-voltage logic elements) on the same silicon chip. This allows for the sharing of some fabrication steps between the memory and logic elements (e.g., using the same polysilicon deposition step to simultaneously form the gates for both memory and logic elements). This type of memory, formed together with logic elements, can be called embedded memory, which offers advantages such as high integration, space and cost savings, and enhanced performance.

[0003] However, other fabrication steps in forming embedded memory can affect logic elements, and vice versa. Therefore, fabricating both types of elements on the same wafer is typically complex and difficult. Consequently, those skilled in the art need to focus on reducing the number of fabrication steps in embedded memory to lower costs and cycle times, thereby enhancing product competitiveness. Summary of the Invention

[0004] In view of the problems encountered in the prior art, the present invention proposes a novel method for manufacturing memory elements, characterized in that the hard mask contact opening and word line patterning of the memory cell are integrated in the same manufacturing process, thus saving the related photomask and photolithography steps.

[0005] The present invention aims to provide a method for manufacturing a memory element, the steps of which include: providing a substrate; sequentially forming a first insulating layer, a first silicon layer, a second insulating layer, a second silicon layer, and a mask layer on the substrate; patterning the mask layer, the second silicon layer, and the second insulating layer into a two-layer structure, wherein the mask layer, the second silicon layer, and the second insulating layer are respectively transformed into a hard mask, a control gate, and a barrier oxide layer in each of the two-layer structures; and patterning the first silicon layer and the first insulating layer respectively. The control gate is formed in each of the two stacked structures as a floating gate and a tunneling oxide layer; a source is formed in the substrate between the two stacked structures; a polysilicon layer is formed between and on the outside of the two stacked structures; a photolithography process is performed to pattern the two hard masks and the polysilicon layer, such that a contact opening is formed in each hard mask to expose the control gate, and the polysilicon layer on the outside of the two stacked structures is transformed into two word lines; a drain is formed on the outside of the two word lines respectively; and contacts are formed in the two contact openings to connect the two control gates.

[0006] Specifically, this invention is applicable to high-efficiency / low-power / low-leakage logic devices, mixed-signal devices, embedded memories, BCD (Bipolar-CMOS-DMOS), high-voltage devices, and other related products and manufacturing processes using polysilicon gate / high dielectric metal gate.

[0007] These and other objects of the invention should become more apparent to the reader after reading the detailed description of the preferred embodiments, which are illustrated in various figures and drawings below. Attached Figure Description

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 as well as Figure 13 This is a cross-sectional schematic diagram of the manufacturing process of a memory element according to Embodiment 1 of the present invention.

[0009] It should be noted that all illustrations in this specification are for illustrative purposes. For clarity and ease of illustration, the size and scale of the components in the illustrations may be exaggerated or reduced. Generally, the same reference symbols in the illustrations are used to indicate corresponding or similar component features in modified or different embodiments.

[0010] Symbol explanation:

[0011] 100 base

[0012] 102 First Insulation Layer

[0013] 102a Tunneling Oxide Layer

[0014] 104 First silicon layer

[0015] 106 Second Insulation Layer

[0016] 106a barrier oxide layer

[0017] 108 Second silicon layer

[0018] 110 Mask layer

[0019] 110a Hard Mask

[0020] 110b Contact opening

[0021] 112 First Spacing Layer

[0022] 114 Second Spacing Layer

[0023] 116 partition wall

[0024] 118 Third Spacing Layer

[0025] 120 Photoresist

[0026] 122 Silica spacer wall

[0027] 123 Silicon oxide layer

[0028] 124 Photoresist

[0029] 130 Photoresist

[0030] 132 Insulation Layer

[0031] 134a polycrystalline silicon layer

[0032] 134b polycrystalline silicon layer

[0033] 136 Photoresist

[0034] 136a Opening

[0035] 138 lightly doped drain

[0036] 139 partition wall

[0037] 140 contact hole

[0038] 141 interlayer dielectric layer

[0039] 142 Contacts

[0040] CG control grid

[0041] D drain

[0042] EG erase gate

[0043] FG Floating Gate

[0044] I1 ion implantation fabrication process

[0045] I2 ion implantation fabrication process

[0046] S source pole

[0047] S1 stacked structure

[0048] S2 stacked structure

[0049] WL lettering Detailed Implementation

[0050] Exemplary embodiments of the present invention will now be described in detail below, with reference to the accompanying drawings illustrating the described features to enable the reader to understand and achieve the technical effects. The reader will understand that the descriptions herein are merely illustrative and are not intended to limit the scope of the invention. Various embodiments of the invention and various non-conflicting features thereof can be combined or rearranged in various ways. Modifications, equivalents, or improvements to the invention will be understood by those skilled in the art without departing from the spirit and scope of the invention, and are intended to be included within the scope of the invention.

[0051] Readers should readily understand that the meanings of "on," "above," and "above" in this context should be interpreted broadly. "On" not only means "directly on" something, but also includes being "on" something with an intervening feature or layering structure. Similarly, "above" or "above" not only means "above" or "above" something, but also includes being "above" or "above" something without an intervening feature or layering structure (i.e., directly on something). Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to describe the relationship between one element or feature and one or more other elements or features, as shown in the accompanying drawings.

[0052] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a extent smaller than that of the structure below or above. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any opposing horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along an inclined surface. A substrate may be a layered structure, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0053] Readers can generally understand the terminology used in this invention, at least in part, from its usage in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," "the," or "described" can also be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.

[0054] Readers will better understand that when words such as "comprising" and / or "containing" are used in this specification, they expressly define the presence of the stated features, areas, wholes, steps, operations, elements and / or components, but do not preclude the possibility of the presence or addition of one or more other features, areas, wholes, steps, operations, elements, components and / or combinations thereof.

[0055] The text uses designations such as "N" and "P," generally referring to donor and acceptor dopants that promote electron-hole transport, such as P-type boron (B) atoms or N-type phosphorus (P) and arsenic (As) atoms. A dopant type ending in "++" indicates a higher doping concentration than dopants ending in "+". Conversely, a dopant type ending in "-" indicates a lower doping concentration than dopants without a suffix.

[0056] The following text will now refer to the following in sequence. Figures 1 to 12To illustrate embodiments of the method of the present invention, these cross-sectional views illustrate the steps of fabricating pairs of memory cells in a memory cell region of a substrate. The paired memory cells referred to herein may be memory based on the ESF3 (3rd-Gen Embedded SuperFlash) architecture, where the two memory cells share a source line and an erase gate, and the structure includes components such as a word line, control gate, floating gate, and bit line as select gates. However, it should be noted that although the embodiments show an ESF3 architecture memory, the present invention is not limited to this type of memory, but can also be applied to memories with the same inventive concept and corresponding features, and is not limited thereto. Furthermore, unless otherwise specified, all types of material layers described herein and in the figures can be formed using suitable deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and other deposition processes.

[0057] First, please refer to... Figure 1 The process begins by forming a first insulating layer 102, such as a silicon oxide layer, on a substrate 100 (e.g., a P-type monocrystalline silicon substrate). This layer serves as a tunnel oxide layer between the substrate 100 and the floating gate to be formed subsequently. Next, a first silicon layer 104, which can be made of monocrystalline silicon or amorphous silicon, is formed on the first insulating layer 102. This first silicon layer 104 can then be patterned into strip-shaped active regions (not shown) using a photolithography process to further divide it into floating gates in subsequent fabrication processes. Following this, a second insulating layer 106, which can be made of silicon oxide or an ONO composite layer composed of silicon oxide / silicon nitride / silicon oxide layers, is formed on the first silicon layer 104. This layer serves as a blocking oxide layer between the floating gate and the control gate in the memory element. Finally, a second silicon layer 108, which can be made of monocrystalline silicon or amorphous silicon, is formed on the second insulating layer 106. This layer serves as the material layer for the control gate to be formed subsequently. Subsequently, a mask layer 110 is formed on the second silicon layer 108. The material of the mask layer 110 can be silicon nitride, an ONO composite layer, or a NON composite layer composed of silicon nitride / silicon oxide / silicon nitride layers, which is used as a hard mask in the subsequent etching process.

[0058] Please refer to Figure 2After forming the above-mentioned layer structure, a photolithography process is then performed to pattern the mask layer 110, the second silicon layer 108, and the second insulating layer 106 in the layer structure, thus forming the paired stacked structures S1 and S2 as shown in the figure. Specifically, in this step, a photoresist with a stacked pattern is used as a mask to perform an anisotropic etching process to remove the uncovered parts of the mask layer 110, the second silicon layer 108, and the second insulating layer 106 until the underlying first silicon layer 104 is exposed. In this step, the patterned second silicon layer 108 becomes the control gate CG of the memory cell, the second insulating layer 106 becomes the barrier oxide layer 106a between the control gate CG and the floating gate to be formed subsequently, and the mask layer 110 becomes the hard mask 110a of the memory cell. In the embodiment, the region located between the two stacked structures S1 and S2 is called the inner region, and the region located outside the two stacked structures S1 and S2 is called the outer region.

[0059] Please refer to Figure 3 After the control gate CG is formed in the stacked structures S1 and S2, a first spacer layer 112 and a second spacer layer 114 are sequentially formed on the stacked structures S1 and S2. The materials of the first spacer layer 112 and the second spacer layer 114 can be silicon oxide and silicon nitride, respectively, and are not limited thereto. Then, an anisotropic etching process is performed on the first spacer layer 112 and the second spacer layer 114 to form a composite spacer wall 116 composed of the first spacer layer 112 and the second spacer layer 114 on the sidewall of the stacked structures S1 and S2, wherein the first spacer layer 112 is located inside the spacer wall 116 and the second spacer layer 114 is located outside the spacer wall 116. In this embodiment, the spacer wall 116 is used to protect the formed hard mask 110a and the control gate CG, and can be used to define the subsequent floating gate pattern.

[0060] Please refer to Figure 4After the spacer 116 is formed, a third spacer layer 118 is then formed on the spacer 116. The third spacer layer 118 can be made of silicon oxide, and its formation method can be the same as that of the spacer 116, by first forming a material layer on the surface of the stacked structures S1, S2 and then performing an anisotropic etching process. After the third spacer layer 118 is formed, a photoresist 120 is then formed on the inner region between the stacked structures S1, S2. In the embodiment, the photoresist 120 completely covers the inner region and partially covers the stacked structures S1, S2, but does not cover the spacer 116 portion on the outer region. Then, using the photoresist 120 as a mask, an isotropic etching process is performed to remove the exposed third spacer layer 118 on the outer region. Thus, the spacer 116 located on the outer region will only contain the first spacer layer 112 and the second spacer layer 114, while the spacer 116 located on the inner region will contain a three-layer structure consisting of the first spacer layer 112, the second spacer layer 114, and the third spacer layer 118. The different thicknesses of the inner and outer spacers can define the desired grating pattern in subsequent manufacturing processes.

[0061] Please refer to Figure 5 After removing the third spacer layer 118 on the outer region, the photoresist 120 is then removed. Anisotropic etching is then performed using the stacked structure S1, S2 plus the inner and outer spacer walls 116 as a mask to pattern the first silicon layer 104 and the first insulating layer 102. Thus, the first silicon layer 104 becomes the floating gate FG of the memory cell, and the first insulating layer 102 becomes the tunneling oxide layer 102a between the floating gate FG and the substrate 100, completing the full definition of the stacked structure S1, S2 of the memory cell of the present invention. From top to bottom, this includes the hard mask 110a, the control gate CG, the barrier oxide layer 106a, the floating gate FG, and the tunneling oxide layer 102a. It can be seen that due to the presence of the third spacer layer 118, the floating gate FG in the embodiment extends horizontally inward beyond the upper control gate CG, thereby improving electric field control, increasing memory density, and enhancing programming and erasing efficiency. In one embodiment, a portion of the thinner first insulating layer 102 may be left on the substrate 100 to prevent damage to the substrate 100.

[0062] Please refer to Figure 6After the floating gate FG and tunneling oxide layer 102a are formed, a silicon monoxide layer is formed on the stacked structures S1 and S2, followed by an anisotropic etching process to form silicon oxide spacers 122 on the sidewalls of the stacked structures S1 and S2 and a silicon monoxide layer 123 on the substrate 100. This step may also remove part of the first spacer layer 112, which is also made of silicon oxide. Next, a photoresist 124 is formed on the outer region of the stacked structures S1 and S2. In this embodiment, the photoresist 124 completely covers the outer region and part of the stacked structures S1 and S2, but does not cover the spacers 116 located in the inner region, thus leaving an opening between the stacked structures S1 and S2. Then, an ion implantation process is performed using the photoresist 124 and the stacked structures S1 and S2 as a mask to dope and form a source electrode 126 in the substrate 100. Next, an etching process, such as wet etching, is performed to remove the silicon oxide layer 123 and silicon oxide spacer 122 in the internal region, thus forming the structure shown in the figure. It can be seen that in this embodiment, the formed source 126 is shared by the stacked structures S1 and S2 (memory cells) on both sides, which can also be called a source line.

[0063] Please refer to Figure 7 After the source electrode S is formed, the photoresist 124 on the outer region is removed, and a high-temperature thermal annealing process is performed to activate the implanted ions, thus completing the diffusion and final shaping of the source electrode S. Next, a conformal insulating layer 128 is formed over the entire structure. The insulating layer 128 covers the surfaces of the substrate 100 and the stacked structures S1 and S2. Then, a photoresist 130 is formed on the inner region between the stacked structures S1 and S2. In this embodiment, the photoresist 130 completely covers the inner region and partially covers the insulating layer 128, but does not cover the portion of the insulating layer 128 located on the outer region. Then, using the photoresist 130 as a mask, an anisotropic dry etching process and an isotropic wet etching process are performed to remove the insulating layer 128 on the outer region and the silicon oxide layer 123 on the substrate 100. This step also reduces the thickness of the silicon oxide spacer 122 on the outer side of the stacked structures S1 and S2, resulting in... Figure 7 The structure shown is illustrated. The remaining insulating layer 128 on the internal region will serve as the gate insulating layer between the gate and the substrate for subsequent erasure. In this embodiment, the source S of the substrate 100 may also be partially oxidized to increase the thickness of the insulating layer 128 above the source S.

[0064] Please refer to Figure 8After the insulating layer 128 is formed, the photoresist 130 is removed, and another conformal insulating layer 132 is formed over the entire structure. The insulating layer 132 preferably comprises a first thin silicon oxide layer as an interface layer (IL) and a second high-k material layer (having a dielectric constant K greater than that of silicon oxide, such as HfO2, ZrO2, TiO2, Ta2O5, or other suitable materials). The threshold voltage for the select gate (word line) of the split-gate flash memory cell can be adjusted by changing the thickness of the insulating layer 132. A capping layer, such as TiN, TaN, or TiSiN, may also be included in the insulating layer 132 to protect the high-k material layer from damage in subsequent processing steps.

[0065] Rereference Figure 8 After the insulating layer 132 is formed, the photoresist 130 is removed, and a polysilicon layer is deposited over the entire structure. Subsequently, a chemical mechanical planarization process is performed to remove structures above a certain height, thus obtaining the structure shown below. Figure 8 The diagram shows polysilicon layers 134a in the inner region and 134b in the outer region. It can be seen that the formed polysilicon layers 134a and 134b are flush with the hard mask 110a of the stacked structures S1 and S2. In this invention, the polysilicon layer 134a serves as the material layer for the erase gate of the memory element to be formed subsequently, and the polysilicon layer 134b serves as the material layer for the word line (i.e., select gate) of the memory element to be formed subsequently. The polysilicon layers 134a and 134b can also serve as logic gate material layers in the wafer logic regions (including core logic and non-core logic regions).

[0066] Please refer to Figure 9 After the polysilicon layers 134a and 134b are formed, an etching process is then performed to remove portions of the polysilicon layers 134a and 134b, causing their height to drop below the top surface of the mask layer 110. In this way, the polysilicon layer 134a located in the inner region between the stacked structures S1 and S2 is transformed into the erase gate EG of the memory cell, while the polysilicon layer 134b located in the outer region outside the stacked structures S1 and S2 can form word lines in subsequent fabrication processes.

[0067] Please refer to Figure 10After the erase gate EG is formed, a photoresist 136 is then formed on the substrate 100. In this embodiment, the photoresist 136 covers the stacked structures S1 and S2 and defines the word line edges to be formed on the outer side of the stacked structures S1 and S2. Furthermore, unlike the prior art, in this embodiment of the invention, the photoresist 136 also has two openings 136a, which are respectively located above the hard mask 110a of the two stacked structures S1 and S2, for forming contact openings in the hard mask 110a. After the photoresist 136 is formed, an anisotropic etching process is then performed to remove the exposed polysilicon layer 134b and the hard mask 110a. Thus, the polysilicon layer 134b located on the outer region of the stacked structures S1 and S2 is transformed into the word line WL, and the contact opening 110b is formed in the hard mask 110a to expose the underlying control gate CG.

[0068] In existing technologies, the contact opening 110b of the aforementioned memory cell is formed through a separate manufacturing process. That is, the contact opening 110b is formed using an additional dedicated photomask, photoresist, and photolithography step, instead of sharing the same photomask, photoresist, and photolithography step as in existing technologies with the word line WL. Therefore, the present invention integrates the contact opening 110b of the hard mask 110a and the word line WL into a single step, reducing the cost of one photomask and one photolithography step in memory element fabrication. This is its advantage and advancement.

[0069] Please refer to Figure 11 After the contact opening 110b and word line WL are formed, a lightly doped (N-) ion implantation process I1 is performed using photoresist 136 as a mask to form a lightly doped drain (LDD) 138 in the substrate 100. In an embodiment, the lightly doped drain 138 allows the bit line junctions to be exposed from both sides of the word line WL, with a portion overlapping the word line WL in the vertical direction. In an embodiment, the same or different ion implantation steps can also be performed to form lightly doped drains for logic elements in the logic region.

[0070] Please refer to Figure 12After the lightly doped drain 138 is formed, the photoresist 136 is removed, and spacers 139 are formed on the word line WL and the sidewalls of the hard mask 110a. The spacers 139 can be made of silicon nitride, which can be formed by depositing a silicon nitride layer and then performing an anisotropic etching process on that silicon nitride layer. It should be noted that the spacers 139 may also be formed in the contact openings 110b of the hard mask 110a, but this does not affect the size of the contact holes to be formed subsequently. After the spacers 139 are formed, a heavily doped (N+) ion implantation process I2 and a thermal activation process are performed using the spacers 139, the word line WL, the stacked structures S1 and S2, and the erase gate EG as masks to form a drain D adjacent to the spacers 139 in the substrate 100. The formed drain D is connected to the lightly doped drain 138. In the embodiments, the same or different ion implantation steps may also be performed to form the source and drain of logic elements in the logic region.

[0071] Please refer to Figure 13 After the drain D is formed, an interlayer dielectric (ILD) 141 is then formed on the entire substrate 100. This interlayer dielectric can be made of silicon oxide or a low-k material. The formed ILD 141 covers the aforementioned word line WL, stacked structures S1, S2, erase gate EG, and other structures, and may be located in the contact opening 110b of the hard mask 110a. Subsequently, a photolithography process is performed to form contact holes 140 in the ILD 141 corresponding to the various endpoints of the device, including the erase gate EG, control gate CG, word line WL, drain D, etc. In this embodiment, the contact holes 140 in the ILD 141 may be smaller than or in contact with the contact opening 110b in the hard mask 110a, and are not limited thereto. Next, metal is deposited in the contact holes 140 to form contacts 142 that connect the endpoints to an external circuit to provide electrical operation, such as programming, erasing and reading of the memory cell.

[0072] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a memory element, comprising: Provide a base; A first insulating layer, a first silicon layer, a second insulating layer, a second silicon layer, and a mask layer are sequentially formed on the substrate. The mask layer, the second silicon layer, and the second insulating layer are patterned into a two-layer structure, wherein the mask layer, the second silicon layer, and the second insulating layer are respectively transformed into a hard mask, a control gate, and a barrier oxide layer in each of the two-layer structures; The first silicon layer and the first insulating layer are respectively patterned into the floating gate and tunneling oxide layer in each of the two-layer stacked structures; A source electrode is formed in the substrate between the two stacked structures; A polycrystalline silicon layer is formed between the two stacked structures and on the outside; The two hard masks and the polysilicon layer are patterned using a photolithography process, so that a contact opening is formed in each hard mask to expose the control gate, and the polysilicon layer on the outside of the two stacked structures is transformed into two lines. Drain electrodes are formed on the outer sides of the two lines respectively; and Contact elements are formed in the two contact openings to connect the two control gates.

2. The method for manufacturing a memory element as claimed in claim 1 further includes performing an etching process before the photolithography process to reduce the height of the polysilicon layer to below the top surface of the two hard masks, such that the polysilicon layer between the two stacked structures is transformed into an erase gate.

3. The method of manufacturing a memory element as claimed in claim 2 further includes forming a third insulating layer on the sidewall between the two stacked structures and the substrate before forming the polysilicon layer, the insulating layer being located between the erase gate and the substrate.

4. The method for manufacturing a memory element as described in claim 2 further includes performing a chemical mechanical planarization process before the etching process to remove the polysilicon layer and the two hard masks above a certain height, so that the top surfaces of the polysilicon layer and the two hard masks are flush.

5. The method for manufacturing a memory element as claimed in claim 1, wherein the step of forming the contacts comprises: An interlayer dielectric layer is formed on the substrate, which covers the two word lines and the two stacked structures. Contact holes are formed in the interlayer dielectric layer, each contact hole being located in the contact opening and exposing the corresponding control gate; and Metal is filled into these contact holes to form these contacts.

6. The method of manufacturing a memory element as claimed in claim 1 further comprises forming a first spacer wall on the sidewall of the two-layer structure after the hard mask, the control gate, and the barrier oxide layer are formed.

7. The method for manufacturing a memory element as claimed in claim 6 further includes an etching process using the two hard masks and the first spacer as masks to pattern the first silicon layer and the first insulating layer into the floating gate and the tunneling oxide layer in each of the two-layer stacked structures.

8. The method of manufacturing a memory element as claimed in claim 1, further comprising forming a fourth insulating layer on the sidewall outside the two-layer structure and on the substrate before forming the polysilicon layer, the fourth insulating layer being located between the two word lines and the substrate.

9. The method of manufacturing a memory element as claimed in claim 1 further comprises forming lightly doped drains on the outer sides of the two word lines, the lightly doped drains being connected to the drains.

10. The method of manufacturing a memory element as claimed in claim 1, further comprising forming a second spacer wall on the sidewalls of the two word lines, and performing an ion implantation process using the second spacer walls as a mask to form the drain on the outside of the two word lines respectively.

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