Memory and method of making the same

Abstract

The application provides a memory and a preparation method thereof. The memory comprises a plurality of memory cells, and comprises: a silicon substrate, wherein a source region and two bit line doped regions of the source region are arranged in the silicon substrate, and two adjacent memory cells share one source region; a control gate located above the source region, and two adjacent memory cells share one control gate; an erase gate located on a surface of the silicon substrate away from the control gate, and the erase gates of two adjacent memory cells are symmetrically arranged relative to the control gate; a floating gate located on the surface of the silicon substrate, and the floating gates of two adjacent memory cells are symmetrically arranged relative to the control gate, and the cross section of the floating gate is box-shaped; and a selection gate located on the surface of the silicon substrate and located on a side of the floating gate away from the control gate.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, specifically to a memory and its fabrication method. Background Technology

[0002] Embedded flash memory (eFlash) has become one of the mainstream technologies in the field of non-volatile memory (NVM) due to its low cost, low power consumption, and excellent access speed. As integrated circuit technology nodes continue to advance towards smaller sizes, the market demands higher integration density, stronger operational performance, and better long-term reliability from eFlash memory devices. Among various eFlash architectures, the 1.5T (1.5-Transistor) floating-gate memory cell is widely used in various embedded system chips due to its small cell area and good process compatibility.

[0003] Figure 1 This paper illustrates the structure of a typical 1.5T floating-gate eFlash memory. In this structure, two memory cells (bits) are arranged symmetrically and can be read and written independently. The two memory bits share the same source region (CommonSource, CS), the same control gate (CG), and the same erase poly (EP). The floating gate (FG) is formed using a self-aligned process through the sidewall etching of the select gate (SG), and its cross-sectional shape is approximately triangular. This structure utilizes a channel hot electron injection (CHEI) mechanism for programming operations and leverages the enhanced Fowler-Nordheim (FN) tunneling effect at the sharp corner of the floating gate for erasing operations, thereby reducing power consumption while maintaining operating speed.

[0004] However, the aforementioned 1.5T floating-gate eFlash memory still faces numerous challenges in its manufacturing process, especially as device size shrinks further, making process uniformity issues increasingly prominent. Specifically, the shape and size of the floating gate primarily depend on the control precision of the selected gate sidewall etching process, and its final morphology is influenced by a combination of factors, including but not limited to: the aspect ratio of the selected gate trench, the deposition thickness and step coverage of the floating gate polysilicon layer, and the selectivity of subsequent etching processes. Under the combined effect of these factors, the floating gate etching process window is extremely limited, easily leading to various types of structural defects. For example, when etching is insufficient, bridging (FGbridging) may occur between the floating gates of adjacent memories due to polysilicon residue, resulting in inter-bit leakage or short-circuit failure; while when etching is excessive, it may cause over-etching damage to the substrate in the common-source region, leading to increased junction leakage or device isolation failure. These process uniformity issues severely restrict the consistency of the memory's electrical performance and significantly reduce the overall chip manufacturing yield, making this structure face a technical bottleneck for large-scale mass production at advanced technology nodes.

[0005] Therefore, there is an urgent need to provide an improved floating gate type eFlash memory and its manufacturing method to overcome the defects of the existing technology, such as the difficulty in accurately controlling the floating gate morphology, the narrow process window, and the low yield, so as to meet the requirements of high-density, high-performance eFlash memory for manufacturing consistency and reliability.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] To address the problems in the prior art, the purpose of this application is to provide a memory and its fabrication method. This fabrication method obtains a floating gate with a box-shaped structure, increases the floating gate FG etching process window, prevents common source substrate damage defects, and improves the yield of mass production.

[0008] This application provides a memory, including multiple memory cells, the memory comprising: A silicon substrate, wherein a source region and two bit-line doped regions are provided in the silicon substrate, and two adjacent memory cells share one source region; A control gate is located above the source region, and two adjacent memory cells share one control gate; An erase gate is located on the surface of the control gate away from the silicon substrate, and the erase gates of two adjacent memory cells are symmetrically arranged with respect to the control gate; A floating gate is located on the surface of the silicon substrate, and the floating gates of two adjacent memory cells are symmetrically arranged with respect to the control gate. The cross-section of the floating gate is box-shaped. The selection gate is located on the surface of the silicon substrate and on the side of the floating gate opposite to the control gate.

[0009] In some embodiments, the memory satisfies any of the following conditions: (1) The thickness of the floating grid is 1300~1500 angstroms; (2) The width of the floating gate is 1000~1200 angstroms; (3) The distance between two adjacent floating gates is 700~900 angstroms.

[0010] This application also provides a method for fabricating a memory, the method comprising the following steps: A silicon substrate is provided, and a selection gate and an isolation layer are formed on the surface of the silicon substrate; A polycrystalline silicon floating gate layer and a nitride layer are sequentially deposited on the surface of the silicon substrate, wherein the floating gate layer forms a trench structure between two adjacent select gates; The nitride layer and the floating gate layer are etched along the thickness direction of the silicon substrate, and the first etching stops at the isolation layer at the top of the select gate; The upper surface of the floating gate layer is oxidized; Remove the nitride layer within the trench structure; A second etching is performed on the floating gate layer at the bottom of the trench structure along the thickness direction of the silicon substrate, and the second etching stops at the isolation layer on the silicon substrate to form a box-shaped floating gate.

[0011] In some embodiments, the nitride layer is a silicon nitride layer.

[0012] In some embodiments, the thickness of the nitride layer is 1000-1200 angstroms.

[0013] In some embodiments, the first etching is maskless etching, which includes a first sub-etch and a second sub-etch; The first sub-etching includes etching away the nitride layer outside the trench structure and etching away a portion of the thickness of the floating gate layer; The second sub-etch includes etching the isolation layer that stops at the top of the select gate.

[0014] In some embodiments, the etching gas selection ratio of the first sub-etching process for the nitride layer and the floating gate layer is less than 5:1; The etching gas in the second sub-etching process has an etching selectivity ratio of greater than 50:1 for the floating gate layer and the isolation layer.

[0015] In some embodiments, the first sub-etching process etches 60% to 80% of the thickness of the floating gate layer.

[0016] In some embodiments, after etching the nitride layer and the floating gate layer using the first etching process, the thickness of the nitride layer within the trench structure is greater than 300 angstroms.

[0017] In some embodiments, the preparation method satisfies any of the following conditions: (1) The upper surface of the floating gate layer is oxidized using a thermal oxidation process; (2) The nitride layer in the trench structure is removed by wet etching process.

[0018] The memory fabrication method of this application introduces a nitride layer as an in-situ protective layer in the trench structure between two select gates in the floating gate layer, and combines it with a two-step maskless etching process to finally form a box-shaped floating gate with a flat top surface. This significantly relaxes the tolerance for process fluctuations such as trench aspect ratio, polysilicon deposition thickness and etching selectivity, and greatly increases the etching process window. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0020] Figure 1 This is a cross-sectional schematic diagram of a memory according to an embodiment of this application; Figure 2 This is a flowchart of a method for fabricating a memory according to an embodiment of this application; Figures 3-9 This is a schematic diagram of the fabrication process of a memory according to an embodiment of this application. Detailed Implementation

[0021] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted. The words “or” and “or” in the specification may mean “and” or “or”. Spatial relation terms such as “…above” are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, the element or feature described as “…above” will be oriented “…below” other elements or features. Therefore, the exemplary term “…above” can include both upper and lower orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.

[0022] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items. Although “first” or “second,” etc., are used in this specification to denote certain features, this is merely indicative of function and not a limitation on the number or importance of the specific features.

[0023] The memory and its preparation method of the present invention are further described below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments are not intended to limit the scope of protection of the present invention.

[0024] The floating gate of existing memory structures is triangular. Although this structure can enhance the FN erasure efficiency through the tip, the process window is extremely narrow due to the coupling effect of multiple factors such as trench aspect ratio, polysilicon deposition thickness and etching selectivity. This can easily lead to short circuits in the floating gate bridge caused by insufficient etching, or damage to the common source substrate caused by excessive etching, which seriously restricts the consistency of device performance and manufacturing yield.

[0025] This invention provides a method for fabricating a memory. By improving the floating gate structure and manufacturing process, the floating gate structure is designed as a box shape, thereby increasing the floating gate etching process window, preventing common source substrate damage defects, and improving the yield of mass production.

[0026] Figure 1 This is a cross-sectional structural diagram of a memory according to an embodiment of the present invention. The memory is a floating-gate type and includes multiple memory cells. Figure 1 Only a cross-sectional view of two adjacent memory cells is shown. The two adjacent memory cells (Bits) have a symmetrical structure, and each memory cell can be read and written independently. Specifically, the memory includes: Silicon substrate 1, in which an active region CS and two bit line doped regions BL are formed, and two adjacent memory cells share a source region CS; The control gate CG is located above the source region CS, and two adjacent memory cells share one control gate; The erase gate EP is located on the side of the control gate CG away from the silicon substrate 1, and the erase gates EP of two adjacent memory cells are symmetrically arranged with respect to the control gate. A floating gate (FG) is located on the surface of the silicon substrate 1, and the floating gates FG1 and FG2 of two adjacent memory cells are symmetrically arranged with respect to the control gate (CG). In a preferred embodiment, the thickness of the floating gate (the vertical distance between the upper and lower surfaces of the floating gate) is 1300-1500 angstroms, the width of the floating gate (the vertical distance between the two sidewalls of a single floating gate) is 1000-1200 angstroms, and the distance between two adjacent floating gates (the sidewalls of floating gate FG1 and floating gate FG2) is 700-900 angstroms.

[0027] The select gate SG is located on the surface of the silicon substrate 1, and on the side of the floating gate opposite to the control gate CG, as shown below. Figure 1 As shown, selection grid SG1 is located to the left of floating grid FG1, and selection grid SG2 is located to the right of floating grid FG2. The distance between two adjacent floating grids (the sidewall of selection grid SG1 and the sidewall of selection grid SG2) is 3200~3400 angstroms.

[0028] Compared to traditional solutions, the most significant difference in this application's memory is that the shape of the floating gate FG1 / FG2 has changed from triangular to box-shaped. The box-shaped floating gate optimizes the memory's electrical performance and process compatibility by providing a flat top surface and regular sidewall profile. During erase operations, the box-shaped floating gate avoids the inconsistent electric field concentration caused by curvature radius fluctuations at the triangular tip, resulting in a more concentrated distribution of the erase threshold voltage and effectively improving the data retention capability and write / erase durability of the memory cells. This structure also helps to increase the etching process window of the floating gate FG, prevent common-source substrate damage defects, and improve the yield of mass production.

[0029] The following describes in detail the preparation method of the above-mentioned box-shaped floating grid structure, in conjunction with the process steps. Figure 2This is a flowchart of a method for fabricating a memory according to an embodiment of this application. Specifically, the fabrication method mainly includes the following steps S100 to S600.

[0030] Step S100: A silicon substrate is provided, and a selection gate 2 and an isolation layer 3 are formed on the surface of the silicon substrate 1. The silicon substrate 1 may be a single-crystal silicon substrate or other silicon-based materials suitable for semiconductor device manufacturing.

[0031] The select gate 2 is typically made of polycrystalline silicon. In actual fabrication, a select gate material layer and an oxide hard mask layer are deposited sequentially on a silicon substrate 1. For example, a polycrystalline silicon thin film can be deposited on the surface of the silicon substrate 1 using a low-pressure chemical vapor deposition (LPCVD) process as the subsequent select gate material layer. The thickness of this polycrystalline silicon thin film can be controlled according to device design requirements. Subsequently, a hard mask layer is formed on top of the polycrystalline silicon thin film using a chemical vapor deposition process, and the hard mask layer is patterned. Specifically, a photoresist layer is spin-coated onto the surface of the hard mask layer, and then the pattern of the select gate is defined on the photoresist layer using a photolithography process (including exposure, development, etc.). Then, using this patterned photoresist layer as a mask, an anisotropic dry etching process (e.g., reactive ion etching) is used to etch the exposed hard mask layer, transferring the pattern on the photoresist to the hard mask layer, forming a patterned hard mask layer. The remaining photoresist layer is removed using a resist stripping process. Subsequently, the polysilicon select gate material layer is etched using the patterned hard mask layer as a mask. This etching step preferably employs an anisotropic dry etching process (e.g., reactive ion etching) to precisely control the etching profile. The etching process continues until the surface of the silicon substrate 1 beneath the select gate material layer is exposed, thereby dividing the polysilicon thin film into multiple discrete and isolated select gates 2. In one embodiment, the distance between two adjacent select gates 2 is 3200–3400 angstroms.

[0032] It should be noted that the isolation layer 3 in this application is not a single structure, but is specifically divided according to its location and functional differences into: a first isolation layer 31 located on top of the select gate 2, a second isolation layer 32 located on the sidewall of the select gate 2, and a third isolation layer 33 located on the surface of the silicon substrate 1 between the two select gates 2, as follows. Figure 3 As shown. Due to differences in manufacturing processes and device performance requirements, the three differ in structure and material composition.

[0033] For example, the first isolation layer 31 includes at least a silicon nitride layer, which can be a single layer of silicon oxide or a silicon nitride / silicon oxide stack structure, such as consisting of a lower silicon oxide buffer layer with a thickness of 50-80 angstroms and an upper silicon nitride hard mask layer with a thickness of 300-500 angstroms. The first isolation layer acts as a high-selectivity etch stop layer in the subsequent floating gate maskless etching process (utilizing the high etch selectivity of silicon nitride over polysilicon), while protecting the top of the selected gate from damage or accidental oxidation in subsequent wet cleaning or oxidation processes.

[0034] A second isolation layer 32 is formed on the sidewall surface of the select gate, located between the select gate SG and the subsequently formed floating gate FG. The second isolation layer is a silicon oxide layer with a thickness of 100-200 angstroms. During the subsequent deposition of the floating gate polysilicon, the second isolation layer is used to electrically isolate the select gate and the floating gate, preventing direct contact or leakage between them.

[0035] The third isolation layer 33, serving as a tunneling layer between the silicon substrate 1 and the floating gate FG, acts as a barrier layer for charge carriers to tunnel through. Its thickness directly affects the erase / write efficiency and data retention capability of the memory cell. In some embodiments of this application, the third isolation layer can be a silicon oxide thin film formed using an in-situ vapor generation (ISSG) process. This film exhibits high density and uniformity to meet the device's requirements for reliability and electrical performance, and its thickness can be between 90 and 110 angstroms. In the illustrations of subsequent steps, to clearly demonstrate the key structural changes during the process, only the parts of the isolation layer 3 directly related to the current step may be shown, without detailed differentiation or labeling of the entire composition of the isolation layer 3.

[0036] Step S200: A polysilicon floating gate layer 4 and a nitride layer 5 are sequentially deposited on the surface of a silicon substrate 1 having a selected gate 2 structure, such as... Figure 5 As shown. In the region between two adjacent selection gates 2, the floating gate layer 4 naturally forms a trench structure C due to topographic coverage, such as... Figure 4 As shown. The profile (such as the tilt angle) of the sidewall of the select gate 2 affects the step coverage morphology of the floating gate layer 4 on the select gate 2, indirectly affecting the final floating gate structure. In this application, the sidewall of the select gate 2 is nearly vertical, that is, the angle between the sidewall and the surface of the silicon substrate 1 is close to 90° (e.g., 85°~90°). This nearly vertical sidewall profile is conducive to the formation of a uniform thickness distribution along the sidewall during the deposition process of the floating gate layer 4, avoiding insufficient polysilicon filling at the bottom of the trench or excessively thin sidewall coverage due to excessive sidewall tilt, thereby ensuring the uniformity of the residual thickness of the nitride layer in the trench after subsequent maskless etching, and providing a good morphological basis for forming a box-shaped floating gate structure.

[0037] In this embodiment, a floating gate layer 4 and a nitride layer 5 can be sequentially deposited on a silicon substrate 1 using a furnace tube low-pressure chemical vapor deposition (LPCVD) process. The thickness of the floating gate layer 4 is 1000~1400 angstroms. The nitride layer 5 can be a silicon nitride (Si3N4) layer, and its thickness is preferably 1000~1200 angstroms. This nitride layer 5 serves as a protective layer and an etch barrier layer in subsequent processes.

[0038] Step S300: Perform a first etching along the thickness direction of the silicon substrate on the nitride layer 5 and the floating gate layer 4. The first etching stops at the first isolation layer 31 at the top of the select gate 2, and leaves a portion of the nitride layer within the trench structure, such as... Figure 6 As shown.

[0039] In this embodiment, the first etching is maskless etching. Step S300 uses a maskless dry etching process to etch the entire substrate, eliminating the need for an additional photomask (self-alignment) and reducing process costs. More specifically, this first etching process mainly includes two sub-etchings: The first sub-etch: Etching is performed using a low-selectivity gas with an etching selectivity of less than 5:1 for the nitride layer 5 (e.g., Si3N4) and the floating gate layer 4 (polysilicon). The main purpose of this step is to remove the nitride layer 5 outside the trench structure by etching, while simultaneously removing a portion of the thickness of the floating gate layer 4. In one embodiment, this step etches away 60% to 80% (e.g., approximately 70%) of the total thickness of the floating gate layer.

[0040] The second sub-etching: Etching is performed using a gas with a high selectivity ratio, where the etching selectivity ratio of the gas for the floating gate layer (polysilicon) and the isolation layer (silicon oxide) is greater than 50:1. This step uses the isolation layer 31 on top of the select gate 2 as the etching stop layer, and continues etching the remaining thickness of the floating gate layer until the isolation layer 31 on top of the select gate 2 is exposed.

[0041] After step S300, the nitride layer 5' within the trench structure C has a sufficient residual thickness. In some embodiments, the upper surface of the nitride layer 5' within the trench structure C is substantially flush with the upper surface of the floating gate layer 4'. Preferably, after step S300, the thickness of the nitride layer 5' within the trench structure C is greater than 300 angstroms.

[0042] In existing processes, a self-aligned process (requiring no additional photomask) is also used. The difference is that the etching step usually only uses a single step or an etching process with imprecise control of the selectivity ratio, resulting in the following consequences: During the etching process, the floating gate layer within the trench structure is not covered by a nitride layer. As etching progresses, the floating gate layer at the top of the selected gate is removed, while the floating gate layer within the trench is simultaneously affected by lateral etching (thinning) and longitudinal etching. After etching, the floating gate layer within the trench structure exhibits a cross-sectional profile that is wider at the top and narrower at the bottom, ultimately forming an approximately triangular floating gate structure. Although this triangular floating gate structure can enhance the FN tunneling and erasure efficiency through its sharp apex, its morphology is highly dependent on the precision of the etching process. Furthermore, due to the lack of an independent etching stop layer and protective layer, the process window is extremely limited, easily leading to floating gate bridging due to insufficient etching or substrate damage due to excessive etching.

[0043] Unlike existing technologies, this application deposits a nitride layer in the trench structure C formed in the region between two adjacent select gates 2 of the floating gate layer 4. Then, through the above two etching steps, while removing the floating gate layer on top of the select gate, the floating gate layer in this region is retained due to the protective effect of the nitride layer in the trench structure on the floating gate layer below.

[0044] Step S400: Oxidize the upper surface of the floating gate layer 4'.

[0045] In this embodiment, a thermal oxidation process, such as a furnace tube dry oxidation process, can be used to grow an oxide layer 6 on the exposed floating gate layer (polycrystalline silicon) at a temperature of 900~1100°C. Figure 7 As shown. The thickness of the oxide layer 6 can be between 150 and 200 angstroms. This oxide layer 6 serves as an etching hard mask in subsequent steps to protect the floating gate layer 4' from being etched.

[0046] Step S500: Remove the nitride layer 5' within the trench structure C.

[0047] A wet etching process was employed, using a heated phosphoric acid (H3PO4) solution to selectively remove the nitride layer 5' within the trench structure C, such as... Figure 8 As shown. This wet etching process has a high selectivity for silicon nitride and silicon oxide, and can effectively remove the nitride layer 5' while minimizing damage to the oxide layer 6, which serves as a hard mask, and the isolation layer (which includes at least a silicon monoxide layer), which serves as a stop layer.

[0048] Step S600: Along the thickness direction of the silicon substrate 1, using the oxide layer 6 on the upper surface of the floating gate layer 4' and the first isolation layer 31 as a mask, a second etching is performed on the floating gate layer 4' at the bottom of the trench structure C. The second etching stops at the third isolation layer 33 on the silicon substrate 1, forming a box-shaped floating gate 4''. The two floating gates 4'' between two adjacent selection gates 2 correspond to... Figure 1 Floating gates FG1 and FG2 in memory, such as Figure 9 As shown.

[0049] In this embodiment, the second etching step S600 can be dry etching, using the oxide layer 6 formed on the upper surface of the floating gate layer in step S400 and the first isolation layer 31 located on top of the select gate as a hard mask to etch the floating gate layer at the bottom of the trench structure C that is not covered by the oxide layer. This step can use a high-selectivity etching gas (selectivity ratio of polysilicon to silicon oxide greater than 50:1). The etching gas anisotropically etches the polysilicon along the thickness direction (i.e., the vertical direction) of the silicon substrate and stops at the isolation layer on the silicon substrate, forming the floating gates FG1 and FG2 on both sides of the trench structure C. Due to the protective effect of the oxide layer 6, the floating gates FG1 and FG2 are box-shaped with flat top surfaces and regular sidewall profiles.

[0050] This completes the fabrication of the box-shaped floating gate. After step S600, preferably, the thickness of the floating gate 4'' is 1300-1500 angstroms, the width of the floating gate 4'' is 1000-1200 angstroms, and the distance between two adjacent floating gates 4'' (floating gate FG1 and floating gate FG2) is 700-900 angstroms. Subsequently, according to conventional processes, structures such as the erase gate and control gate can be formed to complete the fabrication of the entire memory. The flat top surface of the box-shaped floating gate FG in this application provides a better step coverage morphology for the subsequent deposition of the erase gate EP and control gate CG, which helps reduce interlayer leakage and enhances the long-term reliability of the device. Furthermore, the regular cross-sectional shape of the box-shaped floating gate makes the contact interface between the floating gate FG and the tunneling oxide layer (third isolation layer 33) more uniform, avoiding the degradation of the tunneling oxide layer caused by tip discharge or excessively strong local electric fields, thereby extending the lifespan of the memory. At the process level, the box structure does not rely on the tip morphology to enhance the erasure efficiency. Therefore, its performance is significantly less dependent on the etching process precision. It can maintain a highly consistent morphology across different batches and wafer locations, fundamentally ensuring the uniformity and repeatability of device performance during mass production.

[0051] In summary, the memory fabrication method of this application introduces a nitride layer as an in-situ protective layer within the trench structure between two select gates in the floating gate layer, and combines it with a two-step maskless etching process to ultimately form a box-shaped floating gate with a flat top surface. This significantly relaxes the tolerance for process fluctuations such as trench aspect ratio, polysilicon deposition thickness, and etching selectivity, and greatly increases the etching process window. The fabrication method of this application fundamentally solves the core problems of narrow process windows and easy damage to the common source substrate in traditional triangular floating gate processes. The fabrication process does not require an additional photomask, is completely self-aligned, and achieves high consistency and high reliability of box-shaped floating gate fabrication at low cost, significantly improving the yield of mass production and the electrical performance of devices.

[0052] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. A memory, characterized in that, The memory includes multiple storage units, and the memory includes: A silicon substrate, wherein a source region and two bit-line doped regions are provided in the silicon substrate, and two adjacent memory cells share one source region; A control gate is located above the source region, and two adjacent memory cells share one control gate; An erase gate is located on the surface of the control gate away from the silicon substrate, and the erase gates of two adjacent memory cells are symmetrically arranged with respect to the control gate; A floating gate is located on the surface of the silicon substrate, and the floating gates of two adjacent memory cells are symmetrically arranged with respect to the control gate. The cross-section of the floating gate is box-shaped. The selection gate is located on the surface of the silicon substrate and on the side of the floating gate opposite to the control gate.

2. The memory according to claim 1, characterized in that, The memory satisfies any of the following conditions: (1) The thickness of the floating grid is 1300~1500 angstroms; (2) The width of the floating gate is 1000~1200 angstroms; (3) The distance between two adjacent floating gates is 700~900 angstroms.

3. A method for fabricating a memory, characterized in that, The preparation method includes the following steps: A silicon substrate is provided, and a selection gate and an isolation layer are formed on the surface of the silicon substrate; A polycrystalline silicon floating gate layer and a nitride layer are sequentially deposited on the surface of the silicon substrate, wherein the floating gate layer forms a trench structure between two adjacent select gates; The nitride layer and the floating gate layer are etched along the thickness direction of the silicon substrate, and the first etching stops at the isolation layer at the top of the select gate; The upper surface of the floating gate layer is oxidized; Remove the nitride layer within the trench structure; A second etching is performed on the floating gate layer at the bottom of the trench structure along the thickness direction of the silicon substrate, and the second etching stops at the isolation layer on the silicon substrate to form a box-shaped floating gate.

4. The method for fabricating a memory according to claim 3, characterized in that, The nitride layer is a silicon nitride layer.

5. The method for fabricating a memory according to claim 4, characterized in that, The thickness of the nitride layer is 1000~1200 angstroms.

6. The method for fabricating a memory according to claim 3, characterized in that, The first etching is maskless etching, which includes a first sub-etch and a second sub-etch; The first sub-etching includes etching away the nitride layer outside the trench structure and etching away a portion of the thickness of the floating gate layer; The second sub-etch includes etching the isolation layer that stops at the top of the select gate.

7. The method for fabricating a memory according to claim 6, characterized in that, The etching gas in the first sub-etching process has an etching selectivity ratio of less than 5:1 for the nitride layer and the floating gate layer. The etching gas in the second sub-etching process has an etching selectivity ratio of greater than 50:1 for the floating gate layer and the isolation layer.

8. The method for fabricating a memory according to claim 6, characterized in that, The first sub-etching process etches 60% to 80% of the thickness of the floating gate layer.

9. The method for fabricating a memory according to claim 6, characterized in that, After etching the nitride layer and the floating gate layer using the first etching process, the thickness of the nitride layer within the trench structure is greater than 300 angstroms.

10. The method for fabricating a memory according to claim 3, characterized in that, Meet any of the following conditions: (1) The upper surface of the floating gate layer is oxidized using a thermal oxidation process; (2) The nitride layer in the trench structure is removed by wet etching process.

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