Semiconductor device and method of manufacturing the same, electronic device

Abstract

A semiconductor device, a manufacturing method thereof, and an electronic device, the semiconductor device comprising: a first semiconductor structure and a second semiconductor structure stacked along a first direction and bonded together; the first semiconductor structure having a first metal part formed of a first metal material, and the second semiconductor structure having a second metal part formed of a second metal material; there being a bonding part between the first metal part and the second metal part, and the first metal part and the second metal part being bonded together through the bonding part; at least a partial region of the bonding part being of an integral structure with at least one of the first metal part and the second metal part; and the first metal part and the second metal part each having a projection in a first plane perpendicular to the first direction falling within a projection range of the bonding part in the first plane. The semiconductor device of the embodiments of the present application has a high bonding strength between the two semiconductor structures, and has a low risk of the semiconductor structures falling off.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device. The bonding strength between the two semiconductor structures of the semiconductor device is high, and the risk of semiconductor structure detachment is low.

[0006] This application provides a semiconductor device comprising: a first semiconductor structure and a second semiconductor structure stacked and bonded together along a first direction; the first semiconductor structure having a first metal component formed of a first metal material, and the second semiconductor structure having a second metal component formed of a second metal material; a bonding component being provided between the first metal component and the second metal component, the first metal component and the second metal component being bonded together by the bonding component; at least a portion of the bonding component being integrally formed with at least one of the first metal component and the second metal component;

[0007] The orthographic projection of the first metal component onto a first plane perpendicular to the first direction falls within the range of the orthographic projection of the bonding component onto the first plane; the orthographic projection of the second metal component onto the first plane falls within the range of the orthographic projection of the bonding component onto the first plane.

[0008] In some embodiments of this application, the bonding component includes at least one of a first region formed of the first metallic material and a second region formed of the second metallic material;

[0009] Wherein, the first region and the first metal component are an integral structure, and the average density of the first region is less than the average density of the first metal component;

[0010] The second region and the second metal component are an integral structure, and the average density of the second region is less than the average density of the second metal component.

[0011] In some embodiments of this application, the orthographic projection of the first metal component on the first plane completely coincides with or partially overlaps the orthographic projection of the second metal component on the first plane.

[0012] In some embodiments of this application, the height of the bonding component in the first direction is in the range of 50 nm to 200 nm.

[0013] In some embodiments of this application, the bonding component has a metal bond with the first metal component, and / or the bonding component has a metal bond with the second metal component.

[0014] In some embodiments of this application, the bonding component further includes a metal layer formed of a third metallic material;

[0015] The first metallic material may be the same as or different from the second metallic material; and / or,

[0016] The third metallic material may be the same as or different from the first metallic material; and / or,

[0017] The third metallic material may be the same as or different from the second metallic material.

[0018] In some embodiments of this application, the first metal material, the second metal material, and the third metal material are the same and are selected from any one of copper, copper-nickel alloy, copper-tin alloy, silver, and tungsten.

[0019] This application also provides a method for manufacturing a semiconductor device, the method comprising:

[0020] A first initial semiconductor structure is provided, the first initial semiconductor structure having a first substrate and a first initial metal component formed of a first metallic material, the first initial metal component having a first end remote from the first substrate; a portion of the sidewalls and end face of the first end are exposed.

[0021] A second substrate having an insulating layer on one side is provided, and a groove and a second initial metal component formed of a second metal material are formed in the insulating layer to obtain a second initial semiconductor structure; the second initial metal component has a second end remote from the second substrate; the second end is exposed by the groove; the groove is configured to accommodate the first end;

[0022] The first end is placed in the groove, and at least a portion of the sidewall of the groove has a pore between it and the sidewall of the first end;

[0023] Annealing causes at least one of the first initial metal component and the second initial metal component to expand and fill the groove, resulting in a bonding component located in the groove and a first metal component and a second metal component located on both sides of the groove. The first initial semiconductor structure and the second initial semiconductor structure on both sides of the bonding component form a first semiconductor structure and a second semiconductor structure, respectively, and the bonding component bonds the first semiconductor structure and the second semiconductor structure together.

[0024] In some embodiments of this application, forming a groove in the insulating layer and a second initial metal component formed of a second metal material to obtain a second initial semiconductor structure includes:

[0025] The second initial metal component is formed in the insulating layer using a second metal material, and the insulating layer at least exposes the end face of the second end;

[0026] A sacrificial layer covering the second end is formed on the surface of the insulating layer;

[0027] The sacrificial layer is etched to form multiple island-like structures spaced apart, with each island-like structure covering one of the second ends;

[0028] The insulating layer is filled around the island-shaped structure;

[0029] The island-like structure is removed to form the groove, thus obtaining the second initial semiconductor structure.

[0030] In some embodiments of this application, forming a groove in the insulating layer and a second initial metal component formed of a second metal material to obtain a second initial semiconductor structure includes:

[0031] A third initial metal component is formed in the insulating layer using a second metal material, and at least one end face of the third initial metal component away from the second substrate is exposed;

[0032] The third initial metal component is etched to form the groove and the second initial metal component, thereby obtaining the second initial semiconductor structure.

[0033] In some embodiments of this application, forming a groove in the insulating layer and a second initial metal component formed of a second metal material to obtain a second initial semiconductor structure includes:

[0034] The second initial metal component is formed inside the insulating layer using a second metal material, and the second initial metal component is covered by the insulating layer.

[0035] At least a portion of the insulating layer covering the second initial metal component is removed to expose at least a portion of the second initial metal component, forming the groove to obtain the second initial semiconductor structure.

[0036] In some embodiments of this application, the manufacturing method further includes: after forming the groove, but before placing the first end into the groove.

[0037] A metal layer is formed on the inner wall of the groove using a third metal material;

[0038] Wherein, the first metal material may be the same as or different from the second metal material; and / or,

[0039] The third metallic material may be the same as or different from the first metallic material; and / or,

[0040] The third metallic material may be the same as or different from the second metallic material.

[0041] In some embodiments of this application, placing the first end in the groove, and leaving a gap between a portion of the sidewall of the groove and the sidewall of the first end, includes:

[0042] The entire sidewall and end face of the first end are placed in the groove, and the end face of the first end is in contact with the end face of the second end, and a gap is left between a portion of the sidewall of the groove and the sidewall of the first end.

[0043] In some embodiments of this application, the opening size of the groove allows the first end to extend into it; and after the first end is placed in the groove, the opening of the groove contacts the sidewall of the first end, or there is a gap between the opening of the groove and the sidewall of the first end.

[0044] In some embodiments of this application, the groove exposes only the end face of the second end; or, the groove exposes at least a portion of the sidewall and end face of the second end.

[0045] In some embodiments of this application, the annealing temperature is 250°C to 400°C.

[0046] In some embodiments of this application, the distance between the opening of the groove and the end face of the second end is equal to the length of the exposed portion of the first end.

[0047] In some embodiments of this application, the depth of the groove is 50 nm to 200 nm.

[0048] In some embodiments of this application, the ratio of the maximum size of the opening of the groove to the maximum size of the bottom of the groove does not exceed 0.8.

[0049] In some embodiments of this application, the etching selectivity ratio between the sacrificial layer and the insulating layer is not less than 10:1.

[0050] This application also provides an electronic device, which includes the semiconductor device described above, or includes a semiconductor device obtained by the manufacturing method described above.

[0051] The semiconductor device manufacturing method of this application embodiment causes at least one of the first initial metal component and the second initial metal component to expand and fill the groove by annealing, so that a mortise-and-tenon-like structure is formed at the interface of the first semiconductor structure and the second semiconductor structure. This method can effectively improve the bonding strength between the two semiconductor structures (e.g., two wafers) and help reduce the risk of semiconductor structure detachment.

[0052] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0053] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0054] Figure 1 A schematic longitudinal cross-sectional view of a semiconductor device in a first direction, which is an exemplary embodiment of this application;

[0055] Figure 2 A schematic longitudinal cross-sectional view of another semiconductor device in a first direction, which is an exemplary embodiment of this application;

[0056] Figure 3 A schematic longitudinal section of another semiconductor device according to an exemplary embodiment of this application in a first direction;

[0057] Figure 4 A process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application;

[0058] Figure 5 A schematic longitudinal section of a semiconductor device manufacturing method, as an exemplary embodiment of this application, after the formation of a sacrificial layer;

[0059] Figure 6 A schematic longitudinal section view in a first direction of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application, after forming an island-like structure;

[0060] Figure 7 A schematic longitudinal section in a first direction is shown in an exemplary embodiment of this application of a method for manufacturing a semiconductor device after an insulating layer is formed on the surface of an island structure.

[0061] Figure 8 A schematic longitudinal section view in a first direction after a groove is formed, illustrating a method for manufacturing a semiconductor device according to an exemplary embodiment of this application;

[0062] Figure 9 A schematic longitudinal section view in a first direction of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application, after placing the first end in a groove;

[0063] Figure 10 A schematic longitudinal section view in a first direction of another method for manufacturing a semiconductor device, which is an exemplary embodiment of this application, after providing two semiconductor structures;

[0064] Figure 11 A schematic longitudinal section view in a first direction after forming a groove, according to another method of manufacturing a semiconductor device as an exemplary embodiment of this application;

[0065] Figure 12 A schematic longitudinal section view in a first direction of another method for manufacturing a semiconductor device, which is an exemplary embodiment of this application, after the first end is placed in a groove;

[0066] Figure 13 A schematic longitudinal section view in a first direction of another method for manufacturing a semiconductor device, which is an exemplary embodiment of this application, after providing two semiconductor structures;

[0067] Figure 14 A schematic longitudinal section view in a first direction after forming a groove, according to another exemplary embodiment of the present application, of a method for manufacturing a semiconductor device;

[0068] Figure 15 A schematic longitudinal section view in a first direction after the metal layer is formed, according to another exemplary embodiment of this application, a method for manufacturing a semiconductor device;

[0069] Figure 16 This is a longitudinal cross-sectional view in a first direction of another method for manufacturing a semiconductor device, which is an exemplary embodiment of this application, after the first end is placed in a groove.

[0070] The meanings of the symbols in the attached diagram are as follows:

[0071] 10 - Insulating layer; 11 - First substrate; 12 - Second substrate; 13 - Sacrificial layer; 14 - Metal layer; 21' - First initial metal component; 22' - Second initial metal component; 23' - Third initial metal component; 30 - Bonding component; 100 - First semiconductor structure; 100' - First initial semiconductor structure; 200 - Second semiconductor structure; 200' - Second initial semiconductor structure; 200" - Third initial semiconductor structure. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0073] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0074] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0075] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0076] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0077] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.

[0078] In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.

[0079] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0080] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0081] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0082] The embodiments of this application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments, but other shapes and sizes are also possible. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this application are not limited to the shapes or values ​​shown in the drawings.

[0083] The size and proportional relationships between the various film layers or components in the accompanying drawings of this application can serve as a reference in actual processes and represent embodiments with better technical effects, but are not limited thereto. For example, the aspect ratio of the semiconductor layer, the thickness of each film layer, and the spacing can be adjusted according to actual needs.

[0084] In this application, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.

[0085] In this application, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, unless otherwise specified, in this application, the "source electrode" and "drain electrode" can be interchanged.

[0086] In this application, "electrical connection" or "connection" includes situations where constituent elements are connected together by a component having some electrical function, such as an electrical signal connection (coupled connection, e.g., coupled to), or a physical direct connection. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0087] In this application, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0088] In this application, "film" and "layer" can be interchanged. For example, "insulating layer" can sometimes be replaced with "insulating film".

[0089] In this application's embodiments, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected layers on a single film layer. For example, A and B may be formed using the same material to create a single film layer and simultaneously formed with interconnected structures through the same patterning process, or B may be directly grown on A via epitaxy, and the materials of the two may not be exactly the same.

[0090] The substrate in the embodiments of this application can be a support structure, such as a silicon substrate, or a support structure on which other films or functional circuits are already distributed. The device involved in the inventive structure of the embodiments of this application is disposed on the main surface of the support structure.

[0091] In this application, the spacing distribution can be understood as a separate distribution, which can be achieved through physical structural breaks or electrical characteristic breaks. For example, the semiconductor layer between the effective channels of two transistors is modified to achieve insulation, thereby realizing the electrical spacing between the two channels.

[0092] With the continuous advancement of device miniaturization, 3D integrated circuit design and packaging technology will gradually become the mainstream development direction of the semiconductor industry. Hybrid bonding, as an innovative interconnection method, vertically stacks and connects chips or wafers with different functions, and is one of the key technologies for realizing 3D chip integration. Hybrid bonding technology precisely aligns and directly presses the metal layers of multi-layer chips to form direct electrical contacts, increasing interconnection density while also achieving lower contact resistance and power consumption, thus meeting the needs of graphics processing units and high-performance computing. However, existing metal interconnect structures suffer from variations in bonding stability and uniformity, and insufficient bonding strength leads to easy wafer-to-wafer (WTW) wafer detachment, posing a significant challenge to the development of hybrid bonding technology.

[0093] This application provides a semiconductor device. Figure 1 A schematic longitudinal cross-sectional view of a semiconductor device in a first direction, which is an exemplary embodiment of this application; Figure 2 A schematic longitudinal cross-sectional view of another semiconductor device in a first direction, which is an exemplary embodiment of this application; Figure 3 This is a schematic longitudinal section of another semiconductor device in a first direction, which is an exemplary embodiment of this application.

[0094] like Figures 1 to 3 As shown, the semiconductor device includes: a first semiconductor structure 100 and a second semiconductor structure 200 stacked and bonded together along a first direction; the first semiconductor structure 100 has a first metal component 21 formed of a first metal material, and the second semiconductor structure 200 has a second metal component 22 formed of a second metal material; a bonding component 30 is provided between the first metal component 21 and the second metal component 22, and the first metal component 21 and the second metal component 22 are bonded together by the bonding component 30; at least a portion of the bonding component 30 is integrally formed with at least one of the first metal component 21 and the second metal component 22.

[0095] The orthographic projection of the first metal component 21 onto the first plane perpendicular to the first direction falls within the range of the orthographic projection of the bonding component 30 onto the first plane; the orthographic projection of the second metal component 22 onto the first plane falls within the range of the orthographic projection of the bonding component 30 onto the first plane.

[0096] The semiconductor device in this application embodiment bonds a first semiconductor structure and a second semiconductor structure through a bonding component. At least a portion of the bonding component is integral with at least one of the first metal component and the second metal component, which is equivalent to forming a mortise and tenon-like structure at the interface between the first semiconductor structure and the second semiconductor structure. This can effectively improve the bonding strength between the two semiconductor structures and help reduce the risk of semiconductor structure detachment.

[0097] In some embodiments of this application, the bonding component includes at least one of a first region formed of the first metallic material and a second region formed of the second metallic material;

[0098] Wherein, the first region and the first metal component are an integral structure, and the average density of the first region is less than the average density of the first metal component;

[0099] The second region and the second metal component are an integral structure, and the average density of the second region is less than the average density of the second metal component.

[0100] In some embodiments of this application, the orthographic projection of the first metal component 21 onto the first plane completely coincides with or partially overlaps the orthographic projection of the second metal component 22 onto the first plane. For example, in Figure 1 and Figure 2 In the semiconductor device shown, the orthographic projection of the first metal component 21 onto the first plane completely coincides with the orthographic projection of the second metal component 22 onto the first plane; Figure 3 In the semiconductor device shown, the orthographic projection of the first metal component 21 on the first plane and the orthographic projection of the second metal component 22 on the first plane partially overlap.

[0101] In some embodiments of this application, the height of the bonding component in the first direction is in the range of 50 nm to 200 nm. For example, the height of the bonding component in the first direction can be 50 nm, 75 nm, 100 nm, 125 nm, 150 nm, 175 nm, or 200 nm.

[0102] In some embodiments of this application, the bonding component has a metal bond with the first metal component, and / or the bonding component has a metal bond with the second metal component.

[0103] In some embodiments of this application, such as Figure 2 and Figure 3 As shown, the bonding component 30 includes a metal layer 14 formed of a third metallic material;

[0104] The first metallic material may be the same as or different from the second metallic material; and / or,

[0105] The third metallic material may be the same as or different from the first metallic material; and / or,

[0106] The third metallic material may be the same as or different from the second metallic material.

[0107] The addition of a metal layer can increase the effective bonding area of ​​the metal material, thereby improving the bonding strength and reliability.

[0108] In some embodiments of this application, the first metal material, the second metal material, and the third metal material are the same and are selected from any one of copper, copper-nickel alloy, copper-tin alloy, silver, and tungsten.

[0109] This application also provides a method for manufacturing a semiconductor device. The semiconductor device described above can be obtained by this manufacturing method. Figure 4 This is a process flow diagram of a method for manufacturing a semiconductor device, which is an exemplary embodiment of this application.

[0110] like Figure 4 As shown, the manufacturing method includes:

[0111] A first initial semiconductor structure is provided, the first initial semiconductor structure having a first substrate and a first initial metal component formed of a first metallic material, the first initial metal component having a first end remote from the first substrate; a portion of the sidewalls and end face of the first end are exposed.

[0112] A second substrate having an insulating layer on one side is provided, and a groove and a second initial metal component formed of a second metal material are formed in the insulating layer to obtain a second initial semiconductor structure; the second initial metal component has a second end remote from the second substrate; the second end is exposed by the groove; the groove is configured to accommodate the first end;

[0113] The first end is placed in the groove, and at least a portion of the sidewall of the groove has a pore between it and the sidewall of the first end;

[0114] Annealing causes at least one of the first initial metal component and the second initial metal component to expand and fill the groove, resulting in a bonding component located in the groove and a first metal component and a second metal component located on both sides of the groove. The first initial semiconductor structure and the second initial semiconductor structure on both sides of the bonding component form a first semiconductor structure and a second semiconductor structure, respectively, and the bonding component bonds the first semiconductor structure and the second semiconductor structure together.

[0115] The semiconductor device manufacturing method of this application embodiment causes at least one of the first initial metal component and the second initial metal component to expand and fill the groove by annealing, so that a mortise-and-tenon-like structure is formed at the interface of the first semiconductor structure and the second semiconductor structure. This method can effectively improve the bonding strength between the two semiconductor structures (e.g., two wafers) and help reduce the risk of semiconductor structure detachment.

[0116] In some embodiments of this application, forming a groove in the insulating layer and a second initial metal component formed of a second metal material to obtain a second initial semiconductor structure includes:

[0117] The second initial metal component is formed in the insulating layer using a second metal material, and the insulating layer at least exposes the end face of the second end;

[0118] A sacrificial layer covering the second end is formed on the surface of the insulating layer;

[0119] The sacrificial layer is etched to form multiple island-like structures spaced apart, with each island-like structure covering one of the second ends;

[0120] The insulating layer is filled around the island-shaped structure;

[0121] The island-like structure is removed to form the groove, thus obtaining the second initial semiconductor structure.

[0122] In some embodiments of this application, forming a groove in the insulating layer and a second initial metal component formed of a second metal material to obtain a second initial semiconductor structure includes:

[0123] A third initial metal component is formed in the insulating layer using a second metal material, and at least one end face of the third initial metal component away from the second substrate is exposed;

[0124] The third initial metal component is etched to form the groove and the second initial metal component, thereby obtaining the second initial semiconductor structure.

[0125] In some embodiments of this application, forming a groove in the insulating layer and a second initial metal component formed of a second metal material to obtain a second initial semiconductor structure includes:

[0126] The second initial metal component is formed inside the insulating layer using a second metal material, and the second initial metal component is covered by the insulating layer.

[0127] At least a portion of the insulating layer covering the second initial metal component is removed to expose at least a portion of the second initial metal component, forming the groove to obtain the second initial semiconductor structure.

[0128] In some embodiments of this application, the manufacturing method further includes: after forming the groove, but before placing the first end into the groove.

[0129] A metal layer is formed on the inner wall of the groove using a third metal material;

[0130] Wherein, the first metal material may be the same as or different from the second metal material; and / or,

[0131] The third metallic material may be the same as or different from the first metallic material; and / or,

[0132] The third metallic material may be the same as or different from the second metallic material.

[0133] By setting a metal layer on the inner wall of the groove, the effective bonding area of ​​the metal material can be increased, thereby improving the bonding strength and reliability.

[0134] In some embodiments of this application, placing the first end in the groove, and leaving a gap between a portion of the sidewall of the groove and the sidewall of the first end, includes:

[0135] The entire sidewall and end face of the first end are placed in the groove, and the end face of the first end is in contact with the end face of the second end, and a gap is left between a portion of the sidewall of the groove and the sidewall of the first end.

[0136] In some embodiments of this application, the opening size of the groove allows the first end to extend into it; and after the first end is placed in the groove, the opening of the groove contacts the sidewall of the first end, or there is a gap between the opening of the groove and the sidewall of the first end.

[0137] In some embodiments of this application, the groove exposes only the end face of the second end; or, the groove exposes at least a portion of the sidewall and end face of the second end.

[0138] In some embodiments of this application, the annealing temperature is between 250°C and 400°C. For example, the annealing temperature can be 250°C, 275°C, 300°C, 325°C, 350°C, 375°C, or 400°C.

[0139] In some embodiments of this application, the distance between the opening of the groove and the end face of the second end is equal to the length of the exposed portion of the first end.

[0140] In some embodiments of this application, the depth of the groove is from 50 nm to 200 nm. For example, the depth of the groove can be 50 nm, 75 nm, 100 nm, 125 nm, 150 nm, 175 nm or 200 nm.

[0141] In some embodiments of this application, the ratio of the maximum size of the opening of the groove to the maximum size of the groove bottom does not exceed 0.8. Here, "maximum size" refers to the maximum distance between two points on the opening or the groove bottom.

[0142] In some embodiments of this application, the etching selectivity ratio between the sacrificial layer and the insulating layer is not less than 10:1.

[0143] The technical solutions of the embodiments of this application are further illustrated below through the manufacturing process of a semiconductor device using exemplary embodiments. The "patterning etching" mentioned in this embodiment includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations here.

[0144] like Figures 5 to 9 and Figure 1 As shown, in one exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.

[0145] S1: Provide a first initial semiconductor structure 100' and a third initial semiconductor structure 200";

[0146] The first initial semiconductor structure 100' includes a first substrate 11, an insulating layer 10 located on one side of the first substrate 11, and a first initial metal component 21' located in the insulating layer 10. The first initial metal component 21' is formed of a first metal material and has a first end away from the first substrate 11. A portion of the sidewalls and end faces of the first end are exposed by the insulating layer 10.

[0147] The third initial semiconductor structure 200” includes a second substrate 12, an insulating layer 10 located on one side of the second substrate 12, and a second initial metal component 22' located in the insulating layer 10. The second initial metal component 22' is formed of a second metal material and has a second end away from the second substrate 12. The sidewall of the second end is covered by the insulating layer 10, and the end face is exposed by the insulating layer 10.

[0148] For example, the first initial metal part 21' can be formed using a damascus process.

[0149] For example, the formation process of the first initial semiconductor structure 100' may include:

[0150] A first substrate 11 is provided, and an insulating layer 10 and a first metal layer are sequentially formed on one side of the first substrate 11, wherein the first metal layer is formed of a first metal material;

[0151] The first metal layer is etched to form a plurality of first initial metal parts 21' spaced apart, each first initial metal part 21' having a first end away from the first substrate 11;

[0152] An insulating layer 10 is formed on the surface of the first substrate 11 to cover the first initial metal component 21';

[0153] The insulating layer 10 on the surface of the first initial metal component 21' is etched to expose a portion of the sidewall and end face of the first end of the first initial metal component 21'.

[0154] For example, the formation process of the third initial semiconductor structure 200” may include:

[0155] A second substrate 12 is provided, and an insulating layer 10 and a second metal layer are sequentially formed on one side of the second substrate 12, wherein the second metal layer is formed using a second metal material;

[0156] The second metal layer is etched to form a plurality of second initial metal parts 22' spaced apart, the second initial metal parts 22' having a second end away from the second substrate 12;

[0157] An insulating layer 10 is formed on the surface of the second substrate 12 to completely cover the second initial metal component 22'. The insulating layer 10 on the surface of the second initial metal component 22' is planarized by a chemical mechanical polishing (CMP) process until the end face of the second end of the second initial metal component 22' is exposed, and the sidewall of the second end is covered by the insulating layer 10.

[0158] For example, the first metal material may be the same as or different from the second metal material.

[0159] For example, the first metallic material is the same as the second metallic material, and can be selected from any one of copper, copper-nickel alloy, copper-tin alloy, silver and tungsten.

[0160] When the first metal material is different from the second metal material, the bonding strength and coefficient of thermal expansion in the subsequent bonding process need to be considered when selecting their materials to ensure effective bonding and avoid semiconductor structure detachment.

[0161] S2: A sacrificial layer 13 is formed on the side of the third initial semiconductor structure 200” away from the second substrate 12, covering the insulating layer 10 and the second end of the second initial metal component 22', as shown. Figure 5 As shown.

[0162] For example, the thickness of the sacrificial layer 13 may be the same as the length of the first exposed area of ​​the first end of the first initial metal component 21'.

[0163] For example, the etching selectivity ratio between the sacrificial layer and the insulating layer is not less than 10:1. For instance, the etching selectivity ratio between the sacrificial layer and the insulating layer can be 10:1, 15:1, 20:1, 30:1, 40:1, 50:1, 100:1, or 150:1. For example, the material of the sacrificial layer can be silicon nitride, silicon carbonitride, or silicon carbide, and the material of the insulating layer can be silicon oxide.

[0164] S3: Etch the sacrificial layer 13, for example, using photolithography and etching processes, to form multiple island-like structures spaced apart, with each island-like structure covering one of the second ends, such as... Figure 6 As shown.

[0165] For example, the island structure can be trapezoidal, circular, square, irregular, etc. This application does not limit the shape of the island structure. The shape of the island structure is the same as the shape of the groove T formed later, as long as the size of the groove T allows the first end of the first initial metal part 21' to extend into and accommodate the first end therein.

[0166] S4: An insulating layer 10 covering each island structure is formed on the side of the third initial semiconductor structure 200” away from the second substrate 12, and the insulating layer 10 on the surface of the island structure is planarized using a CMP process until the surface of each island structure is exposed, such as... Figure 7 As shown.

[0167] S5: Remove the island-like structure to form a groove T; the third initial semiconductor structure 200” is transformed into a second initial semiconductor structure 200' with a groove T, as shown in the figure. Figure 8 As shown.

[0168] For example, the distance between the opening of the groove T and the end face of the second end is equal to the length of the exposed portion of the first end.

[0169] For example, the depth of the groove T can be from 50 nm to 200 nm. For instance, the depth of the groove T can be 50 nm, 75 nm, 100 nm, 125 nm, 150 nm, 175 nm or 200 nm.

[0170] For example, the ratio of the maximum size of the opening of the groove T to the maximum size of the bottom of the groove does not exceed 0.8.

[0171] For example, the island-like structure of silicon nitride can be etched away using thermal phosphoric acid.

[0172] S6: The inverted first initial semiconductor structure 100' and the second initial semiconductor structure 200' are joined together, such that each first end of the first initial metal component 21' is placed in a groove T, and a gap exists between a portion of the sidewall of the groove T and the sidewall of the first end, such as... Figure 9 As shown.

[0173] like Figure 9 As shown, the opening of the groove T contacts the sidewall of the first end, and the end face of the first end contacts the end face of the second end.

[0174] S7: The first initial semiconductor structure 100' and the second initial semiconductor structure 200' are extruded and annealed, causing at least one of the first initial metal component 21' and the second initial metal component 22' to expand due to heat and fill the groove T, resulting in a bonding component 30 located in the groove T and the first metal component 21 and the second metal component 22 located on both sides of the groove T, respectively; the first initial semiconductor structure 100' on one side of the bonding component 30 forms a first semiconductor structure 100 including the first metal component 21, and the second initial semiconductor structure 200' on the other side of the bonding component 30 forms a second semiconductor structure 200 including the second metal component 22, and the bonding component 30 bonds the first semiconductor structure 100 and the second semiconductor structure 200 together, resulting in... Figure 1 The semiconductor device shown.

[0175] For example, the annealing temperature is between 250°C and 400°C. For instance, the annealing temperature can be 250°C, 275°C, 300°C, 325°C, 350°C, 375°C, or 400°C.

[0176] As can be seen, the bonding component 30 is formed by the thermal expansion of a portion of any one or both of the first initial metal component 21' and the second initial metal component 22'. Therefore, the bonding component 30 includes any one or both of the first region formed by the first metal material and the second region formed by the second metal material. The first metal component 21 is the remaining region of the first initial metal component 21' after removing the expanded portion. Therefore, the first region and the first metal component 21 are an integral structure, and the average density of the first region is less than the average density of the first metal component. The second metal component 22 is the remaining region of the second initial metal component 22' after removing the expanded portion. Therefore, the second region and the second metal component 22 are an integral structure, and the average density of the second region is less than the average density of the second metal component 22.

[0177] like Figures 10 to 12 and Figure 2 As shown, in another exemplary embodiment, the method of manufacturing the semiconductor device may include the following processes.

[0178] S10: Provide a first initial semiconductor structure 100' and a third initial semiconductor structure 200";

[0179] The first initial semiconductor structure 100' includes a first substrate 11, an insulating layer 10 located on one side of the first substrate 11, and a first initial metal component 21' located in the insulating layer 10. The first initial metal component 21' is formed of a first metal material and has a first end away from the first substrate 11. A portion of the sidewalls and end faces of the first end are exposed by the insulating layer 10.

[0180] The third initial semiconductor structure 200" includes a second substrate 12, an insulating layer 10 located on one side of the second substrate 12, and a third initial metal component 23' located in the insulating layer 10. The third initial metal component 23' is formed of a second metal material and has a second end away from the second substrate 12. The sidewall of the second end is covered by the insulating layer 10, and the end face is exposed by the insulating layer 10, such as... Figure 10 As shown.

[0181] For example, the third initial metal component 23' also has a third end near the second substrate 12, the second end and the third end may have different dimensions. For example, the orthographic projection of the third end on the second substrate 12 may fall within the range of the orthographic projection of the second end on the second substrate 12, and the orthographic projection area of ​​the third end on the second substrate 12 is smaller than the orthographic projection area of ​​the second end on the second substrate 12.

[0182] For example, the first initial metal part 21' can be formed using a damascus process, and the third initial metal part 23' can be formed using a double damascus process.

[0183] S20: The second end of the third initial metal component 23' is etched, for example, by using photoresist combined with IBE process to form a groove T and a second initial metal component 22', and a second metal material of a set thickness is retained on the inner wall of the groove T to form a metal layer 14; the third initial semiconductor structure 200" is transformed into a second initial semiconductor structure 200' with the groove T, such as Figure 11 As shown.

[0184] For example, the distance between the opening of the groove T and the end face of the second end is equal to the length of the exposed portion of the first end.

[0185] For example, the depth of the groove T can be from 50 nm to 200 nm. For instance, the depth of the groove T can be 50 nm, 75 nm, 100 nm, 125 nm, 150 nm, 175 nm or 200 nm.

[0186] For example, the ratio of the maximum size of the opening of the groove T to the maximum size of the bottom of the groove does not exceed 0.8.

[0187] S30: The inverted first semiconductor structure 100 and the second semiconductor structure 200 are joined together, such that each first end of the first initial metal component 21' is placed in a groove T, and a gap exists between a portion of the sidewall of the groove T and the sidewall of the first end, such as... Figure 12 As shown.

[0188] like Figure 12 As shown, there is a gap between the opening of the groove T and the sidewall of the first end, and the end face of the first end is in contact with the end face of the second end.

[0189] S40: The first initial semiconductor structure 100' and the second initial semiconductor structure 200' are extruded and annealed, causing at least one of the first initial metal component 21' and the second initial metal component 22' to expand due to heat and fill the groove T, resulting in a bonding component 30 located in the groove T and the first metal component 21 and the second metal component 22 located on both sides of the groove T, respectively; the first initial semiconductor structure 100' on one side of the bonding component 30 forms a first semiconductor structure 100 including the first metal component 21, and the second initial semiconductor structure 200' on the other side of the bonding component 30 forms a second semiconductor structure 200 including the second metal component 22, and the bonding component 30 bonds the first semiconductor structure 100 and the second semiconductor structure 200 together, resulting in... Figure 2 The semiconductor device shown.

[0190] For example, the annealing temperature is between 250°C and 400°C. For instance, the annealing temperature can be 250°C, 275°C, 300°C, 325°C, 350°C, 375°C, or 400°C.

[0191] like Figures 13 to 16 and Figure 3 As shown, in another exemplary embodiment, the method of manufacturing the semiconductor device may include the following processes.

[0192] S100: Provides a first initial semiconductor structure 100' and a third initial semiconductor structure 200";

[0193] The first initial semiconductor structure 100' includes a first substrate 11, an insulating layer 10 located on one side of the first substrate 11, and a first initial metal component 21' located in the insulating layer 10. The first initial metal component 21' is formed of a first metal material and has a first end away from the first substrate 11. A portion of the sidewalls and end faces of the first end are exposed by the insulating layer 10.

[0194] The third initial semiconductor structure 200" includes a second substrate 12, an insulating layer 10 located on one side of the second substrate 12, and a second initial metal component 22' located inside the insulating layer 10. The second initial metal component 22' is formed of a second metal material and has a second end away from the second substrate 12. The second initial metal component 22' is completely covered by the insulating layer 10, such as... Figure 13 As shown.

[0195] For example, the first initial metal part 21' can be formed using a damascus process.

[0196] For example, the formation process of the third initial semiconductor structure 200” may include:

[0197] A second substrate 12 is provided, and an insulating layer 10 and a second metal layer are sequentially formed on one side of the second substrate 12, wherein the second metal layer is formed using a second metal material;

[0198] The second metal layer is etched to form a plurality of second initial metal parts 22' spaced apart;

[0199] An insulating layer 10 is formed on the surface of the second substrate 12 to completely cover the second initial metal component 22'.

[0200] S200: The insulating layer 10 covering the second initial metal component 22' is etched to form a groove T, the groove T exposing the end face of the second end of the second initial metal component 22', and the third initial semiconductor structure 200" is transformed into a second initial semiconductor structure 200' with the groove T, as shown. Figure 14 As shown.

[0201] For example, the distance between the opening of the groove T and the end face of the second end is equal to the length of the exposed portion of the first end.

[0202] For example, the depth of the groove T can be from 50 nm to 200 nm. For instance, the depth of the groove T can be 50 nm, 75 nm, 100 nm, 125 nm, 150 nm, 175 nm or 200 nm.

[0203] For example, the ratio of the maximum size of the opening of the groove T to the maximum size of the bottom of the groove does not exceed 0.8.

[0204] S300: A third metal material is deposited on the side of the second initial semiconductor structure 200' away from the second substrate 12, covering the inner wall of the trench T. The third metal material covering the insulating layer 10 is removed, and the remaining third metal material on the inner wall of the trench T forms a metal layer 14, such as... Figure 15 As shown.

[0205] S400: The inverted first semiconductor structure 100 and the second semiconductor structure 200 are joined together such that each first end of the first initial metal component 21' is placed in a groove T, and a gap exists between a portion of the sidewall of the groove T and the sidewall of the first end, such as... Figure 16 As shown.

[0206] like Figure 16 As shown, there is a gap between the opening of the groove T and the sidewall of the first end, and the end face of the first end is in contact with the end face of the second end.

[0207] S500: The first initial semiconductor structure 100' and the second initial semiconductor structure 200' are extruded and annealed, causing at least one of the first initial metal component 21' and the second initial metal component 22' to expand due to heat and fill the groove T, resulting in a bonding component 30 located in the groove T and the first metal component 21 and the second metal component 22 located on both sides of the groove T, respectively; the first initial semiconductor structure 100' on one side of the bonding component 30 forms a first semiconductor structure 100 including the first metal component 21, and the second initial semiconductor structure 200' on the other side of the bonding component 30 forms a second semiconductor structure 200 including the second metal component 22, and the bonding component 30 bonds the first semiconductor structure 100 and the second semiconductor structure 200 together, resulting in... Figure 3 The semiconductor device shown.

[0208] For example, the annealing temperature is between 250°C and 400°C. For instance, the annealing temperature can be 250°C, 275°C, 300°C, 325°C, 350°C, 375°C, or 400°C.

[0209] This application also provides an electronic device, which includes the semiconductor device described above, or includes a semiconductor device obtained by the manufacturing method described above.

[0210] In some embodiments of this application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0211] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor structure and a second semiconductor structure are stacked and bonded together along a first direction; The first semiconductor structure has a first metal component formed of a first metal material, and the second semiconductor structure has a second metal component formed of a second metal material; a bonding component is provided between the first metal component and the second metal component, and the first metal component and the second metal component are bonded together by the bonding component; at least a portion of the bonding component is integrally formed with at least one of the first metal component and the second metal component. The orthographic projection of the first metal component onto a first plane perpendicular to the first direction falls within the range of the orthographic projection of the bonding component onto the first plane; the orthographic projection of the second metal component onto the first plane falls within the range of the orthographic projection of the bonding component onto the first plane.

2. The semiconductor device according to claim 1, characterized in that, The bonding component includes at least one of a first region formed of the first metallic material and a second region formed of the second metallic material; Wherein, the first region and the first metal component are an integral structure, and the average density of the first region is less than the average density of the first metal component; The second region and the second metal component are an integral structure, and the average density of the second region is less than the average density of the second metal component.

3. The semiconductor device according to claim 1, characterized in that, The orthographic projection of the first metal component on the first plane completely coincides with or partially overlaps the orthographic projection of the second metal component on the first plane.

4. The semiconductor device according to claim 1, characterized in that, The height of the bonding component in the first direction is in the range of 50 nm to 200 nm.

5. The semiconductor device according to claim 1, characterized in that, The bonding component has a metal bond with the first metal component, and / or the bonding component has a metal bond with the second metal component.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, The bonding component further includes a metal layer formed of a third metallic material; The first metallic material may be the same as or different from the second metallic material; and / or, The third metallic material may be the same as or different from the first metallic material; and / or, The third metallic material may be the same as or different from the second metallic material.

7. The semiconductor device according to claim 6, characterized in that, The first metal material, the second metal material, and the third metal material are the same and are selected from any one of copper, copper-nickel alloy, copper-tin alloy, silver, and tungsten.

8. A method for manufacturing a semiconductor device, characterized in that, include: A first initial semiconductor structure is provided, the first initial semiconductor structure having a first substrate and a first initial metal component formed of a first metallic material, the first initial metal component having a first end remote from the first substrate; a portion of the sidewalls and end face of the first end are exposed. A second substrate having an insulating layer on one side is provided, and a groove and a second initial metal component formed of a second metal material are formed in the insulating layer to obtain a second initial semiconductor structure. The second initial metal component has a second end remote from the second substrate; the second end is exposed by the groove; the groove is configured to accommodate the first end; The first end is placed in the groove, and at least a portion of the sidewall of the groove has a pore between it and the sidewall of the first end; Annealing causes at least one of the first initial metal component and the second initial metal component to expand and fill the groove, resulting in a bonding component located in the groove and a first metal component and a second metal component located on both sides of the groove. The first initial semiconductor structure and the second initial semiconductor structure on both sides of the bonding component form a first semiconductor structure and a second semiconductor structure, respectively, and the bonding component bonds the first semiconductor structure and the second semiconductor structure together.

9. The manufacturing method according to claim 8, characterized in that, The formation of a groove in the insulating layer and a second initial metal component formed of a second metal material to obtain a second initial semiconductor structure includes: The second initial metal component is formed in the insulating layer using a second metal material, and the insulating layer at least exposes the end face of the second end; A sacrificial layer covering the second end is formed on the surface of the insulating layer; The sacrificial layer is etched to form multiple island-like structures spaced apart, with each island-like structure covering one of the second ends; The insulating layer is filled around the island-shaped structure; The island-like structure is removed to form the groove, thus obtaining the second initial semiconductor structure.

10. The manufacturing method according to claim 8, characterized in that, The formation of a groove in the insulating layer and a second initial metal component formed of a second metal material to obtain a second initial semiconductor structure includes: A third initial metal component is formed in the insulating layer using a second metal material, and at least one end face of the third initial metal component away from the second substrate is exposed; The third initial metal component is etched to form the groove and the second initial metal component, thereby obtaining the second initial semiconductor structure.

11. The manufacturing method according to claim 8, characterized in that, The formation of a groove in the insulating layer and a second initial metal component formed of a second metal material to obtain a second initial semiconductor structure includes: The second initial metal component is formed inside the insulating layer using a second metal material, and the second initial metal component is covered by the insulating layer. At least a portion of the insulating layer covering the second initial metal component is removed to expose at least a portion of the second initial metal component, forming the groove to obtain the second initial semiconductor structure.

12. The manufacturing method according to any one of claims 9 to 11, characterized in that, Also includes: After the groove is formed, before placing the first end into the groove, A metal layer is formed on the inner wall of the groove using a third metal material; Wherein, the first metal material may be the same as or different from the second metal material; and / or, The third metallic material may be the same as or different from the first metallic material; and / or, The third metallic material may be the same as or different from the second metallic material.

13. The manufacturing method according to any one of claims 9 to 11, characterized in that, The step of placing the first end in the groove, and having a gap between at least a portion of the sidewall of the groove and the sidewall of the first end, includes: The entire sidewall and end face of the first end are placed in the groove, and the end face of the first end is in contact with the end face of the second end, and a gap is left between a portion of the sidewall of the groove and the sidewall of the first end.

14. The manufacturing method according to any one of claims 9 to 11, characterized in that, The opening size of the groove allows the first end to extend into it; and after the first end is placed in the groove, the opening of the groove contacts the sidewall of the first end, or there is a gap between the opening of the groove and the sidewall of the first end.

15. The manufacturing method according to any one of claims 9 to 11, characterized in that, The groove exposes only the end face of the second end; or, the groove exposes at least a portion of the sidewall and end face of the second end.

16. The manufacturing method according to any one of claims 9 to 11, characterized in that, The annealing temperature is between 250°C and 400°C.

17. The manufacturing method according to any one of claims 9 to 11, characterized in that, The distance between the opening of the groove and the end face of the second end is equal to the length of the exposed portion of the first end.

18. The manufacturing method according to any one of claims 9 to 11, characterized in that, The depth of the groove is 50 nm to 200 nm.

19. The manufacturing method according to any one of claims 9 to 11, characterized in that, The ratio of the maximum size of the opening of the groove to the maximum size of the bottom of the groove shall not exceed 0.

8.

20. The manufacturing method according to claim 9, characterized in that, The etching selectivity ratio between the sacrificial layer and the insulating layer is not less than 10:

1.

21. An electronic device, characterized in that, It includes the semiconductor device according to any one of claims 1 to 7, or the semiconductor device obtained by the manufacturing method according to any one of claims 8 to 20.

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