Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: forming a gate on a blocking oxide layer of a storage region; after forming the gate, performing an oxidation process on a charge storage layer of a first logic region to form an oxide layer, the oxide layer and a tunneling oxide layer of the first logic region forming a gate oxide layer; due to the tunneling oxide layer and the charge storage layer being sequentially formed on the substrate, the oxidation process is performed on the charge storage layer of the first logic region to form the oxide layer, the oxide layer and the tunneling oxide layer jointly forming the gate oxide layer of the first logic region, and under the premise that the final thickness of the gate oxide layer is the same, compared with a scheme of directly oxidizing the substrate of the first logic region to form the gate oxide layer, the heating time of the high-temperature oxidation process can be shortened, the thermal budget can be reduced, and the manufacturing efficiency can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] Semiconductor memories used for data storage are generally divided into volatile memories and non-volatile memories. Volatile memories are prone to data loss when power is interrupted, while non-volatile memories retain data even when power is interrupted. Compared with other non-volatile storage technologies (such as disk drives), non-volatile semiconductor memories have significant advantages such as small size, low power consumption, and fast read / write speeds. Therefore, non-volatile memories have been widely used in many fields such as mobile communication systems, memory cards, wearable devices, and Internet of Things (IoT) terminals.

[0003] SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory devices are widely used in embedded non-volatile memory applications due to their small cell size, good data retention, low operating voltage, and strong compatibility with standard CMOS processes. SONOS memory devices utilize electron tunneling (Fowler-Nordheim tunneling, FN tunneling) for data writing and storage, and hole injection for data erasure. Unlike floating-gate technology where electrons are stored in a floating gate, SONOS memory devices are storage cells based on discrete traps within an insulating dielectric (Si3N4) to store charge. A silicon oxide dielectric layer exists between the insulating dielectric layer and the substrate and gate electrode.

[0004] However, the existing manufacturing process for SONOS memory devices still has many shortcomings and needs further improvement. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to improving the manufacturing efficiency of semiconductor structures.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a storage region and a first logic region surrounding the storage region, a tunneling oxide layer formed on the substrate, and a charge storage layer formed on the tunneling oxide layer; forming a barrier oxide layer on the charge storage layer of the storage region, the barrier oxide layer exposing the charge storage layer of the first logic region; forming a gate on the barrier oxide layer of the storage region; and after forming the gate, oxidizing the charge storage layer of the first logic region to form an oxide layer, wherein the oxide layer located in the first logic region and the tunneling oxide layer constitute a gate oxide layer.

[0007] Optionally, the substrate further includes: a second logic region located between the storage region and the first logic region, wherein a tunneling oxide layer is formed on the substrate of the second logic region, and a charge storage layer is formed on the tunneling oxide layer; the step of oxidizing the charge storage layer of the first logic region further includes: oxidizing the charge storage layer of the second logic region to form an oxide layer; after oxidizing the charge storage layer of the first logic region, the step further includes: removing the oxide layer of the second logic region.

[0008] Optionally, the step of removing the oxide layer of the second logic region includes: forming a second mask layer on the oxide layer of the first logic region; using the second mask layer as a mask, removing the oxide layer of the second logic region, while retaining the oxide layer of the first logic region.

[0009] Optionally, after forming the gate on the barrier oxide layer of the storage region and before oxidizing the first logic region, the method further includes: forming a first sidewall material layer on the top and sidewalls of the gate; forming a second sidewall material layer on the top and sidewalls of the first sidewall material layer, the second sidewall material layer also covering the charge storage layer of the first logic region and the second logic region, the second sidewall material layer having a removal selectivity ratio with respect to the first sidewall material layer; using the first sidewall material layer as a stop layer, removing the second sidewall material layer on top of the first sidewall material layer and on top of the charge storage layer of the first logic region and the second logic region, the remaining second sidewall material layer on the sidewalls of the first sidewall material layer serving as the second sidewall; the step of removing the oxide layer of the second logic region further includes: removing the first sidewall material layer on top of the gate, the remaining first sidewall material layer on the sidewalls of the gate serving as the first sidewall.

[0010] Optionally, the removal selection ratio between the second sidewall material layer and the first sidewall material layer is greater than or equal to 2:1.

[0011] Optionally, the process for oxidizing the charge storage layer of the first logic region includes atmospheric pressure chemical vapor deposition or in-situ vapor generation oxidation.

[0012] Optionally, the oxidation process for the charge storage layer of the first logic region is an atmospheric pressure chemical vapor deposition process, wherein the process parameters of the atmospheric pressure chemical vapor deposition process include: the reaction gas is oxygen and the process temperature is 700 degrees Celsius to 900 degrees Celsius.

[0013] Optionally, the substrate further includes: a second logic region located between the storage region and the first logic region, wherein a tunneling oxide layer is formed on the substrate of the second logic region, and a charge storage layer is formed on the tunneling oxide layer; the step of forming a barrier oxide layer on the charge storage layer of the storage region includes: forming a barrier oxide material layer on the charge storage layer of the first logic region, the second logic region, and the storage region; forming a first mask layer on the barrier oxide material layer of the storage region; using the first mask layer as a mask, removing the barrier oxide material layers of the first logic region and the second logic region, and using the remaining barrier oxide material layer of the storage region as the barrier oxide layer; after forming the barrier oxide layer, the step further includes: removing the first mask layer.

[0014] Optionally, after forming a barrier oxide layer on the charge storage layer of the first logic region, the second logic region, and the storage region, and before forming a first mask layer on the barrier oxide layer of the storage region, the method further includes: forming a gate material layer on the barrier oxide layer of the first logic region, the second logic region, and the storage region; in the step of forming a first mask layer on the barrier oxide layer of the storage region, forming a first mask layer on the gate material layer of the storage region; and in the step of removing the barrier oxide layers of the first logic region and the second logic region using the first mask layer as a mask, the method further includes: removing the gate material layers of the first logic region and the second logic region using the first mask layer as a mask, with the remaining gate material layer of the storage region serving as the gate.

[0015] Optionally, the material of the charge storage layer includes silicon nitride.

[0016] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages: This invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a storage region and a first logic region surrounding the storage region, forming a tunneling oxide layer on the substrate, and forming a charge storage layer on the tunneling oxide layer; forming a barrier oxide layer on the charge storage layer of the storage region, the barrier oxide layer exposing the charge storage layer of the first logic region; forming a gate on the barrier oxide layer of the storage region; after forming the gate, oxidizing the charge storage layer of the first logic region to form an oxide layer, the oxide layer in the first logic region and the tunneling oxide layer constituting a gate oxide layer; since the tunneling oxide layer and the charge storage layer are sequentially formed on the substrate, oxidizing the charge storage layer of the first logic region to form an oxide layer, the oxide layer and the tunneling oxide layer together constituting the gate oxide layer of the first logic region, under the premise that the final thickness of the gate oxide layer is the same, compared with the scheme of directly oxidizing the substrate of the first logic region to form the gate oxide layer, this application can shorten the heating time of the high-temperature oxidation process, thereby reducing the thermal budget and improving manufacturing efficiency. Attached Figure Description

[0017] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor formation method of the present invention. Detailed Implementation

[0018] As can be seen from the background technology, the manufacturing process of SONOS memory devices still needs further improvement.

[0019] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a storage region and a first logic region surrounding the storage region, forming a tunneling oxide layer on the substrate, and forming a charge storage layer on the tunneling oxide layer; forming a barrier oxide layer on the charge storage layer of the storage region, the barrier oxide layer exposing the charge storage layer of the first logic region; forming a gate on the barrier oxide layer of the storage region; and after forming the gate, oxidizing the charge storage layer of the first logic region to form an oxide layer, wherein the oxide layer located in the first logic region and the tunneling oxide layer constitute a gate oxide layer.

[0020] In the scheme disclosed in the embodiments of the present invention, since a tunneling oxide layer and a charge storage layer are sequentially formed on the substrate, the charge storage layer of the first logic region is oxidized to form an oxide layer. The oxide layer and the tunneling oxide layer together constitute the gate oxide layer of the first logic region. Under the premise that the final thickness of the gate oxide layer is the same, compared with the scheme of directly oxidizing the substrate of the first logic region to form the gate oxide layer, the present application can shorten the heating time of the high-temperature oxidation process, thereby reducing the thermal budget and improving the manufacturing efficiency.

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0022] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor formation method of the present invention.

[0023] refer to Figure 1 A substrate 100 is provided, the substrate 100 including a storage region 100C and a first logic region 100B surrounding the storage region 100C, a tunneling oxide layer 101 is formed on the substrate 100, and a charge storage layer 102 is formed on the tunneling oxide layer 101.

[0024] As an example, in this embodiment, the semiconductor structure is an embedded flash memory, specifically a SONOS flash memory, which is a non-volatile storage device.

[0025] Substrate 100 provides the basis for the process operation of semiconductor structure formation.

[0026] In some embodiments, the substrate 100 is made of silicon. In other embodiments, the substrate may be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium dihydrogen phosphate. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0027] Storage region 100C is used to provide space for forming a gate, which together with tunnel oxide layer 101, charge storage layer 102 and barrier oxide layer constitute a SONOS memory cell.

[0028] The first logic area 100B is a high-voltage area, used to provide the high voltage required for programming and erasing operations of the storage area 100C.

[0029] In some embodiments, the substrate 100 further includes a second logic region 100A located between the storage region 100C and the first logic region 100B, wherein a tunneling oxide layer 101 is formed on the substrate 100 of the second logic region 100A, and a charge storage layer 102 is formed on the tunneling oxide layer 101.

[0030] The second logic area 100A is a low-voltage area, and its operating voltage is lower than that of the first logic area 100B. It is used to realize high-speed logic operations.

[0031] Specifically, the tunneling oxide layer 101 located in the storage region 100C serves as both a charge tunneling channel and a barrier layer, allowing charge to selectively pass through and be injected into the charge storage layer 102 during programming or erasing operations, and preventing charge leakage to the substrate 100 during the data retention phase; the tunneling oxide layer 101 located in the first logic region 100B constitutes at least a portion of the gate oxide layer of the high-voltage transistor; the tunneling oxide layer 101 located in the second logic region 100A is removed to prepare for the subsequent formation of the gate oxide layer of the low-voltage transistor.

[0032] In some embodiments, the material of the tunneling oxide layer 101 includes silicon oxide. Silicon oxide has a large band gap, thus allowing charges to tunnel precisely under specific conditions and be injected into the charge storage layer 102 during programming or erasing; during the data retention phase, it can effectively prevent the stored charges from leaking back to the substrate 100, thereby ensuring that data is not lost.

[0033] Specifically, the charge storage layer 102 located in storage region 100C provides discrete charge trapping levels to capture and store charges tunneling through the tunnel oxide layer 101, thereby achieving non-volatile data storage; the charge storage layer 102 located in the first logic region 100B is oxidized in a subsequent process, and its oxidation products together with the tunnel oxide layer 101 constitute the gate oxide layer of the high-voltage transistor to meet the voltage withstand requirements of the high-voltage device; the charge storage layer 102 located in the second logic region 100A is removed to prepare for the subsequent formation of the gate oxide layer of the low-voltage transistor.

[0034] As an example, the material of the charge storage layer 102 includes silicon nitride. Silicon nitride has discrete charge trapping energy levels, thus enabling the capture and storage of charges tunneling through the tunneling oxide layer 101 during programming or erasure; during the data retention phase, it effectively prevents the stored charge from leaking back to the substrate 100, thereby ensuring the reliability of data storage.

[0035] refer to Figures 1 to 2 A barrier oxide layer 103 (e.g., ...) is formed on the charge storage layer 102 of the storage region 100C. Figure 2 As shown), the blocking oxide layer 103 exposes the charge storage layer 102 of the first logic region 100B.

[0036] The barrier oxide layer 103 is used to prevent the charge stored in the charge storage layer 102 from leaking to the gate during the data retention phase, while allowing the electric field to penetrate during programming or erasing to achieve charge tunneling injection or extraction.

[0037] Specifically, the barrier oxide layer 103 also exposes the charge storage layer 102 of the second logic region 100A, that is, the barrier oxide layer 103 exposes the charge storage layer 102 of the first logic region 100B and the second logic region 100A, so that the charge storage layer 102 can be oxidized in subsequent processes.

[0038] In some embodiments, the material of the barrier oxide layer 103 includes silicon oxide. Silicon oxide has good insulating properties, thereby preventing the charge stored in the charge storage layer 102 from leaking upwards to the gate.

[0039] Specifically, the step of forming a barrier oxide layer 103 on the charge storage layer 102 of the storage region 100C includes: referencing Figure 1 An oxide barrier layer 104 is formed on the charge storage layer 102 of the first logic region 100B, the second logic region 100A, and the storage region 100C; a first mask layer (not shown in the figure) is formed on the oxide barrier layer 104 of the storage region 100C; Reference Figure 2 Using the first mask layer as a mask, the barrier oxide material layer 104 of the first logic region 100B and the second logic region 100A is removed, and the remaining barrier oxide material layer 104 of the storage region 100C is used as the barrier oxide layer 103.

[0040] The oxide barrier material layer 104 is used to form the oxide barrier layer 103.

[0041] The first mask layer is used as a mask for forming the barrier oxide layer 103.

[0042] In some embodiments, the material of the first mask layer includes photoresist. The photoresist has high resolution, thereby accurately exposing the first logic region 100B and the second logic region 100A; simultaneously, the photoresist is easy to remove, thereby reducing process complexity and improving production efficiency. In other embodiments, the first mask layer may also be made of other materials that can serve as etching masks and are easy to remove.

[0043] Continue to refer to Figure 2 After forming the barrier oxide layer 103, the process further includes: removing the first mask layer.

[0044] It should be noted that removing the first mask layer is to prepare for the subsequent formation of the gate on the barrier oxide layer 103.

[0045] Specifically, the process for removing the first mask layer includes an ashing process or a wet adhesive removal process.

[0046] Continue to refer to Figures 1 to 2 A gate 105 is formed on the barrier oxide layer 103 of the storage region 100C (e.g., Figure 2(As shown).

[0047] The gate 105 controls charge injection and extraction by applying voltages of different polarities, thereby enabling data writing and erasure. Specifically, during programming, a positive voltage is applied to the gate 105, driving electrons to tunnel and inject into the charge storage layer 102, raising the threshold voltage of the semiconductor structure; during erasure, a negative voltage is applied, causing hole injection or electron extraction, restoring the threshold voltage to a low state. During reading, a read voltage between the high and low threshold voltages is applied to the gate 105, and the storage state of the memory cell is determined by detecting the magnitude of the drain current.

[0048] In some embodiments, the gate 105 is made of polysilicon. The work function of polysilicon can be tuned by ion implantation doping (such as N-type or P-type doping), thereby affecting key characteristics of the semiconductor structure such as programming, erasing, and data retention.

[0049] The steps of forming a gate 105 on the barrier oxide layer 103 of the storage region 100C are described in detail below with reference to the accompanying drawings.

[0050] refer to Figure 1 In some embodiments, after forming a barrier oxide layer 104 on the charge storage layer 102 of the first logic region 100B, the second logic region 100A, and the storage region 100C, and before forming a first mask layer on the barrier oxide layer 104 of the storage region 100C, the method further includes forming a gate material layer 109 on the barrier oxide layer 104 of the first logic region 100B, the second logic region 100A, and the storage region 100C.

[0051] A gate material layer 109 is used to form the gate 105. Accordingly, the material of the gate material layer 109 includes polysilicon.

[0052] In some embodiments, in the step of forming a first mask layer on the barrier oxide material layer 104 of the storage region 100C, a first mask layer is formed on the gate material layer 109 of the storage region 100C.

[0053] It should be noted that a first mask layer is formed on the gate material layer 109 of the storage region 100C to facilitate the removal of the gate material layer 109 and the barrier oxide layer 104 of the storage region 100C using the first mask layer as a mask. In other words, the gate material layer 109 and the barrier oxide layer 104 can be patterned simultaneously in a single photolithography process. Compared with the scheme of patterning the gate material layer and the barrier oxide layer separately, the number of photomasks can be reduced, thereby reducing production costs.

[0054] Reference Figure 1 and reference Figure 2In some embodiments, the step of removing the barrier oxide material layer 104 of the first logic region 100B and the second logic region 100A using the first mask layer as a mask further includes: removing the gate material layer 109 of the first logic region 100B and the second logic region 100A using the first mask layer as a mask, with the remaining gate material layer 109 of the memory region 100C serving as the gate 105.

[0055] It should be noted that by utilizing the first mask layer, the barrier oxide material layer 104 and the gate material layer 109 of the first logic region 100B and the second logic region 100A can be removed in the same process step, which helps to simplify the process flow and improve production efficiency.

[0056] refer to Figure 3 After forming the gate 105 on the barrier oxide layer 103 of the storage region 100C, and before oxidizing the charge storage layer 102 of the first logic region 100B, the method further includes forming a first sidewall material layer 110 on the top and sidewall of the gate 105.

[0057] The first sidewall material layer 110 is used to form the first sidewall.

[0058] In some embodiments, forming a first sidewall material layer 110 on the top and sidewalls of the gate 105 includes a rapid thermal oxidation (RTO) process.

[0059] It should be noted that after the patterned gate material layer 109 forms the gate 105, the sidewalls of the gate 105 will suffer lattice damage and dangling bonds due to the etching process. Meanwhile, the well region (not shown in the figure) has already formed a precise doping distribution in the substrate 100 through prior implantation and annealing. Therefore, after patterning, an RTO process is used to form a first sidewall material layer 110 on the sidewalls of the gate 105 through second-level high-temperature oxidation. The thickness of the first sidewall material layer 110 can be precisely controlled, which not only consumes and repairs the damage layer and passivates interface defects introduced by etching, but also provides a buffer protection layer for the subsequent second sidewall process. At the same time, the RTO process forms the first sidewall material layer 110 in a very short high-temperature time, which significantly reduces the thermal budget and effectively suppresses the lateral and vertical diffusion of doped atoms in the well region, thereby protecting the channel doping distribution and avoiding reliability issues such as short-channel effects.

[0060] Correspondingly, the material of the first sidewall material layer 110 is silicon dioxide.

[0061] Continue to refer to Figure 3A second sidewall material layer 111 is formed on the top and sidewall of the first sidewall material layer 110. The second sidewall material layer 111 also covers the charge storage layer 102 of the first logic region 100B and the second logic region 100A. The second sidewall material layer 111 and the first sidewall material layer 110 have a removal selectivity ratio.

[0062] The second sidewall material layer 111 is used to form the second sidewall.

[0063] Specifically, there is a removal selectivity between the second sidewall material layer 111 and the first sidewall material layer 110. Therefore, in the subsequent process of removing the second sidewall material layer 111 on top of the first sidewall material layer 110, it is beneficial for the etching to stop at the surface of the first sidewall material layer 110, thereby protecting the top of the gate 105.

[0064] In some embodiments, the process of forming a second sidewall material layer 111 on the top and sidewalls of the first sidewall material layer 110 includes a low-pressure chemical vapor deposition (LPCVD) process.

[0065] It should be noted that the low-pressure chemical vapor deposition process has good conformal coverage and can form a second sidewall material layer 111 with uniform thickness and high density on the top and sidewalls of the first sidewall material layer 110, providing a good process basis for the subsequent formation of the second sidewall.

[0066] In some embodiments, the material of the second sidewall material layer 111 includes silicon nitride.

[0067] refer to Figure 4 Using the first sidewall material layer 110 as the stop layer, the second sidewall material layer 111 on the top of the first sidewall material layer 110 and the top of the charge storage layer 102 of the first logic region 100B and the second logic region 100A is removed, and the remaining second sidewall material layer 111 on the sidewall of the first sidewall material layer 110 is used as the second sidewall 108.

[0068] The second sidewall 108 is used to protect the sidewall of the first sidewall, and together with the first sidewall, protects the sidewall of the gate 105.

[0069] Specifically, a second sidewall material layer 111 conformally covers the top and sidewalls of the first sidewall material layer 110, as well as the charge storage layers 102 of the first logic region 100B and the second logic region 100A, and has a uniform thickness. Based on this, anisotropic etching is performed using the etching selectivity ratio between the second sidewall material layer 111 and the first sidewall material layer 110, with the first sidewall material layer 110 as the stop layer. This etching process removes the second sidewall material layer 111 from the top of the first sidewall material layer 110 and the top of the charge storage layers 102 of the first logic region 100B and the second logic region 100A, while the second sidewall material layer 111 on the sidewalls of the first sidewall material layer 110 is retained as the second sidewall 108. After the charge storage layers 102 of the first logic region 100B and the second logic region 100A are exposed, they are easier to oxidize or remove subsequently.

[0070] The removal selectivity ratio between the second sidewall material layer 111 and the first sidewall material layer 110 should not be too small. If the removal selectivity ratio between the second sidewall material layer 111 and the first sidewall material layer 110 is too small, the probability of the first sidewall material layer 110 being removed during the process of removing the second sidewall material layer 111 from the top of the first sidewall material layer 110 and the top of the charge storage layer 102 of the first logic region 100B and the second logic region 100A will easily increase, thereby increasing the probability of damage to the top of the gate 105. Therefore, in some embodiments, the removal selectivity ratio between the second sidewall material layer 111 and the first sidewall material layer 110 is greater than or equal to 2:1.

[0071] In some embodiments, the process of removing the second sidewall material layer 111 from the top of the first sidewall material layer 110 and the top of the charge storage layer 102 of the first logic region 100B and the second logic region 100A, with the first sidewall material layer 110 as the stop layer, includes a dry etching process.

[0072] refer to Figures 5 to 6 After forming the gate 105, the charge storage layer 102 of the first logic region 100B is oxidized to form an oxide layer 112. The oxide layer 112 located in the first logic region 100B and the tunneling oxide layer 101 constitute the gate oxide layer 114 (e.g., Figure 6 (As shown).

[0073] It should be noted that, since a tunneling oxide layer 101 and a charge storage layer 102 are sequentially formed on the substrate 100, the charge storage layer 102 of the first logic region 100B is oxidized to form an oxide layer 112. The oxide layer 112 and the tunneling oxide layer 101 together constitute the gate oxide layer 114 of the first logic region 100B. Under the premise that the final thickness of the gate oxide layer 114 is the same, compared with the scheme of directly oxidizing the substrate of the first logic region to form the gate oxide layer, this application can shorten the heating time of the high-temperature oxidation process, thereby reducing the thermal budget and improving manufacturing efficiency.

[0074] refer to Figure 5 In some embodiments, the step of oxidizing the charge storage layer 102 of the first logic region 100B further includes oxidizing the charge storage layer 102 of the second logic region 100A to form an oxide layer 112.

[0075] It should be noted that since the charge storage layer 102 of both the first logic region 100B and the second logic region 100A are exposed to an oxidizing atmosphere, when the charge storage layer 102 of the first logic region 100B is oxidized, the charge storage layer 102 of the second logic region 100A is oxidized simultaneously.

[0076] Specifically, after the second sidewall 108 is formed, the charge storage layer 102 of the first logic region 100B and the second logic region 100A is oxidized to form an oxide layer 112.

[0077] It should be noted that since the second sidewall 108 and the charge storage layer 102 are made of the same material, silicon nitride, in the actual process of forming the second sidewall 108, there may be residues of the second sidewall material layer 111 on the surface of the charge storage layer 102 of the first logic region 100B and the second logic region 100A. Therefore, after forming the second sidewall 108, the charge storage layer 102 of the first logic region 100B and the second logic region 100A is oxidized. This oxidation process can not only convert the charge storage layer 102 into an oxide layer 112, but also oxidize and eliminate the residues of the second sidewall material layer 111. This avoids the residues from obstructing or contaminating subsequent etching or cleaning processes, thereby improving device yield and process stability.

[0078] In some embodiments, the thickness of the second sidewall 108 is greater than the thickness of the charge storage layer 102.

[0079] It should be noted that during the oxidation process of the charge storage layer 102 of the first logic region 100B and the second logic region 100A, the exposed surface of the second sidewall 108 also undergoes an oxidation reaction simultaneously, consuming part of its thickness. Therefore, the thickness of the second sidewall 108 needs to be set to be greater than the thickness of the charge storage layer 102 to ensure that sufficient second sidewall 108 remains after oxidation.

[0080] In some embodiments, the oxidation treatment of the charge storage layer 102 of the first logic region 100B includes an atmospheric pressure chemical vapor deposition process or an in-situ vapor generation oxidation process.

[0081] It is understood that the charge storage layer 102 of the first logic region 100B is oxidized at the same time as the charge storage layer 102 of the second logic region 100A. Therefore, the process for oxidizing the charge storage layer 102 of the second logic region 100A includes atmospheric pressure chemical vapor deposition or in-situ vapor generation oxidation.

[0082] Specifically, both atmospheric pressure chemical vapor deposition and in-situ vapor generation oxidation processes can achieve the oxidation of the charge storage layer 102 of the first logic region 100B and the second logic region 100A with relatively low thermal budgets.

[0083] In some embodiments, the charge storage layer 102 of the first logic region 100B is oxidized using an atmospheric pressure chemical vapor deposition process. The process parameters of the atmospheric pressure chemical vapor deposition process include: the reaction gas is oxygen, and the process temperature is 700 degrees Celsius to 900 degrees Celsius.

[0084] Oxygen is used as an oxidant to oxidize the charge storage layer 102 to form an oxide layer 112.

[0085] The process temperature should not be too high or too low. If the process temperature is too high, it will exacerbate the unintended diffusion of doped atoms in the well region of the substrate 100; if the process temperature is too low, the oxidation rate will be too slow, requiring a longer process time, which will lead to an increase in the accumulated thermal budget and reduce production efficiency. Therefore, in some embodiments, the process temperature is between 700 degrees Celsius and 900 degrees Celsius.

[0086] refer to Figure 6 After oxidizing the charge storage layer 102 of the first logic region 100B, the method further includes removing the oxide layer 112 of the second logic region 100A.

[0087] In some embodiments, the step of removing the oxide layer 112 of the second logic region 100A further includes: removing the first sidewall material layer 110 on the top of the gate 105, with the remaining first sidewall material layer 110 on the sidewall of the gate 105 serving as the first sidewall 107.

[0088] The first sidewall 107 is formed between the sidewall of the gate 105 and the second sidewall 108 as a buffer layer to isolate the stress exerted by the second sidewall 108 on the gate 105 and to passivate the surface of the gate 105.

[0089] It should be noted that removing the oxide layer 112 of the second logic region 100A and the first sidewall material layer 110 on top of the gate 105 in the same step simplifies the process and improves production efficiency.

[0090] Specifically, during the oxidation process of the charge storage layer 102 of the first logic region 100B and the second logic region 100A, the second sidewall 108 of a certain thickness is also oxidized. Therefore, the step of removing the oxide layer 112 of the second logic region 100A also includes removing the oxidized part of the second sidewall 108, thereby achieving the key dimension adjustment of the second sidewall 108 without adding an additional photomask or etching step.

[0091] In some embodiments, the process of removing the oxide layer 112 of the second logic region 100A includes a wet etching process.

[0092] Specifically, the step of removing the oxide layer 112 of the second logic region 100A includes: forming a second mask layer (not shown in the figure) on the oxide layer 112 of the first logic region; using the second mask layer as a mask, removing the oxide layer 112 of the second logic region 100A, and retaining the oxide layer 112 of the first logic region 100B.

[0093] The second mask layer serves as a mask layer for forming the oxide layer 112.

[0094] In some embodiments, the second mask layer also serves as a mask layer forming the first sidewall 107.

[0095] Specifically, the first sidewall material layer 110 on top of the gate 105 is removed using the second mask layer as a mask.

[0096] In some embodiments, the material of the second mask layer includes photoresist. The photoresist has high resolution, thereby accurately exposing the second logic region 100A and the memory region 100C; simultaneously, the photoresist is easy to remove, thereby reducing process complexity and improving production efficiency. In other embodiments, the second mask layer may also be made of other materials that can serve as etching masks and are easy to remove.

[0097] In some embodiments, after forming the oxide layer 112, the method further includes removing the second mask layer.

[0098] Specifically, the process for removing the second mask layer includes an ashing process or a wet desmearing process.

[0099] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a storage region and a first logic region surrounding the storage region, a tunneling oxide layer is formed on the substrate, and a charge storage layer is formed on the tunneling oxide layer; A barrier oxide layer is formed on the charge storage layer of the storage region, and the barrier oxide layer exposes the charge storage layer of the first logic region. A gate is formed on the barrier oxide layer of the storage region; After the gate is formed, the charge storage layer of the first logic region is oxidized to form an oxide layer. The oxide layer located in the first logic region and the tunneling oxide layer constitute the gate oxide layer.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate further includes: a second logic region located between the storage region and the first logic region, wherein a tunneling oxide layer is formed on the substrate of the second logic region, and a charge storage layer is formed on the tunneling oxide layer; The step of oxidizing the charge storage layer of the first logic region further includes: oxidizing the charge storage layer of the second logic region to form an oxide layer; After oxidizing the charge storage layer of the first logic region, the process further includes removing the oxide layer of the second logic region.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The steps for removing the oxide layer from the second logic region include: A second mask layer is formed on the oxide layer of the first logic region; Using the second mask layer as a mask, the oxide layer of the second logic region is removed, while the oxide layer of the first logic region is retained.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, After the gate is formed on the barrier oxide layer of the storage region and before the first logic region is oxidized, the method further includes: A first sidewall material layer is formed on the top and sidewalls of the gate; A second sidewall material layer is formed on the top and sidewall of the first sidewall material layer. The second sidewall material layer also covers the charge storage layer of the first logic region and the second logic region. The second sidewall material layer has a removal selectivity ratio with the first sidewall material layer. Using the first sidewall material layer as the stop layer, the second sidewall material layer at the top of the first sidewall material layer and at the top of the charge storage layer of the first logic area and the second logic area is removed, and the remaining second sidewall material layer on the sidewall of the first sidewall material layer is used as the second sidewall. The step of removing the oxide layer of the second logic region further includes: removing the first sidewall material layer on the top of the gate, with the remaining first sidewall material layer of the gate sidewall serving as the first sidewall.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The removal selection ratio between the second sidewall material layer and the first sidewall material layer is greater than or equal to 2:

1.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for oxidizing the charge storage layer of the first logic region includes atmospheric pressure chemical vapor deposition or in-situ vapor generation oxidation.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The oxidation process for the charge storage layer of the first logic region is an atmospheric pressure chemical vapor deposition process. The process parameters of the atmospheric pressure chemical vapor deposition process include: the reaction gas is oxygen and the process temperature is 700 degrees Celsius to 900 degrees Celsius.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate further includes: a second logic region located between the storage region and the first logic region, wherein a tunneling oxide layer is formed on the substrate of the second logic region, and a charge storage layer is formed on the tunneling oxide layer; The step of forming a barrier oxide layer on the charge storage layer of the storage region includes: An oxide barrier layer is formed on the charge storage layer of the first logic region, the second logic region, and the storage region; A first mask layer is formed on the oxide barrier material layer in the storage area; Using the first mask layer as a mask, the barrier oxide material layers of the first logic region and the second logic region are removed, and the remaining barrier oxide material layer of the storage region is used as the barrier oxide layer. After forming the barrier oxide layer, the process further includes: removing the first mask layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, After forming a barrier oxide layer on the charge storage layer of the first logic region, the second logic region, and the storage region, and before forming a first mask layer on the barrier oxide layer of the storage region, the method further includes: forming a gate material layer on the barrier oxide layer of the first logic region, the second logic region, and the storage region. In the step of forming a first mask layer on the barrier oxide material layer of the storage region, a first mask layer is formed on the gate material layer of the storage region; The step of removing the blocking oxide material layer of the first logic region and the second logic region using the first mask layer as a mask further includes: removing the gate material layer of the first logic region and the second logic region using the first mask layer as a mask, with the remaining gate material layer of the memory region serving as the gate.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the charge storage layer includes silicon nitride.

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