Memory devices and methods of manufacturing memory devices

Abstract

The present application relates to memory devices and methods of manufacturing memory devices. The memory device includes a stack including conductive layers and interlayer insulating layers alternately stacked with each other, a cell plug extending through the stack, a contact in electrical contact with at least one of the conductive layers. The memory device further includes a spacer between the contact and the stack. The memory device further includes a support structure extending through the stack. The support structure includes a first portion and a second portion below the first portion, the second portion having a greater width than the first portion. An interface between the first portion and the second portion is located at a different level than an interface between the conductive layers and the interlayer insulating layers.

Description

Technical Field

[0001] Some embodiments of this disclosure relate to memory devices and methods of manufacturing memory devices, and more specifically, to memory devices comprising memory blocks having a three-dimensional structure and methods of manufacturing memory devices. Background Technology

[0002] Memory devices can include non-volatile memory devices, in which stored data remains intact even when the power supply is interrupted. Non-volatile memory devices can be classified as two-dimensional or three-dimensional structures depending on how their memory cells are arranged. The memory cells of a two-dimensional non-volatile memory device can be arranged in a single layer on a substrate, while the memory cells of a three-dimensional non-volatile memory device can be stacked vertically on the substrate. The integration density of a three-dimensional non-volatile memory device is higher than that of a two-dimensional non-volatile memory device. Therefore, electronic devices using three-dimensional non-volatile memory devices have been increasing recently.

[0003] A non-volatile memory device with a three-dimensional structure includes layers stacked in a vertical direction. A support structure is formed to penetrate the stacked layers and support the stacked layers. Summary of the Invention

[0004] According to an embodiment, a memory device may include: a stack comprising conductive layers and interlayer insulating layers alternately stacked on top of each other; a cell plug extending through the stack; a contact electrically contacting at least one of the conductive layers; a spacer between the contact and the stack; and a support structure extending through the stack. The support structure includes a first portion and a second portion below the first portion, the second portion having a wider width than the first portion. The interface between the first portion and the second portion is located at a different level than the interface between the conductive layers and the interlayer insulating layers.

[0005] According to an embodiment, a method of manufacturing a memory device may include the following steps: forming an initial laminate comprising sacrificial layers and interlayer insulating layers alternately stacked on top of each other; forming an opening through the initial laminate; forming a barrier layer on a side surface of the initial laminate exposed through the opening; forming a cover layer on a portion of the barrier layer, exposing the remaining portion of the barrier layer; forming a barrier pattern exposing a portion of the side surface of the initial laminate by removing the exposed portion of the barrier layer; forming an enlarged opening relative to the opening by etching the portion of the side surface of the initial laminate exposed through the barrier pattern; and forming a support structure in the enlarged opening.

[0006] According to an embodiment, a memory device may include: a stack comprising alternating conductive layers and interlayer insulating layers; a contact electrically contacting the conductive layers; a spacer between the contact and the stack; and a first support structure and a second support structure extending through the stack. Each of the first support structures includes a first portion and a second portion below the first portion, the second portion having a width greater than the first portion. The width of each of the second support structures is constant or decreases linearly from the top to the bottom of the second support structure. Attached Figure Description

[0007] Figure 1 This is a diagram illustrating a memory device according to an embodiment of the present disclosure;

[0008] Figure 2 This is a diagram illustrating a memory device according to an embodiment of the present disclosure;

[0009] Figures 3A to 3C This is a diagram illustrating a memory device including a support structure according to an embodiment of the present disclosure;

[0010] Figures 4A to 4K This is a diagram illustrating a method for manufacturing a memory device including a support structure according to an embodiment of the present disclosure;

[0011] Figure 5 This is a diagram illustrating a memory device according to an embodiment of the present disclosure, including a support structure extending through the source structure;

[0012] Figures 6A to 6C This is a diagram illustrating a memory device including a first support structure and a second support structure according to some embodiments of the present disclosure;

[0013] Figures 7A to 7C This is a diagram showing the positional relationship between the support structure and the contact elements according to an embodiment of the present disclosure;

[0014] Figure 8 This is a diagram illustrating a memory card system using a memory device according to an embodiment of the present disclosure; and

[0015] Figure 9 This is a diagram illustrating a solid-state drive (SSD) system for a memory device applied according to an embodiment of the present disclosure. Detailed Implementation

[0016] The specific structural or functional descriptions illustrating examples of embodiments of the concepts disclosed in this specification are provided for the purpose of describing examples of embodiments of the concepts only, and examples of embodiments of the concepts can be implemented in various forms, but the descriptions are not limited to the examples of embodiments described in this specification.

[0017] In the following, some embodiments of the present disclosure are described in detail with reference to the accompanying drawings to enable those skilled in the art to implement the technical spirit of the present disclosure. Embodiments of the memory device and its manufacturing method may reduce defects in the laminate by improving the shape of the support structure.

[0018] Figure 1 This is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0019] Reference Figure 1 The memory device 100 may include a memory cell array 110, peripheral circuitry 170, and control circuitry 180.

[0020] The memory cell array 110 may include first memory blocks BLK1 to the i-th memory block BLKi. Each of the first memory blocks BLK1 to the i-th memory block BLKi may include a memory cell capable of storing data. Drain select line DSL, word line WL, source select line SSL, and source line SL may be connected to each of the first memory blocks BLK1 to the i-th memory block BLKi, and bit line BL may be collectively connected to the first memory blocks BLK1 to the i-th memory block BLKi.

[0021] The first memory block BLK1 to the i-th memory block BLKi can be formed with a three-dimensional structure. These memory blocks with a three-dimensional structure can include memory cells stacked vertically from the substrate. (Refer to the following...) Figure 2 , Figure 3A and Figure 3B Describe the configuration of the first memory block BLK1 to the i-th memory block BLKi, which have a three-dimensional structure.

[0022] Depending on the programming method, a memory cell can store one bit of data or two or more bits of data. For example, storing one bit of data in a single memory cell is called the single-level cell method, and storing two bits of data is called the multi-level cell method. Storing three bits of data in a single memory cell is called the three-level cell method, and storing four bits of data in a single memory cell is called the four-level cell method. Additionally, five or more bits of data can be stored in a single memory cell.

[0023] The peripheral circuitry 170 can perform programming operations for storing data in the memory cell array 110, reading operations for outputting data stored in the memory cell array 110, and erasing operations for erasing data stored in the memory cell array 110. For example, the peripheral circuitry 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and input / output circuitry 160.

[0024] Voltage generator 120 can generate various operating voltages Vop for programming, reading, or erasing operations in response to operation code OPCD. For example, voltage generator 120 can generate programming voltage, turn-on voltage, turn-off voltage, negative voltage, pre-charge voltage, verification voltage, read voltage, pass voltage, or erase voltage in response to operation code OPCD. The operating voltage Vop generated by voltage generator 120 can be applied to the drain select line DSL, word line WL, source select line SSL, and source line SL of a selected memory block via line decoder 130.

[0025] Programming voltages can be applied to selected word lines (WL) during programming operations, and these voltages can be applied to increase the threshold voltage of the memory cell connected to the selected word line. Turn-on voltages can be applied to the drain select line (DSL) or the source select line (SSL), and these voltages can be applied to turn on the drain select transistor or the source select transistor. Turn-off voltages can be applied to the drain select line (DSL) or the source select line (SSL), and these voltages can be applied to turn off the drain select transistor or the source select transistor. For example, the turn-off voltage can be set to 0V. A precharge voltage higher than 0V can be applied to the bit line during read operations. Verification voltages can be applied during verification operations to determine if the threshold voltage of the selected memory cell has risen to a target level. Verification voltages can be set to various levels based on the target level and can be applied to the selected word line.

[0026] A read voltage can be applied to a selected word line during a read operation on a selected memory cell. For example, the read voltage can be set to various levels depending on how the selected memory cell is programmed. Voltages can be applied to unselected word lines WL during programming or read operations, and they can be applied to turn on memory cells connected to the unselected word lines. Erase voltages can be applied to the source lines SL, and they can be applied during erase operations to erase memory cells included in a selected memory block.

[0027] The row decoder 130 can transmit the operating voltage Vop to the drain select line DSL, word line WL, source select line SSL, and source line SL connected to the selected memory block according to the row address RADD. For example, the row decoder 130 can be connected to the voltage generator 120 via a global line and connected to the first memory block BLK1 to the i-th memory block BLKi via the drain select line DSL, word line WL, source select line SSL, and source line SL.

[0028] Page buffer group 140 may include page buffers (not shown) respectively connected to first memory blocks BLK1 through i-th memory blocks BLKi. More specifically, the page buffers may be connected to the first memory blocks BLK1 through i-th memory blocks BLKi respectively via bit lines BL. During a read operation, the page buffers may sense a current or voltage across the bit lines, which changes in response to the page buffer control signal PBSIG according to a threshold voltage of the selected memory cell, and they may temporarily store the sensed data.

[0029] The column decoder 150 can transfer data between the page buffer group 140 and the input / output circuitry 160 in response to the column address CADD. For example, the column decoder 150 can be coupled to the page buffer group 140 via column line CL, and it can transmit an enable signal via column line CL. In response to the enable signal, the page buffers (not shown) included in the page buffer group 140 can receive or output data via data line DL.

[0030] Input / output circuitry 160 can receive or output commands (CMD), addresses (ADD), or data via input / output lines (I / O). For example, input / output circuitry 160 can transmit commands (CMD) and addresses (ADD) received from an external controller to control circuitry 180 via input / output lines (I / O), and it can transmit data received from an external controller to page buffer group 140 via input / output lines (I / O). Alternatively, input / output circuitry 160 can output data received from page buffer group 140 to an external controller via input / output lines (I / O).

[0031] Control circuit 180 can output at least one of the following in response to command CMD and address ADD: operation code OPCD, row address RADD, page buffer control signal PBSIG, or column address CADD. For example, when command CMD input to control circuit 180 corresponds to a programming operation, control circuit 180 can control peripheral circuit 170 to perform a programming operation on the memory block selected by address ADD. When command CMD input to control circuit 180 corresponds to a read operation, control circuit 180 can control peripheral circuit 170 to perform a read operation on the memory block selected by address and output the read data. When command CMD input to control circuit 180 corresponds to an erase operation, control circuit 180 can control peripheral circuit 170 to perform an erase operation on the selected memory block.

[0032] Figure 2 This is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0033] Reference Figure 2 The memory device 100 may include a peripheral circuit structure PC and a first memory block BLK1 to the i-th memory block BLKi disposed on a substrate SUB. The first memory block BLK1 to the i-th memory block BLKi may overlap with the peripheral circuit structure PC.

[0034] The substrate SUB can be a single-crystal semiconductor layer. For example, the substrate SUB can be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or a selectively epitaxial thin layer formed by a selective epitaxial growth method.

[0035] The peripheral circuit structure PC may include a row decoder 130, a column decoder 150, a page buffer group 140, and a control circuit 180, which constitute circuitry for controlling the operation of the first memory block BLK1 to the i-th memory block BLKi. For example, the peripheral circuit structure PC may include NMOS transistors, PMOS transistors, resistors, and capacitors electrically connected to the first memory block BLK1 to the i-th memory block BLKi. The peripheral circuit structure PC may be disposed between the substrate SUB and the first memory block BLK1 to the i-th memory block BLKi.

[0036] Each of the first memory block BLK1 to the i-th memory block BLKi may include a source structure, bit lines, a cell string electrically connected to the source structure and the bit lines, a word line electrically connected to the cell string, and a selected word line electrically connected to the cell string. Each cell string may include a memory cell and a select transistor connected in series via cell plugs. Each select line may serve as the gate electrode of the corresponding select transistor, and each word line may serve as the gate electrode of the corresponding memory cell.

[0037] In another embodiment, the substrate SUB, the peripheral circuit structure PC, and the first memory blocks BLK1 to the i-th memory blocks BLKi can be coupled with... Figure 2 The stacking order shown is the reverse of the previous order. For example, the peripheral circuit structure PC can be placed on top of the first memory block BLK1 to the i-th memory block BLKi.

[0038] In another embodiment, with Figure 2 In different embodiments, the peripheral circuit structure PC can be disposed on a portion of the substrate SUB that does not overlap with the first memory blocks BLK1 to the i-th memory blocks BLKi. For example, the peripheral circuit structure PC and the first memory blocks BLK1 to the i-th memory blocks BLKi can be disposed in different regions of the substrate SUB.

[0039] Figures 3A to 3C This is a diagram illustrating a memory device including a support structure according to an embodiment of the present disclosure. Figure 3B It corresponds to Figure 3A The cross-sectional view of section A-A'. Figure 3C This is an explanation Figure 3B A three-dimensional view of one of the unit plugs CPL and one of the support structures SS.

[0040] Reference Figure 3A The memory device 100 may include a cell region CR and a contact region CTR. The contact region CTR may be located in the X direction relative to the cell region CR. The contact region CTR may extend from the cell region CR in the X direction. Figure 3A Unlike other regions, the contact area CTR can extend from the element region CR in the Y direction, or it can extend in both the X and Y directions. Furthermore, the element region CR and the contact area CTR can be arranged in various ways.

[0041] Cell plugs (CPLs) may be located within cell regions (CR). Cell plugs (CPLs) may be arranged along the X and Y directions. Cell plugs (CPLs) may be spaced apart from each other in the X and Y directions. Each of the cell plugs (CPLs) may extend in the Z direction. Each of the cell plugs (CPLs) may be electrically connected to a bitline (e.g., via a wiring structure) via a wiring structure. Figure 1 Bit lines (BL) and source lines (e.g., Figure 1 (Source line SL in the middle).

[0042] Each of the cell plugs (CPLs) may include a memory layer ML, a channel layer CH, and a core pillar CO. The memory layer ML may have a cylindrical shape. The memory layer ML may surround the periphery of the channel layer CH. The memory layer ML may include a blocking layer BX, a charge trapping layer CTL, and a tunneling layer TX. The channel layer CH may be formed along the inner wall of the memory layer ML. The core pillar CO may fill the interior of the channel layer CH. The core pillar CO may have a cylindrical shape and be surrounded by the channel layer CH.

[0043] The blocking layer BX and tunneling layer TX may comprise an oxide layer (e.g., a silicon oxide layer), an oxide-oxygen nitride layer (e.g., a silicon-oxygen nitride layer), or a combination thereof. The charge trapping layer CTL may comprise a nitride layer or a variable resistance material. The channel layer CH may comprise an undoped or doped silicon layer. The core post CO may comprise an insulating layer (e.g., an oxide layer).

[0044] The contact element CT can be located within the contact area CTR. Multiple contacts can be positioned within the contact area CTR, and... Figure 3A Only some contact elements (CTs) are shown in the diagram. Contact elements (CTs) can extend in the Z direction. Contact elements (CTs) can include conductive material. Contact elements (CTs) can also be referred to as contact plugs.

[0045] Spacers SP may surround the side surfaces of contacts CT. Contacts CT may fill the interior of spacers SP. Spacers SP may include an insulating layer. For example, spacers SP may include an oxide layer.

[0046] Support structures SS can be located within the contact area CTR. Support structures SS can be spaced apart from each other. Support structures SS can include insulating material. Support structures SS can be arranged around the periphery of the contact element CT. Each contact element CT can be arranged to be surrounded by a support structure SS. However, as... Figure 3A The arrangement of the support structures SS and contact elements CT shown is an example, and various other implementations are possible. For example, there may be five or fewer, or seven or more, support structures SS adjacent to each of the contact elements CT.

[0047] Reference Figure 3B The memory device 100 may include a stacked element STK. The stacked element STK may include a conductive layer CD and an interlayer insulating layer IL. The conductive layer CD and the interlayer insulating layer IL may be stacked alternately in the Z direction. The conductive layer CD may include at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polysilicon (poly-Si). The conductive layer CD may correspond to a gate line (e.g., Figure 1 The drain select line (DSL), word line (WL), and source select line (SSL) are included. The interlayer insulating layer (IL) may include an oxide layer (e.g., a silicon oxide layer).

[0048] Cell plugs (CPLs) can extend through the cell region (CR) of a stacked array (STK). Each cell plug (CPL) may include a memory layer (ML), a channel layer (CH), a capping layer (CAP), and a core pillar (CO). The capping layer (CAP) may contact the channel layer (CH). The capping layer (CAP) may be located on the core pillar (CO). Memory cells and select transistors may be formed at the intersection of the cell plug (CPL) and the conductive layer (CD), respectively. The cell plug (CPL) can serve as the channel region of a cell string.

[0049] Contacts CT may extend in the Z-direction within the contact region CTR of the laminate STK. Each contact CT may contact one of the conductive layers CD. For example, a contact CT may extend in the Z-direction from a first conductive layer CD1 included in the conductive layers CD of the laminate STK. The lower surface of the contact CT may contact a portion of the upper surface of the first conductive layer CD1. The contact CT may be electrically connected to the first conductive layer CD1.

[0050] According to this disclosure, the stacked element STK may not be formed as a stepped structure. For example, within the contact region CTR, the stacked element STK may not be stepped. Therefore, the contact CT may penetrate a portion of the stacked element STK. For example, the contact CT may penetrate the second conductive layer CD2 located on top of the first conductive layer CD1. The contact CT may be electrically isolated from the second conductive layer CD2.

[0051] Spacer SP may surround the side surface of contact CT. Spacer SP may be positioned between contact CT and stack STK. Spacer SP may isolate contact CT from other conductive layers CD except for the first conductive layer CD1. For example, spacer SP may isolate contact CT from conductive layers CD located above the first conductive layer CD1 (e.g., the second conductive layer CD2).

[0052] The support structure SS can penetrate the contact area CTR of the laminate STK. The support structure SS can penetrate the conductive layer CD and the interlayer insulating layer IL. The support structure SS can extend in the Z direction.

[0053] Each of the support structures SS may include a first portion P1 and a second portion P2. The second portion P2 may be disposed below the first portion P1. The first portion P1 may be disposed from the second portion P2 along the Z direction. The first portion P1 may penetrate the upper portion of the laminate STK, and the second portion P2 may penetrate the lower portion of the laminate STK.

[0054] Refer to together Figure 3B and Figure 3CThe width WS2 of the second part P2 of the supporting structure SS can be greater than the width WS1 of the first part P1. For example, at the interface between the first part P1 and the second part P2, the width WS1 of the first part P1 can be smaller than the width WS2 of the second part P2. As the distance from the interface between the first part P1 and the second part P2 increases, the width WS2 of the second part P2 can have a value closer to the width WS1 of the first part P1. In another example, the minimum width of the second part P2 can be greater than the maximum width of the first part P1. In another example, the second part P2 can have a width greater than the extension of the first part P1 (e.g., Figure 3C (The dashed line in the middle) is wider.

[0055] At the first level LV1, the width WS1 of the first part P1 of the support structure SS can be substantially the same as the width WC1 of the unit plug CPL. At the second level LV2, which is below the first level LV1, the width WS2 of the second part P2 of the support structure SS can be greater than the width WC2 of the unit plug CPL.

[0056] The side surfaces of the second portion P2 may protrude further toward the stacked component STK than the side surfaces of the first portion P1. Some portions of the upper surface of the second portion P2 may overlap with the first portion P1, while other portions may not overlap. For example, some portions of the upper surface of the second portion P2 may contact the lower surface of the first portion P1, and other portions of the upper surface of the second portion P2 may contact the interlayer insulating layer IL (or conductive layer CD). See reference. Figure 3B The side surface of the supporting structure SS may include grooves GR. In an embodiment, the groove represents a shoulder or shelf, where the width WS2 of the second portion P2 is wider than the width WS1 of the first portion P1, and where the second portion P2 intersects the first portion P1. For example, a portion of the upper surface of the second portion P2 does not overlap with the first portion P1, thereby creating a shoulder or shelf, such as... Figure 3B As shown.

[0057] Reference Figure 3B The interface between the first portion P1 and the second portion P2 may be located at a different level than the interface between the conductive layer CD and the interlayer insulating layer IL. For example, the interface between the first portion P1 and the second portion P2 may be located inside one of the interlayer insulating layers IL. The trench GR formed on the side surface of the support structure SS may be located inside one of the interlayer insulating layers IL. For example, the trench included in the side surface of the support structure SS may be surrounded by one of the interlayer insulating layers IL.

[0058] Figures 4A to 4K This is a diagram illustrating a method for manufacturing a memory device including a support structure according to an embodiment of the present disclosure. Figures 4A to 4KThis describes the steps corresponding to each step during the manufacturing process of the memory device 100. Figure 3A The cross section A-A'.

[0059] Reference Figure 4A An initial stack-up pSTK can be formed on the lower structure LS. The lower structure LS may include a substrate (e.g., Figure 2 The substrate (SUB) may be an initial stack-up (pSTK) that may include an interlayer insulating layer (IL) and a sacrificial layer (SF) stacked alternately on top of each other. The interlayer insulating layer (IL) may include an insulating material. For example, the interlayer insulating layer (IL) may include an oxide layer (e.g., a silicon oxide layer). The sacrificial layer (SF) may include a material that can be selectively removed in subsequent processes. The sacrificial layer (SF) may include a material that has a different etch selectivity than the interlayer insulating layer (IL). For example, the sacrificial layer (SF) may include a nitride layer.

[0060] Subsequently, channel openings CHH and OP can be formed through the initial laminate pSTK. The channel opening CHH can penetrate the cell region CR of the initial laminate pSTK. The channel opening OP can penetrate the contact region CTR of the initial laminate pSTK. The channel openings CHH and OP can expose the side surfaces of the initial laminate pSTK. The channel openings CHH and OP can extend into the lower structure LS. The channel openings CHH and OP can expose a portion of the lower structure LS. The channel openings CHH and OP can have a cylindrical shape. For example, the channel openings CHH and OP can have a circular or elliptical planar shape.

[0061] Channel openings (CHH) and openings (OP) can be formed simultaneously. For example, channel openings (CHH) and openings (OP) may not be formed in separate etching processes, but rather together in a single etching process. During a process that simultaneously etches openings with high aspect ratios, openings (OP) can be formed simultaneously with channel openings (CHH). By simultaneously etching openings with high aspect ratios, the cost and time required for the etching process can be reduced in some implementations. Anisotropic dry etching processes can be performed to form channel openings (CHH) and openings (OP) at specific locations.

[0062] In one embodiment, the channel opening CHH and the opening OP may have the same planar area. In another embodiment, the channel opening CHH and the opening OP may have different planar areas.

[0063] Subsequently, a first sacrificial pattern SFP1 and a second sacrificial pattern SFP2 can be formed in the channel opening CHH and the opening OP. Each of the first sacrificial patterns SFP1 can fill at least a portion of the channel opening CHH. Each of the second sacrificial patterns SFP2 can fill at least a portion of the opening OP. For example, the first sacrificial pattern SFP1 can be located on top of the channel opening CHH. The second sacrificial pattern SFP2 can be located on top of the opening OP. The first sacrificial pattern SFP1 and the second sacrificial pattern SFP2 can include a carbon layer. For example, the first sacrificial pattern SFP1 and the second sacrificial pattern SFP2 can include a carbon layer, a carbon layer and polysilicon, or a carbon layer and a metal nitride (e.g., TiN).

[0064] Reference Figure 4B The first sacrificial pattern SFP1 can be removed from the channel opening CHH. Subsequently, a cell plug CPL can be formed within the channel opening CHH. For example, the memory layer ML, the channel layer CH, and the die CO can be formed sequentially along the inner surface of each of the channel opening CHH. Additionally, a capping layer CAP can be formed that contacts the inner surface of the channel layer CH and the upper surface of the die CO.

[0065] Subsequently, a contact opening COP can be formed in the contact region CTR of the initial laminate pSTK. The contact opening COP can be spaced apart from the opening OP. The contact opening COP can expose the first sacrificial layer SF1 in the sacrificial layer SF. The contact opening COP can extend from the first sacrificial layer SF in the Z direction. The contact opening COP can expose the upper surface of the first sacrificial layer SF1.

[0066] To form the contact opening COP, a process can be performed to alternately remove the interlayer insulating layer IL and the sacrificial layer SF. A process can be performed to sequentially etch the oxide layer and the nitride layer, such that the contact opening COP can be formed to a specific depth (e.g., corresponding to the depth of the first sacrificial layer SF1). Because the etching process is performed in multiple steps, the planar area of ​​the contact opening COP can be larger than the planar area of ​​each of the channel opening CHH or the opening OP.

[0067] Subsequently, a spacer layer SPL can be formed along the inner surface of the contact opening COP. The spacer layer SPL can extend along the side and bottom surfaces of the contact opening COP. The spacer layer SPL can be formed on the side and top surfaces of the initial laminate pSTK exposed through the contact opening COP. The spacer layer SPL can be conformally formed along the side surfaces of the initial laminate pSTK. The spacer layer SPL may include an insulating material. For example, the spacer layer SPL may include an oxide layer.

[0068] Subsequently, a third sacrificial pattern SFP3 can be formed to fill the interior of the contact opening COP. The third sacrificial pattern SFP3 can fill the interior of the spacer layer SPL. The third sacrificial pattern SFP3 can be surrounded by the spacer layer SPL. The third sacrificial pattern SFP3 can be separated from the initial stack-up pSTK by the spacer layer SPL. The third sacrificial pattern SFP3 may include at least one of a carbon layer or polysilicon.

[0069] Subsequently, the upper insulating layer UIL can be stacked on top of the interlayer insulating layer IL and the sacrificial layer SF. The upper insulating layer UIL can cover the cell plug CPL and the second sacrificial pattern SFP2 and the third sacrificial pattern SFP3. The upper insulating layer UIL can include the same material as the interlayer insulating layer IL.

[0070] Reference Figure 4C A portion of the insulating layer UIL can be etched to expose the second sacrificial pattern SFP2. Subsequently, the second sacrificial pattern SFP2 can be removed. With the second sacrificial pattern SFP2 removed, the opening OP can be revealed and reopened.

[0071] Reference Figure 4D A barrier layer BR can be formed along the inner surface of the opening OP. The barrier layer BR can extend along the side and bottom surfaces of the opening OP. The barrier layer BR can be formed on the side surface of the initial laminate pSTK exposed through the opening OP. The barrier layer BR can extend above the upper surface of the initial laminate pSTK. The barrier layer BR can be conformally formed along the side and top surfaces of the initial laminate pSTK. The barrier layer BR can be formed on the surface of the lower structure LS exposed through the opening OP. After the barrier layer BR is formed, the initial laminate pSTK and the lower structure LS may no longer be exposed through the resulting opening OP'. The barrier layer BR may comprise a metal or a metal nitride (e.g., TiN).

[0072] Reference Figure 4E A capping layer CV can be formed that contacts a portion of the barrier layer BR. The capping layer CV may contact the upper portion of the barrier layer BR but may not contact the lower portion of the barrier layer BR. The capping layer CV may extend along the upper surface of the initial laminate pSTK. The capping layer CV may extend along the side surface of the barrier layer BR formed within the opening OP'. After the capping layer CV is formed, a portion (e.g., the lower portion) of the barrier layer BR may be exposed through the resulting opening OP''. The capping layer CV may include an insulating material. For example, the capping layer CV may include an oxide layer (e.g., ultra-low temperature oxide (ULTO)).

[0073] In an implementation, the capping layer CV can be formed at a depth that contacts a portion (e.g., the upper portion) of the barrier layer BR. For example, the stepped coverage of the capping layer CV can be adjusted so that the capping layer CV can be deposited only to a specified depth of the opening OP' without falling below that depth.

[0074] In another embodiment, a material layer covering the barrier layer BR can be formed, and a portion of the material layer can be removed to form the capping layer CV. For example, the capping layer CV can be formed by selectively etching the lower portion of the material layer that contacts the barrier layer BR.

[0075] The depth of the cover layer CV can be determined independently of the location of the sacrificial layer SF or the interlayer insulation layer IL. The level of the lower portion of the cover layer CV can differ from the level of the interface between the sacrificial layer SF and the interlayer insulation layer IL. For example, the Z-direction position of the lower portion of the cover layer CV can correspond to one of the interlayer insulation layers IL.

[0076] Reference Figure 4F A portion of the barrier layer BR can be removed to form the barrier pattern BRP. Areas of the barrier layer BR not covered by the overlay layer CV can be etched. For example, the portion of the barrier layer BR below the overlay layer CV can be removed. The overlay layer CV can be used as an etch stop layer to etch the lower portion of the barrier layer BR. A portion of the side surface of the initial laminate pSTK can be exposed beneath the barrier pattern BRP. After forming the barrier pattern BRP, the lower portion of the side surface of the initial laminate pSTK can be exposed through the resulting opening OP'''.

[0077] Reference Figure 4G A portion of the initial stack pSTK can be etched through its exposed side surface. Simultaneously with etching this portion of the initial stack pSTK, the capping layer CV can also be removed. While this portion of the initial stack pSTK is being etched, the underlying structure LS may not be etched or may be etched to a lesser extent than the initial stack pSTK. As this portion of the initial stack pSTK is etched, the opening OP''' can be enlarged to form an enlarged opening EOP.

[0078] and Figure 4A Compared to the open OP, each of the enlarged open EOPs can selectively have an enlarged width in the middle section. Figure 4A Compared to the middle portion of each of the openings in OP, the middle portion of each of the openings in EOP can have an increased width. Figure 4G In this context, the middle portion of the enlarged opening EOP can refer to the region corresponding to the lower portion of the initial laminate pSTK. (And...) Figure 4ACompared to the upper portion of the opening OP, the width of the upper portion of the enlarged opening EOP may not be enlarged. The lower portion of each of the enlarged opening EOPs may be relative to... Figure 4A The lower portion of each of the openings OP does not extend in width. Figure 4G In this context, the lower part of the enlarged opening EOP can refer to the region corresponding to the lower structure LS.

[0079] Reference Figure 4H The blocking pattern BRP can be removed. Subsequently, a support structure SS can be formed within the enlarged opening EOP. For example, the support structure SS can be formed by filling the enlarged opening EOP with insulating material.

[0080] Each of the supporting structures SS may include a first portion P1, a second portion P2, and a third portion P3. The first portion P1 may be located in the Z-direction along with the second and third portions P2. The second portion P2 may be located between the first and third portions P1 and P3. The third portion P3 may be located below the first and second portions P1 and P2. The second portion P2 may have a wider width than both the first and third portions P1 and P3. The first portion P1 may have an equal or larger width than the third portion P3. The third portion P3 may be located inside the lower structure LS. The second portion P2 may penetrate the lower portion of the initial laminate pSTK. The first portion P1 may penetrate the upper portion of the initial laminate pSTK.

[0081] Reference Figure 4I The sacrificial layer SF of the initial laminate pSTK can be removed. The sacrificial layer SF can be etched through a slit (not shown) formed through the initial laminate pSTK. As the sacrificial layer SF is removed, empty spaces can be formed between the interlayer insulating layers IL. According to this disclosure, because the support structure SS supports the interlayer insulating layers IL spaced apart from each other, the bending of the interlayer insulating layers IL can be reduced. In particular, as the planar area of ​​the contact opening COP increases, the risk of bending of the interlayer insulating layer IL located below the contact opening COP increases. However, according to this disclosure, the support performance of the support structure SS can be improved because the support structure SS includes a second portion P2 with a width greater than that of the first portion P1.

[0082] Subsequently, a conductive layer CD can be formed in the resulting space after the sacrificial layer SF is removed. The conductive layer CD can fill the space between the interlayer insulating layers IL. Therefore, the sacrificial layer SF can be replaced by the conductive layer CD. For example, Figure 4A The first sacrificial layer SF1 can be replaced by the first conductive layer CD1.

[0083] Reference Figure 4JThe upper insulating layer UIL can be removed to expose the cell plug CPL and the third sacrificial pattern SFP3. The third sacrificial pattern SFP3 within the contact opening COP can then be removed. Subsequently, the lower surface of the spacer layer SPL can be removed to form the spacer SP. The spacer SP can extend along the inner surface of the contact opening COP. With the lower surface of the spacer layer SPL removed, the upper surface of the first conductive layer CD1 can be exposed through the contact opening COP'.

[0084] Reference Figure 4K The contact element CT can be formed within the contact opening COP'. For example, the contact element CT can be formed by filling the inner surface of the contact opening COP' with a conductive material. The contact element CT can be electrically connected to the first conductive layer CD1. The contact element CT can extend from the first conductive layer CD1 in the Z direction.

[0085] Figure 5 This is a diagram illustrating a memory device including a support structure extending through the source structure according to an embodiment of the present disclosure.

[0086] Reference Figure 5 , Figures 4A to 4K The lower structure LS may include a source structure SST and a substrate SUB. The source structure SST may include a first source layer SL1 on the substrate SUB, a second source layer SL2 between the first source layer SL1 and the stacked member STK, and a third source layer SL3 between the first source layer SL1 and the second source layer SL2. A cell plug CPL may extend through the source structure SST. The cell plug CPL may extend into the substrate SUB. The channel layer CH may contact the third source layer SL3. The third source layer SL3 may extend through the memory layer ML and connect to the channel layer CH.

[0087] The support structure SS can extend through the stacked component STK and the source structure SST. The support structure SS can extend into the substrate SUB. The third portion P3 of the support structure SS can extend through the source structure SST and into the substrate SUB. The second portion P2 of the support structure SS can be located on the source structure SST, or they can overlap horizontally with a portion of the source structure SST.

[0088] Reference Figure 5The interface between the first portion P1 and the second portion P2 of each of the support structures SS may correspond to at least one of the conductive layers CD. For example, the interface between the first portion P1 and the second portion P2 may be located inside one of the conductive layers CD. The upper surface of the second portion P2 may contact the lower surface of the first portion P1 and may also contact one of the conductive layers CD. The trenches included in the side surfaces of the support structures SS may be located on the inner surface of one of the conductive layers CD. For example, each of the trenches included in the side surfaces of each of the support structures SS may be surrounded by one of the conductive layers CD.

[0089] Reference Figures 3A to 3C , Figures 4A to 4K and Figure 5 The description includes a support structure SS comprising a second portion P2 having a width larger than the first portion P1. However, in addition to the support structure SS comprising the first portion P1 and the second portion P2 (hereinafter referred to as the first support structure SS1), the memory device 100 according to embodiments of the present disclosure may also include a second support structure SS2 having a constant or decreasing width toward the bottom. (See also...) Figures 6A to 6C The document describes a memory device 100 including a first support structure SS1 and a second support structure SS2.

[0090] Figures 6A to 6C This is a diagram illustrating a memory device including a first support structure and a second support structure according to some embodiments of the present disclosure.

[0091] Reference Figures 6A to 6C The stacked component STK may include a first conductive layer CD1 to a sixth conductive layer CD6 stacked in the Z direction. The first conductive layer CD1 to the sixth conductive layer CD6 may be stacked alternately with an interlayer insulating layer IL. It is understood that the first conductive layer CD1 to the sixth conductive layer CD6 includes... Figure 3B In the conductive layer CD.

[0092] The first contact CT1 to the sixth contact CT6 can extend along the Z direction within the laminate STK. The first contact CT1 to the sixth contact CT6 can respectively contact the first conductive layer CD1 to the sixth conductive layer CD6. It can be understood that the first contact CT1 to the sixth contact CT6 are included within... Figure 3A and Figure 3B In the contact components of CT.

[0093] The contact CT can extend through the conductive layers CD above which it is respectively connected. For example, the first contact CT1 can extend through the second conductive layer CD2 to the sixth conductive layer CD6. Furthermore, because the contact CT has a greater height (e.g., length in the Z direction), it can be formed to have a greater width (e.g., length in the X direction). For example, compared to the second to sixth contacts CT6, the first contact CT1 can have a greater length in the Z direction and a greater length in the X direction. Because the greater the depth of the contact opening COP used to form the contact CT, the greater the number of sacrificial layers SF and interlayer insulating layers IL that need to be etched, the wider the contact opening COP can be.

[0094] First spacers SP1 to sixth spacers SP6 may respectively surround the side surfaces of first contacts CT1 to sixth contacts CT6. First spacers SP1 to sixth spacers SP6 may respectively be disposed between first contacts CT1 to sixth contacts CT6 and the laminate STK. First spacers SP1 to sixth spacers SP6 may be insulated from conductive layers CD other than the conductive layers CD connected to first contacts CT1 to sixth contacts CT6. For example, first spacer SP1 may surround the side surface of first contact CT1. First spacer SP1 may insulate first contact CT1 from second conductive layers CD2 to sixth conductive layers CD6.

[0095] Reference Figures 6A to 6C The memory device 100 may include a first support structure SS1 and a second support structure SS2. The first support structure SS1 and the second support structure SS2 may extend through the laminate STK. The first support structure SS1 and the second support structure SS2 may extend through the first conductive layer CD1 to the sixth conductive layer CD6.

[0096] The first support structure SS1 can each correspond to, as follows: Figures 3A to 3C , Figures 4A to 4K and Figure 5 The support structure SS described herein. For example, each of the first support structures SS1 may include a first portion P1 and a second portion P2 having a greater width than the first portion P1. The second portion P2 may be located below the first portion P1. The first portion P1 and the second portion P2 may be located in the Z direction. The interface between the first portion P1 and the second portion P2 included in the first support structure SS1 may be located at substantially the same level. For example, the height of the second portion P2 included in different first support structures SS1 may be equal to that of each other.

[0097] The width of the second support structure SS2 can be constant or can decrease towards the bottom. For example, the width of the second support structure SS2 can be... Figure 3C The widths of the unit plugs CPL are basically the same. Therefore, in the first level (e.g., Figure 3C At the first level (LV1), the width of the first portion P1 of the first support structure SS1 can be equal to the width of the second support structure SS2. Furthermore, at the second level (e.g., Figure 3C At the second level (LV2), the width of the second part P2 of the first support structure SS1 can be greater than the width of the second support structure SS2.

[0098] Refer to together Figures 4A to 4K Although some of the openings OP are enlarged to form enlarged openings EOP, other openings OP can be covered by the second sacrificial pattern SFP2 and may not be enlarged. The first support structure SS1 may be formed within the enlarged opening EOP, and the second support structure SS2 may be formed within the unenlarged opening OP.

[0099] Reference Figures 6A to 6C The side surface of the first support structure SS1 may include grooves. The side surface of the second support structure SS2 may not include grooves. The side surface of the second support structure SS2 may, for example, be a smooth curved surface in the XY plane extending in a tapered straight line in the Z direction.

[0100] The first support structure SS1 and the second support structure SS2 can be disposed around the periphery of the contact element CT. Within the periphery of the contact element CT, the first support structure SS1 can be disposed in some areas, and the second support structure SS2 can be disposed in other areas. In other words, the first support structure SS1 can be disposed adjacent to a first group of contact elements CT, and the second support structure SS2 can be disposed adjacent to a second group of contact elements CT. The first support structure SS1 and the second support structure SS2 can be arranged in various ways. (Refer to...) Figures 6A to 6C The description is centered on the location where the first support structure SS1 can be set.

[0101] Reference Figure 6A The first support structure SS1 can be disposed around the periphery of the third contact CT3 and the fourth contact CT4, and the second support structure SS2 can be disposed in other areas. The difference between the height of each of the third contact CT3 and the fourth contact CT4 and the height of the first portion P1 of the first support structure SS1 can be less than a threshold value.

[0102] Reference Figure 6BThe first support structure SS1 can be disposed around the periphery of the third contact CT3 to the sixth contact CT6, and the second support structure SS2 can be disposed in other areas. The height of each of the third contact CT3 to the sixth contact CT6 can be less than the height of the first portion P1 of the first support structure SS1 plus a predetermined value of a threshold.

[0103] Reference Figure 6C The first support structure SS1 may be disposed around the periphery of the sixth contact CT6, and the second support structure SS2 may be disposed in other areas. The height of each of the fifth contact CT5 and the sixth contact CT6 may be less than the height of the first portion P1 of the first support structure SS1.

[0104] Apart from Figures 6A to 6C Besides those shown, various other arrangements are also possible. For example, the first support structure SS1 may be selectively formed in the region where the load on the interlayer insulation layer IL at the lower portion of the contact CT is greater than or equal to a threshold. The region where the interlayer insulation layer IL has a high load at the lower portion of the contact CT may include regions where the support structures SS are spaced far apart due to the large size of the contact CT, or regions where the length of the contact CT is reduced such that the interlayer insulation layer IL may not be supported in the region where the sacrificial layer SF is removed.

[0105] Figures 7A to 7C This is a diagram showing the positional relationship between the support structure and the contact element according to some embodiments of this disclosure.

[0106] Figures 7A to 7C It shows Figure 3B Various positional relationships between the supporting structure SS and the contact element CT.

[0107] Reference Figure 7A The support structure SS does not need to vertically overlap with the contact element CT and the spacer element SP.

[0108] Reference Figure 7B The second part P2 of the support structure SS can vertically overlap with the contact CT. The second part P2 of the support structure SS can extend through the interlayer insulation layer IL located below the contact CT.

[0109] Reference Figure 7C The second part P2 of the support structure SS can vertically overlap with the contact element CT and can contact the spacer SP. (See reference...) Figure 4G While forming the enlarged opening EOP, a portion of the spacer layer SPL can be exposed, and a support structure SS can be formed within the enlarged opening EOP.

[0110] Apart from Figures 7A to 7CIn addition, any implementation that forms the support structure SS including the second part P2 can fall within the scope of this disclosure.

[0111] Figure 8 This is a block diagram illustrating a memory card system 3000 according to an embodiment of the present disclosure.

[0112] Reference Figure 8 The memory card system 3000 may include a controller 3100, a memory device 3200, and a connector 3300.

[0113] Controller 3100 can be coupled to memory device 3200. Controller 3100 can access memory device 3200. For example, controller 3100 can control programming, reading, erasing, and background operations of memory device 3200. Controller 3100 provides an interface between memory device 3200 and a host. Controller 3100 can drive firmware for controlling memory device 3200. For example, controller 3100 may include components such as random access memory (RAM), processing unit, host interface, memory interface, and ECC circuitry.

[0114] Controller 3100 can communicate with external devices via connector 3300. Controller 3100 can communicate with external devices (e.g., a host) based on a specific communication protocol. For example, controller 3100 can communicate with external devices via at least one of various communication protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and Non-Volatile Memory Fast (NVMe) protocols. For example, connector 3300 can be defined by at least one of the aforementioned communication protocols.

[0115] Memory device 3200 may include a plurality of memory cells and is configured in accordance with the reference above. Figure 1 The memory device 100 described is configured in the same manner.

[0116] The controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form a memory card. For example, the controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to form memory cards such as PCMCIA cards, compact flash (CF) cards, smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, micro MMC or eMMC), SD cards (SD, miniSD, microSD or SDHC), universal flash memory (UFS), etc.

[0117] Figure 9 This is a block diagram illustrating a solid-state drive (SSD) system 4000 that applies a memory device according to the present disclosure.

[0118] Reference Figure 9 The SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals with the host 4100 via a signal connector 4001 and may receive power via a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a cache memory 4240.

[0119] The controller 4210 can control multiple memory devices 4221 to 422n in response to signals received from the host 4100. In implementations, the signals can be based on the interface between the host 4100 and the SSD 4200. For example, the signals can be defined by at least one of various interfaces, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and Non-Volatile Memory Fast (NVMe) interface.

[0120] The plurality of memory devices 4221 to 422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221 to 422n can be coupled with... Figure 1 The memory device 100 shown is configured in the same manner. Multiple memory devices 4221 to 422n can communicate with the controller 4210 via channels CH1 to CHn.

[0121] Auxiliary power supply 4230 can be connected to host 4100 via power connector 4002. Auxiliary power supply 4230 can be powered and charged by host 4100. When power supply from host 4100 is unstable, auxiliary power supply 4230 can provide power to SSD 4200. For example, auxiliary power supply 4230 can be located inside or outside SSD 4200. For example, auxiliary power supply 4230 can be mounted on the motherboard and supply auxiliary power to SSD 4200.

[0122] Buffer memory 4240 can be used as a buffer memory for SSD 4200. For example, buffer memory 4240 may store data received from host 4100 or data received from a plurality of memory devices 4221 to 422n, or it may store metadata (e.g., a mapping table) of the memory devices 4221 to 422n. Buffer memory 4240 may include volatile memory such as DRAM, SDRAM, DDR SDRAM and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM and PRAM.

[0123] According to embodiments of this disclosure, defects such as bending or warping of the stacked layers can be reduced by improving the shape of the support structure.

[0124] It will be apparent to those skilled in the art that various modifications can be made to the above-described embodiments of this disclosure without departing from the spirit or scope of this teaching. Therefore, this teaching is intended to cover all such modifications, provided they fall within the scope of the appended claims and their equivalents.

[0125] Cross-references to related applications

[0126] This application claims priority to Korean Patent Application No. 10-2025-0053621, filed on April 24, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: A laminate comprising conductive layers and interlayer insulating layers that are alternately stacked on top of each other; Unit plug, the unit plug extending through the stack; A contact element that is in electrical contact with at least one of the conductive layers; A spacer between the contact member and the laminate; as well as A support structure extending through the laminated member, The supporting structure includes a first portion and a second portion below the first portion, the second portion having a wider width than the first portion. The interface between the first part and the second part is located at a different level than the interface between the conductive layer and the interlayer insulating layer.

2. The memory device according to claim 1, wherein, A portion of the upper surface of the second part does not overlap with the first part.

3. The memory device according to claim 1, wherein, The upper surface of the second portion contacts the lower surface of the first portion and contacts at least one of the interlayer insulating layers.

4. The memory device according to claim 1, wherein, The upper surface of the second portion is in contact with the lower surface of the first portion and with at least one of the conductive layers.

5. The memory device according to claim 1, wherein, The side surface of the second portion extends laterally into the laminate beyond the side surface of the first portion.

6. The memory device according to claim 1, wherein, The side surface of the support structure includes grooves.

7. The memory device according to claim 6, wherein, The trench is located in at least one of the conductive layers or in at least one of the interlayer insulating layers.

8. The memory device according to claim 1, wherein, At the first level, the width of the first portion is approximately equal to the width of the unit plug, and Wherein, at the second level below the first level, the width of the second portion is greater than the width of the unit plug.

9. The memory device of claim 1, further comprising a lower structure disposed beneath the laminate. in, The support structure also includes a third portion extending from the second portion into the lower structure, and The width of the third part is smaller than the width of the second part.

10. The memory device according to claim 1, wherein, The contact element does not overlap with the support structure in the vertical direction.

11. The memory device according to claim 1, wherein, The contact element overlaps with the second part in the vertical direction.

12. The memory device according to claim 1, wherein, The contact element overlaps with the second part in the vertical direction, and The spacer is in contact with the second part.

13. A method of manufacturing a memory device, the method comprising the following steps: Forming an initial laminate consisting of sacrificial layers and interlayer insulating layers that are alternately stacked on top of each other; An opening is formed through the initial stack; A barrier layer is formed on the side surface of the initial laminate exposed through the opening; A covering layer is formed on a portion of the barrier layer, exposing the remaining portion of the barrier layer; A barrier pattern is formed by removing the exposed portion of the barrier layer to expose a portion of the side surface of the initial laminate; An enlarged opening is formed relative to the opening by etching the portion of the side surface of the initial laminate that is exposed by the blocking pattern; as well as A support structure is formed in the enlarged opening.

14. The method according to claim 13, wherein, The step of forming the barrier layer includes forming the barrier layer on the side surface of the initial laminate and on the top surface of the initial laminate.

15. The method according to claim 13, wherein, The step of forming the cover layer includes: forming the cover layer to contact the upper portion of the barrier layer and exposing the lower portion of the barrier layer.

16. The method according to claim 15, wherein, The step of forming the blocking pattern includes forming the blocking pattern by removing the exposed lower portion of the blocking layer.

17. The method according to claim 15, wherein, The step of forming the enlarged opening includes selectively increasing the width of the lower portion of the opening.

18. The method according to claim 13, wherein, The step of forming the enlarged opening includes removing the cover layer when etching the portion of the side surface of the initial laminate that is exposed by the blocking pattern.

19. The method of claim 13, further comprising the step of: The blocking pattern is removed after the enlarged opening is formed.

20. The method according to claim 13, wherein, The step of forming the support structure includes filling the enlarged opening with an insulating material.

21. The method according to claim 13, further comprising the following step: After the support structure is formed A laminate is formed by replacing the sacrificial layer with a conductive layer; as well as A contact that forms an electrical contact with at least one of the conductive layers and extends upward from at least one of the conductive layers.

22. A memory device, the memory device comprising: A laminate comprising conductive layers and interlayer insulating layers that are alternately stacked on top of each other; A contact element that is in electrical contact with the conductive layer; A spacer between the contact member and the laminate; as well as A first support structure and a second support structure, the first support structure and the second support structure extending through the laminated member. Each of the first support structures includes a first portion and a second portion below the first portion, wherein the second portion has a width greater than that of the first portion, and In this second support structure, the width of each second support structure is constant or decreases linearly from the top to the bottom in a tapered manner.

23. The memory device according to claim 22, wherein, At the first level, the width of the first portion is approximately equal to the width of each of the second support structures in the second support structure, and Wherein, at the second level below the first level, the width of the second portion is greater than the width of each of the second support structures in the second support structure.

24. The memory device according to claim 22, wherein, Each of the first support structures includes a groove on its side surface, and Wherein, the side surface of each of the second support structures in the second support structure does not include a groove.

25. The memory device according to claim 22, wherein, The conductive layer includes a first conductive layer and a second conductive layer above the first conductive layer. The contact element includes a first contact element that electrically contacts the first conductive layer and a second contact element that electrically contacts the second conductive layer. The first contact extends through the second conductive layer.

26. The memory device according to claim 25, wherein, The width of the first contact is greater than the width of the second contact.

27. The memory device according to claim 22, wherein, The contact elements include a first group and a second group. The first support structure is disposed adjacent to the contact members of the first group, and The second support structure is disposed adjacent to the contact element of the second group.

28. The memory device according to claim 27, wherein, The difference between the height of each contact in the first group and the height of the first portion is less than a threshold.

29. The memory device according to claim 27, wherein, The height of each contact in the first group is less than a threshold, and The threshold is obtained by adding a predetermined value to the height of the first part.

30. The memory device according to claim 27, wherein, The height of each contact in the first group is less than the height of the first part.

Images