A ferroelectric transistor based on a multi-layer SOI substrate and a preparation method thereof
Patent Information
- Application Number
- CN202610981081.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-02
- Publication Date
- 2026-10-27
AI Technical Summary
[0005]本发明的目的在于克服传统铁电晶体管阵列存储密度有限和漏电显著的问题，提供高密度、低功耗的铁电晶体管NAND阵列
本发明通过以下方法有效提升了存储器件的存储密度并降低了漏电功耗：
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Figure CN122995159A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor memory device technology, and in particular to a ferroelectric transistor, a ferroelectric NAND array, and a method for fabricating the same, based on a multilayer SOI substrate. Background Technology
[0002] With the rapid development of artificial intelligence and large-scale modeling technology, the global data generation volume is growing at an unprecedented rate. In recent years, HfO2-based ferroelectric transistors have been regarded as a strong competitor to next-generation high-density non-volatile memory due to their advantages such as fast read / write speeds, low power consumption, and compatibility with CMOS processes. Furthermore, due to their similarity to traditional flash memory structures, they are easy to manufacture using various mature processes, forming the "FeNAND" technology route, which the industry has actively pursued. It is generally believed that compared to continuously pushing the miniaturization of planar arrays, shifting to three-dimensional integration solutions has more significant technological advantages and development prospects. However, HfO2-based ferroelectric transistors based on bulk silicon planar structures lack an effective way to achieve vertical stacking, and simple planar integration cannot achieve a leapfrog increase in storage density. In addition, as device channel lengths continue to shorten, the gate's control over the channel weakens, leading to problems such as short-channel effects and increased leakage current, failing to meet low-power requirements.
[0003] Existing 3D NAND solutions utilize a vertically stacked GAA (Glass-Aperture Alignment) architecture with high aspect ratios to increase storage capacity. However, this approach is complex, costly, and unsuitable for low-power storage applications. Therefore, a novel architecture and operating scheme are urgently needed to achieve high-density, low-power HfO2-based ferroelectric NAND arrays through vertical stacking of ferroelectric transistors and interface engineering.
[0004] In view of this, the present invention is proposed. Summary of the Invention
[0005] The purpose of this invention is to overcome the problems of limited storage density and significant leakage current of traditional ferroelectric transistor arrays, and to provide a high-density, low-power ferroelectric transistor NAND array.
[0006] In a first aspect, the present invention provides a ferroelectric transistor based on a multilayer SOI substrate, comprising: The substrate is the bottom buried oxide layer of a multilayer SOI substrate; A Fin structure located on the substrate, the Fin structure being formed from the multilayer SOI substrate, comprising multiple vertically alternating silicon layers and multiple buried oxide layers, wherein steps are provided at both ends of the Fin structure to expose the two ends of each silicon layer in the Fin structure as the source and drain ends of the corresponding silicon layer; and Multiple gate structures spaced apart along the length of the Fin structure; The multilayer SOI substrate includes multiple silicon layers and multiple buried oxide layers stacked vertically alternately; The gate structure includes vertically stacked ferroelectric layers and a metal gate, wherein the ferroelectric layers are disposed on both sides of the Fin structure and on the top of the Fin structure away from the substrate; The metal gate is disposed on the side of the ferroelectric layer away from the Fin structure, and covers the ferroelectric layer; Except for the vertical projection region of the gate structure, the silicon layer is doped and activated.
[0007] In some embodiments, the material of the buried oxide layer is silicon dioxide.
[0008] In some implementations, the silicon layer is a monocrystalline silicon layer.
[0009] In some embodiments, the material of the ferroelectric layer is selected from at least one of hafnium zirconium oxide, silicon-doped hafnium oxide, aluminum-doped hafnium oxide, yttrium-doped hafnium oxide, gadolinium-doped hafnium oxide, lanthanum-doped hafnium oxide, strontium-doped hafnium oxide, and zirconium-doped hafnium oxide. Preferably, the material of the ferroelectric layer is hafnium zirconium oxide.
[0010] In some embodiments, the material of the metal gate is selected from at least one of titanium nitride, tantalum nitride, conductive oxides, and conductive metals. Preferably, the material of the metal gate is titanium nitride.
[0011] In some embodiments, the thickness of the silicon layer is 8-12 nm, preferably 10 nm. In some embodiments, the width of the Fin structure is 25-35 nm, preferably 30 nm.
[0012] In some embodiments, a channel interface layer is further stacked between the Fin structure and the ferroelectric layer. In some embodiments, a gate interface layer is further stacked between the ferroelectric layer and the metal gate. In some embodiments, an intermediate tunneling dielectric layer is further disposed in the ferroelectric layer.
[0013] In some implementations, the channel interface layer is a SiO2 layer or an Al2O3 layer.
[0014] In some embodiments, the gate interface layer is selected from one or more of the following: SiO2 layer, HfO2 insulating layer, SiO2 / Si3N4 / SiO2 stacked layer, and SiO2 / HfO2 / SiO2 stacked layer.
[0015] In some implementations, the intermediate tunneling dielectric layer is an Al2O3 layer.
[0016] In some embodiments, the thickness of the ferroelectric layer is 8-12 nm, preferably 10 nm. In some embodiments, the thickness of the metal gate is 15-25 nm, preferably 20 nm.
[0017] Secondly, the present invention provides a ferroelectric NAND array based on a multilayer SOI substrate, which includes a plurality of the aforementioned ferroelectric transistors, wherein the corresponding metal gates in the plurality of parallel Fin structures are sequentially connected as word lines, and the source and drain ends at the two ends of the silicon layer in the Fin structure are led out as bit lines.
[0018] Thirdly, the present invention provides a memory comprising a memory array for storing data, the memory array comprising a plurality of the aforementioned ferroelectric transistors or the aforementioned ferroelectric NAND array.
[0019] Fourthly, the present invention provides a method for fabricating the aforementioned ferroelectric transistor or the aforementioned ferroelectric NAND array, comprising the following steps: An oxide thin film is deposited on the top silicon layer of a multilayer SOI substrate; The edge regions of the multilayer SOI substrate are etched step by step to form steps, so as to expose the edges of each silicon layer; Etching penetrates the multilayer SOI substrate to form a Fin structure, while retaining the bottom buried oxide layer as the substrate; A temporary gate dielectric and a dummy gate are sequentially deposited on the surface of the Fin structure, and insulating sidewalls are formed on both sides of the dummy gate along the length direction of the Fin structure. Using the virtual gate and the sidewall as masks, the silicon layer in the multilayer SOI substrate is ion-implanted and then annealed to achieve doping activation. The etched trenches, gaps, and steps are filled with oxide and polished until the top of the virtual gate is exposed. After etching away the temporary gate dielectric and the dummy gate, a ferroelectric layer is deposited, a metal gate is fabricated on the ferroelectric layer, and then annealing is performed. An insulating layer is deposited on the filled oxide and the surface of the metal gate, and contact holes connecting the steps of each layer are etched in the filled oxide to form a vertical conductive channel connecting the source and drain.
[0020] In some embodiments, the temporary gate dielectric is made of SiO2. In some embodiments, the dummy gate is made of polysilicon.
[0021] In some embodiments, the deposition of a channel interface layer is included prior to the deposition of the ferroelectric layer; and / or The process of depositing a gate interface layer is included prior to the fabrication of the metal gate; and / or The step of depositing the ferroelectric layer includes depositing an intermediate tunneling dielectric layer in the ferroelectric layer.
[0022] Fifthly, the present invention provides a method for reading and writing the aforementioned ferroelectric NAND array or the aforementioned memory, comprising: During programming, a positive programming pulse Vwrite is applied to the word line of the target cell. The source and drain lines of the selected layer are connected to GND to achieve polarization reversal of the ferroelectric layer. The polarization reversal points to the channel, which is a low Vth state. A voltage of 1 / 2Vwrite is applied to the source and drain of the word line sharing cell to prevent it from being programmed incorrectly. A zero bias is applied to the word line of the bit line sharing cell, the gate-channel voltage difference is 0, and there is no ferroelectric polarization reversal. During the erase operation, a negative erase pulse -Vwrite is applied to the word line of the target cell. The source and drain lines of the selected layer are connected to GND, realizing the polarization reversal of the ferroelectric layer. The polarization reversal points to the gate, which is a high Vth state. A voltage of -1 / 2Vwrite is applied to the source and drain of the word line shared cell to prevent it from being erased incorrectly. A zero bias voltage is applied to the word line of the bit line shared cell, the gate-channel voltage difference is 0, and there is no ferroelectric polarization reversal. During a read operation, the word line voltages of the selected and unselected cells are increased to Vread and Vpass, respectively, with Vpass being higher than the maximum threshold voltage to ensure that all bit line shared cells remain on. A read voltage Vread is applied to the target cell word line, and a positive voltage Vds is connected to the drain to turn on the channel. No read current is generated if the drain of the word line shared cell is not selected.
[0023] Compared with the prior art, the present invention has at least the following beneficial effects: This invention effectively improves the storage density of storage devices and reduces leakage power consumption through the following methods: Employing a three-dimensional FinFET-based structure, this design enhances gate control over the channel region, effectively suppressing short-channel effects and leakage current. This allows the device to maintain excellent switching performance even at nanoscale channel lengths and significantly improves in-plane storage density. Reports have confirmed that the active region height of a 15nm-width FinFET fin can reach 625nm. With breakthroughs in ultra-high aspect ratio FinFET technology, this approach theoretically enables vertically stacked architectures of 20 or more layers, achieving orders-of-magnitude improvements in storage density.
[0024] The use of a multilayer SOI substrate provides the structural basis for vertical stacking. By controlling the thickness of the single-crystal silicon thin film to 10 nm and its width to 30 nm, it operates in a fully depleted state, achieving extremely low off-state leakage current and minimal static power consumption. The operating voltage is significantly reduced, making it ideal for low-power applications such as IoT and mobile devices.
[0025] Through the above method, the present invention improves the storage density and gate control capability at the three-dimensional scale, effectively overcoming the problems of limited storage density and significant leakage of traditional ferroelectric transistor arrays, and realizing a high-density, low-power ferroelectric transistor NAND array. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0027] Figure 1 This is a schematic diagram of the ferroelectric NAND array based on a multilayer SOI substrate according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the gate stack structure according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the fabrication process of a ferroelectric NAND array based on a multilayer SOI substrate according to an embodiment of the present invention. Figure 4 This is a schematic diagram of a ferroelectric NAND array based on a multilayer SOI substrate, according to an embodiment of the present invention.
[0028] Explanation of reference numerals in the attached figures: 1. Substrate; 2. Step; 3. Fin structure; 4. Gate structure; 11. Word line; 12. Source terminal; 13. Drain terminal; 14. Bit line shared cell; 15. Word line shared cell; 16. Target cell; 31. Silicon layer; 32. Buried oxide layer (silicon dioxide layer); 41. Ferroelectric layer; 42. Metal gate; 43. Channel interface layer; 44. Gate interface layer; 45. Intermediate tunneling dielectric layer. Detailed Implementation
[0029] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.
[0030] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form includes the plural form unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used herein, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof. Unless otherwise stated, all parts, percentages, and ratios used herein are based on mass meters.
[0031] Furthermore, it should be understood that the one or more method steps mentioned in this invention do not preclude the existence of other method steps before or after the combined steps, or the insertion of other method steps between these explicitly mentioned steps, unless otherwise stated; moreover, unless otherwise stated, the numbering of each method step is merely a convenient tool for identifying each method step, and not for limiting the order of the method steps or limiting the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered as within the scope of the invention.
[0032] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0033] The "range" disclosed in this paper is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of the specific range. Ranges defined in this way can include or exclude endpoints and can be combined arbitrarily; that is, any lower limit can be combined with any upper limit to form a range. For example, if 60 is listed for a specific parameter... 120 and 80 The range of 110 is understood to be 60. 110 and 80 The range of 120 is also expected. Furthermore, if the minimum range values 1 and 2 are listed, and if the maximum range values 3, 4, and 5 are listed, then the following ranges are all expected: 1 3.1 4.1 5.2 3, 2 4 and 2 5. In this document, unless otherwise specified, the numerical range "a" is defined as follows: "b" represents a shortened representation of any combination of real numbers from a to b, where both a and b are real numbers. For example, the numerical range "0"... "5" indicates that all "0"s have been listed in this article. All real numbers between "5" and "0". "5" is simply an abbreviation for these numerical combinations. In addition, when a parameter is expressed as an integer greater than or equal to 2, it is equivalent to disclosing that the parameter is, for example, an integer such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.
[0034] Furthermore, the numerical ranges and parameters used to define the present invention are approximate values, and the relevant values in the specific embodiments have been presented as precisely as possible. However, any value inevitably contains standard deviations due to individual test methods. Therefore, unless explicitly stated otherwise, it should be understood that all ranges, quantities, values, and percentages used in this disclosure are modified with the word "approximately." Here, "approximately" generally means an actual value within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range.
[0035] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0036] Example Figure 1 This is a schematic diagram of a ferroelectric NAND array based on a multilayer SOI substrate according to an embodiment of the present invention. The ferroelectric NAND array of this embodiment includes a substrate 1 and multiple ferroelectric transistors located on the substrate 1. The substrate 1 is the bottom SiO2 layer of the multilayer SOI substrate. The ferroelectric transistors include a Fin structure 3 and multiple gate structures 4 spaced apart along the length direction of the Fin structure. The Fin structure 3 is formed from a multilayer SOI substrate and includes multiple vertically alternating silicon layers 31 and multiple SiO2 layers 32. Except for the vertical projection region of the gate structure 4, all silicon layers 31 are doped and activated. The silicon layers in the vertical projection region of the gate structure 4 serve as channels. The two ends of the Fin structure 3 have steps 2 as the source and drain terminals of the corresponding silicon layers. The gate structures 4 are disposed on both sides of the Fin structure 3 and on the top of the Fin structure 3 away from the substrate 1. The corresponding gate structures 4 of the multiple parallel-arranged ferroelectric transistors are connected sequentially.
[0037] The gate structure 4 includes a ferroelectric layer 41 and a metal gate 42. The ferroelectric layer 41 is disposed on both sides of the Fin structure 3 and on the top of the Fin structure 3 away from the substrate 1. The metal gate 42 covers the ferroelectric layer 41 on the side of the ferroelectric layer 41 away from the Fin structure 3. In some embodiments, the material of the ferroelectric layer 41 is HfZrO. x The metal gate 42 is made of TiN layer.
[0038] The source and drain terminals at step 2 serve as bit line leads, the SiO2 layer 32 serves as interlayer isolation, and the metal gate 42 serves as a word line, controlling all covered ferroelectric transistors.
[0039] like Figure 2 As shown, gate structure 4 can be designed as different gate stacking structures.
[0040] In some embodiments, a channel interface layer 43 is provided between the ferroelectric layer 41 and the Fin structure 3 to form an MFIS structure. Figure 2 A), the material of the channel interface layer 43 can be SiO2. In some embodiments, a gate interface layer 44 is further provided between the ferroelectric layer 41 and the metal gate 42. Figure 2 B), forming a MIFIS gate stack, wherein the material of the gate interface layer 44 can be SiO2. In some embodiments, the ferroelectric layer 41 further comprises an intermediate tunneling dielectric layer 45 ( Figure 2 C), the material of the intermediate tunneling dielectric layer 45 can be Al2O3.
[0041] In some embodiments, the gate interface layer 44 is a 2 / 2 / 2nm thick SiO2 / Si3N4 / SiO2 ( Figure 2 D), forming a BE-MIFIS bandgap engineered gate stack structure with an ONO gate interface layer.
[0042] In some embodiments, the gate interface layer 44 includes a SiO2 layer and a high-dielectric-constant HfO2 insulating material, forming a MIKFIS gate stack structure. Figure 2 E).
[0043] In some embodiments, the gate interface layer 44 is a 1.5 / 2.5 / 1.5 nm thick SiO2 / HfO2 / SiO2, forming a MIFIS gate stack structure with an SHS gate interface layer. Figure 2 F).
[0044] In some embodiments, the channel interface layer 43 is made of Al2O3 and is used as a thermally stable high dielectric constant interface layer. Figure 2 F).
[0045] like Figure 3As shown, the specific steps of the fabrication method of HfO2-based ferroelectric transistors based on vertically stacked multilayer SOI substrates in this embodiment are as follows: First, in step S100, a multilayer SOI substrate is prepared. This requires finding a suitable manufacturer to provide at least two SOI substrates, with the Si layer thickness controlled to 10 nm to meet the full depletion requirement. Based on this, the fabrication method of vertically stacked ferroelectric transistors in a Fin structure according to this embodiment includes the following steps: Step S101: Deposit a SiO2 thin film on the top layer Si of the multilayer SOI substrate for isolation of the top layer Si channel and word line, ensuring the consistency of channel control of the gate of each ferroelectric transistor layer; Step S102: The multilayer SOI substrate is etched step by step in the edge region of the array to form steps, providing a contact platform for the electrical lead-out of the bit lines; Step S103: Etch downwards through multiple Si / SiO2 stacks to form a high aspect ratio Fin structure with a Fin width of 30nm, in order to achieve full depletion of the Si channel; Step S104: Using a back-gate process, a SiO2 buffer layer (temporary gate dielectric) is deposited on the surface of the Fin structure, followed by the deposition of polysilicon as a dummy gate material; Step S105: Form insulating sidewalls on both sides of the virtual gate to define the boundaries of subsequent source / drain injections and protect the virtual gate sidewalls; Step S106: Using the virtual gate and sidewall as masks, ion implantation is performed sequentially on the Si layer in the multilayer SOI substrate, followed by annealing to achieve doping activation; Step S107: Oxide filling, filling the etched trenches, gaps or steps with SiO2 dielectric material to achieve electrical isolation and structural support; Step S108: Subsequently, chemical mechanical polishing and planarization are performed until the top of the polysilicon dummy gate is exposed; Step S109: Use a high-selectivity wet etching or dry etching method to completely remove the polysilicon dummy gate and the underlying temporary gate dielectric; Step S110: Gate stacking and interface engineering, HfZrO is prepared by atomic layer deposition. x Thin film, sputtering to prepare metal gate, and selectively deposit bottom channel interface layer, top gate interface layer, intermediate tunnel dielectric layer, etc., to form a series of gate stack structures such as MFIS and MIFIS, and then annealing in nitrogen atmosphere by RTA process. Step S111: Then, chemical mechanical polishing is performed again to remove excess metal, which serves as the word line of the NAND array; Step S112: Perform interlayer dielectric deposition to cover the insulating layer in order to form electrical isolation between multilayer metal interconnects and reduce parasitic capacitance; Step S113: Contact hole formation, etching out contact holes connecting each layer of steps to form a vertical conductive channel connecting the source and drain electrodes with the upper metal layer.
[0046] In some embodiments, after the virtual polysilicon gate is removed, the SiO2 buffer layer covering the Fin structure is removed, the surface is cleaned with diluted hydrofluoric acid and SC-1 solution, and a 1 nm thick dense SiO2 film is formed as the channel SiO2 interface layer; a 10 nm thick HfZrO is grown by atomic layer deposition at 270 °C. x Thin film: A 20 nm thick TiN layer is deposited by metal sputtering, followed by metallization annealing at 550 °C in a nitrogen atmosphere to crystallize each layer, resulting in an MFIS gate stack structure. Before sputtering the TiN layer, a 3 nm thick SiO2 layer can be deposited using another atomic layer deposition device with water vapor as the oxidant, serving as the gate SiO2 interface layer, thus obtaining the MIFIS gate stack scheme.
[0047] In some embodiments, a gate stacking scheme containing an intermediate tunneling dielectric layer is obtained by inserting a 1 nm thick Al2O3 intermediate layer into the ferroelectric layer through atomic layer deposition.
[0048] In some embodiments, in HfZrO x After the ferroelectric layer deposition is completed, a 2 / 2 / 2 nm thick SiO2 / Si3N4 / SiO2 layer is deposited using atomic layer deposition technology to form a BE-MIFIS bandgap engineering gate stacking scheme with an ONO gate interface layer; and HfZrO x By depositing a layer of HfO2 insulating material with a high dielectric constant on the ferroelectric layer, a MIKFIS gate stack structure can be obtained.
[0049] In some embodiments, an Al2O3 interface layer is inserted between the ferroelectric layer and the silicon channel by atomic layer deposition as a thermally stable high dielectric constant interface layer.
[0050] In some embodiments, in HfZrO x After the ferroelectric layer deposition is completed, 1.5 / 2.5 / 1.5 nm thick SiO2 / HfO2 / SiO2 layers are deposited using atomic layer deposition technology to form a MIFIS gate stacking scheme with an SHS gate interface layer.
[0051] After the gate stacking process is completed, contact electrodes and array interconnect structures are formed through metal deposition and stripping processes.
[0052] The operation scheme of the ferroelectric NAND array based on a multilayer SOI substrate in this embodiment is as follows: Figure 4 As shown in Table 1, a gate control voltage needs to be applied to word line 11, and word line sharing unit 15 is affected by programming and erasing voltages; bit line sharing unit 14 needs to have a pass voltage applied to its gate during read operations to keep the channel on; the drain terminal 13 and source terminal 12 on the same bit line are subject to specific voltages according to the operating state, and the specific operation scheme is as follows: 1. During programming, a positive programming pulse Vwrite is applied to the word line of the target cell 16. The source and drain lines of the selected layer are connected to GND to achieve polarization reversal of the ferroelectric layer. The polarization reversal points to the channel, which is a low Vth state. A voltage of 1 / 2 Vwrite is applied to the source and drain of the word line sharing cell 15 to prevent incorrect programming. A zero bias voltage is applied to the word line of the bit line sharing cell 14, the gate-channel voltage difference is 0, and there is no ferroelectric polarization reversal. 2. During the erase operation, a negative erase pulse -Vwrite is applied to the word line of the target cell 16. The source and drain lines of the selected layer are connected to GND, realizing the polarization reversal of the ferroelectric layer. The polarization reversal points to the gate, which is a high Vth state. A voltage of -1 / 2Vwrite is applied to the source and drain of the word line sharing cell 15 to prevent it from being erased incorrectly. A zero bias voltage is applied to the word line of the bit line sharing cell 14, the gate-channel voltage difference is 0, and there is no ferroelectric polarization reversal. 3. During the read operation, the word line voltages of the selected and unselected cells are increased to Vread and Vpass, respectively. Vpass must be higher than the maximum threshold voltage to ensure that all bit line sharing cells 14 remain on; the read voltage Vread is applied to the word line of the target cell 16, and the drain is connected to a positive voltage Vds to turn on the channel; the drain of the word line sharing cell 15 is not selected, so no read current is generated.
[0053] Table 1. Operation scheme of ferroelectric NAND array based on multilayer SOI substrate
[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A ferroelectric transistor based on a multilayer SOI substrate, characterized in that, The ferroelectric transistor includes: The substrate is the bottom buried oxide layer of a multilayer SOI substrate; A Fin structure located on the substrate, the Fin structure being formed from the multilayer SOI substrate, comprising multiple vertically alternating silicon layers and multiple buried oxide layers, wherein steps are provided at both ends of the Fin structure to expose the two ends of each silicon layer in the Fin structure as the source and drain ends of the corresponding silicon layer; and Multiple gate structures spaced apart along the length of the Fin structure; The multilayer SOI substrate includes multiple silicon layers and multiple buried oxide layers stacked vertically alternately; The gate structure includes vertically stacked ferroelectric layers and a metal gate, wherein the ferroelectric layers are disposed on both sides of the Fin structure and on the top of the Fin structure away from the substrate; The metal gate is disposed on the side of the ferroelectric layer away from the Fin structure, and covers the ferroelectric layer; Except for the vertical projection region of the gate structure, the silicon layer is doped and activated.
2. The ferroelectric transistor according to claim 1, characterized in that, The material of the ferroelectric layer is selected from at least one of hafnium zirconium oxide, silicon-doped hafnium oxide, aluminum-doped hafnium oxide, yttrium-doped hafnium oxide, gadolinium-doped hafnium oxide, lanthanum-doped hafnium oxide, strontium-doped hafnium oxide, and zirconium-doped hafnium oxide; Preferably, the material of the metal gate is selected from at least one of titanium nitride, tantalum nitride, conductive oxide, and conductive metal.
3. The ferroelectric transistor according to claim 1, characterized in that, The thickness of the silicon layer is 8-12 nm, and the width of the Fin structure is 25-35 nm; Preferably, a channel interface layer is further stacked between the Fin structure and the ferroelectric layer; Preferably, a gate interface layer is further stacked between the ferroelectric layer and the metal gate; Preferably, the ferroelectric layer further includes an intermediate tunneling dielectric layer; Preferably, the channel interface layer is a SiO2 layer or an Al2O3 layer; Preferably, the gate interface layer is selected from one or more of the following: SiO2 layer, HfO2 insulating layer, SiO2 / Si3N4 / SiO2 stacked layer, and SiO2 / HfO2 / SiO2 stacked layer; Preferably, the intermediate tunneling dielectric layer is an Al2O3 layer.
4. The ferroelectric transistor according to claim 1, characterized in that, The thickness of the ferroelectric layer is 8-12 nm, and the thickness of the metal gate is 15-25 nm.
5. A ferroelectric NAND array based on a multilayer SOI substrate, characterized in that, The ferroelectric NAND array includes multiple ferroelectric transistors as described in any one of claims 1-4, and the corresponding metal gates in the multiple parallel Fin structures are sequentially connected as word lines, with the source and drain terminals at the two ends of each silicon layer in the Fin structure serving as bit line leads.
6. A memory, characterized in that, The memory includes a storage array for storing data, the storage array including a plurality of ferroelectric transistors as described in any one of claims 1-4 or a ferroelectric NAND array as described in claim 5.
7. A method for fabricating the ferroelectric transistor according to any one of claims 1-4 or the ferroelectric NAND array according to claim 5, characterized in that, Includes the following steps: An oxide thin film is deposited on the top silicon layer of a multilayer SOI substrate; The edge regions of the multilayer SOI substrate are etched step by step to form steps, so as to expose the edges of each silicon layer; Etching penetrates the multilayer SOI substrate to form a Fin structure, while retaining the bottom buried oxide layer as the substrate; A temporary gate dielectric and a dummy gate are sequentially deposited on the surface of the Fin structure, and insulating sidewalls are formed on both sides of the dummy gate along the length direction of the Fin structure. Using the virtual gate and the sidewall as masks, the silicon layer in the multilayer SOI substrate is ion-implanted and then annealed to achieve doping activation. The etched trenches, gaps, and steps are filled with oxide and polished until the top of the virtual gate is exposed. After etching away the temporary gate dielectric and the dummy gate, a ferroelectric layer is deposited, a metal gate is fabricated on the ferroelectric layer, and then annealing is performed. An insulating layer is deposited on the filled oxide and the surface of the metal gate, and contact holes connecting the steps of each layer are etched in the filled oxide to form a vertical conductive channel connecting the source and drain.
8. The preparation method according to claim 7, characterized in that, The temporary gate dielectric is made of SiO2, and the virtual gate is made of polycrystalline silicon.
9. The preparation method according to claim 7, characterized in that, The process includes the step of depositing a channel interface layer prior to depositing the ferroelectric layer; and / or The process of depositing a gate interface layer is included prior to the fabrication of the metal gate; and / or The step of depositing the ferroelectric layer includes depositing an intermediate tunneling dielectric layer in the ferroelectric layer.
10. The method for reading and writing the ferroelectric NAND array according to claim 5 or the memory according to claim 6, characterized in that, include: During programming, a positive programming pulse Vwrite is applied to the word line of the target cell. The source and drain lines of the selected layer are connected to GND to achieve polarization reversal of the ferroelectric layer. The polarization reversal points to the channel, which is a low Vth state. A voltage of 1 / 2Vwrite is applied to the source and drain of the word line shared cell to prevent it from being programmed incorrectly. When a zero bias is applied to the word line of the shared bit line cell, the gate-channel voltage difference is zero, and there is no ferroelectric polarization switching. During the erase operation, a negative erase pulse -Vwrite is applied to the word line of the target cell. The source and drain lines of the selected layer are connected to GND, realizing the polarization reversal of the ferroelectric layer. The polarization reversal points to the gate, which is a high Vth state. A voltage of -1 / 2Vwrite is applied to the source and drain of the word line shared cell to prevent it from being erased incorrectly. A zero bias voltage is applied to the word line of the bit line shared cell, the gate-channel voltage difference is 0, and there is no ferroelectric polarization reversal. During a read operation, the word line voltages of selected and unselected cells are increased to Vread and Vpass, respectively, with Vpass being higher than the maximum threshold voltage to ensure that all bit line shared cells remain on. A read voltage Vread is applied to the target cell word line, and a positive voltage Vds is connected to the drain terminal to turn on the channel; if the drain terminal of the word line shared cell is not selected, no read current is generated.