Semiconductor device and method of manufacturing a semiconductor device

Abstract

A semiconductor device includes an electrode stack including conductive layers and insulating layers, the conductive layers and insulating layers being alternately stacked to form a stepped structure; a conductive plug extending through the electrode stack; a memory cell disposed between the conductive layers and the conductive plug; an interlayer insulating layer disposed on the stepped structure; contact vias extending through the interlayer insulating layer and electrically connected to the conductive layers, respectively, and at least two of the contact vias have different widths; and barrier layers covering the contact vias, respectively, and at least two of the barrier layers have different thicknesses.

Description

Cross-references to related applications

[0001] Pursuant to 35 USC §119, this application claims priority to Korean Patent Application No. 10-2025-0053979, filed April 24, 2025, and Korean Patent Application No. 10-2025-0119316, filed August 26, 2025, which are incorporated herein by reference in their entirety. Technical Field

[0002] Embodiments of this disclosure relate to electronic devices and methods of manufacturing electronic devices, and more particularly, to semiconductor devices and methods of manufacturing semiconductor devices. Background Technology

[0003] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as improvements in the integration density of semiconductor devices with memory cells formed in a single layer on a substrate have reached their limits, three-dimensional semiconductor devices in which memory cells are stacked on a substrate are being proposed. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0004] According to one embodiment of the present disclosure, a semiconductor device may include: an electrode stack including a conductive layer and an insulating layer that are alternately stacked to form a stepped structure; a conductive plug extending through the electrode stack; a memory cell disposed between the conductive layer and the conductive plug; an interlayer insulating layer disposed on the stepped structure; contact vias extending through the interlayer insulating layer and electrically connected to the conductive layer respectively, and at least two contact vias having different widths; and barrier layers covering the contact vias respectively, and at least two barrier layers having different thicknesses.

[0005] According to one embodiment of this disclosure, a semiconductor device may include: an electrode stack including a first conductive layer and a second conductive layer located above the first conductive layer, the first conductive layer extending laterally beyond the second conductive layer to form a stepped structure; a conductive plug extending through the electrode stack; a selection transistor disposed below the electrode stack and connected to the conductive plug; a first memory cell disposed between the first conductive layer and the conductive plug, and spaced from the selection transistor by a first distance; a second memory cell disposed between the second conductive layer and the conductive plug, and spaced from the selection transistor by a second distance greater than the first distance; an interlayer insulating layer disposed on the stepped structure; a first contact structure extending through the interlayer insulating layer to connect to the first conductive layer and having a first resistance; and a second contact structure extending through the interlayer insulating layer to connect to the second conductive layer and having a second resistance less than the first resistance.

[0006] According to one embodiment of the present disclosure, a semiconductor device may include: an electrode stack including alternately stacked conductive layers and insulating layers; a conductive plug extending through the electrode stack; a selection transistor disposed below the electrode stack and connected to the conductive plug; a memory cell disposed between the conductive layers and the conductive plug; and contact structures respectively connected to the conductive layers.

[0007] According to one embodiment of this disclosure, a method of manufacturing a semiconductor device may include: forming a sacrificial stack comprising alternating stacked first and second material layers on a substrate to form a stepped structure exposing an upper surface of the second material layer; forming an interlayer insulating layer on the stepped structure; forming a memory cell in the sacrificial stack; forming a conductive plug extending through the memory cell; forming a slit extending through the sacrificial stack; removing the second material layer through the slit to form an opening; forming an electrode stack by forming conductive layers in the openings respectively; forming contact holes extending through the interlayer insulating layer and exposing conductive layers respectively, at least two contact holes having different heights; forming barrier layers in the contact holes respectively, at least two barrier layers having different thicknesses; and forming contact vias in the barrier layers respectively, at least two contact vias having different widths.

[0008] According to one embodiment of the present disclosure, a method of manufacturing a semiconductor device may include: forming a selection transistor on a substrate; forming a sacrificial stack comprising alternating layers of a first material and a second material on the selection transistor; forming a memory cell in the sacrificial stack; forming a conductive plug extending through the memory cell and connected to the selection transistor; forming a slit extending through the sacrificial stack; removing a second material layer through the slit to form an opening; forming an electrode stack by forming conductive layers in the openings respectively; forming contact holes exposing conductive layers, at least two contact holes having different heights; and forming contact structures in the contact holes respectively. Attached Figure Description

[0009] Figure 1A , 1B 1C is a diagram illustrating a semiconductor device according to one embodiment of the present disclosure.

[0010] Figure 2 This is a diagram illustrating a semiconductor device according to one embodiment of the present disclosure.

[0011] Figure 3A , Figure 3B , Figure 4 and Figure 5 This is a diagram illustrating a semiconductor device according to one embodiment of the present disclosure.

[0012] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H , Figure 6I and Figure 6J This is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0013] Figure 7A and Figure 7B This is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. Detailed Implementation

[0014] One embodiment of this disclosure provides a semiconductor device with a stable structure and improved properties, and a method for manufacturing the same.

[0015] According to embodiments of this disclosure, semiconductor devices with stable structures and improved reliability can be provided.

[0016] In the following description, some embodiments of this disclosure will be described with reference to the accompanying drawings.

[0017] Figures 1A to 1C This is a diagram illustrating a semiconductor device according to one embodiment of the present disclosure.

[0018] Reference Figures 1A to 1C The semiconductor device may include an electrode stack 110G, a memory cell MC, a conductive plug 150, a contact structure CS, and a select transistor ST. The semiconductor device may further include a substrate 100, peripheral circuitry PC, a first interconnect structure IC1, a component isolation layer ISO, a second interconnect structure IC2, an inner liner layer LN, a slit structure SLS, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, and a third interlayer insulating layer IL3.

[0019] The peripheral circuit PC can be disposed on the substrate 100. The peripheral circuit PC may include transistor 1, capacitors, etc. Transistor 1 may include junctions 1A and 1B, gate electrode 1D, and gate insulating layer 1C. Here, the gate insulating layer 1C may be disposed between the gate electrode 1D and the substrate 100. The component isolation layer ISO may be disposed in the substrate 100, and an active region may be formed by the component isolation layer ISO, and transistor 1 may be disposed in the active region.

[0020] The first interconnect structure IC1 may be disposed on the peripheral circuit PC. The first interconnect structure IC1 may be disposed in the first interlayer insulating layer IL1. Here, the first interlayer insulating layer IL1 may be disposed on the substrate 100. The first interconnect structure IC1 may include a first via ICA and a first line ICB. At least one of the first via ICAs may be connected to the peripheral circuit PC. For example, at least one of the first via ICAs may be connected to transistor 1. At least one of the first lines ICBs may interconnect the first via ICAs. The first interconnect structure IC1 may contain a conductive material such as tungsten. The first interlayer insulating layer IL1 may contain an insulating material such as oxide.

[0021] A second interconnect structure IC2 may be disposed on the first interconnect structure IC1. The second interconnect structure IC2 may be disposed in a second interlayer insulating layer IL2. Here, the second interlayer insulating layer IL2 may be disposed on the first interlayer insulating layer IL1. The second interconnect structure IC2 may include a second line ICC and a third line ICD. One of the second lines ICC may be connected to the first line ICB. For reference, a connection via (not shown) may be disposed between the first line ICB and the second line ICC, and the first line ICB and the second line ICC may be connected via the connection via. The third line ICD may be electrically connected to the second line ICC via a selection transistor ST. Here, the second line ICC may be the first bit line used as the data input / output path for the memory cell MC, and the third line ICD may be a word line used to control the selection transistor ST. The second interconnect structure IC2 may contain a conductive material such as tungsten. The second interlayer insulating layer IL2 may contain an insulating material such as oxide.

[0022] A selection transistor ST may be disposed on (or above) a first interconnect structure IC1. The selection transistor ST may extend through a third line ICD and may be connected to a second line ICC. The selection transistor ST may be configured to correspond to each memory cell MC disposed in a memory array. For example, each selection transistor ST may be configured to correspond to a memory string containing multiple memory cells MC. The selection transistor ST may perform a switching function that selectively activates or deactivates the memory string. For example, the selection transistor may switch to an on or off state in response to a selection signal applied from a word line, and may open or block the current path to the memory cell connected to a particular selection transistor, thereby allowing access to only the desired memory cell. Each selection transistor ST may include a gate electrode, source / drain regions, a gate insulating layer, etc. In the following, implementations will be described based on a memory string corresponding to a selection transistor ST and multiple memory cells MC contained within the memory string.

[0023] Electrode stack 110G may be disposed on select transistor ST. In other words, select transistor ST may be disposed below electrode stack 110G. Electrode stack 110G may include alternately stacked insulating layer 110A and conductive layer 110B, and may include a stepped structure. For example, electrode stack 110G may include alternately stacked insulating layer 110A and conductive layer 110B to form a stepped structure. The upper surface of conductive layer 110B may be exposed through the stepped structure. Here, the upper surface (e.g., a portion of the upper surface) and side surface of conductive layer 110B exposed through the stepped structure may be covered by a third interlayer insulating layer IL3. The third interlayer insulating layer IL3 may be disposed on the stepped structure. Conductive layer 110B may be a wordplate for controlling memory cell MC. The third interlayer insulating layer IL3 may contain an insulating material such as oxide.

[0024] The memory cell MC may be disposed between the conductive layer 110B and the conductive plug 150. For example, each memory cell MC may be disposed between one of the corresponding conductive layers 110B (e.g., disposed therein) and a portion of the corresponding conductive plug 150 (e.g., in contact with it). Here, the conductive plug 150 may extend through the electrode stack 110G. Furthermore, the conductive plug 150 may be connected to the second line ICC by extending through the electrode stack 110G.

[0025] Each memory cell MC may include a first electrode pattern 120, a variable resistor pattern 130, and a second electrode pattern 140. For example, the memory cell MC may include: a first electrode pattern 120, each disposed at a level corresponding to a conductive layer 110B; a second electrode pattern 140 covering the sidewall of the conductive plug 150; and a variable resistor pattern 130 disposed between the first electrode pattern 120 and the second electrode pattern 140. Specifically, each memory cell MC may include: a first electrode pattern 120 disposed at a level substantially the same as one of the corresponding conductive layers 110B; a second electrode pattern 140 covering the sidewall of the conductive plug 150; and a variable resistor pattern 130 disposed between the first electrode pattern 120 and the second electrode pattern 140. For example, when the upper surface of the first electrode pattern 120 and the upper surface of the corresponding conductive layer 110B are located at a first level and a second level from the upper surface of the substrate 100, respectively, the difference between the first level and the second level may not exceed 5%, 3%, or 1% of the thickness of the conductive layer 110B.

[0026] At least one of the first electrode pattern 120 and the second electrode pattern 140 may comprise polycrystalline silicon, tungsten (W), tungsten nitride (WNx), tungsten silicide (WSix), titanium (Ti), titanium nitride (TiNx), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), palladium (Pd), platinum (Pt), molybdenum (Mo), ruthenium (Ru), etc. Throughout this specification and claims, lists of items beginning with phrases such as "at least one," "one or more," or "one or two" indicate inclusion lists. For example, a list of "at least one of A or B" and a list of "one or two of A and B" each indicate A or B or AB (i.e., A and B).

[0027] The variable resistor pattern 130 may contain a resistive material and may have the property of reversibly switching between different resistance states according to the applied voltage or current.

[0028] The variable resistance pattern 130 may contain metal oxides (e.g., transition metal oxides) or metal oxides such as perovskite materials. Therefore, data can be stored in the storage unit MC by creating or eliminating electrical paths in the variable resistance pattern 130.

[0029] The variable resistor pattern 130 may have an MTJ structure and may include a magnetization fixed layer, a magnetization free layer, and a tunnel blocking layer inserted therebetween. For example, the magnetization fixed layer and the magnetization free layer may contain magnetic materials, and the tunnel blocking layer may contain oxides such as magnesium (Mg), aluminum (Al), zinc (Zn), or titanium (Ti). Here, the magnetization direction of the magnetization free layer can be changed by the spin torque of electrons in the applied current. Therefore, data can be stored in the storage unit MC according to the change in the magnetization direction of the magnetization free layer relative to the magnetization direction of the magnetization fixed layer.

[0030] The variable resistance pattern 130 may contain a phase change material and may contain chalcogenides. The variable resistance pattern 130 may contain chalcogenide glasses, chalcogenide alloys, etc. The variable resistance pattern 130 may contain silicon (Si), germanium (Ge), antimony (Sb), tellurium (Te), bismuth (Bi), indium (In), tin (Sn), selenium (Se), etc., or combinations thereof. The variable resistance pattern 130 may be Ge-Sb-Te (GST), and may be Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4, Ge1Sb4Te7, etc. The phase of the variable resistance pattern 130 can be changed according to a programming operation. For example, the variable resistance pattern 130 may have a low-resistance crystalline state through a set operation. Furthermore, the variable resistance pattern 130 may have a high-resistance amorphous state through a reset operation. Therefore, data can be stored in the storage unit MC by using the resistance difference based on the phase of the variable resistance pattern 130.

[0031] The variable resistance pattern 130 may include a variable resistance material in which resistance changes without a phase transition, and may include a chalcogenide-based material. The variable resistance pattern 130 may include germanium (Ge), antimony (Sb), tellurium (Te), arsenic (As), selenium (Se), silicon (Si), indium (In), tin (Sn), sulfur (S), gallium (Ga), etc., or combinations thereof. The variable resistance pattern 130 may include a chalcogenide that remains amorphous during programming operations. The variable resistance pattern 130 may have an amorphous state and may not change to a crystalline state during programming operations. Therefore, the threshold voltage of the memory cell MC can change according to the programming voltage applied to the memory cell MC, and the memory cell can be programmed into at least two states. For example, when a negative programming voltage is applied to the memory cell MC, the memory cell may have a relatively high threshold voltage. Furthermore, when a positive programming voltage is applied to the memory cell MC, the memory cell may have a relatively low threshold voltage. Therefore, data can be stored in the memory cell MC using the threshold voltage difference between the memory cells MC.

[0032] Furthermore, the conductive plug 150 can serve as a second bit line for the data input / output path of the memory cell MC. In other words, the conductive plug 150 and the second line ICC can be electrically connected, and the first and second bit lines can be used as a single bit line. In summary, the third line ICD can be a word line, the conductive layer 110B can be a word board, and the conductive plug 150 and the second line ICC can be bit lines. For example, by applying a voltage to the word line, the selection transistor ST connected to the corresponding word line can be turned on, so current can flow between the memory cell MC corresponding to the selection transistor ST and the bit line. Furthermore, by applying a voltage to the word board, the memory cell MC set at the level corresponding to the word board can be selected. When the selection transistor ST is turned on and the memory cell MC is selected, data of the selected memory cell MC can be read or written via the bit line. Here, the voltage can be applied to the word board via the contact structure CS.

[0033] The contact structure CS may extend through the third interlayer insulating layer IL3 and may be connected to the conductive layer 110B. The contact structure CS may serve as a path for applying voltage to the conductive layer 110B. The heights of the contact structures CS may differ from one another. The widths of the contact structures CS may be substantially the same. For example, the difference in width between a pair of contact structures CS may not exceed 5%, 3%, or 1% of the average width.

[0034] Each contact structure CS may include a barrier layer 160 and a contact via 170. The contact via 170 may extend through the third interlayer insulating layer IL3 to electrically connect to the conductive layer 110B, respectively. Here, the contact via 170 may have different widths. The barrier layer 160 may cover the contact via 170, respectively. For example, the barrier layer 160 may cover one or more side surfaces and the bottom surface of the contact via 170. Here, the barrier layer 160 may have different thicknesses.

[0035] The contact via 170 may have a first resistivity, and the barrier layer 160 may have a second resistivity different from the first resistivity. For example, the second resistivity may be greater than the first resistivity. The contact via 170 may contain a metallic material, and the barrier layer 160 may contain a metal nitride. For example, the contact via 170 may contain tungsten, and the barrier layer 160 may contain tungsten nitride.

[0036] The memory cell MC may include a first memory cell MC1 and a second memory cell MC2 on (or above) the first memory cell MC1. For example, the memory cell MC may include a first memory cell MC1 adjacent to the selection transistor ST and a second memory cell MC2 spaced relatively far from the selection transistor ST than the first memory cell MC1. The conductive layer 110B may include a first conductive layer 110B1 connected to the first memory cell MC1 and a second conductive layer 110B2 connected to the second memory cell MC2.

[0037] The contact structure CS may include a first contact structure CS1 connected to the first conductive layer 110B1 and a second contact structure CS2 connected to the second conductive layer 110B2. Here, the first contact structure CS1 may have a first height H1, and the second contact structure CS2 may have a second height H2 less than the first height H1. The first contact structure CS1 may include a first contact via 170A and a first barrier layer 160A. The second contact structure CS2 may include a second contact via 170B and a second barrier layer 160B. The contact via 170A may include a first contact via 170A electrically connected to the first conductive layer 110B1 and a second contact via 170B electrically connected to the second conductive layer 110B2. The barrier layer 160A may include a first barrier layer 160A covering the first contact via 170A and a second barrier layer 160B covering the second contact via 170B.

[0038] The first memory cell MC1 is electrically connected from the select transistor ST to the first contact structure CS1 via a conductive plug (e.g., the first portion of the conductive plug) 150 and a first conductive layer 110B1. The second memory cell MC2 is electrically connected from the select transistor ST to the second contact structure CS2 via a conductive plug (e.g., the second portion of the conductive plug) 150 and a second conductive layer 110B2. Here, the first memory cell MC1 may have a first distance D1 from the select transistor ST, and the second memory cell MC2 may have a second distance D2 from the select transistor ST that is greater than the first distance D1. For example, the first memory cell (e.g., the upper surface of the first memory cell, the central plane located between the upper and lower surfaces of the first memory cell, etc.) MC1 is spaced apart from the select transistor (e.g., the upper surface of the select transistor ST) by the first distance, and the second memory cell (e.g., the upper surface of the second memory cell, the central plane located between the upper and lower surfaces of the second memory cell ST, etc.) is spaced apart from the select transistor ST by the second distance that is greater than the first distance. The length of the conductive plug 150 from the select transistor ST to the first memory cell MC1 can be substantially the same as the first distance D1, and the length of the conductive plug 150 from the select transistor ST to the second memory cell MC2 can be substantially the same as the second distance D2.

[0039] By applying a voltage to the word line, the select transistor connected to the corresponding word line can be turned on. At this time, current can flow through the bit line to the memory cell corresponding to the select transistor. Furthermore, by applying a voltage to the word board through the contact structure, memory cells positioned horizontally corresponding to the word board can be selected. Here, when the distance between the memory cell and the select transistor is relatively short, i.e., when the length of the bit line connecting the memory cell and the select transistor is relatively short, the resistance of the bit line connection can be relatively small. In this case, high spike currents can instantaneously flow through the memory cell, which can cause electrical stress on the memory cell and damage it.

[0040] When the first memory cell MC1 is positioned relatively closer to the select transistor ST compared to the second memory cell MC2, a current spike may occur, potentially damaging the first memory cell MC1. In other words, because the length of the first portion of the conductive plug 150 connecting the first memory cell MC1 and the select transistor ST is shorter than the length of the second portion connecting the second memory cell MC2 and the select transistor ST, the resistance of the first portion of the conductive plug 150 may be relatively small, thus damaging the first memory cell MC1 connected to the first portion. Therefore, to prevent or minimize damage to the first memory cell MC1, the relatively small resistance of the first portion of the conductive plug 150 connecting the first memory cell MC1 and the select transistor ST can be compensated for.

[0041] The first contact structure CS1 may have a first resistance, and the second contact structure CS2 may have a second resistance smaller than the first resistance. For example, the first contact structure CS1 may have a first height H1, and the second contact structure CS2 may have a second height H2 smaller than the first height H1. Furthermore, the first contact via 170A may have a first width T1, and the second contact via 170B may have a second width T2 greater than the first width T1. The first barrier layer 160A may have a third thickness T3, and the second barrier layer 160B may have a fourth thickness T4 smaller than the third thickness T3. Here, the resistivity of the first barrier layer 160A and the second barrier layer 160B may be greater than the resistivity of the first contact via 170A and the second contact via 170B.

[0042] In other words, the first contact structure CS1 may have a first height H1 that is greater than the second height H2 of the second contact structure CS2. Furthermore, the first width T1 of the first contact via 170A may be smaller than the second width T2 of the second contact via 170B. Additionally, the third thickness T3 of the first barrier layer 160A may be greater than the fourth thickness T4 of the second barrier layer 160B.

[0043] Since the height of the first contact structure CS1 is greater than the height of the second contact structure CS2, the resistance of the first contact structure CS1 can be relatively large. Furthermore, since the first contact structure CS1 includes a relatively narrow first contact via 170A and a relatively thick first barrier layer 160A, the resistance of the first contact structure CS1 can be greater than the resistance of the second contact structure CS2, which includes a relatively wide second contact via 170B and a relatively thin second barrier layer 160B.

[0044] Accordingly, the resistance of the first contact structure CS1 can be higher than the resistance of the second contact structure CS2. In this case, the first contact structure CS1 can compensate for the relatively small resistance of the first portion of the conductive plug 150 connecting the first memory cell MC1 and the select transistor ST. In other words, the sum of the resistance of the first portion of the conductive plug 150 connecting the first memory cell MC1 and the select transistor ST and the resistance of the first contact structure CS1 can be substantially equal to or similar to the sum of the resistance of the second portion of the conductive plug 150 connecting the second memory cell MC2 and the select transistor ST and the resistance of the second contact structure CS2. Therefore, by forming the first contact structure CS1 with a relatively large resistance, damage to the first memory cell MC1 caused by spike currents can be prevented or minimized.

[0045] For reference, the above description of the first memory cell MC1 and the second memory cell MC2 in this disclosure can also be applied to other memory cells MC spaced apart sequentially from the select transistor ST. For example, for a memory cell MC disposed between the first memory cell MC1 and the second memory cell MC2, a contact structure CS can be formed by adjusting the ratio of the contact via 170 to the barrier layer 160, such that the sum of the resistance of the conductive plug 150 connecting the memory cell MC and the select transistor ST and the resistance of the contact structure CS connected to the conductive layer 110B corresponding to the memory cell MC is substantially equal.

[0046] The slit structure SLS can extend through the electrode stack 110G. The slit structure SLS can be formed by forming an insulating material, a semiconductor material, or a conductive material in a slit used in the process of manufacturing semiconductor devices. Therefore, the slit structure SLS may contain at least one of an insulating material, a semiconductor material, or a conductive material.

[0047] The liner layer LN may extend along the upper surface of the electrode stack 110G and between the slot structure SLS and the electrode stack 110G. The liner layer LN may cover the upper surface of the second electrode pattern 140 and the upper surface of the conductive plug 150 during the semiconductor device fabrication process. The liner layer LN may contain an insulating material such as an oxide or nitride.

[0048] For reference, although this figure illustrates the electrode stack 110G with a stepped structure, the electrode stack 110G may not include a stepped structure. In this case, the third interlayer insulating layer IL3 may be absent. The contact structure CS may extend through the electrode stack 110G to connect to each conductive layer 110B. In this case, insulating spacers covering the sidewalls of the contact structure CS may be provided to prevent the remaining conductive layers 110B, except those connected to the contact structure CS, from being electrically connected to the contact structure CS.

[0049] Based on the structure described above, the height of the first contact structure CS1 can be greater than the height of the second contact structure CS2. Furthermore, the first contact structure CS1 may include a first contact via 170A with a width smaller than the width of the second contact via 170B of the second contact structure CS2, and may include a first barrier layer 160A with a thickness greater than the thickness of the second barrier layer 160B of the second contact structure CS2. The first contact via 170A and the second contact via 170B may each have a resistivity smaller than that of the first barrier layer 160A and the second barrier layer 160B. Therefore, the first resistance of the first contact structure CS1 can be greater than the second resistance of the second contact structure CS2.

[0050] In other words, the first resistance of the first contact structure CS1 corresponding to the first memory cell MC1, which is positioned adjacent to the selection transistor ST, can be greater than the second resistance of the second contact structure CS2 corresponding to the second memory cell MC2, which is positioned relatively far from the selection transistor ST. Therefore, the first contact structure CS1 can prevent the first memory cell MC1 from being damaged due to the relatively small distance between the first memory cell MC1 and the selection transistor ST.

[0051] Figure 2 This is a diagram illustrating a semiconductor device according to one embodiment of the present disclosure. For the sake of brevity, content repeated above will be omitted in the following text.

[0052] Reference Figure 2 The semiconductor device may include an electrode stack 210G, a memory cell MC, a conductive plug 250, a contact structure CS, and a selection transistor ST. The semiconductor device may further include a substrate 200, peripheral circuitry PC, a first interconnect structure IC1, a component isolation layer ISO, a second interconnect structure IC2, an inner liner layer LN, a slit structure SLS, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, and a third interlayer insulating layer IL3.

[0053] The peripheral circuit PC can be disposed on the substrate 200. The peripheral circuit PC may include transistor 1, capacitors, etc. Transistor 1 may include junction 1A and junction 1B, gate electrode 1D and gate insulating layer 1C. The component isolation layer ISO can be disposed in the substrate 200, and an active region can be formed by the component isolation layer ISO, and transistor 1 can be disposed in the active region.

[0054] The first interconnect structure IC1 may be disposed on the peripheral circuit PC. The first interconnect structure IC1 may be disposed in the first interlayer insulating layer IL1. Here, the first interlayer insulating layer IL1 may be disposed on the substrate 200. The first interconnect structure IC1 may include a first via ICA and a first line ICB.

[0055] The second interconnect structure IC2 may be disposed on the first interconnect structure IC1. The second interconnect structure IC2 may be disposed in the second interlayer insulating layer IL2. Here, the second interlayer insulating layer IL2 may be disposed on the first interlayer insulating layer IL1. The second interconnect structure IC2 may include a second line ICC and a third line ICD.

[0056] The select transistor ST can be disposed on the first interconnect structure IC1. The select transistor ST can extend through the third line ICD and can be connected to the second line ICC. The select transistor ST can be configured to correspond to each memory cell MC disposed in the memory array. The select transistor ST can perform a selective activation or deactivation function of the memory string. Each select transistor ST can include a gate electrode, source / drain regions, gate insulating layer, etc.

[0057] Electrode stack 210G may be disposed on the select transistor ST. In other words, the select transistor ST may be disposed below electrode stack 210G. Electrode stack 210G may include alternately stacked insulating layers 210A and conductive layers 210B, and may include a stepped structure. For example, electrode stack 210G may include alternately stacked insulating layers 210A and conductive layers 210B to form a stepped structure. Here, the upper surface of the conductive layer 210B exposed by the stepped structure may be covered by a third interlayer insulating layer IL3. The third interlayer insulating layer IL3 may be disposed on the stepped structure.

[0058] The memory cell MC can be disposed between the conductive layer 210B and the conductive plug 250. For example, each memory cell MC can be disposed between one of the corresponding conductive layers 210B (e.g., disposed therein) and a portion of the corresponding conductive plug 250 (e.g., in contact with it). Here, the conductive plug 250 can extend through the electrode stack 210G. Furthermore, the conductive plug 250 can extend through the electrode stack 210G to connect to the second line ICC, respectively.

[0059] Each memory cell may include a first electrode pattern 220, a variable resistor pattern 230, and a second electrode pattern 240. For example, a memory cell MC may include: a first electrode pattern 220 disposed at a level corresponding to the conductive layer 210B; a second electrode pattern 240 covering the sidewall of the conductive plug 250; and a variable resistor pattern 230 disposed between the first electrode pattern 220 and the second electrode pattern 240.

[0060] The contact structures may extend through the third interlayer insulating layer IL3 and may be connected to the conductive layer 210B. Each contact structure may include at least one of a contact via 270 or a barrier layer 260. As an example, the first contact structure CS1 may consist of a barrier layer 260. As another example, the second contact structure CS2 may consist of a contact via 270. The heights of the contact structures may differ from one another.

[0061] The contact via 270 may extend through the third interlayer insulating layer IL3 to electrically connect to the conductive layer 210B, respectively. Here, the contact via 270 may have different widths. A barrier layer 260 may cover the contact via 270. For example, the barrier layer 260 may cover one or more side surfaces and the bottom surface of the contact via 270. Here, the barrier layer 260 may have different thicknesses.

[0062] The contact via 270 may have a first resistivity, and the barrier layer 260 may have a second resistivity greater than the first resistivity. The contact via 270 may comprise a metallic material, and the barrier layer 260 may comprise a metal nitride. For example, the contact via 270 may comprise tungsten, and the barrier layer 260 may comprise tungsten nitride.

[0063] The first contact structure CS1 may have a first resistance, and the second contact structure CS2 may have a second resistance smaller than the first resistance. The height of the first contact structure CS1 may be greater than the height of the second contact structure CS2. Furthermore, the first contact structure CS1 may have a first width W1, and the second contact structure CS2 may have a second width W2 different from the first width W1. Here, the first width W1 may be smaller than the second width W2.

[0064] In other words, the height of the first contact structure CS1 may be greater than the height of the second contact structure CS2, and the first contact structure CS1 may have a first width W1 that is smaller than the second width W2 of the second contact structure CS2. Furthermore, the first contact structure CS1 may include a barrier layer 260 with relatively high resistivity, and the second contact structure CS2 may include a contact via 270 with relatively low resistivity. Therefore, the resistance of the first contact structure CS1 may be relatively greater than the resistance of the second contact structure CS2.

[0065] Accordingly, the resistance of the first contact structure CS1 can be greater than the resistance of the second contact structure CS2. In this case, the first contact structure CS1 can prevent or minimize damage to the memory cell MC, which is set to be relatively adjacent to the selection transistor ST, due to spike current.

[0066] For reference, although this figure illustrates the case where the first width W1 and the second width W2 of the first contact structure CS1 and the second contact structure CS2 are constant from the upper surface to the lower surface, the first contact structure CS1 and the second contact structure CS2 may have tapered cross-sections. In this case, the widths of the first contact structure CS1 and the second contact structure CS2 may decrease from the upper surface to the lower surface.

[0067] Furthermore, although this figure illustrates a case where the first contact structure CS1 does not include the contact via 270 and the second contact structure CS2 does not include the barrier layer 260, the embodiments of this disclosure are not limited thereto. For example, the first contact structure CS1 may include a contact via (not shown) in the barrier layer 260, and the second contact structure CS2 may include a barrier layer (not shown) covering the contact via 270.

[0068] The slit structure SLS can extend through the electrode stack 210G. The slit structure SLS may contain at least one of an insulating material, a semiconductor material, or a conductive material.

[0069] The inner liner layer LN may extend along the upper surface of the electrode stack 210G and between the slit structure SLS and the electrode stack 210G. The inner liner layer LN may contain an insulating material such as an oxide or nitride.

[0070] According to the structure described above, the first contact structure CS1 may have a first width W1 that is relatively smaller than the second width W2 of the second contact structure CS2. Furthermore, the height of the first contact structure CS1 may be relatively greater than the height of the second contact structure CS2. Additionally, the first contact structure CS1 may be composed of a barrier layer 260 with a resistivity greater than that of the contact via 270, and the second contact structure CS2 may be composed of the contact via 270. In this case, the resistance of the first contact structure CS1 may be greater than the resistance of the second contact structure CS2, thus preventing damage to the memory cell MC that is positioned adjacent to the selection transistor ST.

[0071] Figure 3A , Figure 3B , Figure 4 and Figure 5 This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. For the sake of brevity, content that is repeated in the above description may be omitted in the following text.

[0072] Reference Figure 3A , Figure 3B , Figure 4 and Figure 5 The semiconductor device may include an electrode stack 310G, 410G, or 510G, a memory cell MC, conductive plugs 350, 450, or 550, a contact structure CS, and a select transistor ST. The semiconductor device may further include a substrate 300, 400, or 500, peripheral circuitry PC, a first interconnect structure IC1, a component isolation layer ISO, a second interconnect structure IC2, an inner liner layer LN, a slit structure SLS, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, and a third interlayer insulating layer IL3.

[0073] The peripheral circuit PC can be disposed on substrate 300, 400, or 500. The peripheral circuit PC can include transistor 1, capacitors, etc. Transistor 1 can include junction 1A and junction 1B, gate electrode 1D, and gate insulating layer 1C. Component isolation layer ISO can be disposed in substrate 300, 400, or 500, the active region can be formed by component isolation layer ISO, and transistor 1 can be disposed in the active region.

[0074] The first interconnect structure IC1 may be disposed on the peripheral circuit PC. The first interconnect structure IC1 may be disposed in the first interlayer insulating layer IL1. Here, the first interlayer insulating layer IL1 may be disposed on the substrate 300, 400 or 500. The first interconnect structure IC1 may include a first via ICA and a first line ICB.

[0075] The second interconnect structure IC2 may be disposed on the first interconnect structure IC1. The second interconnect structure IC2 may be disposed in the second interlayer insulating layer IL2. Here, the second interlayer insulating layer IL2 may be disposed on the first interlayer insulating layer IL1. The second interconnect structure IC2 may include a second line ICC and a third line ICD.

[0076] The select transistor ST can be disposed on the first interconnect structure IC1. The select transistor ST can extend through the third line ICD and can be connected to the second line ICC. The select transistor ST can be configured to correspond to each memory cell MC disposed in the memory array. The select transistor ST can perform a selective activation or deactivation function of the memory string. Each select transistor ST can include a gate electrode, source / drain regions, gate insulating layer, etc.

[0077] Electrode stacks 310G, 410G, or 510G may be disposed on the select transistor ST. In other words, the select transistor ST may be disposed below the electrode stacks 310G, 410G, or 510G. The electrode stacks 310G, 410G, or 510G may include alternately stacked insulating layers 310A, 410A, or 510A and conductive layers 310B, 410B, or 510B, and may include a stepped structure. Here, the upper surface of the conductive layers 310B, 410B, or 510B exposed by the stepped structure may be covered by a third interlayer insulating layer IL3. The third interlayer insulating layer IL3 may be disposed on the stepped structure.

[0078] The memory cell MC can be disposed between the conductive layers 310B, 410B, or 510B and the conductive plugs 350, 450, or 550. Here, the conductive plugs 350, 450, or 550 can extend through the electrode stacks 310G, 410G, or 510G. Furthermore, the conductive plugs 350, 450, or 550 can extend through the electrode stacks 310G, 410G, or 510G to connect to the second-line ICC, respectively.

[0079] Each memory cell MC may include a first electrode pattern 320, 420, or 520, a variable resistor pattern 330, 430, or 530, and a second electrode pattern 340, 440, or 540. For example, the memory cell MC may include: a first electrode pattern 320, 420, or 520, each disposed at a level corresponding to a conductive layer 310B, 410B, or 510B; a second electrode pattern 340, 440, or 540 covering the sidewalls of conductive plugs 350, 450, or 550; and a variable resistor pattern 330, 430, or 530 disposed between the first electrode pattern 320, 420, or 520 and the second electrode pattern 340, 440, or 540.

[0080] The slit structure SLS can extend through electrode stacks 310G, 410G, or 510G. The slit structure SLS may contain at least one of insulating, semiconductor, or conductive materials.

[0081] The inner liner layer LN may extend along the upper surface of the electrode stacks 310G, 410G, or 510G and between the slit structure SLS and the electrode stacks 310G, 410G, or 510G. The inner liner layer LN may contain an insulating material such as an oxide or nitride.

[0082] The contact structure CS may extend through the third interlayer insulating layer IL3 and may be connected to conductive layers 310B, 410B, or 510B, respectively. The heights of the contact structures CS may differ from one another. Each contact structure CS may include at least one of contact vias 370, 470, or 570 or barrier layers 360, 460, or 560.

[0083] Contact vias 370, 470, or 570 may extend through the third interlayer insulation layer IL3 to electrically connect to conductive layers 310B, 410B, or 510B, respectively. Barrier layers 360, 460, or 560 may cover contact vias 370, 470, or 570. For example, barrier layers 360, 460, or 560 may cover one or more side surfaces and the bottom surface of contact vias 370, 470, or 570. Here, the thicknesses of barrier layers 360, 460, and 560 may be substantially the same.

[0084] Contact vias 370, 470, and 570 may have a first resistivity, and barrier layers 360, 460, and 560 may have a second resistivity greater than the first resistivity. Contact vias 370, 470, and 570 may comprise a metallic material, and barrier layers 360, 460, and 560 may comprise a metal nitride. For example, contact vias 370, 470, and 570 may comprise tungsten, and barrier layers 360, 460, and 560 may comprise tungsten nitride.

[0085] Reference Figure 3A and Figure 3BThe memory cell MC may include a first memory cell MC1 and a second memory cell MC2 on (or above) the first memory cell MC1. For example, the memory cell MC may include a first memory cell MC1 adjacent to the selection transistor ST and a second memory cell MC2 that is relatively far from the selection transistor ST compared to the first memory cell MC1. The conductive layer 310B may include a first conductive layer 310B1 connected to the first memory cell MC1 and a second conductive layer 310B2 connected to the second memory cell MC2.

[0086] The first memory cell MC1 can be electrically connected from the select transistor ST to the first contact structure CS1 via a conductive plug (e.g., the first portion of the conductive plug) 350 and a first conductive layer 310B1. The second memory cell MC2 can be electrically connected from the select transistor ST to the second contact structure CS2 via a conductive plug (e.g., the second portion of the conductive plug) 350 and a second conductive layer 310B2.

[0087] The first memory cell MC1 may have a first distance D1 between itself and the select transistor ST, and the second memory cell MC2 may have a second distance D2 between itself and the select transistor ST that is greater than the first distance D1. For example, the first memory cell (e.g., the upper surface of the first memory cell, the central plane located between the upper and lower surfaces of the first memory cell, etc.) MC1 is spaced apart from the select transistor (e.g., the upper surface of the select transistor) ST by the first distance, and the second memory cell (e.g., the upper surface of the second memory cell, the central plane located between the upper and lower surfaces of the second memory cell, etc.) MC2 is spaced apart from the select transistor ST by the second distance that is greater than the first distance. The length of the conductive plug 350 from the select transistor ST to the first memory cell MC1 may be substantially the same as the first distance D1, and the length of the conductive plug 350 from the select transistor ST to the second memory cell MC2 may be substantially the same as the second distance D2.

[0088] When the cross-sectional area of ​​the contact structure CS in contact with the conductive layer 310B decreases, the resistance of the contact structure CS can increase. Furthermore, when the height of the contact structure CS increases, the resistance of the contact structure CS can also increase.

[0089] The first contact structure CS1 can contact the first conductive layer 310B1 at an interface having a first cross-sectional area S1, and the second contact structure CS2 can contact the second conductive layer 310B2 at an interface having a second cross-sectional area S2 that is different from the cross-sectional area of ​​the second conductive layer 310B2. Here, the first cross-sectional area S1 can be smaller than the second cross-sectional area S2. In addition, the height of the first contact structure CS1 can be greater than the height of the second contact structure CS2.

[0090] In other words, the height of the first contact structure CS1 can be greater than the height of the second contact structure CS2, and the first contact structure CS1 can contact the conductive layer 310B at an interface with a cross-sectional area smaller than that of the second contact structure CS2. Therefore, the second contact structure CS2 can have a second resistance, and the first contact structure CS1 can have a first resistance greater than the second resistance. Here, the thicknesses of the first barrier layer 360A of the first contact structure CS1 and the second barrier layer 360B of the second contact structure CS2 can be substantially the same. For example, when the first barrier layer 360A has a first thickness and the second barrier layer 360B has a second thickness, the difference between the first thickness and the second thickness can be no greater than 5%, 3%, or 1% of the average of the first thickness and the second thickness.

[0091] According to one embodiment of this disclosure, the resistance of the first contact structure CS1 may be greater than the resistance of the second contact structure CS2. In this case, the first contact structure CS1 can prevent or minimize damage to the memory cell MC, which is configured to be relatively adjacent to the selection transistor ST, due to spike current.

[0092] Reference Figure 4 The memory cell MC may include a first memory cell MC1 adjacent to the select transistor ST, a second memory cell MC2 relatively farther from the select transistor ST than the first memory cell MC1, and a third memory cell MC3 relatively farther from the select transistor ST than the second memory cell MC2. Here, considering the distance from the select transistor ST to the memory cell MC, memory cells MC1, MC2, and MC3, which are expected to experience spike currents, may be grouped according to the magnitude of the voltage applied to the word line and / or bit line. The distance between the first memory cell MC1 and the select transistor ST may be shorter than that between the second memory cell MC2 and the third memory cell MC3, and the distance between the second memory cell MC2 and the select transistor ST may be shorter than that between the third memory cell MC3.

[0093] The conductive layer 410B may include a first conductive layer 410B1 connected to the first memory cell MC1, a second conductive layer 410B2 connected to the second memory cell MC2, and a third conductive layer 410B3 connected to the third memory cell MC3.

[0094] Each contact structure CS may include a barrier layer 460 and a contact via 470. Here, the thickness of the barrier layer 460 of the contact structure CS may be substantially the same.

[0095] The first set of contact structures G1 can be connected to the first conductive layer 410B1. For example, the first contact via 470A can be electrically connected to the first one in the first conductive layer 410B1, and the second contact via 470B can be electrically connected to the second one in the first conductive layer 410B1. Here, the first set of contact structures G1 can have substantially the same first width W1. For example, the difference between a pair of widths in the first set of contact structures G1 can be no greater than 5%, 3%, or 1% of the average width. In some embodiments, the first contact via 470A and the second contact via 470B can have substantially the same width. Here, the contact structure CS1 can have different heights.

[0096] The second set of contact structures G2 can be connected to the second conductive layer 410B2. For example, the third contact via 470C can be electrically connected to the first one in the second conductive layer 410B2, and the fourth contact via 470D can be electrically connected to the second one in the second conductive layer 410B2. Here, the second set of contact structures G2 can have substantially the same second width W2. For example, the difference between a pair of widths in the second set of contact structures G2 can be no greater than 5%, 3%, or 1% of the average width. In some embodiments, the third contact via 470C and the fourth contact via 470D can have substantially the same width. Here, the second width W2 can be greater than the first width W1. The contact structure CS2 can have different heights.

[0097] The third set of contact structures G3 can be connected to the third conductive layer 410B3. For example, the fifth contact via 470E can be electrically connected to the first one in the third conductive layer 410B3, and the sixth contact via 470F can be electrically connected to the second one in the third conductive layer 410B3. Here, the third set of contact structures G3 can have substantially the same third width W3. In some embodiments, the fifth contact via 470E and the sixth contact via 470F can have substantially the same width. Here, the third width W3 can be greater than the second width W2. The contact structure CS3 can have different heights.

[0098] The first set of contact structures G1 may have substantially the same first width W1. Meanwhile, the contact structures CS1 may have different heights. In this case, the first set of contact structures G1 may have different resistances. Similarly, the second set of contact structures G2 may have different resistances, and the third set of contact structures G3 may have different resistances.

[0099] According to one embodiment of this disclosure, the memory cells MC and the conductive layer 410B can be grouped horizontally, and thus the contact structures CS can be divided into a first group of contact structures G1, a second group of contact structures G2, and a third group of contact structures G3. In this case, by differentially setting the shapes of the first group of contact structures G1, the second group of contact structures G2, and the third group of contact structures G3, for example, the widths W1, W2, and W3 of each group of contact structures CS1, CS2, and CS3, spike currents are not generated for one or more specific groups of memory cells MC, and the amplitude of the current applied to each group of memory cells MC1, MC2, and MC3 can be controlled. In this way, the value of the current applied to the memory cell groups MC1, MC2, and MC3 can be kept relatively small, and spike currents can be prevented in specific groups of memory cells MC.

[0100] Reference Figure 5 The memory cell MC may include a first memory cell MC1 adjacent to the select transistor ST, a second memory cell MC2 relatively farther from the select transistor ST than the first memory cell MC1, and a third memory cell MC3 relatively farther from the select transistor ST than the second memory cell MC2. Here, considering the distance from the select transistor ST to the memory cell MC, memory cells expected to experience spike currents can be classified according to the magnitude of the voltage applied to the word line and / or bit line. For example, the distance between the first memory cell MC1 and the select transistor ST may be shorter than that between the second memory cell MC2 and the third memory cell MC3, and the distance between the second memory cell MC2 and the select transistor ST may be shorter than that between the third memory cell MC3 and the third memory cell MC3. In this case, spike currents may occur in the first memory cell MC1 and the second memory cell MC2. Since the distance between the third memory cell MC3 and the select transistor ST is relatively large compared to the first memory cell MC1 and the second memory cell MC2, spike currents may not occur.

[0101] The conductive layer 510B may include a first conductive layer 510B1 connected to the first memory cell MC1, a second conductive layer 510B2 connected to the second memory cell MC2, and a third conductive layer 510B3 connected to the third memory cell MC3.

[0102] Each contact structure CS may include a barrier layer 560 and a contact via 570. Here, the thickness of the barrier layer 560 of the contact structure CS may be substantially the same.

[0103] A first contact structure may be connected to a first conductive layer 510B1 and may have a first width W'1. A second contact structure may be connected to a second conductive layer 510B2 and may have a second width W'2 different from the first width W'1. A third contact structure may be connected to a third conductive layer 510B3 and may have a third width W'3 different from the first width W'1 and the second width W'2. Here, the first width W'1 may be smaller than the second width W'2. The second width W'2 may be smaller than the third width W'3. The third contact structure may be formed as a single contact structure group.

[0104] Because the third memory cell MC3 is sufficiently spaced from the select transistor ST, current spikes may not occur. Since current spikes can occur in the first memory cell MC1 and the second memory cell MC2, to prevent this, the first and second resistances of the first and second contact structures corresponding to the first and second memory cells MC1 and MC2, respectively, can be increased. In other words, the resistance of each of the first and second contact structures can be greater than the resistance of the third contact structure.

[0105] According to one embodiment of this disclosure, the first contact structure corresponding to the first memory cell MC1 may have a first width W'1 smaller than the second width W'2 of the second contact structure, and the second contact structure corresponding to the second memory cell MC2 may have a second width W'2 smaller than the third width W'3 of the third contact structure. In this case, the resistance of the first contact structure may be greater than the resistance of the second contact structure. The resistance of the second contact structure may be greater than the resistance of the third contact structure. Therefore, by adjusting the width W'1 of the first contact structure and the width W'2 of the second contact structure, spike currents can be prevented in the first memory cell MC1 and the second memory cell MC2. Here, since the third contact structure is electrically connected to the third memory cell MC3, which does not exhibit spike currents, the width W'3 of the third contact structure does not need to be adjusted, and therefore the third contact structure may have a substantially the same third width W'3.

[0106] According to one implementation method (e.g., refer to...) Figure 3A and Figure 3B The described structure can be adjusted by modifying the contact structure CS and the conductive layer (e.g.) Figure 3A The cross-sectional area of ​​the contact (e.g., 310B) in the middle. Figure 3A and Figure 3B S1 and S2 in the memory cell (MC) are used to prevent spike currents.

[0107] Furthermore, the memory cells MC can be grouped according to their distance from the selection transistor ST, and thus by dividing the contact structure into multiple groups (e.g. Figure 4The first group G1, the second group G2, and the third group G3 in the memory can prevent spike currents in one or more specific memory cell groups (MCs).

[0108] Furthermore, according to one implementation method (e.g.) Figure 5 In the implementation of the above, the width of the contact structure CS electrically connected to the memory cell MC, which is set to be relatively far from the selection transistor ST, can be adjusted to prevent spike currents in the memory cell MC without additional adjustment.

[0109] Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F , Figure 6G , Figure 6H , Figure 6I and Figure 6J This diagram illustrates a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. For the sake of brevity, content repeated above will be omitted in the following text.

[0110] Reference Figure 6A A peripheral circuit PC can be formed on the substrate 600. The peripheral circuit PC may include a transistor 1, etc. The transistor 1 may include junctions 1A and 1B, a gate insulating layer 1C, and a gate electrode 1D. A device isolation layer ISO can be formed in the substrate 600, an active region can be formed from the device isolation layer ISO, and the transistor 1 can be formed in the active region.

[0111] Subsequently, a first interconnect structure IC1 can be formed on the peripheral circuit PC. The first interconnect structure IC1 can be formed in a first interlayer insulating layer IL1. Here, the first interlayer insulating layer IL1 can be formed on the substrate 600. The first interconnect structure IC1 may include a first via ICA and a first line ICB. At least one of the first via ICA can be connected to the peripheral circuit PC. The first line ICB can interconnect the first via ICA. The first interconnect structure IC1 may contain a conductive material such as tungsten, and the first interlayer insulating layer IL1 may contain an insulating material such as oxide.

[0112] Reference Figure 6BA second interconnect structure IC2 can be formed on the first interconnect structure IC1. Here, the second interconnect structure IC2 can be formed in the second interlayer insulating layer IL2. The second interlayer insulating layer IL2 can be formed on the first interlayer insulating layer IL1. The second interconnect structure IC2 may include a second line ICC and a third line ICD. One of the second lines ICC can be connected to the first line ICB. For reference, the first line ICB and the second line ICC can be connected via a connection via (not shown). The third line ICD can be electrically connected to the second line ICC via a select transistor ST.

[0113] The selection transistor ST may be formed on the substrate 600. For example, the selection transistor ST may be formed on the first interconnect structure IC1. The selection transistor ST may be formed to be connected to the second line ICC by extending through the third line ICD.

[0114] Reference Figure 6C A sacrificial stack 610S can be formed by alternately stacking a first material layer 610A and a second material layer 610B on a select transistor ST. For example, the first material layer 610A and the second material layer 610B are stacked alternately to form a stepped structure. Here, the sacrificial stack 610S may include a stepped structure that exposes the upper surface of the second material layer 610B. The first material layer 610A may contain an insulating material such as an oxide, and the second material layer 610B may contain a sacrificial material such as a nitride.

[0115] Subsequently, a third interlayer insulating layer IL3 can be formed on the stepped structure. For example, the third interlayer insulating layer IL3 can be formed to cover the upper surface of the second material layer 610B exposed through the stepped structure. Here, the third interlayer insulating layer IL3 may comprise an insulating material such as an oxide. In other embodiments, the sacrificial stack 610S may not include a stepped structure. In this case, the process of forming the third interlayer insulating layer IL3 can be omitted.

[0116] Subsequently, a memory via MH can be formed extending through the sacrificial stack 610S and exposing the second material layer 610B. Here, the sidewalls of the second material layer 610B can be exposed through the memory via MH. Furthermore, the select transistor ST can be exposed through the memory via MH.

[0117] Reference Figures 6D to 6FA memory cell MC can be formed in a sacrificial stack 610S. First, a trench T can be formed by etching a second material layer 610B through a portion of the memory hole MH. Then, a first electrode pattern 620 can be formed in the trench T. For example, the first electrode layer can be conformally formed along the contours of the memory hole MH and the trench T. Subsequently, the first electrode layer can be etched such that the first electrode pattern 620 is formed at a level corresponding to the second material layer 610B. Specifically, the first electrode layer can be etched such that the upper and lower surfaces of the first electrode pattern 620 are substantially coplanar with the upper and lower surfaces of one of the corresponding (e.g., contacted) second material layers 610B. For example, the horizontal difference between the upper surface of the first electrode pattern 620 and the upper surface of the second material layer 610B may not exceed 5%, 3%, or 1% of the average thickness of the first electrode pattern 620 and the second material layer 610B. Subsequently, a variable resistance pattern 630 can be formed on the first electrode pattern 620. For example, a variable resistance layer can be formed in the memory hole MH to fill the trench T. Subsequently, by removing the portion of the variable resistance layer formed in the storage hole MH while retaining the other portions of the variable resistance layer formed in the trench T, a variable resistance pattern 630 can be formed in the trench T.

[0118] Subsequently, a second electrode pattern 640 may be formed in the memory via MH. For example, a second electrode layer may be conformally formed in the memory via MH. Subsequently, the second electrode pattern 640 may be formed by etching a portion of the second electrode layer, thereby exposing the selection transistor (e.g., the upper surface of the selection transistor) ST. Accordingly, a memory cell MC may be included, which includes a first electrode pattern 620, a variable resistor pattern 630, and a second electrode pattern 640.

[0119] Subsequently, conductive plugs 650 extending through the memory cell MC can be formed. For example, conductive plugs 650 can be formed in memory holes MH.

[0120] The memory cell MC may include a first memory cell MC1 and a second memory cell MC2 on (or above) the first memory cell MC1. Here, the first memory cell MC1 may be spaced from the select transistor ST by a first distance D1, and the second memory cell MC2 may be spaced from the select transistor ST by a second distance D2 greater than the first distance D1.

[0121] Because the first memory cell MC1 has a first distance D1 shorter than the distance D2 of the second memory cell MC2, in other words, because the length of the first portion of the conductive plug 650 from the select transistor ST to the first memory cell MC1 is shorter than the length of the second portion of the conductive plug 650 from the select transistor ST to the second memory cell MC2, a relatively high spike current can briefly flow to the first memory cell MC1 when current flows from the select transistor ST through the conductive plug 650. In this case, the first memory cell MC1 may be damaged. Therefore, according to one embodiment of this disclosure, the relatively small resistance of the first memory cell MC1 can be compensated to substantially prevent or reduce the spike current flowing to the first memory cell MC1.

[0122] Reference Figure 6G and Figure 6H A slit SL extending through the sacrificial stack 610S can be formed. Subsequently, the second material layer 610B can be removed through the slit SL to form an opening OP. A conductive layer 610C can then be formed in the opening OP. Accordingly, an electrode stack 610G comprising alternately stacked first material layers 610A and conductive layers 610C can be formed. For reference, the conductive layer 610C may include a connection to a first memory cell (e.g., Figure 1A The first conductive layer of MC1) and connected to the second memory cell (e.g. Figure 1A The second conductive layer of MC2 in the middle.

[0123] In other embodiments, when the second material layer 610B contains a conductive material, the process of replacing the second material layer 610B with a conductive layer 610C can be omitted, thereby simplifying the manufacturing process of the semiconductor device. In this case, the sacrificial stack 610S can be used as the electrode stack 610G.

[0124] Subsequently, an inner liner layer LN can be formed on the slit SL and the electrode stack 610G. For example, the inner liner layer LN can be formed to extend along the side and bottom surfaces of the slit SL and the top surface of the electrode stack 610G. The inner liner layer LN can contain an insulating material such as an oxide or nitride.

[0125] Subsequently, a slit structure SLS can be formed in the slit SL. For example, the slit structure SLS can be formed by forming at least one of an insulating material, a conductive material, or a semiconductor material in the slit SL.

[0126] Reference Figure 6IContact holes CTHs can be formed at different heights, extending through the third interlayer insulating layer IL3 to expose the conductive layer 610C respectively. Each contact hole CTH may include a first contact hole CTH1 having a first height H1 and a second contact hole CTH2 having a second height H2 different from the first height H1. Here, the first height H1 may be greater than the second height H2. The widths of the contact holes CTHs may be substantially the same. For example, the difference between the widths of a pair of contact holes CTHs may not exceed 5%, 3%, or 1% of the average width. In other embodiments, when the sacrificial stack 610S does not include a stepped structure, contact holes CTHs can be formed to expose the conductive layer 610C separately through the sacrificial stack 610S.

[0127] Reference Figure 6J The barrier layers 660 can be formed in the contact hole CTH with different thicknesses. In some embodiments, at least two barrier layers 660 can have different thicknesses. For example, a first barrier layer 660A can be formed in the first contact hole CTH1 with a third thickness T3, and a second barrier layer 660B can be formed in the second contact hole CTH2 with a fourth thickness T4, which is less than the third thickness T3. Here, the barrier layers 660 can be conformally formed to fill the corresponding (e.g., contacting) portions of the contact hole CTH.

[0128] In other embodiments, when the sacrificial stack 610S does not include a stepped structure, an insulating spacer may be formed before the barrier layer 660 is formed. Here, the insulating spacer insulates the contact structure CS from the remaining conductive layers 610C except for the conductive layer 610C connected to the contact structure CS.

[0129] Subsequently, a contact via 670 can be formed to fill the contact hole CTH. In some embodiments, at least two contact vias 670 with different widths can be formed in the barrier layer 660. For example, a first contact via 670A can be formed in the first barrier layer 660A with a first width T1, and a second contact via 670B can be formed in the second barrier layer 660B with a second width T2 greater than the first width T1.

[0130] The contact via 670 may include a first contact via 670A electrically connected to a first conductive layer and a second contact via 670B electrically connected to a second conductive layer. The barrier layer 660 may include a first barrier layer 660A covering the first contact via 670A and a second barrier layer 660B covering the second contact via 670B.

[0131] The contact via 670 may have a first resistivity, and the barrier layer 660 may have a second resistivity greater than the first resistivity. The contact via 670 may comprise a metallic material, and the barrier layer 660 may comprise a metal nitride. For example, the contact via 670 may comprise tungsten, and the barrier layer 660 may comprise tungsten nitride.

[0132] The contact structure CS may include a contact via 670 and a barrier layer 660. For example, the first contact structure CS1 may include a first contact via 670A and a first barrier layer 660A, and has a first resistor. The second contact structure CS2 may include a second contact via 670B and a second barrier layer 660B, and has a second resistor.

[0133] The first contact structure CS1 may have a first height H1 greater than the second height H2 of the second contact structure CS2. Furthermore, the first contact structure CS1 may include a first contact via 670A with a width smaller than the width of the second contact via 670B of the second contact structure CS2, and may include a first barrier layer 660A with a thickness greater than the thickness of the second barrier layer 660B of the second contact structure CS2. The resistivity of each of the first contact via 670A and the second contact via 670B may be less than the resistivity of each of the first barrier layer 660A and the second barrier layer 660B. Therefore, the first resistance of the first contact structure CS1 may be greater than the second resistance of the second contact structure CS2.

[0134] In other words, the first resistance of the first contact structure CS1 corresponding to the first memory cell MC1 formed adjacent to the selection transistor ST can be greater than the second resistance of the second contact structure CS2 corresponding to the second memory cell MC2 set relatively far from the selection transistor ST. Therefore, the first contact structure CS1 can prevent the first memory cell MC1 from being damaged by compensating for the relatively small resistance between the first memory cell MC1 and the selection transistor ST.

[0135] According to the manufacturing method described above, contact holes CTH with different heights can be formed. Subsequently, a barrier layer 660 with different thicknesses can be formed in the contact holes CTH. Then, contact vias 670 with different widths can be formed in the barrier layer 660. In other words, by adjusting the thickness of the barrier layer 660 formed in the contact holes CTH and the width of the contact vias 670, the resistance of the contact structure can be controlled, thereby compensating for the relatively small resistance associated with the memory cell MC, which is configured as a proximity select transistor ST. Therefore, damage to the memory cell MC formed by the proximity select transistor ST can be prevented.

[0136] Figure 7A and Figure 7B This diagram illustrates a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. For the sake of brevity, content repeated above will be omitted in the following text.

[0137] Reference Figure 7A Semiconductor devices can be used in a manner similar to Figures 6A to 6IThe method involves forming the following: First, a peripheral circuit PC can be formed on the substrate 700. The peripheral circuit PC may include a transistor 1, etc. The transistor 1 may include junctions 1A and 1B, a gate insulating layer 1C, and a gate electrode 1D. A device isolation layer ISO can be formed in the substrate 700, an active region can be formed from the device isolation layer ISO, and the transistor 1 can be formed in the active region.

[0138] Subsequently, a first interconnect structure IC1 can be formed on the peripheral circuit PC. The first interconnect structure IC1 can be formed in a first interlayer insulating layer IL1. Here, the first interlayer insulating layer IL1 can be formed on the substrate 700. The first interconnect structure IC1 may include a first via ICA and a first line ICB.

[0139] Subsequently, a second interconnect structure IC2 can be formed on the first interconnect structure IC1. Here, the second interconnect structure IC2 can be formed in the second interlayer insulating layer IL2. The second interlayer insulating layer IL2 can be formed on the first interlayer insulating layer IL1. The second interconnect structure IC2 may include a second line ICC and a third line ICD.

[0140] Subsequently, a selection transistor ST can be formed on the first interconnect structure IC1. The selection transistor ST can be configured to be connected to the second line ICC by extending through the third line ICD.

[0141] An electrode stack 710G can be formed, comprising a first material layer 710A and a conductive layer 710C alternately stacked on a select transistor ST. For example, the first material layer 710A and the conductive layer 710C are alternately stacked to form a stepped structure. Here, the electrode stack 710G may have a stepped structure that exposes the upper surface of the conductive layer 710C, and the upper surface of the conductive layer 710C exposed by the stepped structure may be covered by a third interlayer insulating layer IL3.

[0142] A memory cell MC and a conductive plug 750 may be formed in the electrode stack 710G. Here, the memory cell MC may include a first electrode pattern 720, a variable resistor pattern 730, and a second electrode pattern 740. A slit structure SLS extending through the electrode stack 710G may be formed. An inner liner layer LN may be formed between the slit structure SLS and the electrode stack 710G.

[0143] Subsequently, contact holes CTHs extending through the third interlayer insulating layer IL3 and exposing the conductive layer 710C can be formed. In some embodiments, at least two contact holes CTHs may have different heights. For example, a contact hole CTH may include a first contact hole CTH1 with a relatively large height and a second contact hole CTH2 with a relatively small height. Here, the first contact hole CTH1 may have a first width W1, and the second contact hole CTH2 may have a second width W2 greater than the first width W1.

[0144] For reference, although this diagram illustrates a case where all contact hole CTH widths are different, not all contact hole CTH widths are formed differently. As an example, contact holes can be grouped based on the distance between the memory cell and the select transistor, and the width of the contact holes can be differentiated according to the grouping. As another example, in memory cells where no current spikes are expected in those cells spaced from the select transistor ST, the width of the corresponding contact holes may not need adjustment, and the contact hole widths can be substantially the same. Conversely, in memory cells where current spikes are expected, the width of the corresponding contact holes may need adjustment, and the contact hole widths can be formed differently.

[0145] Reference Figure 7B Contact structures can be formed in contact holes CTH. Here, the contact structure may include at least one of a barrier layer 760 or a contact via 770. For example, the first contact structure CS1 formed in the first contact hole CTH1 may consist of a barrier layer 760. As another example, the second contact structure CS2 formed in the second contact hole CTH2 may consist of a contact via 770.

[0146] In other words, the height of the first contact structure CS1 may be greater than the height of the second contact structure CS2, and the first contact structure CS1 may have a first width W1 that is smaller than the second width W2 of the second contact structure CS2. Furthermore, the first contact structure CS1 may include a barrier layer 760 with relatively high resistivity, and the second contact structure CS2 may include a contact via 770 with relatively low resistivity. Therefore, the resistance of the first contact structure CS1 may be greater than the resistance of the second contact structure CS2.

[0147] According to one embodiment of this disclosure, the resistance of the first contact structure CS1 may be greater than the resistance of the second contact structure CS2. In this case, the first contact structure CS1 can prevent or minimize damage to the memory cell MC, which is configured to be relatively adjacent to the selection transistor ST, due to spike current.

[0148] For reference, although this figure illustrates the case where the first width W1 and the second width W2 of the first contact hole CTH1 and the second contact hole CTH2 are constant from the upper portion to the lower portion, the first contact hole CTH1 and the second contact hole CTH2 may have tapered cross-sections. For example, the widths of the first contact hole CTH1 and the second contact hole CTH2 may decrease from the upper portion to the lower portion. In this case, the widths of the first contact hole CTH1 and the second contact hole CTH2 may be different, and the cross-sectional area of ​​the conductive layer 710C exposed by the first contact hole CTH1 and the second contact hole CTH2 may be different.

[0149] Furthermore, although this figure illustrates a case where the first contact structure CS1 does not include the contact via 770 and the second contact structure CS2 does not include the barrier layer 760, the embodiments of this disclosure are not limited thereto. For example, the first contact structure CS1 may include the contact via 770, and the second contact structure CS2 may include the barrier layer 760 covering the contact via 770.

[0150] Furthermore, although this figure illustrates cases where the barrier layer 760 and the contact via 770 have different thicknesses and widths, the thickness of the barrier layer 760 and the width of the contact via 770 are not limited to these. For example, a barrier layer of substantially the same thickness can be formed in the contact hole, and contact vias of different widths can be formed in the barrier layer.

[0151] According to the manufacturing method described above, contact holes CTH with different heights can be formed. Here, the contact holes CTH can have different widths. For example, the width of a contact hole CTH with a relatively large height can be smaller than the width of a contact hole CTH with a relatively small height. Subsequently, contact structures can be formed in the contact holes CTH. In this way, the relatively small resistance associated with the memory cell MC, which is set as an adjacent select transistor ST, can be compensated, and damage to such memory cells MC can be prevented.

[0152] While some embodiments based on the technical spirit of this disclosure have been described with reference to the accompanying drawings, the various embodiments of this disclosure are not limited to those described above. Those skilled in the art to which this disclosure pertains can make various substitutions, modifications, and changes to the embodiments, and these also fall within the scope of embodiments of this disclosure.

Claims

1. A semiconductor device comprising: An electrode stack comprising a conductive layer and an insulating layer, wherein the conductive layer and the insulating layer are stacked alternately to form a stepped structure; A conductive plug that extends through the electrode stack; A storage unit disposed between the conductive layer and the conductive plug; An interlayer insulating layer is disposed on the stepped structure; Contact vias extend through the interlayer insulating layer and are electrically connected to the conductive layer, and at least two of the contact vias have different widths; as well as A barrier layer, which respectively covers the contact via, and at least two of the barrier layers have different thicknesses.

2. The semiconductor device of claim 1, wherein, The storage unit includes a first storage unit and a second storage unit above the first storage unit. The conductive layer includes a first conductive layer connected to the first memory cell and a second conductive layer connected to the second memory cell. The contact via includes a first contact via electrically connected to the first conductive layer and a second contact via electrically connected to the second conductive layer. The barrier layer comprises a first barrier layer covering the first contact via and a second barrier layer covering the second contact via. Wherein, the first contact via has a first width, and the second contact via has a second width greater than the first width, and The first barrier layer has a third thickness, and the second barrier layer has a fourth thickness that is less than the third thickness.

3. The semiconductor device of claim 2, further comprising: The selection transistor is located below the electrode stack and connected to the conductive plug.

4. The semiconductor device of claim 3, wherein, The first memory cell is spaced a first distance from the select transistor, and the second memory cell is spaced a second distance from the select transistor that is greater than the first distance. The first contact structure includes the first contact via and the first barrier layer and has a first resistance, and the second contact structure includes the second contact via and the second barrier layer and has a second resistance that is less than the first resistance.

5. The semiconductor device of claim 4, wherein, The width of the first contact structure is substantially the same as the width of the second contact structure.

6. The semiconductor device of claim 4, wherein, The width of the first contact structure is smaller than the width of the second contact structure.

7. The semiconductor device of claim 4, wherein, The first contact structure has a first height, and The second contact structure has a second height that is less than the first height.

8. The semiconductor device of claim 1, wherein, Each of the contact vias has a first resistivity, and each of the barrier layers has a second resistivity greater than the first resistivity.

9. The semiconductor device of claim 8, wherein, Each of the contact vias comprises a metallic material, and each of the barrier layers comprises a metal nitride.

10. The semiconductor device of claim 9, wherein, Each of the contact vias contains tungsten, and each of the barrier layers contains tungsten nitride.

11. The semiconductor device of claim 1, wherein, Each of the storage units contains: The first electrode pattern is disposed at a level substantially the same as that of a corresponding conductive layer; A second electrode pattern covering the sidewall of the conductive plug; and A variable resistance pattern is disposed between the first electrode pattern and the second electrode pattern.

12. A semiconductor device comprising: An electrode stack comprising a first conductive layer and a second conductive layer above the first conductive layer, wherein the first conductive layer extends laterally beyond the second conductive layer to form a stepped structure; A conductive plug that extends through the electrode stack; Select a transistor, which is located below the electrode stack and connected to the conductive plug; A first storage cell is disposed between the first conductive layer and the conductive plug, and is spaced a first distance from the selection transistor; The second storage cell is disposed between the second conductive layer and the conductive plug, and is spaced from the selection transistor by a second distance greater than the first distance; An interlayer insulating layer is disposed on the stepped structure; A first contact structure extends through the interlayer insulating layer to connect to the first conductive layer and has a first resistance; as well as The second contact structure extends through the interlayer insulation layer to connect to the second conductive layer and has a second resistance that is less than the first resistance.

13. The semiconductor device of claim 12, wherein, The first contact structure includes a first contact via and a first barrier layer covering the first contact via. The second contact structure includes a second contact via and a second barrier layer covering the second contact via. Wherein, the first contact via has a first width, and the second contact via has a second width greater than the first width, and The first barrier layer has a third thickness, and the second barrier layer has a fourth thickness that is less than the third thickness.

14. The semiconductor device of claim 13, wherein, The first contact via and the second contact via each have a first resistivity, and the first barrier layer and the second barrier layer each have a second resistivity greater than the first resistivity.

15. The semiconductor device of claim 12, wherein, The width of the first contact structure is substantially the same as the width of the second contact structure.

16. The semiconductor device of claim 12, wherein, The width of the first contact structure is smaller than the width of the second contact structure.

17. The semiconductor device of claim 12, wherein, The first contact structure has a first height, and the second contact structure has a second height that is less than the first height.

18. A semiconductor device comprising: Electrode stacks, comprising alternating stacked conductive and insulating layers; A conductive plug that extends through the electrode stack; A selection transistor is disposed below the electrode stack and connected to the conductive plug; A storage unit disposed between the conductive layer and the conductive plug; as well as Contact structures, which are respectively connected to the conductive layer.

19. The semiconductor device of claim 18, wherein, The contact structure includes: Contact vias, each electrically connected to the conductive layer, and having different widths; and The barrier layers cover the contact vias respectively and have different thicknesses.

20. The semiconductor device of claim 18, wherein, The conductive layer comprises a first conductive layer and a second conductive layer above the first conductive layer, and The contact structure includes a first contact structure connected to the first conductive layer and having a first resistance, and a second contact structure connected to the second conductive layer and having a second resistance less than the first resistance.

21. The semiconductor device of claim 18, wherein, The conductive layer comprises a first conductive layer and a second conductive layer on top of the first conductive layer. The storage unit comprises: a first storage unit disposed between the first conductive layer and the conductive plug and spaced a first distance from the select transistor; and a second storage unit disposed between the second conductive layer and the conductive plug and spaced a second distance from the select transistor greater than the first distance. The contact structure comprises: a first contact structure connected to the first conductive layer and having a first area in contact with the first conductive layer; and a second contact structure connected to the second conductive layer and having a second area in contact with the second conductive layer and larger than the first area.

22. The semiconductor device of claim 21, wherein, The first contact structure includes a first contact via having a first width and a first barrier layer covering the first contact via, and The second contact structure includes a second contact via having a second width greater than the first width and a second barrier layer covering the second contact via.

23. The semiconductor device of claim 22, wherein, The thickness of the first barrier layer and the thickness of the second barrier layer are basically the same.

24. The semiconductor device of claim 18, wherein, The conductive layer comprises a first conductive layer and a second conductive layer on top of the first conductive layer. The storage unit comprises: a first storage unit disposed between the first conductive layer and the conductive plug; and a second storage unit disposed between the second conductive layer and the conductive plug. The contact structure includes: a first set of contact structures, which are respectively connected to the first conductive layer and each has a first width; and a second set of contact structures, which are respectively connected to the second conductive layer and each has a second width greater than the first width.

25. The semiconductor device of claim 24, wherein, The first set of contact structures has substantially the same width, and The second set of contact structures has essentially the same width.

26. The semiconductor device of claim 18, wherein, The conductive layer includes a first conductive layer, a second conductive layer above the first conductive layer, and a third conductive layer above the second conductive layer. The storage unit comprises: a first storage unit disposed between the first conductive layer and the conductive plug; a second storage unit disposed between the second conductive layer and the conductive plug; and a third storage unit disposed between the third conductive layer and the conductive plug. The contact structure includes: a first contact structure connected to the first conductive layer and having a first width; a second contact structure connected to the second conductive layer and having a second width greater than the first width; and a set of third contact structures respectively connected to the third conductive layer and each having a third width greater than the second width.

27. The semiconductor device of claim 26, wherein, The first contact structure has a first resistance. Wherein, the second contact structure has a second resistance smaller than the first resistance, and Each of the group of third contact structures has a third resistance that is smaller than that of the second resistance.

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