Memory and method of making the same
Patent Information
- Application Number
- CN202611051093.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-15
- Publication Date
- 2026-10-27
Smart Images
Figure CN122995162A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and includes, but is not limited to, a memory and its fabrication method. Background Technology
[0002] Phase-change memory (PCM) utilizes the reversible phase transition between amorphous and crystalline states of phase-change materials to store information. It possesses advantages such as non-volatility, high speed, and rewritability, and has been extensively studied in the field of semiconductor memory technology. Three-dimensional phase-change memory (3D PCM), as an important technology for improving storage density, typically achieves higher integration by stacking multiple layers of memory structures in the vertical direction. Each layer of the memory structure is generally formed at the intersection of word lines (WL) and bit lines (BL), and the storage function is jointly implemented by threshold switching structures and phase-change memory structures.
[0003] However, in the formation of three-dimensional phase-change memories (PCMs) in related technologies, the eclipse region typically needs to be removed through an etching process. During this process, some sidewalls of the memory structure are exposed after etching. In the subsequent dielectric filling process, the exposed sidewalls of the memory structure are easily exposed to the dielectric material and related process atmosphere, which can lead to oxidation of the edge regions and further damage to the threshold switching layer or phase-change material layer, thereby affecting the electrical performance of the device and the product yield.
[0004] Therefore, how to effectively protect the exposed memory structure after etching the edge region of the three-dimensional phase change memory to reduce the oxidation risk and performance degradation caused by subsequent dielectric filling processes is a technical problem that needs to be solved in the fabrication of three-dimensional phase change memory. Summary of the Invention
[0005] This application provides a memory and its fabrication method, which can reduce the risk of oxidative damage to the exposed sidewalls of the memory structure during subsequent dielectric deposition processes, thereby improving the electrical performance of the device and increasing product yield.
[0006] The technical solution of this application embodiment is implemented as follows: This application provides a method for fabricating a memory, comprising: forming a memory functional layer; patterning the memory functional layer to form a plurality of memory structures; etching the edge regions of the memory structures to expose the sidewalls adjacent to the memory structures; depositing a protective layer to form a protective layer, the protective layer at least covering the exposed sidewalls of the memory structures; depositing a dielectric filling layer made of an insulating dielectric material on the protective layer; wherein the dielectric filling layer covers the protective layer and fills the space after removing the edge regions; the dielectric filling layer is spaced apart from the memory structures by the protective layer.
[0007] In the above scheme, before forming the storage functional layer, the method further includes: forming a first conductive layer; the step of patterning the storage functional layer to form multiple storage structures includes: forming a first patterned mask structure on the storage functional layer, and using the first patterned mask structure as a reference, using a self-aligned dual patterning process to etch the storage functional layer and the first conductive layer to form multiple loop-shaped storage structures and loop-shaped conductive structures.
[0008] In the above scheme, after forming the loop-shaped memory structure, the method further includes: filling the gaps between the plurality of loop-shaped memory structures and loop-shaped conductive structures with a gap dielectric layer; the etching of the edge regions of the memory structure to expose the sidewalls of the memory structure includes: forming a second patterned mask structure on the first patterned mask structure and the gap dielectric layer, and using the second patterned mask structure as a reference, etching two opposite edge regions of the loop-shaped memory structure and the loop-shaped conductive structure to form a strip-shaped memory structure and conductive lines, while exposing the sidewalls of the strip-shaped memory structure.
[0009] In the above scheme, the deposition to form a protective layer includes: forming a protective layer covering the strip storage structure and the interstitial dielectric layer by chemical vapor deposition process; the material of the protective layer is silicon nitride.
[0010] In the above scheme, the insulating dielectric material includes tetraethyl orthosilicate; the deposition of a dielectric filling layer composed of the insulating dielectric material on the protective layer includes: using the tetraethyl orthosilicate as a reaction precursor, depositing the dielectric filling layer on the protective layer by a chemical vapor deposition process.
[0011] In the above scheme, after depositing a dielectric filling layer composed of an insulating dielectric material on the protective layer, the method further includes: performing a chemical mechanical planarization treatment on the film layer on the storage structure until the top surface of the storage structure is exposed.
[0012] In the above scheme, the method further includes: after the chemical mechanical planarization treatment, forming a third patterned mask structure on the storage structure, etching the storage structure with the third patterned mask structure to form an array of storage cells, the area where the storage cells are located constituting a storage array region; removing the film layer structure around the storage array region to form a protective layer covering the storage array region; depositing a dielectric filling layer made of insulating dielectric material on the protective layer; wherein the dielectric filling layer covers the protective layer and fills the space after removing the edge region; the dielectric filling layer is spaced apart from the storage structure by the protective layer.
[0013] In the above scheme, the method further includes: forming a second conductive layer on the storage structure after the chemical mechanical planarization process and before forming the third patterned mask structure.
[0014] This application provides a memory obtained using the memory fabrication method described above; the memory includes: a memory array including a plurality of memory cells arranged in an array; a protective layer covering at least one sidewall of the memory cells adjacent to an edge region; a dielectric filling layer filling the space outside the edge region, the protective layer separating the dielectric filling layer from the memory cells.
[0015] In the aforementioned memory, the protective layer is a silicon nitride layer, and the dielectric filling layer is a silicon dioxide layer formed by chemical vapor deposition using tetraethyl orthosilicate.
[0016] The above scheme has the following beneficial effects: In this embodiment, after etching the edge region of the memory structure to expose the sidewalls of the memory structure adjacent to the edge region, a protective layer covering at least the sidewalls is formed by further deposition, and a dielectric filling layer is deposited on the protective layer so that the dielectric filling layer does not directly contact the exposed memory structure. This reduces the risk of oxidation damage to the memory structure caused by the subsequent dielectric deposition process, which is beneficial to improving the electrical performance of the device and increasing the product yield. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the structure of a storage array in related technologies; Figure 2 This is a schematic diagram of the cross-sectional structure of a memory in related technologies; Figure 3 This is a schematic flowchart of the method for fabricating a memory provided in an embodiment of this application; Figure 4A This is a schematic diagram of the cross-sectional structure after the bottom contact structure is formed, provided in an embodiment of this application; Figure 4BThis is a schematic diagram of the cross-sectional structure after the storage functional layer is formed, provided in an embodiment of this application; Figure 4C This is a schematic diagram of the cross-sectional structure after the storage structure is formed, provided in an embodiment of this application; Figure 4D This is a schematic diagram of the cross-sectional structure after etching the edge region, provided in an embodiment of this application. Figure 4E This is a schematic diagram of the cross-sectional structure after the deposition of the protective layer provided in the embodiments of this application; Figure 4F This is a schematic diagram of the cross-sectional structure of the end face of the strip storage structure after the deposition of the protective layer provided in the embodiments of this application; Figure 4G This is a schematic cross-sectional view of the memory after the deposition medium filling layer is provided in the embodiment of this application. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0019] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.
[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of the embodiments of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And when a second element, component, area, layer, or portion is discussed, it does not indicate that the embodiments of this application necessarily contain a first element, component, area, layer, or portion.
[0021] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “compose” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0023] To fully understand the embodiments of this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions of the embodiments of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, the embodiments of this application may have other implementation methods.
[0024] Among related technologies, 3D Phase Change Memory (3D PCM) offers higher integration density and greater array expansion potential compared to planar phase change memory. By stacking multiple layers of memory structure arrays vertically, 3D PCM can achieve higher capacity within a limited chip area while maintaining non-volatility, faster read / write speeds, and better rewritable performance, thus attracting widespread attention in the field of high-density memory devices. The core memory structure of 3D PCM typically includes a threshold switching structure and a phase change memory structure. For example, the memory functional layer may include an omonic threshold switching (OTS) layer and a phase change material (PCM) layer. To form a high-density cross-array, related technologies typically form the memory functional layer on top of the conductive layer, and then use a patterning process to form multiple memory structures arranged in an array. Each memory structure can ultimately be formed at the intersection of word lines (WL) and bit lines (BL) to achieve memory array integration.
[0025] In the formation of three-dimensional phase-change memories (PDMs) in related technologies, it is typically necessary to first form a memory structure with a loop-shaped region, and then remove the edge regions through a cutting process or a field removal process. For example... Figure 1 As shown, the x-axis and y-axis directions are parallel to the substrate surface, and the z-axis direction is perpendicular to the substrate surface. The x-axis, y-axis, and z-axis directions are mutually perpendicular. After the first etching, multiple loop-shaped memory structures 110 and edge regions 120 located around the loop-shaped memory structures 110 are formed. In subsequent processes, the loop-shaped memory structures 110 typically need to be etched to remove part of the edge regions 120. For example... Figure 2 As shown, the storage structure 20 after removing the edge region 120 includes conductive lines 400 ( Figure 2 The example shows conductive lines 4001, 4002, 4003, 4004, and 4005, and a plurality of strip storage structures 300 disposed on the conductive lines 400. Figure 2Exemplary examples are shown of strip memory structures 3001, 3002, 3003, 3004, and 3005, and a dielectric filling layer 220 surrounding the multiple strip memory structures. After a portion of the edge region 120 is etched away, the sidewalls at both ends of the strip memory structure 300 along the x-axis are exposed, and the upper surfaces of the bottom contact structures 2101 and 2103 located in the removed region are also exposed. It is worth noting that, since three-dimensional phase-change memory requires multiple patterning steps to form a cross array, the problem of exposing the sidewalls of the edge memory structures due to the removal of the peripheral edge region occurs not only during the stage of forming the elongated strip memory structure but also during the stage of finally forming the columnar memory structure. However, since the end face sidewall of the strip memory structure 300 along the x-axis is exposed, during subsequent deposition, the relevant reactive gas environment can easily act on the exposed end face sidewall of the strip memory structure 300, causing oxidation or other adverse chemical reactions in the exposed memory functional layer, which in turn damages the memory functional layer at the edge of the memory structure and leads to morphological degradation of the bidirectional threshold switch layer and the phase change material layer.
[0026] The aforementioned effects will further manifest in the device's electrical characteristics, potentially causing deviations in parameters such as threshold voltage, reset voltage, and set voltage, thereby adversely impacting array consistency, device performance, and product yield. Therefore, during memory fabrication, minimizing the adverse effects of subsequent dielectric deposition processes on the memory structure after the removal of the edge region 120 is a crucial consideration.
[0027] This application provides a method for fabricating a memory, such as... Figure 3 As shown, the procedure includes the following steps S101 to S105: See Figure 4A , Figure 4A This is a schematic diagram of the cross-sectional structure after the bottom contact structure is formed, as provided in an embodiment of this application. Figure 4A As shown, Figure 4A As shown, prior to step S101, a substrate 230 is first provided, and a plurality of bottom contact structures 210 are formed in the substrate 230, for example... Figure 4A Bottom contact structure 2101, bottom contact structure 2102 and bottom contact structure 2103 are shown in the figure.
[0028] In some embodiments, prior to step S101, the following operation may also be performed: forming a first conductive layer.
[0029] See Figure 4B , Figure 4B This is a schematic cross-sectional view of the structure after the storage functional layer is formed, as provided in an embodiment of this application. Figure 4BAs shown, a first conductive layer 15 is formed on the bottom contact structure 210, thereby providing a basis for the subsequent formation of a storage function layer on the first conductive layer 15.
[0030] S101 forms the storage function layer.
[0031] like Figure 4B As shown, step S101 is used to form a storage functional layer located above the first conductive layer 15. The storage functional layer covers the area above the first conductive layer 15 and includes: a lower electrode layer 123, a bidirectional threshold switch layer 14, an intermediate electrode layer 122, a phase change material layer 13, an upper electrode layer 121, and a silicon nitride cap layer 11, thereby forming a storage functional layer located above the first conductive layer 15. The upper electrode layer 121, the intermediate electrode layer 122, and the lower electrode layer 123 together constitute the electrode layer 12.
[0032] Here, the bidirectional threshold switch layer 14 and the phase change material layer 13 together constitute the core storage functional layer of the memory. The bidirectional threshold switch layer 14 refers to the nonlinear switching dielectric layer acting as an array selector, used to maintain an extremely high resistance state when the applied voltage does not reach the threshold voltage, thereby effectively blocking leakage current (i.e., suppressing sneak current) in unselected storage structures within the array. The phase change material layer 13 refers to the physical dielectric layer acting as the data storage carrier, capable of undergoing a reversible phase transition between a disordered amorphous state (high resistance state) and an ordered crystalline state (low resistance state) driven by Joule heating, thereby achieving non-volatile data writing and reading. Between these functional cores, the lower electrode layer 123, the middle electrode layer 122, and the upper electrode layer 121 act as the bottom input, interlayer series connection, and top lead-out conductive hubs, respectively. In particular, the middle electrode layer 122 physically separates the bidirectional threshold switch layer 14 from the phase change material layer 13, effectively preventing atomic interdiffusion or chemical crosstalk between the two core materials under high-temperature operation, thus ensuring the device's cycle life and performance stability.
[0033] At the very top of the storage functional layer, a silicon nitride cap layer 11 is provided. Here, the silicon nitride cap layer 11 refers to an insulating protective layer that serves as a top physical cover. During subsequent downward etching, the silicon nitride cap layer 11 can act as a hard mask to resist etching; at the same time, the silicon nitride cap layer 11 physically covers the underlying upper electrode layer 121 and phase change material layer 13, which can prevent external impurities or water and oxygen gases from contaminating the storage functional layer in complex process environments such as subsequent deposition and planarization.
[0034] In some embodiments, the multiple films from the first conductive layer 15 to the silicon nitride cap layer 11 can be continuously deposited in situ within the same physical vapor deposition apparatus (such as a multi-chamber cluster system) without compromising the high vacuum. This continuous deposition method minimizes interlayer oxidation and micro-contamination, providing a solid physical basis for improving the operating yield and electrical uniformity of phase-change memory.
[0035] Continue to refer to Figure 3 S102, pattern the storage function layer to form multiple storage structures.
[0036] In some embodiments, step S102 can be implemented by forming a first patterned mask structure on the storage functional layer, and using the first patterned mask structure as a reference, etching the storage functional layer and the first conductive layer using a self-aligned dual patterning process to form a plurality of loop-shaped storage structures and loop-shaped conductive structures.
[0037] Here, the first patterned mask structure refers to the patterned mask structure used for the first patterning process, which defines the formation areas of the loop-shaped memory structure and the loop-shaped conductive structure. In practice, the first patterned mask structure may include an initial mask pattern formed by photolithography, and a pattern transfer structure further formed during the self-aligned dual patterning process.
[0038] Here, the self-aligned dual patterning (SADP) process refers to a key lithography technique used to overcome the resolution limits of traditional optical devices. See also Figure 4B In practice, a sacrificial mandrel is first formed on the top silicon nitride cap layer 11. Then, conformal sidewalls (spacers) are deposited and etched on the mandrel sidewalls. The sacrificial mandrel is then selectively removed, and the remaining extremely narrow sidewalls are used as a high-precision hard mask for pattern transfer downwards. Using the SADP process, the feature size (CD) and spacing of the lithographic pattern can be reduced to half of their original size. In the specific etching process, a reactive ion etching (RIE) process with high longitudinal anisotropy can be used. Using the first patterned mask structure as the etching reference, the silicon nitride cap layer 11, upper electrode layer 121, phase change material layer 13, intermediate electrode layer 122, bidirectional threshold switch layer 14, lower electrode layer 123, and first conductive layer 15 are etched sequentially from top to bottom, thereby forming a pattern as shown below. Figure 4C The multiple loop-shaped storage structures shown ( Figure 4C Exemplary examples are given in the form of a loop-shaped storage structure 1101 and a loop-shaped conductive structure ( ). Figure 4C An exemplary example is given in the diagram (a loop-shaped conductive structure 1501).
[0039] In some embodiments, after forming the loop-shaped memory structure, the following operations may also be performed: filling the gaps between the plurality of loop-shaped memory structures and the loop-shaped conductive structures with a gap dielectric layer.
[0040] like Figure 4C As shown, after etching the storage functional layer and the first conductive layer 15 using the SADP process to form multiple loop-shaped storage structures and loop-shaped conductive structures, an interstitial dielectric layer 240 can be filled inside the etched trenches between adjacent loop-shaped structures. The interstitial dielectric layer 240 can be an insulating isolation medium, such as silicon oxide, a low dielectric constant medium, or other insulating media suitable for interstitial filling. Here, the interstitial dielectric layer 240 not only serves to achieve lateral electrical blocking between adjacent loop-shaped structures, fundamentally eliminating adjacent leakage current and signal crosstalk during read / write operations in dense arrays, but also provides crucial lateral mechanical wrapping and support for the columnar storage structure with extremely high aspect ratio, preventing deformation and collapse of the multilayer film structure during subsequent thermal stress or mechanical polishing.
[0041] S103, etch the edge region of the memory structure to expose the sidewalls of the memory structure.
[0042] In some embodiments, step S103 can be implemented as follows: forming a second patterned mask structure on the first patterned mask structure and the gap dielectric layer; using the second patterned mask structure as a reference, etching two opposite edge regions of the loop-shaped memory structure and the loop-shaped conductive structure to form a strip-shaped memory structure and conductive lines, while exposing the sidewalls of the strip-shaped memory structure.
[0043] In this etching step (e.g., the BF ETCH process), under the constraint of the second patterned mask structure, the edge regions corresponding to the loop-shaped memory structure and the loop-shaped conductive structure are etched vertically from top to bottom to remove the peripheral structures. It should be noted that during the vertical etching of the edge regions corresponding to the loop-shaped memory structure and the loop-shaped conductive structure, not only the edges of the loop-shaped structure in the x-axis direction are etched, but also the edge regions in the y-axis direction. After etching, the memory structures in the retained areas are distributed in a strip shape, thus forming multiple strip-shaped memory structures. Figure 4D The example illustrates multiple strip memory structures 300 (including strip memory structures 3001 to 3005). Corresponding to this strip memory structure, a reserved portion of the first conductive layer forms a conductive line 400. Figure 4D Conductive lines 4001 to 4005 are illustrated in the example. In embodiments of this application, conductive line 4001 may be a bit line or word line of a memory.
[0044] With the removal of the outer structure, the end face sidewalls of the strip storage structure 300 along the x-axis, as well as the bottom contact structure 2101 and bottom contact structure 2103, are exposed.
[0045] S104, deposited to form a protective layer.
[0046] Here, the protective layer 16 at least covers the sidewalls of the exposed storage structure.
[0047] In some embodiments, the material of the protective layer 16 is silicon nitride. Therefore, step S104 can be achieved by forming a protective layer covering the strip storage structure and the interstitial dielectric layer through a chemical vapor deposition process.
[0048] like Figure 4E and Figure 4F As shown, where, Figure 4F This is a cross-sectional view taken by cutting downwards along the midpoint of any strip-shaped memory structure in the y-axis direction. Due to the excellent step coverage of the chemical vapor deposition process used, the deposited protective layer 16 conformally and uniformly covers the following areas: the top surface of the strip-shaped memory structure 300 and the interstitial dielectric layer 240 retained after etching; the sidewalls of the strip-shaped memory structures 3001 and 3005; and the end face sidewalls of the strip-shaped memory structure 300 exposed in the preceding etching step (i.e.,...). Figure 4F The exposed end face sidewall of the strip-shaped storage structure 300 along the x-axis; the opened bottom contact structure 210 (i.e. Figure 4E The exposed upper surface of the leftmost bottom contact structure 2101 and the exposed upper surface of the rightmost bottom contact structure 2103, as well as the upper surface of the exposed substrate 230. Due to the field etching in step S103, the end face sidewalls of the strip memory structure 300 along the x-axis are directly exposed. At these exposed end face sidewalls, the internal core film layers (especially the bidirectional threshold switch layer and phase change material layer, which are extremely sensitive to oxidizing gases) lose their original shielding. If an insulating medium (such as a reactive atmosphere containing oxygen, TEOS, etc.) is directly filled, the exposed end face sidewalls will be oxidized, passivated, and their morphology will deteriorate. In this embodiment, the conformal deposition of the protective layer 16 physically and tightly encapsulates these exposed sidewalls, establishing a robust chemical barrier between the storage functional layer and the subsequent complex deposition environment. This barrier can completely block the adverse erosion of the core film layer by subsequent oxygen-containing atmosphere or plasma, thereby ensuring that the edge memory structure is highly consistent with the central array in key electrical characteristics such as threshold voltage (e.g., Vt_RST and Vt_SET) and read / write resistance, fundamentally improving the overall product yield of the memory.
[0049] S105, depositing a dielectric filling layer made of insulating dielectric material on the protective layer.
[0050] Here, the dielectric filling layer 220 covers the protective layer 16 and fills the space after removing the edge area; the dielectric filling layer 220 is separated from the storage structure by the protective layer 16.
[0051] In some embodiments, the insulating dielectric material includes tetraethyl orthosilicate. Therefore, step S105 can be achieved by depositing a dielectric filling layer on the protective layer using tetraethyl orthosilicate as a reaction precursor through a chemical vapor deposition process.
[0052] like Figure 4G As shown, during chemical vapor deposition using tetraethyl orthosilicate as a precursor, insulating dielectric materials such as silicon dioxide generated by the reaction are continuously deposited on the substrate surface. The final dielectric filling layer 220 completely covers the outer surface of the protective layer 16 and densely fills the remaining space from bottom to top. During the deposition of the dielectric filling layer 220, TEOS gas and related reaction atmospheres (such as oxygen-containing precursors or carbon and oxygen plasmas that may be introduced later) in the deposition equipment chamber first contact and adhere to the surface of the protective layer 16 (such as a dense silicon nitride layer). Therefore, the dielectric filling layer 220 and the film deposition process environment are completely physically isolated from the exposed end face sidewalls of the strip memory structure 300 by the protective layer 16. This isolation structure cuts off the path for external oxidizing gases or reaction byproducts to penetrate into the memory functional layers (especially the phase change material layer and the bidirectional threshold switch layer), thereby avoiding oxidation or morphological damage to the exposed end face during the dielectric filling process.
[0053] In some embodiments, after step S105, the following operations may also be performed: chemically and mechanically planarizing the film layer on the storage structure until the top surface of the storage structure is exposed.
[0054] For example, since the dielectric filler layer 220 is typically over-burdened during initial deposition, its surface often protrudes above the top surface of the memory structure. Therefore, a chemical mechanical planarization process can be used to remove the film layer above the memory structure and the dielectric filler layer 220 protruding above the top surface. After planarization, the upper surface of the dielectric filler layer 220 is flush with the top surface of each memory structure, resulting in a relatively flat upper surface structure.
[0055] In some embodiments, a second conductive layer may also be formed on the storage structure after the chemical mechanical planarization process.
[0056] For example, after the aforementioned chemical mechanical planarization process, a second conductive layer can be formed on the top surface of the memory structure. This second conductive layer can provide the upper conductive connection base for the subsequently formed memory cells and can participate in the construction of subsequent cross-connection structures. Subsequently, a third patterned mask structure can be formed on the second conductive layer, and using the third patterned mask structure as the etching reference, the second conductive layer and the corresponding memory structure below it are patterned to form an array of memory cells. It should be noted that after subsequent etching steps, the second conductive layer can form multiple conductive lines arranged in an array. These conductive lines can be word lines or bit lines of the memory (when the aforementioned conductive line 4001 is a word line of the memory, these conductive lines are bit lines of the memory; when the aforementioned conductive line 4001 is a bit line of the memory, these conductive lines are word lines of the memory).
[0057] In some embodiments, the technical problem of this application is that "the edge region of the array area will contact TEOS and cause oxidation, thereby causing OTS / PCM damage." Furthermore, in this application embodiment, the edge region will be exposed and contact TEOS twice. The first time is after the first conductive layer (which will subsequently form BL lines after etching) / storage function layer / first patterned mask structure is completed, the strip-shaped storage function layer is etched on top of the loop-shaped conductive structure. Figure 4D The structure shown involves etching away the loop-shaped structure, exposing the edge region. Subsequent TEOS deposition will cause oxidation of the exposed sidewalls of the strip-shaped memory structure, thus requiring the deposition of a protective layer. The second step involves etching the memory functional layer along the WL line direction to form the memory structure at the intersection of the WL and BL lines. After filling the space between the memory structures with SOD, the WL loop-shaped region must again be removed, exposing the sidewalls of the memory structure. Subsequent TEOS deposition will also oxidize the exposed sidewalls, necessitating the deposition of a protective layer. Therefore, after chemically and mechanically planarizing the film layers on the memory structure and forming the second conductive layer, the following operations can be performed: forming a third patterned mask structure on the memory structure; etching the memory structure using the third patterned mask structure to form an array of memory cells, with the area containing the memory cells constituting the memory array region; removing the film layer structure surrounding the memory array region to form a protective layer covering the memory array region; and depositing a dielectric filling layer composed of an insulating dielectric material on the protective layer.
[0058] Here, the dielectric filling layer covers the protective layer and fills the space after removing the edge areas; the dielectric filling layer is separated from the storage structure by the protective layer.
[0059] In some embodiments, after the aforementioned chemical mechanical planarization process, the top surfaces of the multiple strip-shaped memory structures are exposed, thereby providing a relatively flat process foundation for subsequent patterning processing. At this point, a third patterned mask structure can be formed on the memory structure, and using the third patterned mask structure as an etching reference, the memory structure is further etched, causing the strip-shaped memory structures originally extending along the first direction (i.e., the aforementioned x-axis direction) to be divided along the second direction (i.e., the aforementioned y-axis direction), thereby forming multiple memory cells arranged in an array, and the area where the multiple memory cells are located constitutes a memory array region. The first direction is perpendicular to the second direction.
[0060] After the memory cells are formed, the outer film structure of the memory array region can be removed. With the removal of the outer film structure, the outer sidewalls of the memory cells located at the edge of the memory array region are exposed again. Since the exposed sidewalls still contain film layers that are sensitive to the subsequent deposition environment, such as phase change material layers and bidirectional threshold switching layers, a protective layer can be further deposited after the outer film structure is removed to cover the memory array region.
[0061] In some embodiments, the protective layer can be prepared using the same or similar formation method as described above. For example, a protective layer covering the edge region of the memory array can be formed by chemical vapor deposition, thereby creating a barrier interface between the edge memory cell and the subsequent insulating dielectric deposition environment. Subsequently, a dielectric filling layer composed of an insulating dielectric material can be deposited on the protective layer to fill the space formed after the removal of the outer film structure. This process reduces the risk of oxidation or morphological damage to the edge memory cell caused by the subsequent dielectric deposition environment after the second edge exposure.
[0062] The memory fabrication method provided in this application involves etching the edge region of the memory structure to expose its sidewalls, and then depositing an additional protective layer covering at least the exposed sidewalls before depositing the insulating dielectric filling layer. This physically isolates the sensitive functional film layers in the memory structure from the subsequent deposition environment. Because the protective layer is located between the exposed sidewalls and the subsequent dielectric filling layer, the reaction precursors and related process atmospheres are blocked by the protective layer during the subsequent deposition of the dielectric filling layer, making it difficult for them to directly act on the exposed sidewalls of the memory structure, especially on the phase change material layer and bidirectional threshold switch layer, which are more sensitive to the process environment. This reduces the risk of adverse reactions such as oxidation and passivation through physical and chemical action pathways, minimizes damage and morphological degradation of the functional film layers at the edge of the memory structure, and helps maintain better electrical consistency between edge devices and devices within the array, thereby improving memory reliability and product yield.
[0063] Based on the same inventive concept, this application also provides a memory that can be fabricated using the memory fabrication method described above. The memory includes: a memory array comprising a plurality of memory cells arranged in an array; a protective layer covering at least one adjacent edge region of the memory cells' sidewalls; and a dielectric filling layer filling the space outside the edge region. The protective layer separates the dielectric filling layer from the memory cells.
[0064] In some embodiments, the protective layer can be a silicon nitride layer, and the dielectric filling layer can be a silicon dioxide layer formed by chemical vapor deposition using tetraethyl orthosilicate. Here, a silicon nitride layer is chosen as the protective layer because dense silicon nitride material has extremely strong water and oxygen barrier properties and chemical inertness; while the dielectric filling layer uses a silicon dioxide layer generated using TEOS as a precursor, which can provide excellent insulation performance and large-volume gap-filling capability. When the surrounding space is filled with silicon dioxide generated from TEOS, the silicon nitride protective layer, which is closely attached to the sidewall of the storage structure, effectively isolates the oxygen-rich elements, reaction byproducts, and potential plasma radiation from the TEOS deposition environment.
[0065] The memory provided in this application, in terms of structural layout, introduces an independent, dense protective layer between the storage structure sidewalls at the array edge and the large-area dielectric filling layer on the periphery. This ensures that the dielectric filling layer and the exposed sidewalls of the storage functional layer are physically isolated from each other. This microscopic insulating isolation structure not only provides lateral mechanical stress buffering for the slender, high aspect ratio storage pillars, but also fundamentally and completely prevents oxidation or passivation damage to the bidirectional threshold switching layer and phase change material layer caused by the peripheral interlayer dielectric (such as TEOS silicon oxide) during deposition. Thus, it effectively ensures the integrity of the storage structure at the array edge in terms of microstructure and internal material composition, avoids drift in electrical parameters such as the threshold voltage of edge devices, and thereby improves the electrical consistency and long-term operational reliability of the entire memory array.
[0066] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0067] The above description is merely an embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this disclosure are included within the scope of protection of this disclosure.
Claims
1. A method for fabricating a memory, characterized in that, The method includes: Form a storage function layer; The storage function layer is patterned to form multiple storage structures; The edge region of the storage structure is etched to expose the sidewalls of the storage structure; A protective layer is deposited to form a protective layer that at least covers the sidewalls of the exposed storage structure; A dielectric filling layer made of an insulating dielectric material is deposited on the protective layer; wherein the dielectric filling layer covers the protective layer and fills the space after removing the edge regions; the dielectric filling layer is spaced apart from the storage structure from the protective layer.
2. The method according to claim 1, characterized in that, Before forming the storage functional layer, the method further includes: forming a first conductive layer; and patterning the storage functional layer to form multiple storage structures, including: A first patterned mask structure is formed on the storage functional layer. Based on the first patterned mask structure, a self-aligned dual patterning process is used to etch the storage functional layer and the first conductive layer to form multiple loop-shaped storage structures and loop-shaped conductive structures.
3. The method according to claim 2, characterized in that, After forming the loop-shaped memory structure, the method further includes filling the gaps between the plurality of loop-shaped memory structures and the loop-shaped conductive structure with a gap dielectric layer; The etching of the edge region of the storage structure to expose the sidewalls of the storage structure includes: A second patterned mask structure is formed on the first patterned mask structure and the gap dielectric layer. Using the second patterned mask structure as a reference, two opposite edge regions of the loop-shaped memory structure and the loop-shaped conductive structure are etched to form a strip-shaped memory structure and conductive lines, while exposing the sidewalls of the strip-shaped memory structure.
4. The method according to claim 3, characterized in that, The deposition forms a protective layer, including: A protective layer is formed by chemical vapor deposition to cover the strip-shaped storage structure and the interstitial dielectric layer; the material of the protective layer is silicon nitride.
5. The method according to claim 4, characterized in that, The insulating dielectric material includes tetraethyl orthosilicate; the deposition of a dielectric filling layer composed of the insulating dielectric material on the protective layer includes: Using the tetraethyl orthosilicate as a reaction precursor, the dielectric filling layer is deposited on the protective layer by chemical vapor deposition.
6. The method according to any one of claims 1 to 5, characterized in that, After depositing a dielectric filling layer composed of an insulating dielectric material on the protective layer, the method further includes: The film layers on the storage structure are subjected to chemical mechanical planarization until the top surface of the storage structure is exposed.
7. The method according to claim 6, characterized in that, The method further includes: After the chemical mechanical planarization process, a third patterned mask structure is formed on the storage structure, and the storage structure is etched with the third patterned mask structure to form an array of storage cells, and the area where the storage cells are located constitutes a storage array region. Remove the film structure surrounding the storage array region to form a protective layer covering the storage array region; A dielectric filling layer made of an insulating dielectric material is deposited on the protective layer; wherein the dielectric filling layer covers the protective layer and fills the space after removing the edge regions; the dielectric filling layer is spaced apart from the storage structure from the protective layer.
8. The method according to claim 7, characterized in that, The method further includes: After the chemical mechanical planarization process, and before the formation of the third patterned mask structure, a second conductive layer is formed on the storage structure.
9. A memory, characterized in that, The memory is obtained using the method for fabricating a memory as described in any one of claims 1 to 8; the memory comprises: A storage array, comprising multiple storage cells arranged in an array; A protective layer that at least covers the sidewall of the storage cell adjacent to one edge region; A dielectric filling layer fills the space outside the edge region, and a protective layer separates the dielectric filling layer from the storage cell.
10. The memory according to claim 9, characterized in that, The protective layer is a silicon nitride layer, and the dielectric filling layer is a silicon dioxide layer formed by chemical vapor deposition using tetraethyl orthosilicate.