High performance microelectronic assemblies including through-silicon via bridges employing first die top approach

Abstract

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly can include a first tier having a first die located in a first insulating material; a second tier located on the first tier, the second tier including a second die having a first thickness and a third die having a second thickness different from the first thickness, the second and third dies located in a second insulating material, wherein the second and third dies have a first surface and an opposing second surface, and wherein the first surfaces of the second and third dies have a combined surface area between 3000 square millimeters (mm 2 ) and 9000 mm 2 ; and a redistribution layer (RDL) located between the first and second tiers, the RDL including conductive vias, wherein the first die is electrically coupled to the second and third dies through the conductive vias and through interconnects.

Description

[0001] This application is a divisional application. The original application was filed with the China Patent Office on August 26, 2024, with application number 202411176260.4 and invention title "High-performance microelectronic component including through-silicon via bridge using a top-die scheme". Background Technology

[0002] Integrated circuit (IC) devices (e.g., dies) are typically coupled together in multi-die IC packages to integrate features or functions and facilitate connections with other components (e.g., the package substrate). Attached Figure Description

[0003] The embodiments can be readily understood by considering the following detailed description in conjunction with the accompanying drawings. To facilitate this description, similar reference numerals denote similar structural elements. The embodiments are illustrated in the drawings by way of example rather than limitation.

[0004] Figure 1 This is a side cross-sectional view of an exemplary microelectronic component according to various embodiments.

[0005] Figures 2A-2F This is a top view of an exemplary microelectronic component according to various embodiments.

[0006] Figures 3A-3C This is a side cross-sectional view of other exemplary microelectronic components according to various embodiments.

[0007] Figure 3D yes Figure 3C A schematic cross-sectional view of a portion of an exemplary microelectronic component.

[0008] Figure 4A-4I These are side cross-sectional views of various stages in an exemplary process for manufacturing microelectronic components according to various embodiments.

[0009] Figures 5A-5H These are side cross-sectional views of various stages in an exemplary process for manufacturing microelectronic components according to various embodiments.

[0010] Figure 6 This is a flowchart of an exemplary method for fabricating an exemplary microelectronic component according to various embodiments.

[0011] Figure 7 This is a flowchart of another exemplary method for fabricating an exemplary microelectronic component according to various embodiments.

[0012] Figure 8 It is a cross-sectional view of a device package including one or more microelectronic components according to any of the embodiments disclosed herein.

[0013] Figure 9 It is a cross-sectional side view of a device assembly including one or more microelectronic components according to any embodiment of the embodiments disclosed herein.

[0014] Figure 10 This is a block diagram of an exemplary computing device including one or more microelectronic components according to any of the embodiments disclosed herein. Detailed Implementation

[0015] Overview For the purpose of illustrating the IC package described herein, it is important to understand the phenomena that begin to function during the assembly and packaging of the IC. The basic information below can be considered as the basis for a proper interpretation of this disclosure. Such information is provided for illustrative purposes only and, accordingly, should not be construed in any way as limiting the broad scope of this disclosure and its potential applications.

[0016] With the continued increase in demand for high-performance computing (HPC), heterogeneous integration has become a significant performance driver. Focus on scaling heterogeneous integration will drive interconnect density along with increased bandwidth and improved power efficiency. Many different advanced packaging architectures have been developed to increase the density of planar and three-dimensional (3D) input / output (I / O) lines per unit area, thereby meeting higher data bandwidth requirements and enabling more efficient die decomposition and heterogeneous integration to shorten time-to-market. Recently, the industry has rapidly moved towards 2.5D / 3D advanced packaging technologies, such as die embedding and / or silicon interposers, to achieve significantly higher package I / O counts and densities, thereby meeting the needs of HPC market segments and product performance requirements.

[0017] Meanwhile, system-level heterogeneous integration has attracted significant attention due to its immense potential in supercomputing, autonomous driving, and machine learning applications. Ultra-high-performance computing has driven significant packaging innovations and groundbreaking system-level architectures. The demands of such high-performance computing have spurred the development of very large form factor packaging and the development of system-level heterogeneous integration of compute tiles, I / O, memory, power delivery, and thermal cooling solutions. The microelectronic components disclosed herein enable very large form factor structures that, compared to conventional solutions, offer increased interconnect density, shorter wiring distances, and improved signal and power integrity without incurring high-cost manufacturing operations. Furthermore, the microelectronic structures and components disclosed herein provide new flexibility for electronic device designers and manufacturers, allowing them to achieve their device goals without excessive cost or manufacturing complexity.

[0018] Accordingly, this document discloses microelectronic components, related apparatuses, and methods. For example, in some embodiments, a microelectronic component may include: a first layer comprising a first die located in a first insulating material; and a second layer located on the first layer, the second layer comprising a second die having a first thickness and a third die having a second thickness different from the first thickness, wherein the second die and the third die are located in a second insulating material, wherein the second die and the third die have a first surface and an opposite second surface, and wherein the first surface of the second die and the third die has a thickness of 3000 square millimeters (mm²). 2 ) and 9000mm 2 The combined surface area between the first and second layers; and a redistribution layer (RDL) located between the first and second layers, the RDL including conductive pathways through which the first die is electrically coupled to the second and third dies via interconnects.

[0019] Each of the structures, components, packages, methods, apparatuses, and systems disclosed herein may have several innovative aspects, and none of them alone is solely responsible for all the desired properties disclosed herein. Details of one or more embodiments of the subject matter described herein are set forth in the following description and accompanying drawings.

[0020] In the following description, various aspects of the exemplary embodiments will be described using terms commonly used by those skilled in the art in order to convey the substance of their work to others skilled in the art.

[0021] The terms “circuit” and “circuit system” can refer to one or more passive and / or active electrical and / or electronic components arranged to cooperate with each other to provide a intended function. These terms refer to analog circuit systems, digital circuit systems, hardwired circuit systems, programmable circuit systems, microcontroller circuit systems, and / or any other type of physical hardware electrical and / or electronic components.

[0022] The term "integrated circuit" refers to a circuit integrated into a single chip semiconductor or similar material.

[0023] In some embodiments, the IC dies disclosed herein may include a generally single-crystal semiconductor, such as silicon or germanium, as a base material (e.g., substrate, body), on which integrated circuits are fabricated using conventional semiconductor processing methods. The semiconductor base material may include, for example, N-type or P-type materials. The die may include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor materials) or a silicon-on-insulator (SOI) structure. In some other embodiments, one or more of the base materials in the IC dies may include alternative materials, which may be bonded to or not bonded to silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium indium arsenide, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV group materials. In still other embodiments, the base material may include a compound semiconductor, for example, having a first sublattice of at least one element from group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from group V of the periodic table (e.g., P, As, Sb). In some embodiments, the base material may include an intrinsic group IV or group III-V semiconductor material or alloy that is not intentionally doped with any electroactive impurities; in alternative embodiments, a nominal level of impurity dopant may be present. In some other embodiments, the die may include an amorphous material, such as a polymer; for example, the base material may include a silicone-filled epoxy resin. In other embodiments, the base material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Generally, the base material may include one or more of the following: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, germanium silicon, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium. Although several examples of materials for dies are described herein, any material or structure that can serve as a substrate (e.g., base material) on which IC circuits and structures as described herein can be built falls within the spirit and scope of this disclosure.

[0024] Unless otherwise described, the IC dies described herein include one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) a certain function. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs implementing memory circuitry systems, such as memory devices, memory arrays, control logic units configured to control memory devices and arrays, etc. In another such example, the term "computing die" may be used to describe a die that includes one or more ICs implementing logic / computing circuitry systems, such as I / O functions, arithmetic operations, data pipeline operations, etc.

[0025] In another example, the terms "package" and "IC package" are synonymous, as are the terms "die" and "IC die". Note that the terms "chip", "die", and "IC die" are used interchangeably in this document.

[0026] The term "optical structure" includes various forms of arrangements made within an IC structure, as described herein, for receiving, converting, and / or transmitting optical signals. These may include optical conductors such as waveguides, electromagnetic radiation sources such as lasers and light-emitting diodes (LEDs), and electro-optic devices such as photodetectors.

[0027] In various embodiments, any photonic IC (PIC) described herein may include semiconductor materials, such as N-type or P-type materials. A PIC may include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor materials) or an SOI structure (or more generally, a semiconductor-on-insulator structure). In some embodiments, a PIC may be formed using alternative materials that may or may not be bonded to silicon, including but not limited to lithium niobate, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium aluminum arsenide, aluminum arsenide, aluminum indium arsenide, indium aluminum antimonide, gallium indium arsenide, gallium nitride, gallium indium nitride, indium aluminum nitride, or gallium antimonide, or other combinations of III-N or IV group materials. In some embodiments, a PIC may include amorphous materials, such as polymers. In some embodiments, a PIC may be formed on a printed circuit board (PCB). In some embodiments, the PIC may be heterogeneous, comprising a carrier material (e.g., glass or silicon carbide) as a base material and having a thin semiconductor layer thereon, upon which is an active side comprising transistors and similar components. Although several examples of materials for PICs are described herein, any material or structure that can serve as the substrate on which a PIC can be built falls within the spirit and scope of this disclosure.

[0028] The term “insulation” means “electrical insulation”, and the term “conduction” means “electrical conductivity”, unless otherwise specified. Referring to optical signals and / or devices, components, and elements that operate on or use optical signals, the term “conduction” may also mean “optical conduction”.

[0029] The terms “oxide,” “carbide,” and “nitride” refer to compounds that contain oxygen, carbon, nitrogen, etc., respectively.

[0030] The term "high-k dielectric" refers to a material with a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material with a lower dielectric constant than silicon oxide.

[0031] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") means a solid material that is substantially non-conductive (and / or a liquid material that solidifies after processing, as described herein). By way of example and not limitation, they may include organic polymers and plastics, as well as inorganic materials such as ionic crystals, ceramics, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and alumina, or combinations thereof. They may include dielectric materials, highly polarizable materials, and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of this disclosure. Other examples of insulating materials are underfills and molding materials, or molding-like materials used in encapsulation applications, including, for example, materials used in organic interposers, encapsulation supports, and other such components.

[0032] In various embodiments, components associated with the IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, components associated with the IC may include those monolithically integrated into the IC, those mounted on the IC, or those connected to the IC. The IC described herein can be analog or digital and can be used in many applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC described herein can be used in a single IC die or as part of a chipset for performing one or more related functions in a computer.

[0033] In various embodiments of this disclosure, the transistors described herein may be field-effect transistors (FETs), such as MOSFETs. In many embodiments, the FET is a four-terminal device. In silicon-on-insulator, nanoribbon, or gate-all-around (GAA) FETs, the FET is a three-terminal device including source, drain, and gate terminals and uses an electric field to control the current flowing through the device. A FET typically includes a channel material, source and drain regions provided in and / or on the channel material, and a gate stack comprising a gate electrode material (alternatively referred to as a "work function" material) provided on the portion of the channel material between the source and drain regions ("channel portion"), and optionally also includes a gate dielectric material located between the gate electrode material and the channel material.

[0034] In a general sense, "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components, thereby facilitating the communication of electrical signals between them; an optical interconnect provides an optical connection between two optical components, thereby facilitating the communication of optical signals between them. As used herein, both electrical interconnects and optical interconnects are included in the term "interconnect." The nature of the described interconnect should be understood in this document with reference to the signal medium associated with the interconnect. Thus, when used with reference to electronic devices (e.g., ICs that operate using electrical signals), the term "interconnect" describes any element formed of conductive material for providing an electrical connection to one or more elements associated with the IC and / or between various such elements. In such cases, the term "interconnect" can refer to both electrical traces (sometimes also called "lines," "wires," "metallic wires," or "trenches") and electrical vias (sometimes also called "vias" or "metallic vias"). Sometimes, conductive traces and vias can be referred to as "conductive traces" and "conductive vias," respectively, emphasizing the fact that these elements include conductive materials such as metals. Similarly, when used in reference devices that also operate on optical signals (e.g., PICs), "interconnect" can also describe any element formed of an optically conductive material that provides an optical connection to one or more elements associated with the PIC. In such cases, the term "interconnect" can refer to optical waveguides, including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0035] The term "waveguide" refers to any structure used to guide light from one location to another (typically through a substrate material such as silicon or glass). In various examples, waveguides can be formed from silicon, doped silicon, silicon nitride, glass (e.g., silica (e.g., silicon dioxide or SiO2)), borosilicates (e.g., 70-80 wt% SiO2, 7-13 wt% B2O3, 4-8 wt% Na2O or K2O, and 2-8 wt% Al2O3), and so on. Waveguides can be formed using various techniques, including but not limited to in-situ waveguide formation. For example, in some embodiments, waveguides can be formed in-situ in glass using cryogenic glass-to-glass bonding or by direct laser writing. In-situ formed waveguides can have lower loss characteristics.

[0036] The term "conductive trace" can be used to describe conductive elements isolated by insulating materials. Within an IC die, such insulating materials include interlayer low-k dielectrics provided within the IC die. Within packaging substrates and PCBs, such insulating materials include organic materials such as Ajinomoto building block film (ABF), polyimide, or epoxy resin. Such conductive lines are typically arranged over several stages or layers of a metallization stack.

[0037] The term "conductive via" can be used to describe a conductive element that interconnects two or more conductive lines at different levels of a metallization stack. For this purpose, vias can be provided as a plane generally perpendicular to the IC die / chip or as a plane on which a support structure for the IC structure is provided, and vias can interconnect two conductive lines in adjacent levels or two conductive lines in non-adjacent levels.

[0038] The term "packaging substrate" can be used to describe any substrate material that helps to package any assembly of semiconductor dies and / or other electrical components (e.g., passive electrical components) together. As used herein, packaging substrates can be formed of any material, including but not limited to insulating materials such as resin-impregnated glass fibers (e.g., PCBs or printed circuit boards (PWB)), glass, ceramics, silicon, silicon carbide, etc. Furthermore, as used herein, packaging substrate can refer to a substrate that includes a building layer (e.g., an ABF layer).

[0039] The term “metallized stack” can be used to refer to one or more interconnect stacks used to provide connections to different circuit components of an IC die / chip and / or package substrate.

[0040] As used herein, the term “split” for interconnects refers to the center-to-center distance between adjacent interconnects.

[0041] In the context of a stack of mutually coupled dies or in the context of dies coupled to a package substrate, the term "interconnect" can also refer to die-to-die (DTD) interconnects and die-to-package substrate (DTPS) interconnects, respectively. A DTD interconnect can also be referred to as a first-level interconnect (FLI). A DTPS interconnect can also be referred to as a second-level interconnect (SLI). Although not specifically shown in all presented figures to avoid confusion, when describing a DTD or DTPS interconnect, the surface of the first die may include a first set of conductive contacts, and the surface of the second die or package substrate may include a second set of conductive contacts. Thus, one or more conductive contacts in the first set can be electrically and mechanically coupled to some conductive contacts in the second set via a DTD or DTPS interconnect. In some embodiments, the spacing of the DTD interconnect may differ from the spacing of the DTPS interconnect, although in other embodiments these spacings may be substantially the same.

[0042] It should be recognized that one or more levels of underfill (e.g., organic polymer materials such as benzotriazole, imidazole, polyimide, or epoxy resin) may be provided in the IC package described herein, and may not be labeled to avoid confusion in the accompanying drawings. In various embodiments, each level of underfill may comprise the same or different insulating materials. In some embodiments, each level of underfill may comprise a thermosetting epoxy resin having silica particles; in some embodiments, each level of underfill may comprise any suitable material capable of performing underfill functions such as supporting the die and reducing thermal stress acting on the interconnect. In some embodiments, the selection of the underfill material may be based on design considerations such as form factor, size, stress, operating conditions, etc.; in other embodiments, the selection of the underfill material may be based on material properties and processing conditions such as curing temperature, glass transition temperature, viscosity, and chemical resistance, along with other factors; in some embodiments, the selection of the underfill material may be based on both design and processing considerations.

[0043] In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable polymer, dry film photoimageable polymer, acrylic resin, solvent) may be provided in the IC package described herein and may not be labeled or illustrated to avoid confusion with the accompanying drawings. The solder resist may be a liquid or dry film material comprising a photoimageable polymer. In some embodiments, the solder resist may be non-photoimageable.

[0044] Based on the context of the specific values ​​described herein or as is known in the art, the terms “generally,” “near,” “roughly,” “approximately,” and “about” generally refer to within + / - 20% of the target value (e.g., within + / - 5% or + / - 10% of the target value).

[0045] Based on the context of the specific values ​​described herein or as known in the art, terms indicating various element orientations, such as “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between elements, generally refer to within + / - 5% to 20% of the target value.

[0046] The term “connection” refers to a direct connection between connected objects (which may be one or more of mechanical, electrical and / or thermal connections) without any intermediate means, while the term “coupling” refers to a direct connection between connected objects or an indirect connection through one or more passive or active intermediate means.

[0047] The description uses the phrase "in the embodiments", which can refer to one or more of the same embodiments or different embodiments.

[0048] Furthermore, the terms “comprising,” “including,” “having,” etc., used in the embodiments of this disclosure are synonymous.

[0049] This disclosure may use perspective-based descriptions, such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used for ease of discussion and are not intended to limit the application of the disclosed embodiments.

[0050] The terms “above,” “below,” “between,” and “above” as used herein refer to the relative position of a material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with said other layer, or may have one or more intervening layers. Furthermore, a layer disposed between two layers may be in direct contact with one or both of said two layers, or may have one or more intervening layers. In contrast, a first layer described as being “above” a second layer refers to a layer in direct contact with that second layer. Similarly, unless otherwise explicitly stated, a feature disposed between two features may be in direct contact with the adjacent feature, or may have one or more intervening layers.

[0051] As used herein, the term “setup” refers to placement, positioning, arrangement and / or arrangement, and not any particular method of formation.

[0052] When used in reference to a range of measurement results, the term "between" includes the endpoints of the range.

[0053] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0054] Although some elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, "conductive material" may include one or more conductive materials. In another example, "dielectric material" may include one or more dielectric materials.

[0055] Unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” and “third” to describe a common object merely indicates that different instances of similar objects are being referenced, and does not imply that the objects being described must be in a given order in time, space, sequence, or any other way.

[0056] In the following detailed description, reference is made to the accompanying drawings, which form part of the description, and in the drawings, illustrative examples of embodiments that can be practiced are shown. It should be understood that other embodiments can be utilized, and structural and logical changes can be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be construed in a limiting sense.

[0057] The accompanying drawings may not be drawn to scale.

[0058] In the accompanying drawings, the same reference numerals refer to the same or similar elements / materials illustrated, and unless otherwise stated, the interpretation of an element / material with a given reference numeral provided in the context of one of the drawings applies to other drawings in which elements / materials with the same reference numerals may be illustrated. Furthermore, singular or plural reference numerals may be used in combination with the reference numerals to respectively indicate single or multiple instances of elements of the same or similar type, category, or kind.

[0059] Furthermore, in the accompanying drawings, some schematic illustrations of exemplary structures of the various devices and components described herein may be shown with precise right angles and straight lines. However, it should be understood that such schematic illustrations may not reflect real-world manufacturing limitations, which may make the features appear less “ideal” when any structure described herein is examined using images obtained using appropriate characterization tools, such as scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, or non-contact surface profilometers. In such images of real-world structures, possible processing and / or surface defects may also be visible, such as surface roughness, curvature or profile deviations, pits or scratches, imperfect straight edges of material, slanted vias or other openings, unintentional rounding of corners or variations in the thickness of different material layers, sporadic screw dislocations, edge dislocations or combination dislocations within (multiple) crystal regions, and / or sporadic dislocation defects of individual atoms or clusters of atoms. Other defects not listed herein but common in the field of device fabrication and / or packaging may also exist.

[0060] Note that in the accompanying drawings, various components (e.g., interconnects) are shown aligned (e.g., at corresponding interfaces) for illustrative purposes only; in reality, some or all of them may be misaligned. Furthermore, other components, such as bonding pads, landing pads, metallization, etc., may be present in the assembly and are not shown in the drawings to avoid confusion. Additionally, the drawings are intended to illustrate the relative arrangement of components within the assembly, and in general, such assemblies may include other components not shown (e.g., various interface layers or other components related to optical functions, electrical connections, or thermal mitigation). For example, in some other embodiments, the assembly shown in the drawings may include more dies along with other electrical components. Furthermore, although some components of the assembly are shown as planar rectangles or formed of rectangular solids in the drawings, this is merely for illustrative purposes, and embodiments of these assemblies may be curved, rounded, or other irregularly shaped, depending on the manufacturing processes used to produce the various components, and sometimes unavoidable due to these manufacturing processes.

[0061] The accompanying drawings show a particular number and arrangement of structures and components for illustrative purposes, and any expected number or arrangement of such structures and components may be present in various embodiments.

[0062] Furthermore, unless otherwise stated, the structures shown in the accompanying drawings may take any suitable form or shape depending on the material properties, manufacturing process, and operating conditions.

[0063] For convenience, if there exists a set of figures designated with different letters (e.g., Figure 4A-4I If there are sets of figures with different numbers (e.g., 148-1, 148-2), then such sets can be referred to in this document without the letters (e.g., referred to as "148").

[0064] The operations can be described sequentially as multiple discrete actions or operations in a manner most helpful for understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations are necessarily sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed, and / or the described operations may be omitted.

[0065] Exemplary embodiments Figure 1This is a side cross-sectional view of an exemplary microelectronic component according to various embodiments. The microelectronic component 100 may include a die 114 of a multilayer 104 coupled via RDL 148. Specifically, the microelectronic component 100 may include a first die 114-1 of a first layer 104-1 and conductive pillars 152, a first RDL 148-1 located on a bottom surface and a second RDL 148-2 located on a top surface. The microelectronic component 100 may also include second dies 114-2 and 114-3 of a second layer 104-2 located on the second RDL 148-2. The first die 114-1 may include a double-sided die 114-1A and a single-sided die 114-1B. The double-sided first die 114-1A may include a bottom surface and a top surface having conductive contacts, and a through-silicon via (TSV) 117. The single-sided first die 114-1B may include a top surface having conductive contacts. In this context, a double-sided die refers to a die with connections on both surfaces. The active surface of a double-sided die is the surface containing one or more active devices and a majority of the interconnects, and it can be oriented in either direction, depending on design and electrical requirements. The first layer die 114-1 (e.g., first layer dies 114-1A and 114-1B) may include conductive contacts 124 located on the top surface. The first layer die 114-1A may also include conductive contacts 122 and TSV 117 located on the bottom surface. The conductive contacts 122 and 124 may have a single pitch or a mixed pitch. The second layer dies 114-2 and 114-3 may include conductive contacts 126 located on the bottom surface. The conductive contacts 126 may have a single pitch or a mixed pitch. In some embodiments, the second layer dies 114-2 and 114-3 may include a double-sided die to be electrically coupled to, for example, a third layer die (not shown). The second-layer dies 114-2 and 114-3 may include dies with a single pitch (e.g., shown for die 114-3) and / or dies with a mixed pitch (e.g., shown for die 114-2). In some embodiments, the first-layer die 114-1 may include an active / passive bridging die (e.g., with or without a metal-insulator-metal (MIM) capacitor) for enabling communication between the second-layer dies 114-2 and 114-3. In some embodiments, the second-layer die 114-2 may include a central processing unit (CPU), a graphics processing die (GPU), a system-on-a-chip (SOC), an input / output (I / O) die, or other similar die, and the second-layer die 114-3 may include a high-bandwidth memory (HBM) die. In some embodiments, the first-layer die 114-1 may have different thicknesses (e.g., the first-layer die 114-1A may have a greater thickness than the first-layer die 114-1B, as shown).In some embodiments, the second die layers 114-2 and 114-3 may have different thicknesses (for example, the second die layer 114-3 may have a greater thickness than the second die layer 114-2, as shown in the figure).

[0066] The first RDL 148-1 and the second RDL 148-2 may include conductive pathways 196 through a dielectric material. The first die 114-1 may be electrically coupled to the second dies 114-2 and 114-3 via the conductive pathways 196 through the second RDL 148-1 and via interconnects 120. Interconnects 120 may also be referred to herein as DTD interconnects. Interconnects 120 may have a single pitch or may have a mixed pitch. In some embodiments, interconnects 120 may have a pitch between 1 micrometer and 75 micrometers (e.g., between 1 micrometer and 10 micrometers, between 10 micrometers and 25 micrometers, or between 25 micrometers and 75 micrometers). In some embodiments, interconnects 120 may include solder 132 (e.g., solder bumps or balls of interconnect 120 subjected to thermal reflow to form interconnects 120, as shown). In such embodiments, the microelectronic assembly 100 may also include a bottom filler material 127-1 surrounding the interconnect 120 located between the top surface of the first die 114-1 and the second RDL 148-1. The bottom filler material 127-1 may have an inverted trapezoidal shape (e.g., a trapezoid with a smaller length (i.e., y-scale) adjacent to the top surface of the first layer die 114-1 and a larger length away from the top surface of the first layer die 114-1 (e.g., toward the second RDL 148-2).

[0067] The first die 114-1A can be electrically coupled to the package substrate 102 via a conductive path 196 through the first RDL 148-1 and via interconnect 130. The second die 114-2 can be electrically coupled to the package substrate 102 via conductive paths through the first RDL 148-1 and the second RDL 148-2, conductive pillars 152 in the first layer, and via interconnect 130. Interconnect 130 may also be referred to herein as a DTPS interconnect. In some embodiments, the interconnect 130 disclosed herein may have a pitch between 50 micrometers and 350 micrometers. In some embodiments, interconnect 130 may include solder 134, and underfill material 127-2 may be located between the bottom surface of the first RDL 148-1 and the top surface of the package substrate 102, surrounding interconnect 130.

[0068] The underfill material 127 may be an insulating material, such as a suitable epoxy resin material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material 127 may include an epoxy flux that assists in soldering during the formation of interconnects 120, 130 and subsequently polymerizes and encapsulates interconnects 120, 130. The underfill material 127 may and is selected to have a coefficient of thermal expansion (CTE) that can alleviate or minimize stress between the die 114, RDL 148, and package substrate 102 caused by uneven thermal expansion in the microelectronic component 100. In some embodiments, the CTE of the underfill material 127 may have a value between the CTE of the package substrate 102 (e.g., the CTE of the dielectric material of the package substrate 102) and the CTE of the insulating material of the die 114 and / or RDL 148.

[0069] Interconnect 120 may have a finer pitch than interconnect 130. In some embodiments, interconnect 120 may include solder interconnects having a solder with a higher melting point than the solder included in interconnect 130. For example, when interconnect 120 is formed prior to interconnect 130, interconnect 120 may use a higher-temperature solder (e.g., with a melting point exceeding 200 degrees Celsius), while interconnect 130 may use a lower-temperature solder (e.g., with a melting point below 200 degrees Celsius). In some embodiments, the higher-temperature solder may include: tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the lower-temperature solder may include tin and bismuth (e.g., eutectic tin-bismuth) or tin, silver, and bismuth. In some embodiments, the lower-temperature solder may include indium, indium, and tin, or gallium.

[0070] As used herein, "conductive contact" can refer to a portion of conductive material (e.g., metal) that serves as an electrical interface between different components (e.g., portions of conductive interconnects); the conductive contact may be recessed into the surface of the component, flush with the surface of the component, or extend from the surface of the component (e.g., as shown in the image). Figure 1 (as shown), and can take any suitable form (e.g., conductive pads or slots, or portions of conductive lines or vias). For example, any conductive contact in the conductive contacts disclosed herein may include bonding pads, solder bumps, conductive pillars, or any other suitable conductive contact. Figure 1As shown, the second-layer dies 114-2 and 114-3 are depicted having conductive contacts extending from the surface of the die, and may be referred to herein as "bumped dies" or "microbumped dies," while the first-layer die 114-1 is depicted having conductive contacts flush with the die surface, and may be referred to herein as "bumpless dies." Dies 114 may include other conductive pathways (e.g., wires and vias) and / or other circuitry (not shown) coupled to the corresponding conductive contacts on the surface of die 114.

[0071] The microelectronic component 100 may further include a first insulating material 133-1 surrounding the first die 114-1 and the conductive pillar 152, and a second insulating material 133-2 surrounding the second dies 114-2 and 114-3. In some embodiments, the insulating material 133 may include a molding material, such as an organic polymer having inorganic silicon oxide, a resin material, or an epoxy resin material. In some embodiments, the insulating material 133 may include a molding material, a resin material, or an epoxy resin material, and may also include a thermally conductive material (e.g., metal particles), such as silver and oxygen (e.g., in the form of silver oxide particles) or aluminum and oxygen (e.g., in the form of aluminum oxide particles) or combinations thereof. In some embodiments, the first insulating material 133-1 and the second insulating material 133-2 are the same material. In some embodiments, the first insulating material 133-1 and the second insulating material 133-2 are different materials.

[0072] RDL 148 may include an insulating material (e.g., a dielectric material formed as multiple layers, as known in the art) and one or more conductive pathways 196 through the dielectric material (e.g., including conductive vias as shown, or including conductive traces and / or conductive vias). In some embodiments, RDL 148 may include multiple layers having a conductive fan-out structure. In some embodiments, the insulating material of RDL 148 may be composed of a dielectric material, bismaleimide triazine (BT) resin, polyimide material, epoxy resin material (e.g., glass-reinforced epoxy matrix material, epoxy resin build film, etc.), molding material, oxide-based material (e.g., silica or spin-coated oxide), or low-k and ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymer dielectrics). RDL 148 may have any suitable thickness; for example, in some embodiments, RDL 148 may have a thickness between 1 micrometer and 35 micrometers.

[0073] For example, the conductive pillar 152 can be formed of any suitable conductive material such as copper, silver, nickel, gold, aluminum, or other metals or alloys. The conductive pillar 152 can be formed using any suitable process, such as photolithography or additive manufacturing processes such as cold spraying or 3D printing. In some embodiments, the conductive pillar 152 disclosed herein can have a spacing between 50 micrometers and 150 micrometers. As used herein, the spacing is measured from center to center (e.g., from the center of the conductive pillar to the center of the adjacent conductive pillar). The conductive pillar 152 can have any suitable size and shape. In some embodiments, the conductive pillar 152 can have a circular, rectangular, or other shaped cross-section. The second layer die 114-2 can be electrically coupled to the conductive path 196 in the RDL 148 and electrically coupled to the conductive pillar 152 in the first layer via metal-to-metal interconnects 125 (e.g., copper-to-copper interconnects or plated interconnects).

[0074] The die 114 disclosed herein may include an insulating material (e.g., a dielectric material formed as multiple layers, as known in the art) and multiple conductive pathways formed through the insulating material. In some embodiments, the insulating material of the die 114 may include a dielectric material such as silicon dioxide, silicon nitride, oxide nitride, polyimide material, glass-reinforced epoxy matrix material, or low-k or ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, organic polymer dielectric, photo-imaging dielectric, and / or benzocyclobutene-based polymer). In some embodiments, the insulating material of the die 114 may include a semiconductor material such as silicon, germanium, or a III-V group material (e.g., gallium nitride) and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive pathways in the die 114 may include conductive traces and / or conductive vias, and may connect any conductive contacts in the die 114 by any suitable means (e.g., connecting multiple conductive contacts located on the same or different surfaces of the die 114). The conductive pathways in die 114 may suitably abut against a liner material, such as an adhesive liner and / or a barrier liner. In some embodiments, die 114 is a wafer. In some embodiments, die 114 is monocrystalline silicon, a fan-out or fan-in package die, or a die stack (e.g., stacked wafers, stacked dies, or stacked multilayer dies). In some embodiments, die 114 may include conductive pathways for wiring power, ground, and / or signals to / from other dies 114 included in the microelectronic assembly 100. For example, first die 114-1 may include a TSV 117 (e.g., as shown in die 114-1A) or other conductive pathways through which power, ground, and / or signals can be transmitted between the package substrate 102 and second dies 114-2, 114-3. In some embodiments, second die 114-2 may be directly coupled to power lines and / or ground lines in the package substrate 102 via conductive posts 152.

[0075] The package substrate 102 may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive pathways (e.g., including conductive traces and / or conductive vias, as shown) for wiring power, ground, and signals through the dielectric material. In some embodiments, the insulating material of the package substrate 102 may be a dielectric material, such as an organic dielectric material, a flame-retardant grade 4 material (FR-4), BT resin, a polyimide material, a glass-reinforced epoxy matrix material, an organic dielectric with inorganic fillers, or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). Specifically, when the package substrate 102 is formed using standard printed circuit board (PCB) processes, the package substrate 102 may include FR-4, and the conductive pathways in the package substrate 102 may be formed by patterned copper sheets separated by the build layers of FR-4. The conductive pathways in the package substrate 102 may suitably adjoin a liner material (such as an adhesive liner and / or a barrier liner). In some embodiments, the encapsulation substrate 102 may be formed using a photolithography-defined via encapsulation process. In some embodiments, the encapsulation substrate 102 may be manufactured using standard organic encapsulation manufacturing processes, and thus the encapsulation substrate 102 may take the form of an organic package. In some embodiments, the encapsulation substrate 102 may be a set of redistribution layers formed on a panel carrier, formed by laminating or spin-coating a dielectric material, and establishing conductive vias and conductive lines by laser drilling and plating. In some embodiments, the encapsulation substrate 102 may be formed on a removable carrier using any suitable technique (e.g., redistribution layer technique). Any method known in the art for fabricating the encapsulation substrate 102 may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.

[0076] In some embodiments, the packaging substrate 102 may be a lower-density dielectric, and the die 114 may be a higher-density dielectric or contain regions of a higher-density dielectric. As used herein, the terms “lower density” and “higher density” are relative terms, indicating that the conductive pathways (e.g., including conductive interconnects, conductive lines, and conductive vias) in the lower-density dielectric are larger and / or have greater spacing compared to the conductive pathways in the higher-density dielectric. In some embodiments, the higher-density dielectric may be manufactured using a modified semi-additive process or semi-additive construction process with advanced photolithography (having small vertical interconnect features formed by advanced laser or photolithography processes), while the lower-density dielectric may be a PCB manufactured using standard PCB processes (e.g., a standard subtractive process using etching chemicals to remove unwanted copper areas and having coarse vertical interconnect features formed by standard laser processes). In other embodiments, the higher-density dielectric may be manufactured using semiconductor fabrication processes such as single-metal damascene or double-metal damascene processes. In some embodiments, an additional die may be disposed on the top surface of the second-layer dies 114-2, 114-3. In some embodiments, additional components may be disposed on the top surface of the second-layer dies 114-2, 114-3. Additional passive components such as surface-mount resistors, capacitors and / or inductors may be disposed on the top or bottom surface of the package substrate 102, or embedded in the package substrate 102.

[0077] Figure 1 The microelectronic component 100 may also include a circuit board (not shown). The package substrate 102 may be coupled to the circuit board via interconnects located on the bottom surface of the package substrate 102. Interconnects may include solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or pads in a pad grid array arrangement. For example, the circuit board may be a motherboard and may have other components attached thereto. As known in the art, the circuit board may include conductive paths and other conductive contacts for routing power, ground, and signals through the circuit board. In some embodiments, the package substrate 102 may not be coupled to the circuit board, but may instead be coupled to another IC package, interposer, or any other suitable component. In some embodiments, the microelectronic component 100 may not include the package substrate 102; instead, the dies of each layer may be electrically coupled to the circuit board via a first RDL 148-1.

[0078] although Figure 1 A microelectronic assembly 100 with a specific number of layers 104, dies 114 and RDL 148 is shown, but this number and arrangement are merely illustrative, and the microelectronic assembly 100 may include any expected number and arrangement of dies 114 and RDL 148.

[0079] Figures 2A-2F This is a top view of an exemplary microelectronic component according to various embodiments. The microelectronic component 100 may have any suitable size, any suitable number of layers, any suitable number of dies, and any suitable die arrangement. The packaging substrate 102 may have a size greater than 2500 square millimeters (mm²). 2 (e.g., 50mm by 50mm) surface area (e.g., xy scale, also known as "form factor"). In some embodiments, the packaging substrate 102 may have a surface area greater than 3600mm². 2 (For example, a surface area of ​​60mm by 60mm). In some embodiments, the packaging substrate 102 may have a surface area greater than 10000mm². 2 (For example, a surface area of ​​100mm by 100mm). In some embodiments, the packaging substrate 102 may have a surface area greater than 14400mm². 2 (For example, a surface area of ​​120mm by 120mm). Typically, the reticle size is equal to 26mm by 33mm. The equivalent silicon content of the second-layer dies 114-2 and 114-3 can be calculated with respect to the reticle size. For example, the total surface area of ​​the second-layer dies 114-2 and 114-3 divided by 858mm². 2 (For example, 26mm by 33mm) equals the equivalent silicon content of the second-layer dies 114-2 and 114-3 relative to the photomask size. In some embodiments, the equivalent silicon content of the second-layer dies 114-2 and 114-3 can be between 3.5 times and 6.5 times the photomask size. For example, the equivalent silicon content of the second-layer dies 114-2 and 114-3 can be 3003mm. 2 (For example, 3.5×26mm×33mm) and 5577mm 2 (e.g., 6.5 × 26 mm × 33 mm). The equivalent silicon content is based on the photomask size, so this value can be even larger, for example, between 6.5 times and 10 times, or even greater than 10 times. In some embodiments, the combined surface area of ​​the second-layer dies 114-2, 114-3 (e.g., the sum of the xy scales of each of the second-layer dies 114-2, 114-3) or the combined surface area of ​​the second-layer die 114-2 (e.g., ... Figure 3A (As shown) at 3000mm 2 and 9000mm 2 between. Figure 2AA top view of a microelectronic assembly 100 is shown, comprising a first die 114-1A located on and coupled to a packaging substrate 102, and second dies 114-2 and 114-3 located on and coupled to the first die 114-1A. The first die 114-1A and the second dies 114-2 and 114-3 are shown as repeating units located on and coupled to the packaging substrate 102. The second die 114-2 may be electrically coupled to the packaging substrate 102 via a conductive post 152 (not shown). Although Figure 2A Only two repeating units are shown, but the microelectronic component 100 can have any appropriate number of repeating units and can be based on the surface area of ​​the packaging substrate 102 (e.g., xy scale). Figure 2B A top view of a microelectronic assembly 100 is shown, comprising three first-layer dies 114-1 (e.g., two first-layer dies 114-1A including TSV and a single first-layer die 114-1B without TSV 117) and four second-layer dies 114-2, 114-3 (e.g., two of each of the second-layer dies 114-2, 114-3) located on a packaging substrate 102. Figure 2C It shows including, for example Figure 2B A top view of the microelectronic assembly 100 showing repeating units of the first die 114-1 and the second dies 114-2, 114-3. Figure 2C As shown, the microelectronic component 100 may include twelve (12) first-layer dies 114-1, eight (8) second-layer dies 114-2 and eight (8) second-layer dies 114-3. Figure 2D A top view of a microelectronic assembly 100 comprising nine (9) first-layer dies 114-1, six (6) second-layer dies 114-2 and twelve (12) second-layer dies 114-3 located on a packaging substrate 102 is shown, wherein two (2) second-layer dies 114-3 are coupled to the first-layer dies 114-1. Figure 2E A top view of a microelectronic assembly 100 is shown, comprising nineteen (19) first-layer dies 114-1 (e.g., twelve (12) first-layer dies 114-1A and seven (7) first-layer dies 114-1B coupled to second-layer dies 114-2), six (6) second-layer dies 114-2, and twelve (12) second-layer dies 114-3 located on a packaging substrate 102, wherein each second-layer die 114-3 is coupled to each first-layer die 114-1A. Although Figure 2E First-layer die 114-1A and 114-1B are shown, but first-layer die 114-1 may include different arrangements, and in some embodiments, only first-layer die 114-1A may be included. Figure 2FA top view of a microelectronic assembly 100 is shown, comprising twenty (20) first-layer dies 114-1A, one (1) second-layer die 114-2, and twenty (20) second-layer dies 114-3 located on a packaging substrate 102, wherein each second-layer die 114-3 is coupled to each first-layer die 114-1. Although Figure 2F Twenty (20) first-layer dies 114-1 and twenty (20) second-layer dies 114-3 are shown, but the microelectronic assembly 100 may include fewer, for example, sixteen (16) first-layer dies 114-1 and sixteen (16) second-layer dies 114-3.

[0080] Figure 1 Many elements of the microelectronic component 100 are included in other figures; these elements will not be repeated in the discussion of these figures, and any of these elements may take any form disclosed herein. Furthermore, in Figure 1 Several components are illustrated as being included in the microelectronic assembly 100, but some of these components may not be present in the microelectronic assembly 100. For example, in various embodiments, the underfill material 127-2 and the packaging substrate 102 may not be included. In some embodiments, each microelectronic assembly 100 disclosed herein may serve as a system-in-package (SiP), including multiple dies 114 with different functions. In such embodiments, the microelectronic assembly 100 may be referred to as a SiP.

[0081] Figure 3A This is a side cross-sectional view of yet another exemplary microelectronic component according to various embodiments. The embodiments shown in this figure are similar to... Figure 1 Similarly, except that the first layer 104-1 only includes a first die 114-1A with TSV 117, and the second material 104-2 only includes a second die 114-2 with the same thickness (e.g., z-height), the second die 114-2 having conductive contacts flush with the bottom surface, and the microelectronic assembly 100 also includes a thermal interface material (TIM) 183 and a heat sink 181. The heat sink 181 can be used to dissipate heat from the second dies 114-2, 114-3 (e.g., to make heat more easily dissipated by a heat sink or other thermal management device). The heat sink 181 can include any suitable thermally conductive material (e.g., metal, suitable ceramic, etc.) and can include any suitable features (e.g., fins). In some embodiments, the heat sink 181 can be an integrated heat sink. In some embodiments, the heat sink 181 can include an extension or a base along the z-height (as shown), thereby providing physical contact with the TIM 183.

[0082] Figure 3AThe microelectronic component 100 may also include a thermal interface material (TIM) 183 located between the second dies 114-2, 114-3 and the heat sink 181. TIM 183 may include a thermally conductive material (e.g., metal particles) in a polymer or other binder. TIM 183 may be a thermal interface material paste or a thermally conductive epoxy resin (which may be fluid upon application and harden upon curing, as known in the art). TIM may include solder TIM. TIM 183 may provide a path for heat generated by the second dies 114-2, 114-3 to flow easily to the heat sink 181, where the heat can diffuse and / or dissipate.

[0083] Figure 3B This is a side cross-sectional view of yet another exemplary microelectronic component according to various embodiments. The embodiment shown in this figure is similar to... Figure 3A Similarly, the microelectronic component 100 also includes a spacer 182 located between the second die 114-2 and the TIM 183. The spacer 182 can comprise any suitable material, such as metals and metal alloys like copper, aluminum, and nickel. In some embodiments, the spacer 182 can be physically attached to the top surface of the second die 114-2 using an adhesive 184 or other similar material. The thickness (e.g., z-height) of the spacer 182 and the second die 114-2 can be substantially equal to the thickness of the second die 114-3. For example, the second die 114-2 can comprise a CPU with a thickness of 370 micrometers, and the second die 114-3 can comprise an HBM with a thickness of 750 micrometers, and the spacer 182 can have a thickness of 380 micrometers.

[0084] Figure 3C This is a side cross-sectional view of yet another exemplary microelectronic component according to various embodiments. The embodiment shown in this figure is similar to... Figure 3A Similarly, except that the microelectronic component 100 includes a hybrid bonding interconnect 106 to electrically couple the first die 114-1 to the second dies 114-2, 114-3. Figure 3DThis is a schematic cross-sectional view showing details of a specific one of the interconnects 106 in the microelectronic component 100. In some embodiments, examples of interconnects 106 include a hybrid bonding including metal-metal bonding and dielectric-dielectric bonding. In a general sense, interconnect 106 may include a metal-metal bonding between bonding pads 136 of layer 106-1 and bonding pads 137 of layer 106-2 at interface 138 between layers 106-1 and 106-2, and a dielectric-dielectric bonding in layers 106-1 and 106-2. Bonding pads 136 of layer 106-1 may be bonded to bonding pads 137 of layer 106-2. Bonding pads 136, 137 may also be referred to herein as conductive contacts or metal contacts. The material of the metal-metal bonding (e.g., bonding pads 136, 137) may include copper-copper. Dielectric materials 105 in layers 106-1 and 106-2 may be bonded to each other. The dielectric material 105 may include an inorganic dielectric (e.g., silicon and oxygen in the form of silicon oxide) or an organic dielectric (e.g., polyimide). The bonded metallic and dielectric materials form an interconnect 106 including a hybrid bond, which provides electrical and mechanical coupling between layers 106-1 and 106-2. In some embodiments, the interconnect 106 may have a pitch between 1 micrometer and 75 micrometers.

[0085] Exemplary methods The microelectronic component 100 disclosed herein can be manufactured using any suitable technology. For example, Figure 4A-4I It is for manufacturing according to various embodiments Figure 1 Side cross-sectional views of various stages in an exemplary process of the microelectronic component 100. Although referenced below... Figure 4A-4I (And other accompanying drawings illustrating the manufacturing process) The operations described are shown in a specific order, but these operations can be performed in any suitable order. Furthermore, additional operations, not shown, may be performed without departing from the scope of this disclosure. Moreover, the links herein can be modified in accordance with this disclosure. Figure 4A-4I The operations described herein are used to create other microelectronic components in the microelectronic component 100 disclosed herein.

[0086] Figure 4AThe assembly is shown after the second dies 114-2, 114-3 have been mounted onto the first carrier 401-1, with conductive contacts facing the first carrier 401-1. The second dies 114-2, 114-3 can be placed using any suitable method, such as automated pick-and-place. The carrier 401 can include any suitable material for providing mechanical stability during manufacturing operations, and in some embodiments, can include semiconductor wafers (e.g., silicon wafers) or glass (e.g., glass panels). The second dies 114-2, 114-3 can be attached to the first carrier 401-1 using any suitable technique (e.g., removable adhesive 403).

[0087] Figure 4B The assembly is shown after a second insulating material 133-2 has been deposited onto and around the second-layer dies 114-2, 114-3 and the top surface of the second insulating material 133-2 has been planarized. The second insulating material 133-2 can be formed using any suitable process, including molding. In some embodiments, the second insulating material 133-2 can be dispensed in liquid form to flow around and conform to components and metallization of various shapes, and can subsequently undergo a process that solidifies the second insulating material 133-2, such as curing. The second insulating material 133-2 can be removed (e.g., planarized) using any suitable technique, including abrasion or chemical mechanical polishing (CMP).

[0088] Figure 4C This demonstrates attaching the second carrier 401-2 to... Figure 4B The component following the top surface of the first component. The second carrier 401-2 may include any suitable carrier, as referenced above. Figure 4A As described above, and can be attached using any suitable technique (e.g., removable adhesive 403).

[0089] Figure 4D The diagram shows the assembly after the first carrier 401-1 has been removed, the assembly has been inverted, and a second RDL 148-2 with conductive pathways 196 and conductive pillars 152 have been formed on the top surface of the assembly. The second RDL 148-2 can be manufactured using any suitable technique, such as PCB technology or redistribution layer technology. The conductive pillars 152 can be formed using any suitable technique, such as photolithography or additive processes, such as cold spraying or 3D printing.

[0090] Figure 4E This shows the placement of the first layer die 114-1 in... Figure 4DOn the top surface of the component, an interconnect 120 is formed between the first die 114-1 and the second dies 114-2, 114-3, and an underfill material 127-1 is deposited around the interconnect 120 after the component is assembled. The first die 114-1 can be placed using any suitable method, such as automated pick-and-place. Figure 4E The components can withstand solder reflow processes.

[0091] Figure 4F The diagram shows an assembly after a first insulating material 133-1 has been deposited on and around the first die 114-1 and the conductive pillar 152, and the top surface of the first insulating material 133-1 has been planarized. The first insulating material 133-1 can be formed and planarized using any suitable process, including those referenced above. Figure 4B The process described above.

[0092] Figure 4G It shows in Figure 4F The component is formed on its top surface with a first RDL 148-1 having a conductive path 196 and a conductive contact 174 thereafter. The first RDL 148-1 can be manufactured using any suitable technology, as referenced above. Figure 4D As mentioned above.

[0093] Figure 4H The assembly is shown after solder 134 has been deposited on the conductive contact 174. In some embodiments, other finishing operations may be performed. Exemplary finishing operations include depositing solder resist (not shown).

[0094] Figure 4I The component is shown after the second carrier 401-2 has been removed and the component has been inverted. If multiple components are manufactured together, they can be individualized after the second carrier 401-2 has been removed. Figure 4I The component itself can be a microelectronic component 100, as shown in the figure. It can be used for... Figure 4I The microelectronic component 100 undergoes further manufacturing operations to form other microelectronic components 100; for example, solder 134 can be used to connect them via interconnect 130. Figure 4I The microelectronic component 100 is coupled to the packaging substrate 102, which is... Figure 1 Similar to the microelectronic component 100, and attached to TIM 183 and heat sink 181, this is... Figure 3A Similar to microelectronic components.

[0095] Figures 5A-5H It is for manufacturing according to various embodiments Figure 3B Side cross-sectional views of various stages in an exemplary process of a microelectronic component 100. Figure 5AThe assembly is shown after the spacer 182 has been mounted on the carrier 501. The carrier 501 may include any suitable material for providing mechanical stability during manufacturing operations, and in some embodiments may include a semiconductor wafer (e.g., a silicon wafer) or glass (e.g., a glass panel). The spacer 182 may be attached to the carrier 501 using any suitable technique (e.g., a removable adhesive 503). In some embodiments, adhesive 184 may be located on the top surface of the spacer 182 or may be deposited thereon.

[0096] Figure 5B The assembly is shown after the second dies 114-2 and 114-3 have been mounted onto the carrier 501, with the conductive contacts facing away from the carrier 501. The second die 114-2 can be attached to adhesive 184 on the top surface of the spacer 182, and the second die 114-3 can be attached to adhesive 503 on the top surface of the carrier 501. The second dies 114-2 and 114-3 can be placed using any suitable method, such as automated pick-and-place.

[0097] Figure 5C The diagram illustrates an assembly after a second insulating material 133-2 has been deposited on and around spacer 182 and second-layer dies 114-2, 114-3, and the top surface of the second insulating material 133-2 has been planarized. The second insulating material 133-2 can be formed using any suitable process, including molding. In some embodiments, the second insulating material 133-2 can be dispensed in liquid form, flowing and conformally conforming to components and metallization of various shapes, and subsequently subjected to processes that solidify the second insulating material 133-2, such as curing. The second insulating material 133-2 can be removed using any suitable technique (e.g., planarization), including grinding or CMP.

[0098] Figure 5D It shows in Figure 5C The component is formed on its top surface by creating a second RDL 148-2 with conductive pathways 196 and conductive pillars 152. The second RDL 148-2 can be manufactured using any suitable technology, such as PCB technology or redistribution layer technology. The conductive pillars 152 can be formed using any suitable technology, such as photolithography or additive processes, such as cold spraying or 3D printing.

[0099] Figure 5E This shows the placement of the first layer die 114-1 in... Figure 5DOn the top surface of the component, an interconnect 120 is formed between the first die 114-1 and the second dies 114-2, 114-3, and an underfill material 127-1 is deposited around the interconnect 120 after the component is assembled. The first die 114-1 can be placed using any suitable method, such as automated pick-and-place. Figure 5E The components can withstand solder reflow processes.

[0100] Figure 5F The diagram shows an assembly after a first insulating material 133-1 has been deposited on and around the first die 114-1 and the conductive pillar 152, and the top surface of the first insulating material 133-1 has been planarized. The first insulating material 133-1 can be formed and planarized using any suitable process, including those referenced above. Figure 5C The process described above.

[0101] Figure 5G It shows in Figure 5F The component has a first RDL 148-1 with conductive pathways 196 and conductive contacts 174 formed on its top surface. A final processing operation is performed, and solder 134 is deposited on the conductive contacts 174 after this process. The first RDL 148-1 can be manufactured using any suitable technique, as referenced above. Figure 5D The exemplary final processing operation includes depositing solder resist (not shown).

[0102] Figure 5H The component is shown after the carrier 501 has been removed and the component has been inverted. If multiple components are manufactured together, each component can be individualized after the carrier 501 has been removed. Figure 5H The component itself can be a microelectronic component 100, as shown in the figure. It can be used for... Figure 5H The microelectronic component 100 undergoes further manufacturing operations to form other microelectronic components 100; for example, solder 134 can be used to connect them via interconnect 130. Figure 5H The microelectronic component 100 is coupled to the packaging substrate 102 and attached to the TIM 183 and the heat sink 181, which is consistent with... Figure 3B Similar to microelectronic components.

[0103] Figure 6This is a flowchart of an exemplary method for fabricating an exemplary microelectronic component according to various embodiments. At 602, second dies 114-2, 114-3 can be attached to a first carrier (e.g., first carrier 401-1 in FIG. 4), wherein the conductive contacts face the first carrier. The second dies 114-2, 114-3 can be encapsulated with a second insulating material 133-2, and the top surface of the second insulating material 133-2 can be planarized. At 604, a second carrier opposite to the first carrier (e.g., second carrier 401-2 in FIG. 4) can be attached. The first carrier can be removed, the component can be inverted, and a second RDL 148-2 and conductive pillar 152 can be formed on the top surface of the component. At 606, the first die 114-1 can be electrically coupled to the second dies 114-2 and 114-3 via interconnect 120. An underfill material 127-1 can be deposited around the interconnect 120, and a first insulating material 133-1 can be deposited on and around the first die 114-1 and planarized. At 608, a first RDL 148-1 with conductive pathways 196 can be formed on the first insulating material 133-1. At 610, final processing operations can be performed, including depositing solder resist and attaching solder 134 to the conductive contact 174. The second carrier can be removed, and the assembly can be inverted.

[0104] Figure 7This is a flowchart of an exemplary method for fabricating an exemplary microelectronic component according to various embodiments. At 702, a spacer 182 may be attached to a carrier (e.g., carrier 501 in FIG. 5). The spacer 182 may include an adhesive 184 on its top surface, or an adhesive may be deposited on the top surface of the spacer. At 704, second dies 114-2, 114-3 may be attached to the carrier, wherein conductive contacts face away from the carrier, the second dies 114-2, 114-3 may be encapsulated with a second insulating material 133-2, and the top surface of the second insulating material 133-2 may be planarized. The second die 114-2 may be attached to the top surface of the spacer 182, and the second die 114-3 may be attached to the top surface of the carrier. At 706, a second RDL 148-2 and conductive pillars 152 may be formed on the top surface of the component. At 708, the first die 114-1 can be electrically coupled to the second dies 114-2 and 114-3 via interconnect 120. An underfill material 127-1 can be deposited around the interconnect 120, and a first insulating material 133-1 can be deposited on and around the first die 114-1 and planarized. At 710, a first RDL 148-1 with conductive pathways 196 can be formed on the first insulating material 133-1. At 712, final processing operations can be performed, including depositing solder resist and attaching solder 134 to the conductive contact 174. The carrier can be removed, and the assembly can be inverted.

[0105] Exemplary devices and components The encapsulation disclosed in this article (e.g., Figure 1 Any embodiment shown in -3 or any other embodiment described herein may be included in any suitable electronic component. Figure 8-10 Various examples of packages, components, and devices that can be used in conjunction with or may include any IC package disclosed herein are shown.

[0106] Figure 8 This may be a side cross-sectional view of an exemplary IC package 2200 that may include any embodiment of the IC package disclosed herein. In some embodiments, the IC package 2200 may be a SiP (System-in-Package).

[0107] As shown in the figure, the encapsulation substrate 2252 may be formed of an insulator (e.g., ceramic, a building film, an epoxy film having filler particles, etc.) and may have conductive pathways extending through the insulator between the first surface 2272 and the second surface 2274, or extending between different locations on the first surface 2272 and / or between different locations on the second surface 2274. These conductive pathways may take the form of any interconnect structure including wires and / or vias.

[0108] The package substrate 2252 may include conductive contacts 2263 coupled to conductive passages 2262 through the package substrate 2252, thereby allowing circuitry within the die 2256 and / or inserter 2257 to be electrically coupled to individual conductive contacts in the conductive contacts 2264 (or to other means, not shown, included in the package substrate 2252).

[0109] IC package 2200 may include an interposer 2257 coupled to package substrate 2252 via conductive contacts 2261, a first-level interconnect 2265, and conductive contacts 2263 of package substrate 2252. The first-level interconnect 2265 shown in the figure is a solder bump, but any suitable first-level interconnect 2265, such as a solder bump, solder pillar, or bonding wire, can be used.

[0110] IC package 2200 may include one or more dies 2256 coupled to interposer 2257 via conductive contacts 2254, first-level interconnects 2258, and conductive contacts 2260 of interposer 2257. Conductive contacts 2260 may be coupled to conductive paths (not shown) through interposer 2257, thereby allowing circuitry within die 2256 to be electrically coupled to individual conductive contacts 2261 in conductive contacts 2261 (or to other means (not shown) included in interposer 2257). The first-level interconnect 2258 shown in the figure is a solder bump, but any suitable first-level interconnect 2258, such as a solder bump, solder post, or bonding wire, may be used. As used herein, "conductive contact" may refer to a portion of conductive material (e.g., metal) that acts as an interface between different components; conductive contacts may be recessed into, flush with, or extend from the surface of a component, and may take any suitable form (e.g., conductive pad or socket).

[0111] In some embodiments, underfill material 2266 may be disposed between package substrate 2252 and interposer 2257, surrounding first-level interconnect 2265, and molding material 2268 may be disposed surrounding die 2256 and interposer 2257, and in contact with package substrate 2252. In some embodiments, underfill material 2266 may be the same as molding material 2268. Exemplary materials that may be used for underfill material 2266 and molding material 2268, where appropriate, are epoxy resins. Second-level interconnect 2270 may be coupled to conductive contact 2264. The second-level interconnect 2270 shown in this figure is a solder ball (e.g., for a ball grid array (BGA) arrangement), but any suitable second-level interconnect 2270 may be used (e.g., pins in a pin grid array arrangement or pads in a pad grid array arrangement). The second-level interconnect 2270 may be used to couple IC package 2200 to another component, such as a circuit board (e.g., motherboard), interposer, or another IC package, as known in the art and referenced below. Figure 9 As stated above.

[0112] In embodiments where IC package 2200 includes a plurality of dies 2256, IC package 2200 may be referred to as a multi-chip package (MCP). Dies 2256 may include circuitry performing any intended function. For example, in addition to one or more of dies 2256 being microelectronic component 100 as described herein, one or more of dies 2256 may be logic dies (e.g., silicon-based dies), and one or more of dies 2256 may be memory dies (e.g., HBM), etc. In some embodiments, any die 2256 may be implemented in accordance with the discussion made with reference to any of the preceding figures. In some embodiments, at least some of dies 2256 may not include the implementations described herein.

[0113] Although the IC package 2200 shown in the figure is a flip-chip package, other packaging architectures can be used. For example, the IC package 2200 can be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 can be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are shown in the IC package 2200, the IC package 2200 can include any intended number of dies 2256. The IC package 2200 can include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252 or on either side of the interposer 2257. More generally, the IC package 2200 can include any other active or passive components known in the art.

[0114] In some embodiments, the interposer 2257 may not be included in the IC package 2200; instead, the die 2256 may be directly coupled to the conductive contact 2263 at the first surface 2272 by the first interconnect 2265.

[0115] Figure 9 This is a cross-sectional side view of an IC device assembly 2300 that may include components having one or more microelectronic components 100 according to any embodiment of the embodiments disclosed herein. The IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302 (e.g., a motherboard). The IC device assembly 2300 includes components disposed on a first surface 2340 of the circuit board 2302 and an opposite second surface 2342 of the circuit board 2302; generally, components may be disposed on one or both of surfaces 2340 and 2342. Specifically, any suitable component of the IC device assembly 2300 may include any microelectronic component of one or more microelectronic components 100 according to any embodiment of the embodiments disclosed herein; for example, any IC package discussed below with reference to the IC device assembly 2300 may take the form of the above-referenced IC package. Figure 8 The embodiments of the IC package 2200 discussed herein take any form.

[0116] In some embodiments, circuit board 2302 may be a PCB, comprising a plurality of metal layers spaced apart from each other by insulating layers and interconnected by conductive vias. Any one or more of the metal layers may be formed according to a predetermined circuit pattern, thereby (optionally in conjunction with other metal layers) routing electrical signals between components coupled to circuit board 2302. In other embodiments, circuit board 2302 may be a non-PCB package substrate.

[0117] As shown in the figure, in some embodiments, the IC device assembly 2300 may include an interposer-on-package structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling member 2316. The coupling member 2316 may electrically and mechanically couple the interposer-on-package structure 2336 to the circuit board 2302 and may include solder balls (as shown), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0118] The on-package structure 2336 of the interposer may include an IC package 2320 coupled to the interposer 2304 via a coupling member 2318. Depending on the intended function, the coupling member 2318 may take any suitable form, such as the form discussed above with reference to coupling member 2316. In some embodiments, the IC package 2320 may be or may include an IC package 2200, for example, as described above with reference to... Figure 8 As described.

[0119] Although a single IC package 2320 is shown in the figure, multiple IC packages can be coupled to interposer 2304; in fact, additional interposers can be coupled to interposer 2304. Interposer 2304 can provide an intermediary package substrate for bridging circuit board 2302 and IC package 2320. Generally, interposer 2304 can redistribute connections to a wider pitch or rewire connections to different connections. For example, interposer 2304 can couple IC package 2320 to the BGA of coupling component 2316 for coupling to circuit board 2302.

[0120] In the embodiment shown in the figure, the IC package 2320 and the circuit board 2302 are attached to opposite sides of the interposer 2304. In other embodiments, the IC package 2320 and the circuit board 2302 may be attached to the same side of the interposer 2304. In some embodiments, three or more components may be interconnected via the interposer 2304.

[0121] Intercalator 2304 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic materials, or polymeric materials such as polyimide. In some embodiments, intercalator 2304 may be formed of alternating rigid or flexible materials, including the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and IV materials. Intercalator 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. Intercalator 2304 may also include embedded devices 2314, which may include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on intercalator 2304. The on-package structure 2336 can take any form of on-package structure known in the art.

[0122] In some embodiments, IC device assembly 2300 may include IC package 2324 coupled to a first side 2340 of circuit board 2302 via coupling member 2322. Coupling member 2322 may take the form of any of the embodiments discussed above with reference to coupling member 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0123] In some embodiments, the IC device assembly 2300 may include a package-on-package structure 2334 coupled to a second side 2342 of a circuit board 2302 via a coupling member 2328. The package-on-package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together via a coupling member 2330, such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling members 2328 and 2330 may take the form of any embodiment of the coupling member 2316 discussed above, and the IC package 2326 and / or 2332 may take the form of any embodiment of the IC package 2320 discussed above. The package-on-package structure 2334 may be configured according to any package-on-package structure known in the art.

[0124] Figure 10 This is a block diagram of an exemplary computing device 2400 that may include one or more components having one or more IC packages having any of the embodiments disclosed herein. For example, any suitable component of the computing device 2400 may include a microelectronic component 100 having any of the embodiments disclosed herein. In another example, any one or more of the components of the computing device 2400 may include any embodiment of IC package 2200 (e.g., such as...). Figure 8 (As shown in the illustration). In yet another example, any one or more components of computing device 2400 may include IC device assembly 2300 (e.g., as shown in the illustration). Figure 9 (as shown in the image).

[0125] Several components are shown as included in computing device 2400 in this figure, but any one or more of these components may be omitted or doubled, depending on the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured on a single system-on-a-chip (SoC) die.

[0126] Furthermore, in various embodiments, computing device 2400 may not include one or more of the components shown in the figure, but computing device 2400 may include interface circuitry systems for coupling to said one or more components. For example, computing device 2400 may not include display device 2406, but may include display device interface circuitry systems (e.g., connector and driver circuitry systems) to which display device 2406 may be coupled. In another set of examples, computing device 2400 may not include audio input device 2418 or audio output device 2408, but may include audio input or output device interface circuitry systems (e.g., connector and support circuitry systems) to which audio input device 2418 or audio output device 2408 may be coupled.

[0127] Computing device 2400 may include processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any means or part of a means of processing electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. Processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing means. Computing device 2400 may include memory 2404, which itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drives. In some embodiments, memory 2404 may include memory that shares a die with processing device 2402. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0128] In some embodiments, computing device 2400 may include communication chip 2412 (e.g., one or more communication chips). For example, communication chip 2412 may be configured to manage wireless communication for transmitting data to and from computing device 2400. The term "wireless" and its derivatives can be used to describe circuits, apparatus, systems, methods, techniques, communication channels, etc., that can transmit data via non-solid-state media using modulated electromagnetic radiation. This term does not imply that associated apparatuses do not contain any wires, although they may not in some embodiments.

[0129] The 2412 communication chip can implement any of many wireless standards or protocols, including but not limited to IEEE standards (including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision)), LTE initiatives with any revisions, updates, and / or modifications (e.g., Advanced LTE initiatives, Ultra Mobile Broadband (UMB) initiatives (also known as "3GPP2"), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks. WiMAX is an acronym for Global Microwave Access Interoperability, a certification mark for products that have passed the IEEE 802.16 standard's compliance and interoperability tests. The 2412 communication chip can operate according to GSM, GPRS, UMTS, HSPA, Evolved HSPA (E-HSPA), or LTE networks. Communication chip 2412 may operate according to GSM Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication chip 2412 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO), their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher. In other embodiments, communication chip 2412 may operate according to other wireless protocols. Computing device 2400 may include antenna 2422 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0130] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 may include multiple communication chips. For example, a first communication chip 2412 may be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, and others. In some embodiments, the first communication chip 2412 may be dedicated to wireless communications, and the second communication chip 2412 may be dedicated to wired communications.

[0131] The computing device 2400 may include a battery / power circuitry system 2414. The battery / power circuitry system 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or a circuitry system for coupling components of the computing device 2400 to an energy source (e.g., AC line power) separate from the computing device 2400.

[0132] The computing device 2400 may include a display device 2406 (or a corresponding interface circuit system, as discussed above). The display device 2406 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0133] The computing device 2400 may include an audio output device 2408 (or a corresponding interface circuitry, as discussed above). The audio output device 2408 may include any means of generating audible indications, such as a speaker, headphones, or earphones.

[0134] The computing device 2400 may include an audio input device 2418 (or a corresponding interface circuit system, as discussed above). The audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0135] The computing device 2400 may include a GPS device 2416 (or a corresponding interface circuit system, as discussed above). The GPS device 2416 may communicate with a satellite-based system and may receive the location of the computing device 2400, as is known in the art.

[0136] The computing device 2400 may include other output devices 2410 (or corresponding interface circuitry, as discussed above). Examples of other output devices 2410 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0137] The computing device 2400 may include other input devices 2420 (or corresponding interface circuitry, as discussed above). Examples of other input devices 2420 may include accelerometers, gyroscopes, compasses, image acquisition devices, keyboards, cursor control devices such as mice, styluses, touchpads, barcode readers, quick-response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0138] The computing device 2400 can have any anticipated form factor, such as a portable or mobile computing device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, notebook computer, ultrabook computer, personal digital assistant (PDA), super mobile personal computer, etc.), desktop computing device, server or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device. In some embodiments, the computing device 2400 can be any other electronic device for processing data.

[0139] Selected Example The description of the illustrative embodiments of this disclosure (including those described in the abstract) is not intended to be exhaustive or to limit this disclosure to the exact forms disclosed. Although specific embodiments and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications may be possible within the scope of this disclosure, as will be recognized by those skilled in the art.

[0140] The following paragraphs provide various examples of the embodiments disclosed herein.

[0141] Example 1 is a microelectronic component comprising: a first layer including a first die located in a first insulating material; and a second layer located on the first layer, the second layer including a second die having a first thickness and a third die having a second thickness different from the first thickness, wherein the second die and the third die are located in a second insulating material, wherein the second die and the third die have a first surface and an opposite second surface, wherein the first surface of the second die and the third die has a thickness of 3000 square millimeters (mm²). 2 ) and 9000mm 2 The combined surface area between the first and second layers; and the redistribution layer (RDL) located between the first and second layers, the RDL including conductive paths through the RDL, wherein the first die is electrically coupled to the second and third dies through the conductive paths through the RDL and through interconnections.

[0142] Example 2 may include the subject of Example 1, and may further specify that the interconnect includes solder.

[0143] Example 3 may include the subject of Example 2, and may also include: a bottom filler material located between the second surface of the first die and the RDL and surrounding the interconnect, wherein the bottom filler material has an inverted trapezoidal shape.

[0144] Example 4 may include the subject matter of Example 1 and may further specify that the interconnection includes metal-metal bonding and dielectric-dielectric bonding.

[0145] Example 5 may include the subject of any of Examples 1-4, and may further specify that the spacing of the interconnect is between 1 micrometer and 75 micrometers.

[0146] Example 6 may include the subject of any of the examples in Examples 1-5, and may further specify that some of the first dies also include through-silicon vias (TSVs).

[0147] Example 7 may include the subject of any of the examples 1-6, and may further specify that the first layer also includes conductive posts that pass through the first insulating material and are electrically coupled to the second die.

[0148] Example 8 may include the subject matter of any of the examples in Examples 1-7, and may further specify that the first insulating material or the second insulating material comprises conductive particles in a molding material, resin material or epoxy resin material.

[0149] Example 9 may include the subject of Example 8 and may further specify that the conductive particles include silver and oxygen, aluminum and oxygen, or combinations thereof.

[0150] Example 10 may include the subject of any of the examples in Examples 1-9, and may further specify that the first die includes a bridge die.

[0151] Example 11 may include the subject matter of any of the examples 1-10, and may further specify that the second die includes a central processing unit (CPU), a graphics processing unit (GPU), an input / output (I / O) block, or a system-on-a-chip (SoC) die, and the third die includes a high-bandwidth memory (HBM) die.

[0152] Example 12 may include the subject of any of the examples in Examples 1-11, and may also include: a spacer on the second die in the second layer.

[0153] Example 13 may include the subject matter of Example 12 and may further specify that the material of the spacer includes one or more of the following: copper, aluminum, nickel, or a metal alloy.

[0154] Example 14 may include the subject matter of any of the examples 1-13, and may further specify that: the RDL is a second RDL including a second conductive path, and the microelectronic component may also include: a first RDL including a first conductive path, wherein the first layer is located on the first RDL.

[0155] Example 15 may include the subject of Example 14, and may also include: a packaging substrate electrically coupled to the first RDL.

[0156] Example 16 may include the subject matter of Example 15 and may further specify that the surface area of ​​the packaging substrate is 2500 square millimeters (mm²). 2 ) and 14400mm 2 between.

[0157] Example 17 may include the subject matter of Example 15 and may further specify that the surface area of ​​the encapsulation substrate is greater than 2500 square millimeters.

[0158] Example 18 may include the subject of Example 15, and may also include: a heat sink located on the second layer.

[0159] Example 19 may include the subject of Example 18, and may also include: thermal interface material (TIM) located between the heat sink and the second layer.

[0160] Example 20 is a microelectronic component comprising: a first die surrounded by a first insulating material; a redistribution layer (RDL) on the first die including conductive pathways through the RDL; and a second die on the RDL surrounded by a second insulating material, the second die having a first surface and an opposite second surface, wherein the first surface of the second die has a diameter of 3000 square millimeters (mm²). 2 ) and 9000mm 2 The combined surface area between them, and may be further specified: the first die is electrically coupled to the second die via an interconnect including solder, wherein the interconnect is surrounded by a bottom filler material having an inverted trapezoidal shape.

[0161] Example 21 may include the subject of Example 20, and may further specify that the spacing of the interconnect is between 25 micrometers and 75 micrometers.

[0162] Example 22 includes the subject of Example 20 or 21 and may be further specified: some of the first dies also include through-silicon vias (TSVs).

[0163] Example 23 may include the subject of any of the examples 20-22, and may also include: conductive posts of some of the second dies that pass through the first insulating material and are electrically coupled to the second die.

[0164] Example 24 may include the subject matter of any of the examples 20-23, and may further specify that the first insulating material or the second insulating material comprises conductive particles in a molding material, resin material or epoxy resin material.

[0165] Example 25 may include the subject of Example 24 and may further specify that the conductive particles include silver and oxygen, aluminum and oxygen, or combinations thereof.

[0166] Example 26 includes the subject matter of any of Examples 20-25, and may be further specified that the first die includes a bridge die.

[0167] Example 27 may include the subject matter of any of the examples 20-26, and may further specify that some of the second dies include a central processing unit (CPU), a graphics processing unit (GPU), an input / output (I / O) block, or a system-on-a-chip (SoC) die, and that some of the second dies include a high-bandwidth memory die.

[0168] Example 28 may include the subject matter of any of the examples 20-26, and may further specify that some of the second dies have a first thickness, and some of the second dies have a second thickness greater than the first thickness.

[0169] Example 29 may include the subject of Example 28, and may also include: a spacer located on some second cores having a first thickness and surrounded by a second insulating material.

[0170] Example 30 may include the subject matter of any of Examples 20-29 and may further specify that: the first die includes a third surface and an opposite fourth surface, wherein the RDL is a second RDL including a second conductive path located at the fourth surface of the first die, and the microelectronic assembly may further include: a first RDL including a first conductive path located at the third surface of the first die, and a packaging substrate electrically coupled to the first conductive path in the first RDL, wherein the surface area of ​​the packaging substrate is 2500 square millimeters (mm²). 2 ) and 14400mm 2 between.

[0171] Example 31 may include the subject of Example 30, and may also include: a heat sink located on a second insulating material surrounding the second die.

[0172] Example 32 may include the subject of Example 31, and may also include a thermal interface material (TIM) located between the heat sink and the second insulating material.

[0173] Example 33 is a microelectronic component comprising: a first redistribution layer (RDL) including a first conductive path; a first layer located on the first RDL, the first layer including a first die located in a first insulating material; a second RDL located on the first layer, the second RDL including a second conductive path; and a second layer located on the second RDL, the second layer including a second die having a first thickness and a third die having a second thickness different from the first thickness, wherein the second die and the third die are located in a second insulating material, wherein the second die and the third die have a first surface and an opposite second surface, and the first surface of the second die and the third die has a thickness of 3000 square millimeters (mm²). 2 ) and 9000mm 2 The combined surface area between them, and wherein the first die is electrically coupled to the second die and the third die through a second conductive path through the second RDL and through an interconnect.

[0174] Example 34 may include the subject of Example 33 and may further specify that the interconnect includes solder.

[0175] Example 35 may include the subject matter of Example 34 and may further specify that: the first die includes a third surface and an opposite fourth surface, and the microelectronic assembly may also include: an underfill material located between the fourth surface of the first die and the second RDL and surrounding the interconnect, wherein the underfill material has an inverted trapezoidal shape.

[0176] Example 36 may include the subject of Example 33 and may further specify that the interconnection includes metal-metal bonding and dielectric-dielectric bonding.

[0177] Example 37 may include the subject of any of the examples 33-36, and may further specify that the spacing of the interconnect is between 1 micrometer and 75 micrometers.

[0178] Example 38 may include the subject matter of any of the examples 33-37, and may further specify that the first layer also includes a conductive post that passes through the first insulating material and is electrically coupled to the second die via a second conductive path.

[0179] Example 39 may include the subject matter of any of the examples 33-38, and may further specify that the first insulating material or the second insulating material comprises conductive particles in a molding material, a resin material or an epoxy resin material.

[0180] Example 40 may include the subject of Example 39 and may further specify that the conductive particles include silver and oxygen, aluminum and oxygen, or combinations thereof.

[0181] Example 41 may include the subject of any of the examples in Examples 33-40, and may further specify that the first die includes a bridge die.

[0182] Example 42 may include the subject matter of any of the examples in Examples 33-41, and may further specify that the second die includes a central processing unit (CPU), a graphics processing unit (GPU), an input / output (I / O) block, or a system-on-a-chip (SoC) die, and the third die includes a high-bandwidth memory (HBM) die.

[0183] Example 43 may include the subject matter of any of the examples 33-42, and may further specify that the equivalent silicon content of the second and third dies is greater than 3000 square millimeters (mm²). 2 ).

[0184] Example 44 may include the subject matter of any of the examples 33-42, and may further specify that the equivalent silicon content of the second and third dies is greater than 5500 square millimeters (mm²). 2 ).

[0185] Example 45 may include the subject of any of the examples 33-44, and may also include: a spacer on the second die in the second layer.

[0186] Example 46 may include the subject matter of any of Examples 33-45, and may further include: a packaging substrate electrically coupled to a first conductive path in a first RDL, wherein the surface area of ​​the packaging substrate is 2500 square millimeters (mm²). 2 ) and 14400mm 2 between.

[0187] Example 47 may include the subject of Example 46, and may also include a heat sink located on the second layer.

[0188] Example 48 may include the subject of Example 47, and may also include a thermal interface material (TIM) located between the heat sink and the second layer.

Claims

1. A microelectronic component, comprising: A packaging substrate having a top side above a bottom side; A first redistribution layer (RDL) is coupled to the top side of the packaging substrate via a first interconnect; An underfill material is located between the first RDL and the packaging substrate and surrounds the first interconnect; A first die, a second die, and a third die are located on the first RDL. The second die is laterally located between the first die and the third die and is spaced apart from the first die and the third die. The first die and the third die have through-silicon vias (TSVs). A first insulating material surrounds the first core, the second core, and the third core; A conductive post is located in the first insulating material. The conductive post is laterally spaced from the first core, the second core, and the third core. The conductive post has a vertical thickness that is the same as the vertical thickness of the first insulating material. The second RDL is located on the first insulating material, on the first die, the second die and the third die and coupled to the first die, the second die and the third die, and on the conductive post and coupled to the conductive post, and the second RDL is coupled to the first RDL through the conductive post; A first high-bandwidth memory (HBM) is vertically positioned on the first die and coupled to the second RDL via a second interconnect; A first graphics processing unit (GPU) die, the first GPU die being vertically positioned above the first die and the second die and coupled to the second RDL via a third interconnect, the first GPU die being laterally spaced from the first HBM; The second GPU die is vertically located above the second die and the third die and coupled to the second RDL via a fourth interconnect. The second GPU die is laterally spaced from the first GPU die. The second HBM is vertically located above the third die and coupled to the second RDL via a fifth interconnect, and the second HBM is laterally spaced from the second GPU die; as well as A second insulating material is located between the first HBM and the second RDL, between the first GPU die and the second RDL, between the second GPU die and the second RDL, and between the second HBM and the second RDL, with the second insulating material along the sides of the first HBM, the first GPU die, the second GPU die, and the second HBM.

2. The microelectronic component according to claim 1, wherein, Each of the first die, the second die, and the third die has a vertical thickness less than the vertical thickness of the first insulating material.

3. The microelectronic component according to claim 1, wherein, The first die and the third die are located on the first RDL.

4. The microelectronic component according to claim 1, wherein, The second insulating material is located on the top of the first GPU die and on the top of the second GPU die.

5. The microelectronic component according to claim 1, wherein, The first GPU die has a top surface that is at the same level as the top surface of the second GPU die.

6. The microelectronic component according to claim 5, wherein, The top surface of the first GPU die is at a different level from the top surface of the first HBM, and the top surface of the second GPU die is at a different level from the top surface of the second HBM.

7. The microelectronic component according to claim 1, wherein, The first subset of the conductive posts is laterally located between the first die and the second die, and the second subset of the conductive posts is laterally located between the second die and the third die.

8. A microelectronic component, comprising: A packaging substrate having a top side above a bottom side; A first redistribution layer (RDL) is coupled to the top side of the packaging substrate via a first interconnect; A first insulating material is located between the first RDL and the packaging substrate and surrounds the first interconnect; A first die, a second die, and a third die are located on the first RDL. The second die is laterally located between and spaced apart from the first die and the third die. The first die and the third die have through-silicon vias (TSVs). A second insulating material surrounds the first core, the second core, and the third core; A conductive post is located in the second insulating material. The conductive post is laterally spaced from the first core, the second core, and the third core. The conductive post has the same vertical thickness as the second insulating material. The second RDL is located on the second insulating material, on the first die, the second die and the third die and coupled to the first die, the second die and the third die, and on the conductive post and coupled to the conductive post, and the second RDL is coupled to the first RDL through the conductive post; A first memory die, the first memory die being vertically positioned above the first die and coupled to the second RDL via a second interconnect; A first graphics processing unit (GPU) die, which is vertically positioned above the first die and the second die and coupled to the second RDL via a third interconnect, the first GPU die being laterally spaced from the first memory die; The second GPU die is vertically located above the second die and the third die and coupled to the second RDL via a fourth interconnect. The second GPU die is laterally spaced from the first GPU die. The second memory die is vertically positioned above the third die and coupled to the second RDL via a fifth interconnect, and the second memory die is laterally spaced from the second GPU die. as well as A third insulating material is located between the first memory die and the second RDL, between the first GPU die and the second RDL, between the second GPU die and the second RDL, and between the second memory die and the second RDL, with the third insulating material along the side of the first memory die, the first GPU die, the second GPU die, and the second memory die.

9. The microelectronic component according to claim 8, wherein, Each of the first die, the second die, and the third die has a vertical thickness less than the vertical thickness of the first insulating material.

10. The microelectronic component according to claim 8, wherein, The first die and the third die are located on the first RDL.

11. The microelectronic component according to claim 8, wherein, The third insulating material is located on top of the first GPU die and on top of the second GPU die.

12. The microelectronic component according to claim 8, wherein, The first GPU die has a top surface at the same level as the top surface of the second GPU die, wherein the top surface of the first GPU die is at a different level from the top surface of the first memory die, and the top surface of the second GPU die is at a different level from the top surface of the second memory die.

13. The microelectronic component according to claim 8, wherein, The first subset of the conductive posts is laterally located between the first die and the second die, and the second subset of the conductive posts is laterally located between the second die and the third die.

14. A method for manufacturing a microelectronic component, the method comprising: A packaging substrate having a top side above the bottom side is provided; A first redistribution layer (RDL) is formed on the top side of the packaging substrate via a first interconnect. An underfill material is formed between the first RDL and the packaging substrate and around the first interconnect; A first die, a second die, and a third die are provided on top of the first RDL, the second die being laterally located between and spaced apart from the first die and the third die, and the first die and the third die having through-silicon vias (TSVs). A first insulating material is formed around the first core, the second core, and the third core; Conductive pillars are formed in the first insulating material, the conductive pillars being laterally spaced from the first die, the second die, and the third die, and the conductive pillars having the same vertical thickness as the first insulating material; A second RDL is formed on the first insulating material, the second RDL is located on and coupled to the first die, the second die and the third die, and the second RDL is located on and coupled to the conductive post, and the second RDL is coupled to the first RDL through the conductive post; A first high-bandwidth memory (HBM) is provided, which is vertically located on the first die and coupled to the second RDL via a second interconnect; A first graphics processing unit (GPU) die is provided, which is vertically located above the first die and the second die and coupled to the second RDL via a third interconnect, the first GPU die being laterally spaced from the first HBM; A second GPU die is provided, which is vertically positioned above the second die and the third die and coupled to the second RDL via a fourth interconnect, the second GPU die being laterally spaced from the first GPU die; A second HBM is provided, which is vertically positioned above the third die and coupled to the second RDL via a fifth interconnect, the second HBM being laterally spaced from the second GPU die; as well as A second insulating material is formed between the first HBM and the second RDL, between the first GPU die and the second RDL, between the second GPU die and the second RDL, and between the second HBM and the second RDL, the second insulating material being along the side of the first HBM, the first GPU die, the second GPU die, and the second HBM.

15. The method according to claim 14, wherein, Each of the first die, the second die, and the third die has a vertical thickness less than the vertical thickness of the first insulating material.

16. The method of claim 14, wherein, The first die and the third die are located on the first RDL.

17. The method of claim 14, wherein, The second insulating material is located on the top of the first GPU die and on the top of the second GPU die.

18. The method according to claim 14, wherein, The first GPU die has a top surface that is at the same level as the top surface of the second GPU die.

19. The method according to claim 18, wherein, The top surface of the first GPU die is at a different level from the top surface of the first HBM, and the top surface of the second GPU die is at a different level from the top surface of the second HBM.

20. The method of claim 14, wherein, The first subset of the conductive posts is laterally located between the first die and the second die, and the second subset of the conductive posts is laterally located between the second die and the third die.

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