Mim capacitor structure and manufacturing method thereof
Patent Information
- Application Number
- CN202510525806.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-24
- Publication Date
- 2026-10-27
AI Technical Summary
但是这种MIM电容结构的漏电(Leakage)较大，严重影响了MIM电容结构的性能及稳定性
[0023]如上所述，本发明的MIM电容结构及其制作方法通过于形成第二极板层之前，形成预设厚度的待处理层，待处理层的材质与第二极板层的材质相同且覆盖介质层的上表面，并将待处理层转变成第二缓冲层，改善了第二极板层与介质层之间的接触界面，减小了MIM电容的漏电，提升了MIM电容的性能及可靠性，具有高度产业利用价值。
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Figure CN122995165A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a MIM capacitor structure and its fabrication method. Background Technology
[0002] With the development of wireless communication technology, the frequencies used in communication equipment are increasing, placing higher demands on radio frequency (RF) systems. To obtain powerful RF systems, high-performance decoupling and filtering capacitors used in system-on-a-chip (SoC) circuits are typically embedded into the copper interconnect terminals of integrated circuits. This requires the embedded capacitors to have high capacitance density and precisely controllable voltage values. Therefore, metal-insulator-metal (MIM) capacitors are usually introduced in the back-end processes of integrated circuits. ZAZ (ZrO2 layer-Al2O3 layer-ZrO2 layer) composite materials, due to their high capacitance density, are often used as the dielectric material between the plates of MIM capacitor structures in RF systems, such as... Figure 1 The diagram shows a schematic of a MIM capacitor structure, including a substrate 01, an insulating layer 011, a TiN lower electrode layer 012, a TiO layer 013, a ZAZ dielectric layer 014, and a TiN upper electrode layer 015. This type of MIM capacitor structure typically forms a TiO layer directly through an oxidation process after the TiN lower electrode layer is formed, followed by the sequential formation of the ZAZ dielectric layer and the TiN upper electrode layer on top of the TiO layer. However, this type of MIM capacitor structure exhibits significant leakage, severely impacting its performance and stability.
[0003] Therefore, there is an urgent need to find a method for fabricating MIM capacitor structures that can reduce leakage current. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a MIM capacitor structure and its manufacturing method to solve the problem of large leakage current in the prior art MIM capacitor structure.
[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a MIM capacitor structure, comprising the following steps:
[0006] A semiconductor structure is provided in which a first electrode layer, a first buffer layer and a dielectric layer are sequentially stacked on the upper surface, and a layer to be processed of a predetermined thickness is formed on the upper surface of the dielectric layer;
[0007] The layer to be processed is processed to transform it into a second buffer layer;
[0008] A second electrode layer is formed on the upper surface of the second buffer layer.
[0009] Optionally, the semiconductor structure further includes a substrate, with the first electrode layer located on the upper surface of the substrate.
[0010] Optionally, forming the layer to be processed includes the following steps:
[0011] A precursor material layer is formed on the upper surface of the dielectric layer;
[0012] The precursor material layer is thinned to a preset thickness to obtain the layer to be processed.
[0013] Optionally, the method for thinning the precursor material layer includes wet etching.
[0014] Optionally, the precursor material layer is subjected to wet etching, and the etching solution used to treat the precursor material layer includes SC1 solution, H2O2 solution, and acid solution.
[0015] Optionally, the range of the preset thickness is: Alternatively, the material of the layer to be processed may be the same as the material of the second electrode layer.
[0016] Optionally, the method for processing the layer to be processed includes oxidation.
[0017] Optionally, the method for oxidizing the layer to be treated includes oxidizing liquid treatment and oxygen treatment.
[0018] The present invention also provides a MIM capacitor structure, comprising:
[0019] A semiconductor structure, the upper surface layer comprising a first electrode layer, a first buffer layer and a dielectric layer stacked sequentially;
[0020] The second buffer layer is located on the upper surface of the medium layer;
[0021] The second electrode layer is located on the upper surface of the second buffer layer.
[0022] Optionally, the material of the first buffer layer is the same as the material of the second buffer layer.
[0023] As described above, the MIM capacitor structure and its manufacturing method of the present invention improve the contact interface between the second electrode layer and the dielectric layer by forming a pre-thickness treatment layer before forming the second electrode layer. The material of the treatment layer is the same as that of the second electrode layer and covers the upper surface of the dielectric layer, and the treatment layer is transformed into a second buffer layer. This reduces the leakage current of the MIM capacitor, improves the performance and reliability of the MIM capacitor, and has high industrial application value. Attached Figure Description
[0024] Figure 1 The diagram shown is a cross-sectional view of a MIM capacitor structure.
[0025] Figure 2 The diagram shows the process flow of the method for manufacturing the MIM capacitor structure of the present invention.
[0026] Figure 3 The diagram shows a cross-sectional view of the semiconductor structure used in the fabrication method of the MIM capacitor structure of the present invention.
[0027] Figure 4 The diagram shows a cross-sectional structure after the formation of the precursor material layer in the method for fabricating the MIM capacitor structure of the present invention.
[0028] Figure 5 The diagram shows a cross-sectional structure after the formation of the layer to be processed, which is a method for fabricating the MIM capacitor structure of the present invention.
[0029] Figure 6 The diagram shows a cross-sectional structure after the layer to be processed is transformed into a second buffer layer, which is a method for manufacturing the MIM capacitor structure of the present invention.
[0030] Figure 7 The diagram shows a cross-sectional view of the MIM capacitor structure fabrication method of the present invention after the formation of the second electrode layer.
[0031] Explanation of icon numbers
[0032] 01 Substrate
[0033] 011 Insulation layer
[0034] 012 TiN lower electrode layer
[0035] 013 TiO layer
[0036] 014 ZAZ dielectric layer
[0037] 015 TiN upper electrode layer
[0038] 1. Semiconductor Structure
[0039] 11. Isolation Structure
[0040] 12 First electrode layer
[0041] 13 First Buffer Layer
[0042] 14. Dielectric layer
[0043] 15 Layers to be processed
[0044] 16 Second Buffer Layer
[0045] 17 Second electrode layer
[0046] 18 Precursor Material Layers Detailed Implementation
[0047] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0048] Please see Figures 2 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0049] Example 1
[0050] This embodiment provides a method for fabricating a MIM capacitor structure, such as... Figure 1 The diagram shown is a process flow chart of the fabrication method of the MIM capacitor structure, including the following steps:
[0051] S1: Provide a semiconductor structure with a first electrode layer, a first buffer layer and a dielectric layer stacked sequentially on the upper surface, and form a layer to be processed of a predetermined thickness on the upper surface of the dielectric layer;
[0052] S2: Process the layer to be processed to transform it into a second buffer layer;
[0053] S3: A second electrode layer is formed on the upper surface of the second buffer layer.
[0054] Please see Figures 3 to 5 Step S1: Provide a semiconductor structure 1 with a first electrode layer 12, a first buffer layer 13 and a dielectric layer 14 stacked sequentially on the upper surface, and form a processing layer 15 of a predetermined thickness on the upper surface of the dielectric layer 14.
[0055] As an example, such as Figure 3 The diagram shows a cross-sectional view of semiconductor structure 1. Semiconductor structure 1 also includes a substrate, with the first electrode layer 12 located on the upper surface of the substrate.
[0056] Specifically, the substrate is the process platform for fabricating the first electrode layer 12, in which one or more electronic devices such as semiconductor devices, resistors, and inductors are typically formed. While ensuring the quality of the first electrode layer 12, the thickness, size, and shape of the substrate can be selected according to the actual situation.
[0057] It should be noted that when electronic devices are formed in the substrate, an isolation structure 11 is usually formed between the substrate and the first electrode layer 12 to isolate the subsequently fabricated MIM capacitor structure from the electronic devices below it.
[0058] Specifically, the isolation structure 11 can be a single-layer insulation layer or a multi-layer composite insulation layer, and its specific thickness can be selected according to the actual situation.
[0059] It should be noted that the upper surface of the isolation structure 11 typically needs to have good adhesion to the first electrode layer 12. Therefore, the material of the upper surface layer of the isolation structure 11 needs to be selected according to the material of the first electrode layer 12. Preferably, a SiN layer and a PEOX (plasma-enhanced oxide) layer stacked sequentially are used as the isolation structure 11.
[0060] Specifically, the material of the first electrode layer 12 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials. Preferably, a titanium nitride layer is used as the first electrode layer 12.
[0061] It should be noted that the first buffer layer 13 is usually used to improve the contact interface between the first electrode layer 12 and the subsequently formed dielectric layer 14. After the first electrode layer 12 is formed by magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition or other suitable methods, the upper surface layer of the first electrode layer 12 is transformed into the first buffer layer 13 by an oxidation process.
[0062] Specifically, the dielectric layer 14 can be a single-layer high-k dielectric layer or a multi-layer composite high-k dielectric layer, and its material includes zirconium oxide (ZrO2), hafnium oxide (HfO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), titanium oxide (TiO2), hafnium silicate (HfSiO4), or other suitable high-k dielectric materials. Preferably, a zirconium oxide layer, an aluminum oxide layer, and a zirconium oxide layer stacked sequentially are used as the dielectric layer.
[0063] As an example, forming the layer to be processed 15 includes the following steps: forming a precursor material layer 18 on the upper surface of the dielectric layer 14; thinning the precursor material layer 18 to a preset thickness to obtain the layer to be processed 15.
[0064] Specifically, such as Figure 4 The diagram shown is a cross-sectional view of the structure after the formation of the precursor material layer 18. The methods for forming the precursor material layer 18 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
[0065] Specifically, the precursor material layer 18 may be made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum or other suitable conductive materials.
[0066] As an example, such as Figure 5 The diagram shown is a cross-sectional view of the structure after the formation of the layer 15 to be processed. The method for thinning the precursor material layer 18 includes wet etching or other suitable methods.
[0067] As an example, the precursor material layer 18 is processed by wet etching. The etching solution used to process the precursor material layer 18 includes SC1 solution (a mixture of ammonium hydroxide, hydrogen peroxide, and water), H2O2 solution, acid solution, or other suitable solutions for etching the precursor material layer 18.
[0068] It should be noted that during the thinning process, the process conditions need to be adjusted to thin the precursor material layer 18 slowly and uniformly. The thinning time of the precursor material layer 18 is related to the concentration of the etching solution, the processing temperature, the type of etching solution, and the material of the precursor material layer 18. These conditions can be selected according to the actual situation.
[0069] As an example, the preset thickness range is: That is, the thickness range of the layer 15 to be processed is For example, it could be
[0070] It should be noted that when the deposition equipment can directly control the thickness of the deposited precursor material layer 18, it is within the range specified in the original text. The precursor material layer 18 obtained by deposition can also be directly used as the layer to be processed 15, which can save the step of thinning the precursor material layer 18.
[0071] Please see Figures 6 to 7 Steps S2 and S3 are performed: the layer to be processed 15 is processed to transform the layer to be processed 15 into the second buffer layer 16; a second electrode layer 17 is formed on the upper surface of the second buffer layer 16.
[0072] As an example, such as Figure 6 The diagram shown is a cross-sectional view of the structure after the layer to be treated 15 is transformed into the second buffer layer 16. The methods for treating the layer to be treated 15 include oxidation treatment or other suitable methods.
[0073] Specifically, by making the thickness of the layer to be treated 15 thinner, it is easier to completely transform the layer to be treated 15 into the second buffer layer 16 during the treatment process, that is, to completely oxidize the layer to be treated 15 into the second buffer layer 16, providing a good process platform for the subsequent formation of the second electrode layer 17, while improving the contact interface between the dielectric layer 14 and the second electrode layer 17, and improving the quality of the second electrode layer 17.
[0074] As an example, the method for oxidizing the layer 15 to be treated includes oxidizing liquid treatment, oxygen treatment, or other suitable methods. Oxidizing liquid treatment here refers to completely transforming the layer 15 to be treated into an oxide layer using an oxidizing liquid. Preferably, an oxygen treatment process is used to completely oxidize the layer 15 to be treated into a second buffer layer 16.
[0075] Specifically, the methods for forming the second electrode layer 17 include magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.
[0076] As an example, the material of the layer to be processed 15 is the same as the material of the second electrode layer 17.
[0077] Specifically, by making the material of the layer to be treated 15 the same as that of the second electrode layer 17, so that the second buffer layer 16 is an oxide of the material in the second electrode layer 17, it is equivalent to achieving oxidation treatment on the lower surface of the second electrode layer 17, improving the interface between the second electrode layer 17 and the dielectric layer 14, and improving the leakage performance of the fabricated MIM capacitor.
[0078] Specifically, such as Figure 7 The diagram shows a cross-sectional view of the second electrode layer 17 after its formation. The material of the second electrode layer 17 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials. Preferably, a titanium nitride layer is used as the second electrode layer 17.
[0079] Specifically, after forming the dielectric layer 14, a processing layer 15 of a predetermined thickness and the same material as the second electrode layer 17 is formed on the upper surface of the dielectric layer 14. Then, the processing layer 15 is transformed into a second buffer layer 16, which improves the contact interface between the second electrode layer 17 and the dielectric layer 14, thereby reducing the leakage current of the MIM capacitor structure and improving the performance of the MIM capacitor structure.
[0080] The method for manufacturing the MIM capacitor structure in this embodiment improves the manufacturing process of the MIM capacitor structure. Before forming the second electrode layer 17, a processing layer 15 of a predetermined thickness and the same material as the second electrode layer 17 is formed on the upper surface of the dielectric layer 14. The processing layer 15 is then transformed into a second buffer layer 16. By forming a thinner second buffer layer 16 on the upper surface of the dielectric layer 14, the contact interface between the second electrode layer 17 and the dielectric layer 14 is improved, the leakage current of the MIM capacitor structure is reduced, and the performance and reliability of the MIM capacitor structure are improved.
[0081] Example 2
[0082] This embodiment also provides a MIM capacitor structure, such as Figure 7 The diagram shown is a cross-sectional view of the MIM capacitor structure. The MIM capacitor structure includes a semiconductor structure 1, a second buffer layer 16, and a second electrode layer 17. The upper surface of the semiconductor structure 1 includes a first electrode layer 12, a first buffer layer 13, and a dielectric layer 14 stacked sequentially. The second buffer layer 16 is located on the upper surface of the dielectric layer 14. The second electrode layer 17 is located on the upper surface of the second buffer insulating layer.
[0083] Specifically, the semiconductor structure 1 also includes a substrate and an isolation structure 11 for isolating the substrate from the first electrode layer 12. The first electrode layer 12 is located on the upper surface of the substrate, and electronic devices that work in conjunction with the MIM capacitor are usually formed in the substrate.
[0084] Specifically, while ensuring the performance of the MIM capacitor structure, the shape, size and thickness of the first electrode layer 12 can be selected according to the actual situation.
[0085] Specifically, while ensuring the performance of the MIM capacitor structure, the thickness of the first buffer layer 13 can be selected according to the actual situation. Preferably, the thickness range of the first buffer layer 13 is [insert range here]. For example, it could be
[0086] Specifically, while ensuring the performance of the MIM capacitor structure, the thickness of the dielectric layer 14 can be selected according to the actual situation.
[0087] Specifically, the thickness range of the second buffer layer 16 is... For example, it could be
[0088] It should be noted that by controlling the thickness of the second buffer layer 16 to within The second buffer layer 16 introduced between the dielectric layer 14 and the second electrode layer 17 can avoid affecting the performance of the capacitor structure.
[0089] As an example, the first buffer layer 13 and the second buffer layer 16 are made of the same material.
[0090] It should be noted that, while ensuring the improvement of the contact interface between the second electrode layer 17 and the dielectric layer 14, the material of the second buffer layer 16 may also be different from that of the first buffer layer 13.
[0091] Specifically, while ensuring the performance of the MIM capacitor structure, the thickness of the second electrode layer 17 can be selected according to the actual situation.
[0092] Specifically, by providing a second buffer layer 16 between the dielectric layer 14 and the second electrode layer 17, the contact interface between the second electrode layer 17 and the dielectric layer 14 is improved, thereby reducing leakage current in the MIM capacitor structure and enhancing its performance.
[0093] In this embodiment, the MIM capacitor structure improves the contact interface between the second electrode layer 17 and the dielectric layer 14 by providing a second buffer layer 16 between the dielectric layer 14 and the second electrode layer 17, thereby reducing leakage current and improving the performance of the MIM capacitor structure.
[0094] In summary, the MIM capacitor structure and its manufacturing method of the present invention improve the manufacturing process of the MIM capacitor structure by forming a pre-defined thickness layer covering the upper surface of the dielectric layer before forming the second electrode layer. The material of the layer to be processed is the same as that of the second electrode layer. This layer is then transformed into a second buffer layer, which improves the contact interface between the second electrode layer and the dielectric layer, reduces leakage current in the MIM capacitor structure, and enhances its performance and reliability. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.
[0095] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a MIM capacitor structure, characterized in that, Includes the following steps: A semiconductor structure is provided in which a first electrode layer, a first buffer layer and a dielectric layer are sequentially stacked on the upper surface, and a layer to be processed of a predetermined thickness is formed on the upper surface of the dielectric layer; The layer to be processed is processed to transform it into a second buffer layer; A second electrode layer is formed on the upper surface of the second buffer layer.
2. The method for fabricating the MIM capacitor structure according to claim 1, characterized in that: The semiconductor structure also includes a substrate, with the first electrode layer located on the upper surface of the substrate.
3. The method for fabricating the MIM capacitor structure according to claim 1, characterized in that, Forming the layer to be processed includes the following steps: A precursor material layer is formed on the upper surface of the dielectric layer; The precursor material layer is thinned to a preset thickness to obtain the layer to be processed.
4. The method for fabricating the MIM capacitor structure according to claim 3, characterized in that: The method for thinning the precursor material layer includes wet etching.
5. The method for fabricating the MIM capacitor structure according to claim 4, characterized in that: The precursor material layer is treated by wet etching, and the etching solution used to treat the precursor material layer includes SC1 solution, H2O2 solution, and acid solution.
6. The method for fabricating the MIM capacitor structure according to claim 1, characterized in that: The range of the preset thickness is: Alternatively, the material of the layer to be processed may be the same as the material of the second electrode layer.
7. The method for fabricating a MIM capacitor structure according to claim 1, characterized in that: The method for processing the layer to be processed includes oxidation treatment.
8. The method for fabricating a MIM capacitor structure according to claim 7, characterized in that: The methods for oxidizing the layer to be treated include oxidizing liquid treatment and oxygen treatment.
9. A MIM capacitor structure, characterized in that, include: A semiconductor structure, the upper surface layer comprising a first electrode layer, a first buffer layer and a dielectric layer stacked sequentially; The second buffer layer is located on the upper surface of the medium layer; The second electrode layer is located on the upper surface of the second buffer layer.
10. The MIM capacitor structure according to claim 9, characterized in that: The material of the first buffer layer is the same as that of the second buffer layer.