Deep trench capacitor and method of fabrication

Abstract

The application provides a deep trench capacitor and a preparation method thereof, which comprises the following steps: S21, etching a partial thickness of a substrate to form a trench; S22, depositing a polymer on the inner wall of the trench and removing the polymer from the bottom of the trench; S23, etching a partial substrate from the exposed bottom wall of the trench to deepen the trench; S24, performing M stages and recycling steps S22-S23 N times in each stage to obtain a deepened trench as a deep trench; by controlling the process parameters of depositing the polymer and / or the process parameters of etching the substrate in the stage process, the opening width of the trench obtained in each stage is controlled, so that the final deep trench has multiple shrinkage sections in the extension direction; and S3, sequentially depositing an oxide and polycrystalline silicon into the deep trench to form a dielectric layer covering the inner wall of the deep trench and the surface of the substrate and polycrystalline silicon located in the deep trench and covering the surface of the dielectric layer, respectively, and the polycrystalline silicon forms a closed structure at the shrinkage section of the deep trench.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a deep trench capacitor and its fabrication method. Background Technology

[0002] Deep trench capacitors (DTCs) offer advantages such as small size, high integration, excellent high-frequency response, and good temperature stability, making them promising for applications in radio frequency, decoupling, and ultra-wideband fields. Please refer to [link / reference]. Figure 1 A typical deep trench capacitor uses a half-substrate 101 as one electrode plate. A trench is formed in the substrate 101, followed by conformal deposition of a thin dielectric layer 102 on the inner walls and bottom of the trench. Finally, the trench is filled with a conductive material, such as polysilicon 103, to form the other electrode plate of the capacitor. The capacitor is then led out through contact holes 104 (CT) and a top metal layer 105 located above and connected to the contact holes 104. Before forming the contact holes 104, an interlayer dielectric layer 106 is formed on the substrate surface. However, when using polysilicon 103 to fill the trench in a deep trench capacitor, the deep trench causes significant stress in the polysilicon 103 after filling, leading to poor wafer warpage, affecting wafer fabrication, and even causing product scrap.

[0003] Please refer to Figure 2 In order to reduce the impact of polysilicon 103 stress on wafer warpage, existing technologies can adopt a method of not filling the trench with polysilicon 103. After covering the interlayer dielectric layer 106, an air gap 107 is formed in the polysilicon 103 of the trench. This can significantly reduce the stress of polysilicon 103 and improve the wafer warpage.

[0004] However, since some products are primarily 1P1M products with only one top metal layer 105, the structure beneath the top metal layer 105 is more susceptible to stress from wire bonding during pad fabrication. Because the air gap 107, used to mitigate stress, extends almost the entire length of the polysilicon 103 within the trench, its presence makes the structure at this point relatively weak. Therefore, during end-customer wire bonding, wire bonding stress may cause structural breakage on either side of the air gap 107, for example... Figure 3 This results in a loss of product yield, which is approximately 10% to 20%. Summary of the Invention

[0005] The purpose of this invention is to provide a deep trench capacitor and its manufacturing method, which can reduce the area of ​​weak structures and reduce the probability of weak structure breakage caused by wire bonding stress, thereby reducing the loss of product yield.

[0006] To achieve the above objectives, the present invention provides a method for fabricating a deep trench capacitor, comprising:

[0007] S1: Provides a substrate;

[0008] S2: A plurality of deep trenches are formed in the substrate at intervals, the deep trenches being perpendicular to the surface of the substrate and extending into the substrate, the opening width of the trenches being set along the arrangement direction, and the method for forming each of the deep trenches including:

[0009] S21: Etching a portion of the substrate thickness from the substrate surface to form trenches;

[0010] S22: Deposit polymer on the inner wall of the trench, remove polymer from the bottom of the trench, and expose the bottom wall of the trench;

[0011] S23: Etch a portion of the substrate starting from the exposed bottom wall of the trench to deepen the trench;

[0012] S24: Execute M stages and repeat steps S22 to S23 N times within each stage to obtain a deepened trench as a deep trench. The opening width of the trench obtained in each stage is controlled by controlling the process parameters of polymer deposition and / or substrate etching in each stage, so that the final deep trench has multiple contraction points in the extension direction. M is an integer greater than or equal to 3, N is an integer greater than or equal to 1, and N may have the same or different values ​​in the M stages.

[0013] S3: Deposit oxide and fill polysilicon sequentially into the deep trench to form a dielectric layer covering the inner wall of the deep trench and the surface of the substrate, and polysilicon located in the deep trench and covering the surface of the dielectric layer, respectively. The polysilicon forms a closed structure at the end of the deep trench.

[0014] S4: An interlayer dielectric layer is formed on the polysilicon, and two or more air gaps are formed inside the polysilicon and between the polysilicon and the interlayer dielectric layer along the direction of the deep trench.

[0015] S5: A top metal layer is formed on the interlayer dielectric layer, and the top metal layer is connected to the polysilicon through contact holes.

[0016] Optionally, in the method for fabricating the deep trench capacitor,

[0017] A patterned hard mask layer is formed on the substrate;

[0018] The substrate is etched with a patterned hard mask layer to form a plurality of spaced deep trenches within the substrate;

[0019] Remove the patterned hard mask layer.

[0020] Optionally, in the method for fabricating the deep trench capacitor, the method for forming the patterned hard mask layer includes:

[0021] A hard mask layer and a patterned photoresist layer are formed on the substrate;

[0022] A patterned photoresist layer is used as an etching mask to etch a hard mask layer to form a patterned hard mask layer.

[0023] Optionally, in the method for fabricating the deep trench capacitor, the material of the patterned hard mask layer includes silicon oxide, silicon nitride, or ONO.

[0024] Optionally, in the method for fabricating the deep trench capacitor, the dielectric layer includes a high-k dielectric layer.

[0025] Optionally, in the method for preparing the deep trench capacitor, the deep trench is greater than 10 μm.

[0026] Optionally, in the method for fabricating the deep trench capacitor, in step S24, when the number of stages is even, a first operation method and / or a second operation method are selected to be implemented relative to the processes of the preceding and following stages, so that the opening of the trench formed when the number of stages is even is smaller than the opening of the trench formed by the processes of the preceding and following stages. The first operation method is to increase the deposition time, deposition gas pressure, source power and / or deposition gas flow rate; the second operation method is to decrease the etching time, etching gas pressure, source power and / or etching gas flow rate.

[0027] Optionally, in the method for fabricating the deep trench capacitor, the deposition gas is C4F8 and the etching gas is SF6.

[0028] Optionally, in the deep trench capacitor fabrication method, in step S24, the parameter changes of the process before and after the previous stages are linear in each of the N cycles.

[0029] This invention also provides a method for preparing a deep trench capacitor, comprising:

[0030] Substrate;

[0031] A plurality of deep trenches are formed in the substrate at intervals. The deep trenches are perpendicular to the surface of the substrate and extend into the substrate. The opening width of the trenches is set along the arrangement direction. Each deep trench has multiple constriction points in the extension direction.

[0032] A dielectric layer covering the inner wall of the deep trench and the surface of the substrate, respectively, and polycrystalline silicon located inside the deep trench and covering the surface of the dielectric layer;

[0033] An interlayer dielectric layer is located on the polysilicon, and two or more air gaps are formed inside the polysilicon and between the polysilicon and the interlayer dielectric layer along the direction of the deep trench.

[0034] A top metal layer is located on the interlayer dielectric layer, and the top metal layer is connected to the polysilicon through contact holes.

[0035] In the deep trench capacitor and its fabrication method provided by this invention, the deep trench etching process is divided into multiple segments. By controlling the parameters of each segment, the morphology of the deep trench is controlled, resulting in two or more contraction points in the extension direction of the deep trench. After depositing polycrystalline silicon, two or more air gaps are formed in the extension direction of the deep trench, thereby strengthening the structure on both sides of the deep trench, reducing the area of ​​weak structures, and thus reducing the probability of weak structure fracture caused by wire bonding stress, ultimately reducing product yield loss. Furthermore, the air gaps are retained to ensure their effect on improving wafer warpage. Attached Figure Description

[0036] Figures 1 to 3 This is a schematic diagram of the structure of a deep trench capacitor in the prior art;

[0037] Figure 4 This is a flowchart of a method for preparing a deep trench capacitor according to an embodiment of the present invention;

[0038] Figures 5 to 9 This is a schematic diagram of the structure during the fabrication process of the deep trench capacitor according to Embodiment 1 of the present invention;

[0039] Figure 10 This is a schematic diagram of the structure during the fabrication process of the deep trench capacitor according to Embodiment 2 of the present invention;

[0040] In the diagram: 101-substrate, 102-dielectric layer, 103-polysilicon, 104-contact hole, 105-top metal layer, 106-interlayer dielectric layer, 107-air gap, 201-substrate, 202-patterned photoresist layer, 203-patterned hard mask layer, 204-deep trench, 205-dielectric layer, 206-polysilicon, 207-closed structure, 208-interlayer dielectric layer, 209-air gap, 210-top metal layer, 211-contact hole, 301-substrate, 305-dielectric layer, 306-polysilicon, 307-closed structure, 308-interlayer dielectric layer, 309-air gap, 310-top metal layer, 311-contact hole. Detailed Implementation

[0041] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0042] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.

[0043] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.

[0044] Please refer to Figure 4 This invention provides a method for fabricating a deep trench capacitor, comprising:

[0045] S1: Provides a substrate;

[0046] S2: A plurality of deep trenches are formed in the substrate at intervals. The deep trenches are perpendicular to the surface of the substrate and extend into the substrate. The opening width of the trenches is set along the arrangement direction. The method for forming each deep trench includes:

[0047] S21: Etching a portion of the substrate thickness from the substrate surface to form trenches;

[0048] S22: Deposit polymer on the inner wall of the trench, remove polymer from the bottom of the trench, and expose the bottom wall of the trench;

[0049] S23: Etch a portion of the substrate starting from the bottom wall of the exposed trench to deepen the trench;

[0050] S24: Execute M stages and repeat steps S22 to S23 N times within each stage to obtain a deepened trench as a deep trench. The opening width of the trench obtained in each stage is controlled by controlling the process parameters of polymer deposition and / or substrate etching in each stage, so that the final deep trench has multiple contraction points in the extension direction. M is an integer greater than or equal to 3, N is an integer greater than or equal to 1, and N may have the same or different values ​​in the M stages.

[0051] S3: Oxide and polysilicon are deposited sequentially into the deep trench to form a dielectric layer covering the inner wall of the deep trench and the surface of the substrate, and polysilicon located in the deep trench and on the surface of the dielectric layer. The polysilicon forms a closed structure at the end of the deep trench.

[0052] S4: An interlayer dielectric layer is formed on polysilicon, and two or more air gaps are formed inside the polysilicon and between the polysilicon and the interlayer dielectric layer along the direction of the deep trench.

[0053] S5: A top metal layer is formed on the interlayer dielectric layer, and the top metal layer is connected to the polysilicon through contact holes.

[0054] Example 1

[0055] Please refer to Figure 5 First, a substrate 201 is provided. The substrate 201 can be a silicon substrate. A hard mask layer is deposited on the surface of the substrate 201 using processes such as CVD. The material of the hard mask layer can be an oxide, nitride, or ONO structure. A patterned photoresist layer 202 is formed by photolithography. Using the patterned photoresist layer 202 as an etching mask, a patterned hard mask layer 203 is formed by etching.

[0056] Please refer to Figure 6 The patterned photoresist layer 202 is removed, and a patterned hard mask layer 203 is used as an etching mask to form a plurality of spaced deep trenches 204 in the substrate. The deep trenches 204 are perpendicular to the surface of the substrate 201 and extend into the substrate 201. The opening width of the trenches is set along the arrangement direction, and the depth of the deep trenches 204 is greater than 10 μm, for example, 30 μm. The method for forming each deep trench includes:

[0057] S21: Etching a portion of the substrate thickness from the substrate surface to form trenches;

[0058] S22: Deposit polymer on the inner wall of the trench, remove polymer from the bottom of the trench, and expose the bottom wall of the trench;

[0059] S23: Etch a portion of the substrate starting from the bottom wall of the exposed trench to deepen the trench;

[0060] S24: Execute M stages and repeat steps S22 to S23 N times within each stage to obtain a deepened trench as a deep trench. The opening width of the trench obtained in each stage is controlled by controlling the process parameters of polymer deposition and / or substrate etching in each stage, so that the final deep trench has multiple contraction points in the extension direction. M is an integer greater than or equal to 3, N is an integer greater than or equal to 1, and N may have the same or different values ​​in the M stages.

[0061] Taking M=3 as an example, the process is divided into three stages: Stage 1, Stage 2, and Stage 3. In Stage 2, compared to Stages 1 and 3, the first and / or second operation methods are selected to ensure that the opening of the trench formed when the stage number is even is smaller than the opening of the trench formed in the preceding and following stages. The first operation method involves increasing deposition time, deposition gas pressure, source power, and / or deposition gas flow rate; the second operation method involves decreasing etching time, etching gas pressure, source power, and / or etching gas flow rate. This causes the trench morphology to form a contraction in Stage 2, i.e., CD2 < CD1 & CD3, where CD2 is the opening width of the trench formed in Stage 2, CD1 is the opening width of the trench formed in Stage 1, and CD3 is the opening width of the trench formed in Stage 3. Specifically, please refer to Table 1, which is divided into three stages, each with three steps: polymer deposition (dep), etching the polymer at the bottom of the trench (p-etch), and etching the substrate to form the trench (etch). In this embodiment, the second stage involves performing two operations simultaneously. The deposition time in the second stage is increased from 2.0 s in the first stage to 2.1 s, and then decreased to 2.0 s in the third stage. The deposition gas pressure is increased from 50 mT to 55 mT, and then decreased to 50 mT in the third stage. The source power is increased from 3000 W to 3100 W, and then decreased to 3000 W in the third stage. The flow rate of the etching gas C4F8 is increased from 300 sccm to 310 sccm, and then decreased to 300 sccm in the third stage. The etching step time is reduced from 2.0 s to 1.8 s, and then increased again in the third stage. Because the etching difficulty increases with the depth of the trench, the time in the third stage is increased to 3 s. The etching gas pressure is reduced from 50 mT to 45 mT, and then increased to 50 mT in the third stage. The source power was reduced from 3100W to 2900W, and then increased back to 3100W in the third stage. The bias power was reduced from 80W to 75W, and then increased back to 80W in the third stage. The flow rate of the SF6 etching gas was reduced from 600 sccm to 500 sccm, and then increased back to 650 sccm in the third stage. Each stage involved 30 cycles of dep-p-etch-etch, allowing the parameters to change uniformly with each cycle, gradually increasing or decreasing. For example, if the etching time in the second stage decreased from 2s to 1.8s, it could be reduced by 0.2 / 30s each time over 30 cycles. In other embodiments of the invention, N can take other values, and the value of N can vary in each stage.

[0062] Table 1

[0063] Next, please refer to Figure 7 Oxide and polysilicon are sequentially deposited into the deep trench 204 to form a dielectric layer 205 covering the inner wall of the deep trench 204 and the surface of the substrate 201, respectively, and a polysilicon layer 206 located within the deep trench 204 and covering the surface of the dielectric layer 205. The polysilicon layer 206 forms a closed structure 207 at the end of the deep trench 204 (marked by the dashed box in the figure). The dielectric layer 205 includes a high-k dielectric layer, such as silicon oxide, silicon nitride, an ONO layer, or a stacked layer of HfO2 and Al2O3.

[0064] Please refer to Figure 8 An interlayer dielectric layer 208 is formed on polysilicon 206, and two or more air gaps 209 are formed inside polysilicon 206 and between polysilicon 206 and interlayer dielectric layer 208 along the deep trench extension direction.

[0065] Please refer to Figure 9 A top metal layer 210 is formed on the interlayer dielectric layer 208, and the top metal layer 210 is connected to the polysilicon 206 through contact holes 211. Finally, wire bonding is performed on the top metal layer 210 to form a pad.

[0066] Example 2

[0067] Taking M as an example, the process is divided into five stages: Stage 1, Stage 2, Stage 3, Stage 4, and Stage 5. For Stage 2 compared to Stages 1 and 3, and for Stage 4 compared to Stages 3 and 5, the first and / or second operation methods can be selected to ensure that the opening of the trench formed when the stage number is even is smaller than the opening of the trench formed in the preceding and following stages. The first operation method is to increase the deposition time, deposition gas pressure, source power, and / or deposition gas flow rate; the second operation method is to decrease the etching time, etching gas pressure, source power, and / or etching gas flow rate. The trench morphology is designed to create contraction zones in both the second and fourth etching stages, i.e., CD2 < CD1 & CD3, CD4 < CD3 & CD5. CD2 represents the opening width of the trench formed in the second etching stage, CD1 in the first etching stage, CD3 in the third etching stage, CD4 in the fourth etching stage, and CD5 in the fifth etching stage. The final structure is as follows: Figure 10In Example 2, polysilicon 306 forms two closed structures 307, and three air gaps 309 are formed between it and the interlayer dielectric layer 307. Compared with Example 1, more closed structures and air gaps are formed, achieving the same function. The formation steps, relative positions, and functions of the substrate 301, dielectric layer 305, top metal layer 308, and contact hole 311 in Example 2 are the same as in Example 1, and will not be described again in Example 2.

[0068] Using the methods in Examples 1 and 2, the etching of the entire deep trench is divided into multiple stages. After introducing a closing stage, the CD of the closing stage is made smaller than that of other stages. Subsequently, during polysilicon filling, a pre-sealed closed structure is formed at the closing position. This structure provides lateral support to the deep trench, strengthens the internal structure, and prevents breakage caused by wire bonding stress, thereby improving product yield. At the same time, most of the air gaps are retained, ensuring the air gaps' effect on improving wafer warpage.

[0069] This invention also provides a deep trench capacitor fabricated using a method for fabricating deep trench capacitors, comprising: a substrate; a plurality of spaced deep trenches formed in the substrate, the deep trenches being perpendicular to the surface of the substrate and extending into the substrate, the opening width of the trenches being set along the arrangement direction, and each deep trench having multiple constriction sections in the extension direction; a dielectric layer covering the inner wall of the deep trenches and the surface of the substrate respectively; and polysilicon located in the deep trenches and on the surface of the dielectric layer; an interlayer dielectric layer located on the polysilicon, with two or more air gaps formed inside the polysilicon and between the polysilicon and the interlayer dielectric layer along the extension direction of the deep trenches; and a top metal layer located on the interlayer dielectric layer, the top metal layer being connected to the polysilicon through contact holes.

[0070] In summary, in the deep trench capacitor and its fabrication method provided in this invention, the deep trench etching process is divided into multiple segments. By controlling the parameters of each segment, the morphology of the deep trench is controlled, resulting in two or more contraction points in the trench's extension direction. After polysilicon deposition, two or more air gaps are formed in the trench's extension direction, thereby strengthening the structure on both sides of the trench, reducing the area of ​​weak structures, and thus reducing the probability of weak structure fracture caused by wire bonding stress, ultimately reducing product yield loss. Furthermore, the air gaps are retained, ensuring their effectiveness in improving wafer warpage.

[0071] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for fabricating a deep trench capacitor, characterized in that, include: S1: Provides a substrate; S2: A plurality of deep trenches are formed in the substrate at intervals, the deep trenches being perpendicular to the surface of the substrate and extending into the substrate, the opening width of the trenches being set along the arrangement direction, and the method for forming each of the deep trenches including: S21: Etching a portion of the substrate thickness from the substrate surface to form trenches; S22: Deposit polymer on the inner wall of the trench, remove polymer from the bottom of the trench, and expose the bottom wall of the trench; S23: Etch a portion of the substrate starting from the exposed bottom wall of the trench to deepen the trench; S24: Execute M stages and repeat steps S22 to S23 N times within each stage to obtain a deepened trench as a deep trench. The opening width of the trench obtained in each stage is controlled by controlling the process parameters of polymer deposition and / or substrate etching in each stage, so that the final deep trench has multiple contraction points in the extension direction. M is an integer greater than or equal to 3, N is an integer greater than or equal to 1, and N may have the same or different values ​​in the M stages. S3: Oxide and polysilicon are sequentially deposited into the deep trench to form a dielectric layer covering the inner wall of the deep trench and the surface of the substrate, and polysilicon located in the deep trench and covering the surface of the dielectric layer, respectively. The polysilicon forms a closed structure at the end of the deep trench. S4: An interlayer dielectric layer is formed on the polysilicon, and two or more air gaps are formed inside the polysilicon and between the polysilicon and the interlayer dielectric layer along the direction of the deep trench. S5: A top metal layer is formed on the interlayer dielectric layer, and the top metal layer is connected to the polysilicon through contact holes.

2. The method for preparing a deep trench capacitor as described in claim 1, characterized in that, A patterned hard mask layer is formed on the substrate; The substrate is etched with a patterned hard mask layer to form a plurality of spaced deep trenches within the substrate; Remove the patterned hard mask layer.

3. The method for preparing a deep trench capacitor as described in claim 2, characterized in that, Methods for forming patterned hard mask layers include: A hard mask layer and a patterned photoresist layer are formed on the substrate; A patterned photoresist layer is used as an etching mask to etch a hard mask layer to form a patterned hard mask layer.

4. The method for preparing a deep trench capacitor as described in claim 2, characterized in that, The materials for patterned hard mask layers include silicon oxide, silicon nitride, or ONO.

5. The method for preparing a deep trench capacitor as described in claim 1, characterized in that, The dielectric layer includes a high-k dielectric layer.

6. The method for preparing a deep trench capacitor as described in claim 1, characterized in that, The deep trench is greater than 10 μm.

7. The method for preparing a deep trench capacitor as described in claim 1, characterized in that, In step S24, when the number of stages is even, the first operation method and / or the second operation method are selected and implemented relative to the processes of the preceding and following stages, so that the opening of the trench formed when the number of stages is even is smaller than the opening of the trench formed by the processes of the preceding and following stages. The first operation method is to increase the deposition time, deposition gas pressure, source power and / or deposition gas flow rate; the second operation method is to decrease the etching time, etching gas pressure, source power and / or etching gas flow rate.

8. The method for preparing a deep trench capacitor as described in claim 7, characterized in that, The deposition gas is C4F8, and the etching gas is SF6.

9. The method for preparing a deep trench capacitor as described in claim 7, characterized in that, In step S24, the parameter changes of the process before and after the previous stage are linear in each of the N cycles.

10. A deep trench capacitor prepared using the method for preparing a deep trench capacitor according to any one of claims 1 to 9, characterized in that, include: Substrate; A plurality of deep trenches are formed in the substrate at intervals. The deep trenches are perpendicular to the surface of the substrate and extend into the substrate. The opening width of the trenches is set along the arrangement direction. Each deep trench has multiple constriction points in the extension direction. A dielectric layer covering the inner wall of the deep trench and the surface of the substrate, respectively, and polycrystalline silicon located inside the deep trench and covering the surface of the dielectric layer; An interlayer dielectric layer is located on the polysilicon, and two or more air gaps are formed inside the polysilicon and between the polysilicon and the interlayer dielectric layer along the direction of the deep trench. A top metal layer is located on the interlayer dielectric layer, and the top metal layer is connected to the polysilicon through contact holes.

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