A low-arc-discharge high-voltage capacitor device and a preparation method thereof

Abstract

The application relates to a low-arc-discharge high-voltage capacitor device and a preparation method thereof. The preparation method comprises the following steps: providing an initial wafer, a silicon oxide-silicon nitride-silicon oxide composite three-layer insulating stack is formed above a wafer back surface substrate of the initial wafer; performing selective wet etching treatment on the back surface of the wafer, the complete three-layer insulating stack on the back surface is completely stripped through etching, and the etching is terminated on a polysilicon film surface layer of the back surface; the wafer is lifted from a device bearing table surface as a whole through a supporting member, and the wafer with the back surface subjected to medium stripping is subjected to a suspended plasma ashing treatment, and residual photoresist and etching-derived by-products on the wafer surface are removed. The application solves the problem of local electric field distortion caused by charge accumulation, the electrostatic chuck current is completely smooth without fluctuation, the arc discharge occurrence rate is reduced to zero, the yield is greatly improved, and the particle pollution is reduced; and the method does not change the front process parameters and is completely compatible with the existing process, so that the transformation cost is low and mass production is easy.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a low-arc discharge high-voltage capacitor and its fabrication method. Background Technology

[0002] High-voltage capacitors are critical passive components in high-voltage applications such as power semiconductors and RF modules, and their manufacturing yield directly impacts system performance and cost. High-voltage capacitors typically employ a multi-layer stacked structure, containing multiple alternating layers of metal electrodes and dielectric layers, forming a complex metal-dielectric interface at the wafer edge. While pursuing high capacitance density and miniaturization, this structure also introduces a vulnerability sensitive to plasma processes. Arc discharge is a common and serious defect in plasma etching processes, referring to a localized high-current-density discharge phenomenon formed on the wafer surface due to the violent release of charge in a plasma environment. Macroscopically, it manifests as the melting of metal circuitry; microscopically, it exhibits characteristic charred or worm-like morphologies, and is one of the main causes of direct product scrap and cavity particle contamination. In pad etching processes, high RF power and DC bias are necessary to maintain etching rate and anisotropy, but they also directly exacerbate plasma instability.

[0003] Existing technologies primarily address arcing issues by optimizing etching formulations, reducing power consumption, increasing gas flushing during multi-step etching, and eliminating photoresist edge washing. While these methods can reduce the arcing rate from a high level to around one percent, monitoring of machine parameters during mass production reveals frequent fluctuations in the electrostatic chuck current. This indicates that the discharge of charge generated during the process is obstructed, leading to the accumulation of electron shells on the wafer surface, causing localized electric field distortion, and thus maintaining the risk of arcing. In particular, the wafer edges remain high-risk areas for arcing due to factors such as low geometric curvature, concentrated electric field, uneven plasma distribution, and the lack of effective charge discharge pathways caused by back-side dielectric insulation. Existing improvement solutions only address the symptoms by focusing on the front-side process, failing to solve the fundamental problem of the charge discharge pathway. Summary of the Invention

[0004] Therefore, it is necessary to provide a low-arc discharge high-voltage capacitor and its manufacturing method to address the above-mentioned technical problems.

[0005] In a first aspect, this application discloses a method for manufacturing a low-arc discharge high-voltage capacitor, the method comprising the following steps:

[0006] An initial wafer is provided, wherein a silicon oxide-silicon nitride-silicon oxide composite three-layer insulating stack is formed on the back side substrate of the initial wafer;

[0007] Selective wet etching is performed on the back side of the wafer to completely remove the complete silicon oxide-silicon nitride-silicon oxide composite three-layer insulating stack on the back side. The etching ends at the polysilicon film surface on the back side.

[0008] The wafer is lifted off the equipment platform by the support components, and the wafer with the back dielectric stripped is subjected to suspended plasma ashing treatment to remove residual photoresist and etching by-products from the wafer surface.

[0009] The ashing wafers are subjected to overall tank cleaning, and the exposed polysilicon surface on the back is simultaneously passivated for protection.

[0010] During the etching process, the static charge accumulated on the wafer surface is conducted from the exposed polysilicon on the back side to the electrostatic chuck of the equipment for removal.

[0011] Furthermore, the silicon oxide-silicon nitride-silicon oxide composite three-layer insulating stack consists of a top silicon dioxide oxide layer with a thickness of 200 angstroms, an intermediate silicon nitride layer with a thickness of 300 angstroms, and a bottom silicon dioxide oxide layer with a thickness of 600 angstroms, forming a sandwich capacitor structure to bind static charge in the initial state.

[0012] Furthermore, the selective wet etching process on the back side of the wafer includes using a wet etching solution containing hydrofluoric acid to selectively wet etch the back side of the wafer, whereby the hydrofluoric acid wet etching utilizes its high selectivity characteristics.

[0013] The etching rate of the hydrofluoric acid on silicon dioxide and silicon nitride is higher than that on polycrystalline silicon and monocrystalline silicon.

[0014] Furthermore, the etching time for selective wet etching of the back side of the wafer using a wet etching solution containing hydrofluoric acid is 180 seconds.

[0015] Furthermore, the concentration of the hydrofluoric acid is 49%.

[0016] Furthermore, the process of removing the entire wafer from the equipment's support platform using a support member employs a lifting pin method.

[0017] On the other hand, this application also discloses a low-arc discharge high-voltage capacitor device, including a high-voltage capacitor stack structure on the front side of the device and a semiconductor substrate. The back dielectric layer of the semiconductor substrate is completely removed to expose a polysilicon layer on the back side of the substrate. The polysilicon layer serves as a charge release path to release surface-accumulated charges during the etching process and suppress arc discharge.

[0018] Furthermore, the front side of the capacitor is a high-voltage capacitor structure composed of multiple alternating stacked metal electrodes and ceramic dielectric layers.

[0019] The aforementioned low-arc discharge high-voltage capacitor and its fabrication method achieve the following beneficial effects: By adding a back-side cleaning process before pad etching, the back-side dielectric layer is removed to expose the polysilicon, creating a low-resistance charge discharge path. This allows the charge generated during etching to be smoothly released through the electrostatic chuck, solving the problem of local electric field distortion caused by charge accumulation. The electrostatic chuck current remains completely stable without fluctuations, reducing the arc discharge rate to zero, significantly improving product yield, and reducing cavity particle contamination. Simultaneously, the use of a pin-lifting adhesive removal process avoids high-temperature oxidation damage to the polysilicon on the back-side, ensuring device reliability. The entire method only adds a back-side cleaning process without changing the front-side etching parameters, making it fully compatible with existing processes, with low modification costs and easy mass production implementation. Attached Figure Description

[0020] Figure 1 This is a schematic flowchart of a method for preparing a low-arc discharge high-voltage capacitor device in one embodiment;

[0021] Figure 2 This is a process flow diagram of the fabrication process of a low-arc discharge high-voltage capacitor device in one embodiment;

[0022] Figure 3 This is a schematic diagram illustrating the process of removing the backside oxygen-nitrogen-oxygen stack by different etching techniques in one embodiment. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0024] In existing technologies, integrated circuit products utilize furnace tube technology for sidewall dielectric growth. This furnace tube process is comprehensive, forming sidewalls not only on the front of the device but also depositing a dielectric film layer on the back of the wafer, typically a three-layer stacked structure of silicon oxide-silicon nitride-silicon oxide. This dielectric film covers the polycrystalline silicon backing, making the backing insulated. During high-power plasma processes such as pad etching, the charge accumulated on the wafer surface cannot be effectively conducted to the electrostatic chuck for discharge through the insulated backing. Instead, it accumulates on the surface, forming an electron shell, causing localized electric field distortion. This is particularly pronounced at the wafer edges, where the electric field concentration increases. When the electric field strength exceeds the breakdown threshold, arcing occurs.

[0025] In one embodiment, such as Figure 1 and Figure 2 As shown, a method for manufacturing a low-arc discharge high-voltage capacitor is disclosed, which includes the following steps:

[0026] S1: Provide an initial wafer, wherein a silicon oxide-silicon nitride-silicon oxide composite three-layer insulating stack is formed above the back substrate of the initial wafer;

[0027] S2: Selective wet etching is performed on the back side of the wafer to completely remove the complete silicon oxide-silicon nitride-silicon oxide composite three-layer insulating stack on the back side through etching. The etching ends at the polysilicon film surface on the back side.

[0028] S3: The wafer is lifted off the equipment platform by the support components, and the wafer with the back side dielectric stripped is subjected to suspended plasma ashing treatment to remove residual photoresist and etching by-products on the wafer surface.

[0029] S4: Perform a tank-type overall cleaning on the ashing wafer and simultaneously perform surface passivation protection on the exposed polysilicon surface on the back side.

[0030] S5: During the etching process, the static charge accumulated on the wafer surface is conducted from the exposed polysilicon on the back side to the electrostatic chuck of the equipment for removal.

[0031] This embodiment adds a special back-side processing step before the traditional pad etching process. The back-side three-layer dielectric is completely removed by hydrofluoric acid wet etching with specific parameters to expose the polysilicon. Combined with the push-pin lifting plasma ashing to protect the polysilicon, a stable charge discharge path is constructed before normal front-side pad etching is performed.

[0032] In step S1 of this example, the wafer is in its initial feeding state. This step is the initial feeding stage of the process. At this time, the wafer has completed all front-side device manufacturing processes and officially enters the back-side processing flow. No back-side etching or cleaning operations have been performed yet. At this time, the wafer is divided into the front-side device functional surface and the back-side non-device surface. The front side, stacked from top to bottom, consists of a passivation layer, a second top-layer metal interconnect layer, all front-side active device functional layers, and a single-crystal silicon substrate. All functional film layers on the front side have been prepared without any damage. The back side, stacked from the outside to the inside, consists of a 2,000 angstrom thick polycrystalline silicon layer, an oxy-nitrogen-oxygen (ONO) stacked capacitor structure, and a single-crystal silicon substrate. The ONO stacked capacitor structure, from the outside to the inside, consists of a top silicon dioxide oxide layer, a 300 angstrom thick intermediate silicon nitride layer, and a 600 angstrom thick bottom silicon dioxide layer. The back side retains the original ONO stacked structure from the factory. In this initial state, the oxygen-nitrogen-oxygen stack on the back side is a sandwich capacitor structure, which will bind the static charge accumulated inside the wafer, easily causing electrostatic accumulation and discharge breakdown risk. It is also the target film layer that needs to be completely removed in this process.

[0033] In step S2 of this example, a high-concentration hydrofluoric acid wet etching process is used to remove the oxygen-nitrogen-oxygen stack on the back side. This step employs a 49% (w / w) concentrated hydrofluoric acid solution as the etchant. The wafer is immersed back-side down in the etching tank for wet etching, with the etching time precisely controlled to 180 seconds. Immediately after etching, the wafer surface is repeatedly rinsed with high-purity deionized water to remove residual etching solution, followed by high-speed spin drying. This etching process utilizes the selective etching characteristics of hydrofluoric acid: hydrofluoric acid has an extremely high etching rate for silicon dioxide and silicon nitride materials, but an extremely low etching rate for polycrystalline silicon and monocrystalline silicon substrates, achieving highly selective removal of the target film layers. The entire etching process does not damage the front-side device structure or the back-side polycrystalline silicon layer. After etching, the wafer state is as follows: all films on the front side of the wafer remain unchanged, completely preserving the passivation layer, metal interconnect layer, and all active device functional layers; the oxygen-nitrogen-oxygen three-layer capacitor structure on the back side is completely etched and stripped away, leaving only a 2,000 angstrom thick polycrystalline silicon layer and monocrystalline silicon substrate. This etching process completely eliminated the charge-binding effect of the oxygen-nitrogen-oxygen stack, opening up a discharge path for charges within the wafer and significantly reducing the risk of electrostatic accumulation and discharge. For example... Figure 3 The process flow diagrams shown correspond to five different process conditions. The five images from left to right correspond to the five process verification processes in the table below. The table below shows the process of the fifth group, which corresponds to the preparation method of this embodiment. Under this method, the high-voltage capacitor device prepared is the qualified optimal process.

[0034] In step S3 of this example, a pin-lift plasma ashing process is employed. This step utilizes a plasma ashing machine with a pin-lift mounting mode. The wafer is placed face up, and the machine's pins lift and suspend the wafer, exposing the back polysilicon layer to a low-damage plasma chamber for ashing treatment. This thoroughly removes residual photoresist and etching byproducts from the surface. This pin-suspended support mode avoids direct contact between the back of the wafer and the high-temperature stage, allowing for precise control of the plasma's effective range and reaction atmosphere. This significantly reduces the probability of thermal and plasma oxidation of the polysilicon layer during plasma processing, preventing the formation of unnecessary oxide layers on the back polysilicon surface. Simultaneously, the pin-lift method effectively optimizes and homogenizes the plasma distribution at the wafer edges, completely avoiding damage to the polysilicon layer at the wafer edges caused by the plasma process. This is a long-standing but overlooked defect in traditional bonding-stage ashing processes.

[0035] In step S4 of this example, a dedicated cleaning process is performed. After plasma treatment, a semiconductor-specific alkaline cleaning solution is used to thoroughly clean the wafer in a tank to remove residual organic polymers, surface particles, and trace metal impurities from the plasma process. Simultaneously, the polysilicon surface is passivated. After cleaning, the back polysilicon layer remains free of oxidation and contamination, with a smooth and clean surface, providing a reliable guarantee for good ohmic contact with the electrostatic chuck.

[0036] In step S5 of this example, the front pad etching process is completed after the backside etching, ashing, and cleaning. At this point, the polysilicon on the backside is completely exposed without an oxide layer. When the wafer is held in place by the electrostatic chuck, the polysilicon forms a good ohmic contact with the chuck surface, creating a low-resistance charge discharge path from the wafer surface to the chuck. During the etching process, high-power plasma continuously injects charge into the wafer surface. Unlike existing technologies, this charge does not accumulate on the surface but is continuously and smoothly discharged to ground potential through the substrate-polysilicon-electrostatic chuck path. The wafer surface potential remains stable, preventing the formation of high electric field regions due to localized charge accumulation, thus fundamentally eliminating the conditions for arc triggering. Throughout the entire pad etching process, the current monitoring curve of the electrostatic chuck remains completely stable, without the frequent current spikes and abnormal fluctuations seen in existing technologies, verifying the complete solution to the charge accumulation problem from the perspective of machine parameters. After final etching, the arc discharge rate was reduced to zero, and no typical arc defects such as metal melting or worm-like discharge could be observed under a microscope.

[0037] In this embodiment, since arc discharge is essentially a process of instantaneous charge breakdown and release, when the charge accumulates to a certain level and the local electric field strength exceeds the breakdown field strength of the plasma or insulating layer, a momentary high-current discharge occurs, forming an arc. This embodiment provides a low-resistance discharge path, allowing charge to be generated and discharged simultaneously, never reaching the charge accumulation threshold that triggers an arc, thus fundamentally preventing arc discharge. This is fundamentally different from existing technologies that reduce charge generation by lowering etching power or increasing gas flushing: existing technologies "generate less charge," but the possibility of accumulation still exists, failing to completely solve the problem; this embodiment releases charge in a timely manner, preventing charge accumulation altogether, thus achieving a more thorough effect and reducing the arc rate to zero.

[0038] The method in this embodiment is fully compatible with existing pad etching processes. All process parameters for pad etching, including etching gas ratio, RF power, chamber pressure, etching time, and endpoint detection conditions, do not require any changes. Key indicators such as linewidth, sidewall morphology, and etching selectivity after etching are completely consistent with existing processes. This means that there is no need to develop new etching recipes or conduct extensive process verification. Only three steps need to be added before pad etching: backside hydrofluoric acid etching, pin ashing, and cleaning. These three steps are mature and routine processes in semiconductor manufacturing, resulting in extremely low process modification costs and minimal risk of implementation in mass production.

[0039] In this embodiment, the cost of adding a back-side processing step is very limited, while the benefits are significant. Arc discharge not only scraps individual wafers but also contaminates the machine cavity, leading to downtime for maintenance, and in severe cases, even affecting the yield of subsequent batches. Reducing the arc occurrence rate from one percent to zero directly improves product yield, reduces machine downtime for maintenance, and lowers cavity cleaning and component replacement costs, resulting in substantial overall economic benefits. Especially for high-voltage capacitors and other products prone to arcing, the method in this embodiment effectively solves the long-standing arcing problem plaguing production lines and has high practical value.

[0040] Furthermore, the method described in this embodiment is not only applicable to pad etching of high-voltage capacitor products, but also has broad reference value for other plasma processes that experience similar charge accumulation leading to arcing problems, such as via etching and metal etching. Any arcing problem caused by poor charge discharge due to back-side insulation can be resolved by removing the back-side dielectric layer to expose the polysilicon and then using appropriate polysilicon protection processes, demonstrating broad application prospects.

[0041] On the other hand, this embodiment also provides a high-voltage capacitor structure with low arc discharge. This high-voltage capacitor structure mainly includes a semiconductor substrate and a high-voltage capacitor stack structure formed on the front side of the substrate. The core improvement of this embodiment is that the three dielectric layers of silicon oxide-silicon nitride-silicon oxide on the back side of the semiconductor substrate are completely removed, exposing a polycrystalline silicon layer with a thickness of 2,000 angstroms on the back side as a dedicated charge release path. The surface of the polycrystalline silicon layer remains intact, with no dielectric residue, oxide layer, or contamination. During the etching process, the charge accumulated on the surface can be released in a timely manner, fundamentally suppressing the occurrence of arc discharge.

[0042] This embodiment includes the initial state of the completely removed back dielectric layer. These three dielectric layers, formed by the sidewall dielectric grown using a furnace tube process, extend to the back of the wafer. Initially, from the outside in, they are a top silicon dioxide oxide layer, a 300 angstrom thick intermediate silicon nitride layer, and a 600 angstrom thick bottom silicon dioxide oxide layer, completely covering the polycrystalline silicon back, forming a capacitor-like sandwich structure that restricts the movement of static charges within the wafer. This is a natural byproduct of the furnace tube sidewall process. The furnace tube process has excellent step coverage and full-surface film formation characteristics. While forming device sidewalls on the front side, the same film inevitably deposits on the back side. The front dielectric layer performs its intended function as a device sidewall after subsequent photolithography etching, while the back dielectric layer remains in subsequent processes, not only having no positive function but also becoming an insulating layer that hinders charge dissipation. This problem has long been overlooked by the industry. This embodiment specifically addresses this neglected back dielectric insulation problem, proposing a targeted structural improvement that is low-cost and highly effective.

[0043] This embodiment includes the contact characteristics after the polysilicon backing layer is completely exposed. The polysilicon layer is in close contact with the surface of the electrostatic chuck, forming a low-resistance ohmic contact and charge discharge path. The electrostatic chuck is a core component of the etching machine used to fix the wafer and provide temperature control. It is conductive and grounded or connected to a fixed potential. When the polysilicon backing layer is in close contact with the electrostatic chuck, the potential of the entire wafer substrate is stably clamped, preventing potential floating and charge accumulation. This low-resistance metal-semiconductor contact has a much stronger charge discharge capability than the existing technology that relies on weak leakage through the insulating layer or limited edge contact. It can promptly conduct away the continuously injected charge during the etching process, maintaining a stable wafer surface potential and preventing continuous charge accumulation.

[0044] This embodiment includes the pad structure and etching performance. After the pad etching process, a metal pad structure is formed on the front side of the device, which is used for subsequent wire bonding or bump fabrication. Pad etching is a high-power plasma process with a large charge injection volume in high-voltage capacitor manufacturing, and it is also the process with the highest incidence of arc discharge. With the crystal back structure of this embodiment, the current monitoring curve of the electrostatic chuck remains completely stable throughout the entire pad etching process, without the frequent current spikes and abnormal fluctuations seen in existing technologies. This indicates that charge discharge is very smooth, and there is no intermittent charge breakdown release. Because the charge accumulation problem is fundamentally solved, the incidence of etching arc discharge in the device is reduced to zero, and no typical arc defects such as metal melting or worm-like discharges can be observed under a microscope. Compared to existing technologies that can only reduce the arc rate to about one percent by optimizing the etching formula, this embodiment achieves complete elimination of arc defects. This not only avoids direct product scrapping caused by arcs, but also reduces metal spatter and cavity particle contamination generated when arcs occur, improving the overall batch yield. At the same time, it reduces the frequency of cleaning and maintenance of the machine cavity, reducing downtime for maintenance, and has significant economic benefits.

[0045] In this embodiment, the surface state of the polysilicon layer is included. The back polysilicon layer is treated with a pin-lift plasma ashing process, resulting in no surface oxide layer caused by high-temperature oxidation and no damage caused by edge plasma, leaving a smooth and clean surface. If a traditional bonding platform-type ashing process is used, the surface of the back polysilicon will be oxidized to form an insulating oxide layer during high-temperature adhesive removal. This oxide layer may be corroded in subsequent cleaning steps, leading to a rough or damaged polysilicon surface, affecting the contact effect with the electrostatic chuck. After using pin-lift ashing, the back polysilicon remains intact and smooth, without an oxide layer or plasma damage, ensuring the low-resistance characteristics of the charge discharge path.

[0046] This embodiment only processes the back side of the crystal; all structural and process parameters on the front side of the device remain unchanged. Key process parameters such as the stacked structure, etching rate, etching selectivity, and anisotropy of the high-voltage capacitor are unaffected. No new front-side process development is required, and there is no negative impact on the device's electrical performance. Key electrical parameters such as capacitance, withstand voltage, and leakage current remain at their original levels, fully meeting product specifications. This back-side processing characteristic gives the technical solution of this embodiment extremely high process compatibility and safety, without introducing new process risks. The product's electrical performance is completely consistent with products using traditional processes. This high-voltage capacitor is particularly suitable for high-voltage applications such as power semiconductors and RF modules. These applications have high requirements for capacitor withstand voltage and reliability, and are also sensitive to manufacturing costs. Adopting the structure of this embodiment can effectively reduce manufacturing costs and improve product reliability.

[0047] The device structure in this embodiment completely removes the three layers of insulating dielectric on the crystal back and uses the ashing of the ejector pins to protect the polycrystalline silicon, thus constructing a stable and effective low-resistance charge discharge path. This completely solves the arc discharge problem in the etching of high-voltage capacitor pads. The structure is simple, the modification cost is low, the compatibility is good, the effect is significant, and the performance is stable. It is a device structure improvement scheme that is very suitable for mass production and promotion.

[0048] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0049] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a low-arc discharge high-voltage capacitor, characterized in that, Includes the following steps: An initial wafer is provided, wherein a silicon oxide-silicon nitride-silicon oxide composite three-layer insulating stack is formed on the back substrate of the initial wafer; Selective wet etching is performed on the back side of the wafer to completely remove the complete silicon oxide-silicon nitride-silicon oxide composite three-layer insulating stack on the back side. The etching ends at the polysilicon film surface on the back side. The wafer is lifted off the equipment platform by the support components, and the wafer with the back dielectric stripped is subjected to suspended plasma ashing treatment to remove residual photoresist and etching by-products from the wafer surface. The ashing wafers are subjected to overall tank cleaning, and the exposed polysilicon surface on the back is simultaneously passivated for protection. During the etching process, the static charge accumulated on the wafer surface is conducted from the exposed polysilicon on the back side to the electrostatic chuck of the equipment for removal.

2. The method for preparing a low-arc discharge high-voltage capacitor according to claim 1, characterized in that, The silicon oxide-silicon nitride-silicon oxide composite three-layer insulating stack consists of a top silicon dioxide oxide layer with a thickness of 200 angstroms, a middle silicon nitride layer with a thickness of 300 angstroms, and a bottom silicon dioxide oxide layer with a thickness of 600 angstroms, forming a sandwich capacitor structure to bind static charge in the initial state.

3. The method for preparing a low-arc discharge high-voltage capacitor according to claim 1, characterized in that, The selective wet etching process on the back side of the wafer includes using a wet etching solution containing hydrofluoric acid to selectively wet etch the back side of the wafer. Hydrofluoric acid wet etching utilizes the high selectivity characteristic.

4. The method for preparing a low-arc discharge high-voltage capacitor according to claim 3, characterized in that, The etching rate of the hydrofluoric acid on silicon dioxide and silicon nitride is higher than that on polycrystalline silicon and monocrystalline silicon.

5. The method for preparing a low-arc discharge high-voltage capacitor according to claim 3, characterized in that, The etching time, which includes selective wet etching of the back side of the wafer using a wet etching solution containing hydrofluoric acid, is 180 seconds.

6. The method for preparing a low-arc discharge high-voltage capacitor according to claim 3, characterized in that, The concentration of the hydrofluoric acid is 49%.

7. The method for preparing a low-arc discharge high-voltage capacitor according to claim 1, characterized in that, The process of removing the adhesive by lifting the entire wafer off the support platform of the equipment using a support member employs a lifting pin method.

8. A low-arc discharge high-voltage capacitor, characterized in that, The capacitor is prepared by any one of the preparation methods of claims 1 to 7.

9. The low-arc discharge high-voltage capacitor according to claim 8, characterized in that, The front side of the capacitor device is a high-voltage capacitor structure composed of multiple alternating layers of metal electrodes and ceramic dielectric layers.

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