Gallium oxide PIN diode based on ion implantation reduction and preparation method
Patent Information
- Application Number
- CN202511143062.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-15
- Publication Date
- 2026-10-27
AI Technical Summary
[0004]本发明实施例提供了一种基于离子注入还原的氧化镓PIN二极管及制备方法，以解决p型掺杂氧化镓制备难度大，导致难以制备氧化镓PIN二极管的问题
[0015]本发明实施例提供一种基于离子注入还原的氧化镓PIN二极管及制备方法，通过将重掺杂n型氧化镓衬底作为N层，在重掺杂n型氧化镓衬底上制备I层，在I层上进行p型离子注入，并利用还原性气体高温退火激活注入离子实现p型掺杂，得到P层。还原性气体通过还原反应将氧化镓内的氧原子析出，使注入的p型离子占据氧的晶格格点，并夺取镓原子的电子，形成空穴，实现p型离子注入掺杂，降低p型掺杂氧化镓制备难度。再制备阴极电极、阳极电极，降低氧化镓PIN二极管的制备难度。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of gallium oxide device technology, and in particular to a gallium oxide PIN diode based on ion implantation reduction and its fabrication method. Background Technology
[0002] Semiconductor power devices are core components in power electronic systems, widely used in aerospace, communications, industrial control, renewable energy and new energy systems, electric vehicles, rail transportation, and other important fields. The performance of silicon-based power devices is limited by the theoretical limits of the material itself; their power density can no longer meet the application requirements of power supply and efficient drive under high-frequency, high-power, high-temperature, and extreme conditions. Gallium oxide (Ga2O3), as a rising star in semiconductor materials, has a wider bandgap and higher breakdown field strength compared to third-generation semiconductor materials SiC and GaN. Its Baliga figure of merit (BFOM) is more than 10 times that of SiC and more than 4 times that of GaN, demonstrating extremely broad and promising application potential in high-voltage, high-power, and high-efficiency fields. Furthermore, Ga2O3 single-crystal substrates can be grown using the same melt-growing method as silicon, offering a cost advantage over materials like SiC and GaN. Therefore, Ga2O3 is an ideal material for fabricating diodes, field-effect transistors, and other low-power, high-voltage switches and high-power applications.
[0003] PIN diodes exhibit low leakage current and high breakdown voltage under reverse bias, making them a crucial tool for realizing high-voltage power devices with wide applications in rectification, limiting, and switching. However, p-type doping of gallium oxide is challenging, hindering the realization of gallium oxide PIN diodes and preventing the full utilization of gallium oxide's advantages. Existing p-type doping methods include obtaining p-type N-doped gallium oxide thin films through GaN thermal oxidation. However, this method relies on the conversion of GaN into gallium oxide, limiting its operability and the formation of only thin gallium oxide films, making it difficult to achieve thicker films. Summary of the Invention
[0004] This invention provides a gallium oxide PIN diode based on ion implantation reduction and its fabrication method, to solve the problem that the fabrication of p-type doped gallium oxide is difficult, which makes it difficult to fabricate gallium oxide PIN diodes.
[0005] In a first aspect, embodiments of the present invention provide a method for fabricating a gallium oxide PIN diode based on ion implantation reduction, comprising: fabricating an I layer in a PIN junction on the upper surface of a heavily doped n-type gallium oxide substrate; performing p-type ion implantation on the upper surface of the I layer to obtain a P-type implanted layer; performing high-temperature thermal annealing on the P-type implanted layer in a reducing atmosphere to activate the implanted p-type ions, thereby fabricating a P layer in the PIN junction; fabricating a cathode electrode on the lower surface of the heavily doped n-type gallium oxide substrate; and fabricating an anode electrode on the upper surface of the P layer to obtain a gallium oxide PIN diode.
[0006] In one possible implementation, the step of performing high-temperature thermal annealing on the P-type implanted layer in a reducing atmosphere to activate the implanted p-type ions and prepare the P layer in the PIN junction includes: performing thermal annealing on the P-type implanted layer in a hydrogen or ammonia reducing atmosphere to activate the p-type ions in the P-type implanted layer; the reducing gas reacts with gallium oxide in the P-type implanted layer to precipitate O from the gallium oxide material, so that the p-type ions occupy the oxygen lattice points, thereby transforming the ion implantation region into p-type doped material and preparing the P layer in the PIN junction.
[0007] In one possible implementation, the step of fabricating the I layer in the PIN junction on the upper surface of the heavily doped n-type gallium oxide substrate includes: growing an insulating dielectric layer on the lower surface of the n-type gallium oxide substrate; thermally oxidizing the n-type gallium oxide substrate under the protection of the insulating dielectric layer to form the I layer in the PIN junction on the upper surface of the n-type gallium oxide substrate; and removing the insulating dielectric layer on the lower surface of the n-type gallium oxide substrate after thermal oxidation.
[0008] In one possible implementation, the p-type ion includes nitrogen ions or phosphorus ions.
[0009] In one possible implementation, the implantation depth and concentration are controlled by adjusting the ion implantation energy and dose range.
[0010] In one possible implementation, the ion implantation dose range is 1e. 12 up to 1e 14 cm -2 The ion implantation energy power range is 10 to 40 keV.
[0011] In one possible implementation, the p-type doping concentration is controlled by adjusting the annealing temperature, annealing time, and reducing gas flow rate.
[0012] In one possible implementation, the annealing temperature ranges from 800 to 1100°C, the time ranges from 1 to 30 minutes, and the reducing gas flow rate ranges from 100 to 500 sccm.
[0013] In one possible implementation, the cathode electrode is made of titanium gold; and the anode electrode is made of nickel gold.
[0014] In a second aspect, embodiments of the present invention provide a gallium oxide PIN diode based on ion implantation reduction, which is prepared based on a gallium oxide PIN diode preparation method based on ion implantation reduction as described in any possible implementation of the first aspect.
[0015] This invention provides a gallium oxide PIN diode based on ion implantation reduction and its fabrication method. The method involves using a heavily doped n-type gallium oxide substrate as the N-layer, fabricating an I-layer on the substrate, performing p-type ion implantation on the I-layer, and activating the implanted ions through high-temperature annealing with a reducing gas to achieve p-type doping, thus obtaining the P-layer. The reducing gas precipitates oxygen atoms from the gallium oxide through a reduction reaction, allowing the implanted p-type ions to occupy oxygen lattice sites and capture electrons from gallium atoms to form holes, achieving p-type ion implantation doping and reducing the difficulty of fabricating p-type doped gallium oxide. Cathode and anode electrodes are then fabricated, further reducing the fabrication difficulty of the gallium oxide PIN diode. Attached Figure Description
[0016] Figure 1 This is a flowchart illustrating the fabrication method of a gallium oxide PIN diode based on ion implantation reduction provided in an embodiment of the present invention.
[0017] Figure 2 This is a schematic diagram of the structure after the growth of the insulating dielectric layer provided in an embodiment of the present invention;
[0018] Figure 3 This is a schematic diagram of the structure after thermal oxidation provided in an embodiment of the present invention;
[0019] Figure 4 This is a schematic diagram of the structure after the preparation of layer I provided in an embodiment of the present invention;
[0020] Figure 5 This is a schematic diagram of the structure after ion implantation provided in an embodiment of the present invention;
[0021] Figure 6 This is a schematic diagram of the structure after the P layer is prepared according to an embodiment of the present invention;
[0022] Figure 7 This is a schematic diagram of the structure of the cathode electrode after fabrication according to an embodiment of the present invention;
[0023] Figure 8 This is a schematic diagram of the structure after the anode electrode is prepared according to an embodiment of the present invention. Detailed Implementation
[0024] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.
[0025] The term "comprising" and any other variations thereof in the specification, claims, and accompanying drawings of this invention mean "including but not limited to," and are intended to cover a non-exclusive inclusion, not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order.
[0026] The implementation of the present invention will be described in detail below with reference to the accompanying drawings:
[0027] Figure 1 This is a flowchart illustrating a method for fabricating a gallium oxide PIN diode based on ion implantation reduction, as provided in an embodiment of the present invention. (Refer to...) Figure 1 The preparation method includes:
[0028] Step 101: On the upper surface of the heavily doped n-type gallium oxide substrate 1, prepare the I layer 2 in the PIN junction;
[0029] For example, the heavily doped n-type gallium oxide substrate 1 is an n-type heavily doped β-Ga₂O₃ substrate. For instance, the doping concentration is greater than 1.0 × 10⁻⁶. 18 cm -3 As N + layer.
[0030] This step forms a high-resistivity intrinsic layer on a substrate with good conductivity, laying the foundation for the subsequent formation of the PIN junction. Layer I2 is the core functional layer of the PIN diode. A P layer will be fabricated on top of it, together with the heavily doped n-type substrate below (as the N layer), to form a complete three-layer PIN structure.
[0031] Gallium oxide materials have extremely high breakdown field strength. The I layer, as a low-doped high-resistivity region, is the main region in which the device withstands reverse voltage. Its thickness and quality directly determine the device's withstand voltage capability.
[0032] Since this application uses ion implantation reduction technology (the subsequent steps will achieve P-type doping through ion implantation), the I layer prepared here needs to have good crystal quality and surface flatness to ensure the uniformity of subsequent ion implantation and the doping activation effect.
[0033] The I-layer fabrication method in the following embodiments is achieved through a selective thermal oxidation process. The core idea is to use an insulating dielectric layer to protect the lower surface of the substrate, allowing only the upper surface to form a near-intrinsic I-layer through thermal oxidation. This simplifies the process and allows for precise control over the formation area of the I-layer.
[0034] In one possible implementation, fabricating the I layer in the PIN junction on the surface of a heavily doped n-type gallium oxide substrate includes:
[0035] Step 1011: An insulating dielectric layer is grown on the lower surface of the n-type gallium oxide substrate;
[0036] Figure 2 This is a schematic diagram of the structure after the growth of the insulating dielectric layer according to an embodiment of the present invention; see reference. Figure 2 It should be noted that the insulating dielectric layer serves to protect the lower surface of the substrate from subsequent thermal oxidation processes, maintaining its heavily doped n-type characteristics. The core function of the heavily doped n-type gallium oxide substrate is as the N-layer of the PIN junction, requiring high conductivity and providing carrier channels. If the lower surface is modified during thermal oxidation, its doping concentration may decrease, resistivity may increase, and the function of the N-layer may be compromised.
[0037] For example, the insulating dielectric layer can be SiO2, Al2O3, or Si3N4. For example, the growth method can be plasma-enhanced chemical vapor deposition (PECVD), electron beam evaporation, etc. The thickness is typically several hundred nanometers, sufficient to block oxygen diffusion. Using highly dense materials such as SiO2, Al2O3, or Si3N4 for the insulating dielectric layer can improve the protective effect.
[0038] Step 1012: Under the protection of the insulating dielectric layer, the n-type gallium oxide substrate is thermally oxidized to prepare the I layer of the PIN junction on the upper surface of the n-type gallium oxide substrate;
[0039] Figure 3 This is a schematic diagram of the structure after thermal oxidation provided in an embodiment of the present invention; see reference. Figure 3 This step involves thermally oxidizing the upper surface of the substrate to form a low-doped, near-intrinsic I layer.
[0040] For example, annealing is performed in an oxygen atmosphere, with a processing temperature between 500°C and 2200°C, and an annealing time greater than 1 minute. This thermal oxidation process significantly reduces the carrier concentration within a certain thickness on the front side of the β-Ga2O3 substrate, for example, to below 1.0 × 10⁻⁶. 15 cm -3 This forms a semi-insulated, high-resistance region, serving as the I layer in the PIN junction.
[0041] For example, by controlling the temperature and time of the thermal oxidation process, the thickness of the I layer and the carrier concentration can be controlled.
[0042] The principle of thermal oxidation of gallium oxide: In high temperature and an oxygen-containing atmosphere (such as O2), Ga2O3 on the substrate surface reacts with oxygen or adjusts the oxygen vacancy concentration in the crystal lattice through oxygen atom diffusion. Oxygen vacancies are the main n-type doping source in gallium oxide. The high conductivity of heavily doped n-type gallium oxide originates from a large number of oxygen vacancies. Thermal oxidation introduces excess oxygen, filling some of the oxygen vacancies, reducing the donor concentration, and transforming the upper surface region from heavily doped n-type to lightly doped near-intrinsic type, i.e., the I layer.
[0043] Because the lower surface is protected by an insulating dielectric layer, only the upper surface undergoes oxidation modification, achieving regional selective growth of the I layer and avoiding the deterioration of substrate conductivity caused by overall oxidation.
[0044] Step 1013: After thermal oxidation, remove the insulating dielectric layer on the lower surface of the n-type gallium oxide substrate.
[0045] For example, the SiO2 layer on the back side of the β-Ga2O3 substrate can be removed by dry etching or wet etching.
[0046] Figure 4 This is a schematic diagram of the structure after the preparation of layer I according to an embodiment of the present invention; see reference. Figure 4 The insulating dielectric layer only serves a protective function during the thermal oxidation stage and must be removed afterward. If residue remains, it will hinder ohmic contact between the lower surface and the metal electrode, leading to excessive contact resistance. The removal method can be selected based on the dielectric layer material using an etching process; for example, SiO2 can be etched using hydrofluoric acid (HF).
[0047] In this embodiment of the invention, the process employs a three-step method of protection-oxidation-deprotection, utilizing thermal oxidation to reduce the carrier concentration of gallium oxide and achieve an I-layer compatible with the n-type substrate, serving as the basis for subsequent P-layer fabrication and PIN junction formation.
[0048] Step 102: Perform p-type ion implantation on the upper surface of the I layer to obtain a p-type implanted layer;
[0049] Figure 5 This is a schematic diagram of the structure after ion implantation provided in an embodiment of the present invention; see reference. Figure 5 This step introduces p-type dopant elements into the near-intrinsic I-layer surface using ion implantation technology to form a p-type region with hole conductivity.
[0050] Ion implantation is a commonly used doping technique in semiconductor manufacturing. Its principle is as follows: In a high vacuum environment, the ions of p-type dopants are accelerated to a high-energy state, so that they can gain enough kinetic energy to penetrate the lattice on the surface of the I-layer and embed themselves into the crystal structure of gallium oxide. This transforms the implanted region from a near-intrinsic I-layer into a region with p-type conductivity, forming a p-type implanted layer.
[0051] For example, the p-type ion includes nitrogen ions or phosphorus ions.
[0052] In some embodiments, the implantation depth and concentration are controlled by adjusting the ion implantation energy and dose range. For example, the ion implantation dose range is 1e... 12 up to 1e 14 cm -2 The ion implantation energy power range is 10 to 40 keV.
[0053] Step 103: The P-type implanted layer is subjected to high-temperature thermal annealing in a reducing atmosphere to activate the implanted p-type ions and prepare the P layer 3 in the PIN junction.
[0054] Figure 6 This is a schematic diagram of the structure after the P layer is prepared according to an embodiment of the present invention; see reference. Figure 6 In some embodiments, high-temperature thermal annealing is performed in a reducing atmosphere such as H2 or NH3 to react with β-Ga2O3 and precipitate O, allowing N and P ions to occupy oxygen vacancies and achieve p-type doping, which serves as the P layer in the PIN junction.
[0055] During ion implantation, high-energy p-type ions (such as N) + P + Ion impacts can cause two problems: Lattice damage: Ion impacts can cause some Ga or O atoms to detach from their lattice positions, forming vacancies, interstitial atoms, and other defects, disrupting the periodic structure of the crystal and leading to enhanced carrier scattering and decreased mobility. Inactive doped ions: Implanted p-type ions (such as N₂) can cause damage to the dopant ions. + Most of them are located in interstitial positions or combined with other defects, and have not entered the effective acceptor positions to replace oxygen atoms, thus failing to release hole carriers.
[0056] The core function of high-temperature thermal annealing is to solve the above problems by thermally activating energy. Defect repair: High temperature provides sufficient energy to lattice atoms, allowing vacancies and interstitial atoms to recombine, restoring the periodicity of the lattice and reducing carrier scattering centers. Dopant ion activation: Thermal energy drives the injection of p-type ions (such as N₂O₃). + The N atom migrates from the interstitial position to the lattice site of the oxygen atom (substitutional doping) to form a stable acceptor center. At this time, the N atom has one less valence electron than the O atom, and will accept the surrounding electrons to generate conductive hole carriers, so that the injected layer truly has p-type conductivity.
[0057] In one possible implementation, the step of performing high-temperature thermal annealing on the P-type implanted layer in a reducing atmosphere to activate the implanted p-type ions and prepare the P layer in the PIN junction includes: performing thermal annealing on the P-type implanted layer in a hydrogen or ammonia reducing atmosphere to activate the p-type ions in the P-type implanted layer; the reducing gas reacts with gallium oxide in the P-type implanted layer to precipitate O from the gallium oxide material, so that the p-type ions occupy the oxygen lattice points, transforming the ion implantation region into a region with p-type doping characteristics, thereby preparing the P layer in the PIN junction.
[0058] The specific mechanism of the reducing atmosphere in high-temperature thermal annealing in this embodiment of the invention is as follows: oxygen atoms in gallium oxide are actively precipitated through reduction reaction, providing oxygen lattice vacancies for implanted p-type ions, thereby efficiently realizing p-type doping activation.
[0059] The core of the reduction reaction is the precipitation of oxygen atoms, creating lattice vacancies. Hydrogen (H2) or ammonia (NH3), as reducing gases, will undergo a reduction reaction with gallium oxide (Ga2O3) in the P-type implanted layer at high temperatures. The core of this reaction is the capture of oxygen atoms from the gallium oxide lattice, generating gaseous products that escape from the material, thus leaving oxygen lattice vacancies in the crystal lattice.
[0060] p-type ions (such as N) + P + Before annealing, these ions are mostly located in interstitial positions, not entering lattice nodes, or combined with other defects, and cannot effectively generate holes. The oxygen lattice vacancies generated by the reduction reaction provide target sites for these ions. The thermal energy provided by the high temperature drives the p-type ions (N... + P + Oxygen diffuses within the crystal lattice, and the oxygen lattice vacancies generated by the reduction reaction are the lowest-energy stable sites. Group V elements have a high lattice matching degree with oxygen, so ions preferentially migrate and occupy these vacancies, forming substitutional doping. The reduction reaction actively creates oxygen lattice vacancies, avoiding the passive process of p-type ions waiting for natural oxygen vacancies, significantly increasing the proportion of ions occupying effective acceptor sites (i.e., activation rate), and solving the core problem of difficult p-type doping activation in gallium oxide.
[0061] In some embodiments, the p-type doping concentration is controlled by controlling the annealing temperature, annealing time, and reducing gas flow rate.
[0062] In some embodiments, the annealing temperature ranges from 800 to 1100°C, the time ranges from 1 to 30 minutes, and the reducing gas flow rate ranges from 100 to 500 sccm.
[0063] Step 104: Prepare a cathode electrode 4 on the lower surface of a heavily doped n-type gallium oxide substrate;
[0064] Figure 7 This is a schematic diagram of the structure of the cathode electrode after fabrication according to an embodiment of the present invention; see reference. Figure 7 The cathode electrode forms a good ohmic contact with the bottom of the n-layer substrate, ensuring that electrons can be efficiently transferred from the external circuit to the inside of the device.
[0065] In some embodiments, physical vapor deposition techniques such as electron beam evaporation and magnetron sputtering can be used to ensure that the metal film uniformly covers the substrate surface. Then, a high-temperature alloying process is used to rapidly anneal at 450°C for 1-2 minutes to form a good ohmic contact between the metal electrode and the n-type highly doped β-Ga2O3 layer.
[0066] In some embodiments, the cathode electrode is made of titanium; the anode electrode is made of nickel.
[0067] Step 105: On the upper surface of the P layer, an anode electrode 5 is prepared to obtain a gallium oxide PIN diode.
[0068] Figure 8 This is a schematic diagram of the structure after fabrication of the anode electrode according to an embodiment of the present invention. (Refer to...) Figure 8 The anode electrode is in direct contact with the P layer of the PIN junction and is the positive electrode of the device.
[0069] In some embodiments, metal thin films can be prepared by electron beam evaporation or magnetron sputtering, followed by low-temperature annealing (e.g., temperature range 400-600°C, inert atmosphere) to promote the interfacial reaction between the metal and the P layer, reduce contact resistance, and enhance the adhesion of the electrode.
[0070] This invention employs a heavily doped n-type gallium oxide substrate as the N-layer, on which an I-layer is fabricated. P-type ion implantation is then performed on the I-layer, and high-temperature annealing with a reducing gas activates the implanted ions to achieve p-type doping, resulting in the P-layer. The reducing gas precipitates oxygen atoms from the gallium oxide through a reduction reaction, allowing the implanted p-type ions to occupy oxygen lattice sites and capture electrons from gallium atoms, forming holes. This achieves p-type ion implantation doping, reducing the difficulty of fabricating p-type doped gallium oxide. Cathode and anode electrodes are then fabricated, further simplifying the fabrication of gallium oxide PIN diodes.
[0071] This invention proposes a novel method for fabricating gallium oxide PIN diodes. The method involves thermally oxidizing a heavily doped β-Ga2O3 substrate to form an I-layer with low carrier concentration, and then using ion implantation and high-temperature annealing with reducing gases to achieve a p-type doped layer. The reducing gases H2 and NH3 can precipitate oxygen atoms from the gallium oxide through a reduction reaction, allowing the implanted N and P ions to occupy oxygen vacancies and capture electrons from gallium atoms to form holes, thus achieving p-type doping.
[0072] The I-layer of a PIN diode significantly expands the width of the depletion region, and the electric field is uniformly distributed within the I-layer. Compared to gallium oxide SBDs, gallium oxide PIN diodes have a higher breakdown voltage.
[0073] This invention successfully fabricated a gallium oxide PIN diode and proposed a new approach to achieve gallium oxide p-type doping, which plays an important role in improving the voltage withstand capability of gallium oxide diodes.
[0074] This invention provides a gallium oxide PIN diode based on ion implantation reduction, which is prepared according to the gallium oxide PIN diode preparation method based on ion implantation reduction as described in any of the above possible implementations.
[0075] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for fabricating a gallium oxide PIN diode based on ion implantation reduction, characterized in that, include: On the surface of a heavily doped n-type gallium oxide substrate, an I layer in a PIN junction is prepared. p-type ion implantation is performed on the upper surface of the I layer to obtain a p-type implanted layer; The P-type implanted layer is subjected to high-temperature thermal annealing in a reducing atmosphere to activate the implanted p-type ions, thereby preparing the P layer in the PIN junction. A cathode electrode is fabricated on the lower surface of a heavily doped n-type gallium oxide substrate; An anode electrode is fabricated on the upper surface of the P layer to obtain a gallium oxide PIN diode.
2. The method for fabricating a gallium oxide PIN diode based on ion implantation reduction as described in claim 1, characterized in that, The step of performing high-temperature thermal annealing on the P-type implanted layer in a reducing atmosphere to activate the implanted p-type ions and prepare the P-layer in the PIN junction includes: The P-type implanted layer is thermally annealed in a reducing atmosphere of hydrogen or ammonia to activate p-type ions in the P-type implanted layer. The reducing gas reacts with gallium oxide in the P-type implanted layer to precipitate O in the gallium oxide material, so that p-type ions occupy the lattice points of oxygen, and the ion implantation region is transformed into p-type doped, thus preparing the P layer in the PIN junction.
3. The method for fabricating a gallium oxide PIN diode based on ion implantation reduction as described in claim 1, characterized in that, The process of fabricating the I layer in the PIN junction on the surface of a heavily doped n-type gallium oxide substrate includes: An insulating dielectric layer is grown on the lower surface of the n-type gallium oxide substrate; Under the protection of the insulating dielectric layer, the n-type gallium oxide substrate is thermally oxidized to obtain the I layer of the PIN junction on the upper surface of the n-type gallium oxide substrate; After thermal oxidation, the insulating dielectric layer on the lower surface of the n-type gallium oxide substrate is removed.
4. The method for fabricating a gallium oxide PIN diode based on ion implantation reduction as described in claim 1, characterized in that, The p-type ions include nitrogen ions or phosphorus ions.
5. The method for fabricating a gallium oxide PIN diode based on ion implantation reduction as described in claim 1, characterized in that, The implantation depth and concentration can be controlled by adjusting the ion implantation energy and dose range.
6. The method for fabricating a gallium oxide PIN diode based on ion implantation reduction as described in claim 5, characterized in that, The ion implantation dose range is 1e 12 up to 1e 14 cm -2 ; The ion implantation energy power range is 10 to 40 keV.
7. The method for fabricating a gallium oxide PIN diode based on ion implantation reduction as described in claim 1, characterized in that, The p-type doping concentration can be controlled by adjusting the annealing temperature, annealing time, and reducing gas flow rate.
8. The method for fabricating a gallium oxide PIN diode based on ion implantation reduction as described in claim 7, characterized in that, The annealing temperature range is 800 to 1100°C, the time range is 1 to 30 minutes, and the reducing gas flow rate ranges from 100 to 500 sccm.
9. The method for fabricating a gallium oxide PIN diode based on ion implantation reduction as described in claim 1, characterized in that, The cathode electrode is made of titanium; the anode electrode is made of nickel.
10. A gallium oxide PIN diode based on ion implantation reduction, characterized in that, It was prepared according to the method for preparing gallium oxide PIN diodes based on ion implantation reduction as described in any one of claims 1 to 9.