Diode chip and method of manufacturing the same

Abstract

The application discloses a diode chip and a preparation method thereof. The preparation method of the diode chip comprises the following steps: performing one-time phosphorus diffusion on both sides of a P-type substrate silicon wafer, and forming P-N junctions and a first silicon dioxide layer on the both sides of the P-type substrate silicon wafer; performing photoetching patterns on the both sides of the P-type substrate silicon wafer, and forming a hollow circular matrix; the circular matrix covers at least part of the region of the P-N junctions and penetrates through the first silicon dioxide layer; performing two-time phosphorus diffusion, forming P-N junctions and a second silicon dioxide layer on the both sides of the P-type substrate silicon wafer; the second silicon dioxide layer covers the first silicon dioxide layer; grooves are formed at the positions of four peripheral edge angles of the both sides of the P-type substrate silicon wafer, and a glass passivation layer is formed at the grooves; lead hole etching is performed on the both sides of the P-type substrate silicon wafer, and a metal electrode is covered. ‑ ‑ ‑ + The technical scheme provided by the embodiment of the application improves the tolerance of the diode chip to lightning surges.​​​

Description

Technical Field

[0001] This invention relates to the field of diode technology, and in particular to a diode chip and its fabrication method. Background Technology

[0002] Diodes are critical protection devices in electronic circuits, such as transient voltage suppressor diodes (TVS). They are widely used in consumer electronics, industrial control, and new energy equipment. Among them, bidirectional negative resistance TVS, with its symmetrical breakdown characteristics in both positive and negative directions, can adapt to bidirectional transient high-voltage interference scenarios and is one of the core components of current high-voltage, high-reliability protection circuits.

[0003] However, when current diodes are subjected to strong current and the electromagnetic pulses they generate, overvoltage will occur in the diode. When the overvoltage is transmitted along the power line or signal line, it will form a lightning surge. This transient process will generate a large number of electrons and release a lot of heat energy, which will damage the diode and other devices, causing the diode to burn out and lose its ability to protect the circuit. Summary of the Invention

[0004] This invention provides a diode chip and its fabrication method to solve the problem of poor withstand capability of diode chips against lightning surges.

[0005] According to one aspect of the present invention, a method for fabricating a diode chip is provided, comprising: A single phosphorus diffusion process is performed on both sides of a P-type substrate silicon wafer to form a double-sided PN junction. - The junction and the first silicon dioxide layer; Photolithographic patterns are formed on both sides of the P-type substrate silicon wafer to create a hollow circular matrix; the circular matrix covers at least a portion of the P-type substrate silicon wafer. - The region of the junction, and penetrating the first silicon dioxide layer; Secondary phosphorus diffusion is performed to form PN junctions on both sides of the P-type substrate silicon wafer. - -N + The junction and the second silicon dioxide layer; the second silicon dioxide layer covers the first silicon dioxide layer; Trenches are formed at the four corners of both sides of the P-type substrate silicon wafer, and a glass passivation layer is formed in the trenches; Leadholes are etched on both sides of the P-type substrate silicon wafer and covered with metal electrodes.

[0006] Optionally, a secondary phosphorus diffusion is performed to form a PN junction on both sides of the P-type substrate silicon wafer. - -N + Before the junction and the second silicon dioxide layer, it also includes: The doping concentration of phosphorus atoms in the secondary phosphorus diffusion is set; the doping concentration of phosphorus atoms in the primary phosphorus diffusion is less than the doping concentration of phosphorus atoms in the secondary phosphorus diffusion.

[0007] Optionally, the step of forming trenches at the four corners of both sides of the P-type substrate silicon wafer and forming a glass passivation layer at the trenches includes: Photoresist is coated on both sides of the P-type substrate silicon wafer, and double-sided trench lines are etched by exposure, development, and wet etching. Grooves are created at the locations of the groove lines using a wet etching method; Clean the P-type substrate silicon wafer and spin dry; Glass slurry is filled into the trench and crystallized at high temperature to form the glass passivation layer.

[0008] Optionally, the depth of the trench is PN. - -N + A first preset multiple of the junction depth; the first preset multiple is greater than 1.

[0009] Optionally, after filling the trench with glass slurry and performing high-temperature crystallization to form the glass passivation layer, the process includes: The thickness of the glass passivation layer is measured; If the thickness of the glass passivation layer does not reach the preset thickness, continue to fill the trench with glass slurry and perform high-temperature crystallization.

[0010] Optionally, the step of etching lead holes on both sides of the P-type substrate silicon wafer and covering the metal electrodes includes: Photoresist is coated on both sides of the P-type substrate silicon wafer. Through exposure, development, and wet etching, lead holes are etched on both sides, penetrating both the second silicon dioxide layer and the first silicon dioxide layer. The lead holes cover at least a portion of the P-type substrate silicon wafer. - -N + The area of ​​the knot; Metal electrodes are respectively covered on both sides of the lead hole.

[0011] Optionally, phosphorus diffusion is performed on both sides of the P-type substrate silicon wafer to form a double-sided PN junction. - Before the junction and the first silicon dioxide layer, it includes: The P-type substrate silicon wafer is chemically etched and then polished to reduce its thickness; Clean the P-type substrate silicon wafer and spin dry.

[0012] Optionally, a secondary phosphorus diffusion is performed to form a PN junction on both sides of the P-type substrate silicon wafer. - -N + Before the junction and the second silicon dioxide layer, it also includes: Clean the P-type substrate silicon wafer and spin dry.

[0013] Optionally, the cleaning and spin-drying of the P-type substrate silicon wafer includes: The P-type substrate silicon wafer is cleaned by ultrasonic cleaning for the first cleaning time. The P-type substrate silicon wafer was cleaned with SC1 cleaning solution and SC2 cleaning solution respectively for a second cleaning time; Spin dry the P-type substrate silicon wafer.

[0014] According to another aspect of the present invention, a diode chip is provided, which is prepared using the diode chip preparation method described in any embodiment of the present invention.

[0015] The technical solution provided in this invention achieves N-type phosphorus diffusion by performing a single phosphorus diffusion process on both sides of a P-type substrate silicon wafer, photolithographically etching a circular matrix pattern, and then performing a second phosphorus diffusion. + -N - -PN - -N + Integration of diode chips with a specific structure. When N + -N - -PN - -N + When a lightning surge occurs inside the diode chip due to overvoltage, the N-type drift region can absorb the surge voltage, preventing voltage concentration on the surface of the P-type substrate silicon wafer and reducing leakage current. Furthermore, secondary phosphorus diffusion can form a high concentration of N-type phosphorus. + The heavily doped region significantly reduces contact resistance. Large surge currents can be quickly discharged, preventing heat buildup between the surface of the P-type substrate silicon wafer and the metal electrodes, thus preventing localized high temperatures from burning out the diode chip. Therefore, N... + -N - -PN - -N + The diode structure significantly improves the chip's overall resistance to lightning surges by adjusting N. + The concentration of the heavily doped region can also be adjusted to regulate surge capability, playing an important role in protecting the overall circuit.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of a method for fabricating a diode chip according to an embodiment of the present invention; Figure 2 This is a cross-sectional view of a diode chip provided according to an embodiment of the present invention; Figure 3 This is a top view of a diode chip provided according to an embodiment of the present invention; Figure 4 This is a flowchart of another method for fabricating a diode chip according to an embodiment of the present invention; Figure 5 This is a flowchart of another method for fabricating a diode chip according to an embodiment of the present invention; Figure 6 This is a flowchart of another method for fabricating a diode chip according to an embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] This invention provides a method for fabricating a diode chip. Figure 1This is a flowchart illustrating a method for fabricating a diode chip according to an embodiment of the present invention. Figure 2 This is a cross-sectional view of a diode chip provided in an embodiment of the present invention. Figure 3 This is a top view of a diode chip provided in an embodiment of the present invention. (In conjunction with...) Figures 1-3 The methods for fabricating diode chips include: S110. Perform phosphorus diffusion on both sides of a P-type substrate silicon wafer to form a double-sided PN junction. - The junction and the first silicon dioxide layer.

[0022] During a single phosphorus diffusion process, phosphorus atoms diffuse from both sides of the P-type substrate silicon wafer 1 into its interior, simultaneously forming N-drift regions 21 on both sides of the P-type substrate silicon wafer 1, thereby forming a PN junction. - Conclusion 2. During a single phosphorus diffusion process, high-temperature oxidation forms a first silicon dioxide layer 41 on the surface of the P-type substrate silicon wafer.

[0023] For example, the thickness of the first silicon dioxide layer can be between 3000-8000 Å, PN - The sheet resistance of the junction is between 0.5 and 2.5 ohms / sq.

[0024] S120. Photolithographic patterns are formed on both sides of a P-type substrate silicon wafer, creating a hollow circular matrix; the circular matrix covers at least a portion of the P-type substrate. - The junction region extends through the first silicon dioxide layer.

[0025] After the first phosphorus diffusion is completed, both sides of the P-type substrate silicon wafer 1 are covered with a first silicon dioxide layer 41. The first silicon dioxide layer 41 can prevent phosphorus atoms from entering the P-type substrate silicon wafer. Therefore, it is necessary to remove part of the first silicon dioxide layer 41 so that phosphorus atoms can diffuse from both sides of the P-type substrate silicon wafer 1 into the interior of the P-type substrate silicon wafer 1 during the subsequent second phosphorus diffusion.

[0026] By adopting a hollow circular matrix window arrangement, compared to opening and doping the entire area, the continuous electrode area can be divided into multiple dispersed circles, thereby dispersing the current, preventing the current from concentrating in a local position, alleviating the current congestion effect, avoiding excessive local temperature, and improving the diode's ability to withstand lightning surges.

[0027] S130, perform secondary phosphorus diffusion to form PN junctions on both sides of the P-type substrate silicon wafer. - -N + The junction and the second silicon dioxide layer; the second silicon dioxide layer covers the first silicon dioxide layer.

[0028] In this process, because the first silicon dioxide layer 41 is removed only in a portion of the P-type substrate silicon wafer 1 during photolithography on both sides by hollowing out a circular matrix 31, phosphorus atoms only diffuse into the interior of the P-type substrate silicon wafer 1 through the circular matrix 31 during secondary phosphorus diffusion, thereby forming a PN junction. - -N + Region 3.

[0029] During the secondary phosphorus diffusion process, high-temperature oxidation generates a silicon dioxide layer again on the surface of the P-type substrate silicon wafer 1, which is the second silicon dioxide layer 42.

[0030] By removing the first silicon dioxide layer 41 in the circular matrix 31 region and retaining the first silicon dioxide protective layer 41 in other regions, phosphorus atoms can only penetrate into the interior of the N drift region from the hollowed-out circular matrix 31 region, thereby forming PN. - -N + Conclusion 3.

[0031] High concentrations of N can be formed in region 31 of the circular matrix through secondary phosphorus diffusion. + The heavily doped region has low contact resistance, resulting in high current density and strong conductivity during subsequent current path formation. In the event of surge current, the circular matrix 31 region effectively conducts the surge current, reducing electron accumulation and heat generation, thus ensuring the safe operation of the diode chip. Furthermore, the N-drift region 21 is still preserved outside the circular matrix 31 region, which helps maintain the breakdown voltage and ensures the withstand voltage remains constant.

[0032] For example, by adjusting the concentration of secondary phosphorus diffusion, it can be used to adjust N + The concentration of the heavily doped region is adjusted to regulate the surge capability.

[0033] Since both primary and secondary phosphorus diffusion are bifacial diffusion processes, PN junctions are formed on both sides of the P-type substrate silicon wafer. - -N + Conclusion 3, ultimately forming N + -N - -PN - -N + Diode chip with a specific structure.

[0034] For example, the thickness of the second silicon dioxide layer can be between 4000-7000 Å, PN - -N + The sheet resistance of the junction is between 0.3 and 1 ohm / sq.

[0035] S140. Trenches are formed at the four corners of both sides of the P-type substrate silicon wafer, and a glass passivation layer is formed at the trenches.

[0036] By setting the glass passivation layer 5, the edges and corners of the diode chip can be passivated, reducing surface defects and preventing moisture, metal, and other impurities from adhering to the edges and corners. This also prevents PN junction defects. - -N + Junction 3 is corroded by external pollutants, which improves the long-term stability of the diode chip.

[0037] The corners of a diode chip are geometrically sharp points where the electric field intensity increases dramatically in a planar state, making surface breakdown highly likely and resulting in excessive reverse leakage current. Placing a glass passivation layer at the four corner edges mitigates the electric field on the surface of the P-type substrate silicon wafer, reducing the peak electric field at these points. This ensures that avalanche breakdown occurs within the P-type substrate silicon wafer itself, rather than on the diode chip surface, thus reducing leakage current and improving reliability.

[0038] Furthermore, by setting a glass passivation layer, physical protection can be provided for the diode chip, mitigating minor damage caused by dicing, preventing the subsequent propagation of microcracks, and improving the strength of the diode chip.

[0039] S150. Etch lead holes on both sides of the P-type substrate silicon wafer and cover them with metal electrodes.

[0040] Since the first silicon dioxide layer 41 and the second silicon dioxide layer 42 are insulating materials, current cannot pass through them. Therefore, it is necessary to remove the first silicon dioxide layer 41 and the second silicon dioxide layer 42 at the corresponding positions by etching the lead holes, so that the metal electrode 6 can directly contact the P-type substrate silicon wafer 1, thereby forming a conductive path.

[0041] For example, a dicing channel is provided between multiple P-type substrate silicon wafers, and the dicing channel may also be provided with lead holes. The diode chip can be a mesa-type negative resistance TVS chip.

[0042] The technical solution provided in this invention achieves N-type phosphorus diffusion by performing a single phosphorus diffusion process on both sides of a P-type substrate silicon wafer, photolithographically etching a circular matrix pattern, and then performing a second phosphorus diffusion. + -N - -PN - -N + Integration of diode chips with a specific structure. When N + -N - -PN - -N + When a lightning surge occurs inside the diode chip due to overvoltage, the N-type drift region can absorb the surge voltage, preventing voltage concentration on the surface of the P-type substrate silicon wafer and reducing leakage current. Furthermore, secondary phosphorus diffusion can form a high concentration of N-type phosphorus. +The heavily doped region significantly reduces contact resistance. Large surge currents can be quickly discharged, preventing heat buildup between the surface of the P-type substrate silicon wafer and the metal electrodes, thus preventing localized high temperatures from burning out the diode chip. Therefore, N... + -N - -PN - -N + The diode structure significantly improves the chip's overall resistance to lightning surges by adjusting N. + The concentration of the heavily doped region can also be adjusted to regulate surge capability, playing an important role in protecting the overall circuit.

[0043] Based on the above embodiments, optionally, a secondary phosphorus diffusion is performed to form a PN junction on both sides of the P-type substrate silicon wafer. - -N + Before the junction and the second silicon dioxide layer, the process also includes: setting the doping concentration of phosphorus atoms in the secondary phosphorus diffusion; the doping concentration of phosphorus atoms in the primary phosphorus diffusion is less than the doping concentration of phosphorus atoms in the secondary phosphorus diffusion.

[0044] In this process, primary phosphorus diffusion is used to generate lightly doped N. - In the drift region, the surge voltage of the diode chip is mainly determined by N. - The drift region is responsible for this process; if the doping concentration in this region is too high, it will cause a decrease in breakdown voltage, failing to meet the withstand voltage requirements. Therefore, the doping concentration of phosphorus atoms during the primary phosphorus diffusion can be appropriately reduced.

[0045] The phosphorus doping concentration in secondary phosphorus diffusion is negatively correlated with resistance. A higher phosphorus doping concentration reduces the internal resistance of the P-type substrate silicon wafer, thereby reducing the contact resistance between the metal electrode and the P-type substrate silicon wafer. Conversely, a lower phosphorus doping concentration increases the internal resistance of the P-type substrate silicon wafer, thereby increasing the contact resistance between the metal electrode and the P-type substrate silicon wafer. Therefore, by adjusting the phosphorus doping concentration in secondary phosphorus diffusion, the surge resistance of diode chips can be adjusted.

[0046] Specifically, by increasing the phosphorus atom doping concentration, a high concentration of N can be formed through secondary phosphorus diffusion. + Heavily doped regions can significantly reduce the contact resistance between the metal electrode and the P-type silicon substrate. Therefore, surge current in the diode chip can be smoothly discharged, preventing current accumulation and the generation of localized high temperatures, and improving the diode chip's ability to withstand lightning surges.

[0047] This invention, through different phosphorus atom doping concentrations in primary and secondary phosphorus diffusion, enables the diode chip to meet voltage withstand requirements while simultaneously enhancing its short-surge capability, particularly for 8 / 20μs short-surge pulses. Adjusting the phosphorus atom doping concentration allows for flexible adjustment of surge tolerance.

[0048] Figure 4 A flowchart illustrating another method for fabricating a diode chip according to an embodiment of the present invention. (See reference...) Figure 4 Based on the above embodiments, optionally, in step S140, trenches are formed at the four corners of both sides of the P-type substrate silicon wafer, and a glass passivation layer is formed at the trenches, including: S141. Photoresist is coated on both sides of a P-type substrate silicon wafer, and double-sided trench lines are etched by exposure, development, and wet etching.

[0049] In this process, photoresist is uniformly coated on both the upper and lower surfaces of a P-type silicon substrate. The rotation speed is controlled by a spin coater to ensure that the photoresist thickness is uniform on both sides of the P-type silicon substrate. Afterward, a low-temperature pre-baking process is performed to evaporate the internal solvent of the photoresist, allowing it to adhere tightly to the surface of the P-type silicon substrate and preventing it from peeling off, thus preparing it for subsequent exposure.

[0050] For example, a double-sided alignment photolithography process with an alignment accuracy of <10μm is used. The upper and lower surfaces of a P-type substrate silicon wafer are exposed to ultraviolet light according to a preset pattern. The photoresist in the area corresponding to the trench lines undergoes a photosensitive reaction after being irradiated by ultraviolet light. The photoresist in the exposed area is then dissolved using a developer, with the remaining photoresist acting as a protective barrier. At this point, a hollow pattern of trench lines is formed on both sides of the silicon wafer, meaning only the second silicon dioxide layer at the trench location is exposed, while the remaining areas are covered by photoresist. This determines the position, width, and arrangement of the trenches. The second silicon dioxide layer and the covering first silicon dioxide layer can be removed by wet etching.

[0051] S142. Grooves are created at the locations of the groove lines using wet etching.

[0052] Wet etching involves cutting down along the trench lines to etch the P-type substrate silicon wafer, creating trenches of a certain depth.

[0053] For example, the temperature of wet etching can be 10±2 degrees Celsius, and the etching time can be 300-500 seconds.

[0054] S143. Clean the P-type substrate silicon wafer and spin dry.

[0055] After the trench etching is completed, it is necessary to remove the residual etching solution, silicon debris and other impurities on the surface of the P-type substrate silicon wafer. Then, the P-type substrate silicon wafer can be dried by high-speed centrifugation to ensure that the inside of the trench is clean and free of residual impurities, and to prevent defects from occurring during subsequent glass crystallization.

[0056] S144. Fill the trench with glass slurry and crystallize it at high temperature to form a glass passivation layer.

[0057] In this process, glass slurry is filled into the interior of the trench and placed in a high-temperature diffusion furnace for high-temperature annealing. This allows the glass slurry to melt and bond tightly to the sidewalls of the trench. After cooling, it crystallizes and solidifies, forming a dense glass passivation layer in the trench.

[0058] For example, after the glass is filled into the groove, it can be first placed on a hot plate at 130-140 degrees Celsius for baking, and then sintered at a high temperature of 800-820 degrees Celsius for 15-25 minutes to crystallize the glass.

[0059] For example, the glass passivation layer may also use other composite passivation films, such as silicon nitride, PSG (phosphate glass), SIPOS (semi-insulating poly-crystalline silicon), etc., without limitation.

[0060] The embodiments of the present invention improve the electric field distribution of the P-type substrate silicon wafer by setting a glass passivation layer, passivate defects on the silicon surface, and improve the reliability of the diode chip.

[0061] Based on the above embodiments, optionally, the depth of the trench is PN. - -N + The first preset multiple of the junction depth; the first preset multiple is greater than 1.

[0062] For example, the first preset multiple can be 1.3, ensuring that the depth of the trench can accommodate PN. - -N + The entire depth of the knot is covered.

[0063] Continue to refer to Figure 4 Based on the above embodiments, optionally, after filling the trench with glass slurry and performing high-temperature crystallization to form a glass passivation layer, S144 includes: S145. Detect the thickness of the glass passivation layer.

[0064] S146. If the thickness of the glass passivation layer does not reach the preset thickness, continue to fill the trench with glass slurry and carry out high-temperature crystallization.

[0065] If the glass passivation layer is too thin, its shielding effect on the electric field may be insufficient, making the diode chip prone to surface breakdown. Furthermore, a thinner glass passivation layer reduces its isolation and protective capabilities, mechanical strength, and density, weakening its ability to isolate external moisture, dust, and impurities. Therefore, it is necessary to ensure that the thickness of the glass passivation layer meets the preset thickness requirement. For example, the preset thickness can be 30±10μm.

[0066] The embodiments of the present invention ensure the isolation capability of the glass passivation layer by continuously monitoring the thickness of the glass passivation layer, thereby improving the reliability of the diode chip.

[0067] Figure 5 This is a flowchart illustrating another method for fabricating a diode chip according to an embodiment of the present invention. (In conjunction with...) Figure 2 and Figure 5 Based on the above embodiments, optionally, in step S150, etching lead holes on both sides of the P-type substrate silicon wafer and covering the metal electrodes includes: S151. Photoresist is coated on both sides of a P-type substrate silicon wafer. Through exposure, development, and wet etching, wire holes are etched on both sides, penetrating the second silicon dioxide layer and the first silicon dioxide layer; the wire holes cover at least a portion of the P-type substrate silicon wafer. - -N + The region of the knot.

[0068] S152. Cover the lead holes on both sides with metal electrodes respectively.

[0069] Since the first silicon dioxide layer 41 and the second silicon dioxide layer 42 are insulating materials, current cannot pass through them. Therefore, it is necessary to remove the first silicon dioxide layer 41 and the second silicon dioxide layer 42 at the corresponding positions by etching the lead holes, so that the metal electrode 6 can directly contact the P-type substrate silicon wafer 1, thereby forming a conductive path.

[0070] Specifically, the first silicon dioxide layer 41 and the second silicon dioxide layer 42 on the surface of the P-type substrate silicon wafer 1 can be etched by exposure, development and wet etching, so that the metal electrode can directly contact the P-type substrate silicon wafer 1 through the lead hole.

[0071] For example, the metal electrode 6 can be electroless nickel plating or evaporated metal.

[0072] Figure 6 A flowchart illustrating another method for fabricating a diode chip according to an embodiment of the present invention. (See reference...) Figure 6 Based on the above embodiments, optionally, in S110, phosphorus diffusion is performed on both sides of the P-type substrate silicon wafer to form a double-sided PN junction. -Before the junction and the first silicon dioxide layer, it includes: S160. Polish and thin the P-type substrate silicon wafer by chemical etching.

[0073] S170, clean the P-type substrate silicon wafer and spin dry.

[0074] In particular, during the early cutting and mechanical polishing process, invisible microcracks will form on the silicon surface of P-type substrate silicon wafers. If the damaged layer remains, the cracks will extend further during subsequent diffusion and high-temperature sintering processes. When the diode chip is subjected to a large current impact, it is easy to cause damage to the diode chip.

[0075] Therefore, before phosphorus diffusion onto P-type substrate silicon wafers, surface treatment of the P-type substrate silicon wafers is required. Chemical etching can remove the mechanical damage layer and residual stress generated during the initial dicing process of the P-type substrate silicon wafers.

[0076] After polishing and thinning, a cell will form on the surface of the P-type substrate silicon wafer, which can be used to increase the surface area of ​​the P-type substrate silicon wafer and improve the mechanical bonding strength of the subsequent glass passivation layer.

[0077] For example, the thinning removal amount can be 60±5μm, and the corrosion temperature can be 95±5 degrees Celsius.

[0078] Continue to refer to Figure 6 Based on the above embodiments, optionally, a secondary phosphorus diffusion is performed in S130 to form a PN junction on both sides of the P-type substrate silicon wafer. - -N + Before the junction and the second silicon dioxide layer, it also includes: S180, clean the P-type substrate silicon wafer and spin dry.

[0079] Optionally, cleaning and drying the P-type substrate silicon wafer includes: cleaning the P-type substrate silicon wafer by ultrasonic cleaning for a first cleaning time; cleaning the P-type substrate silicon wafer by SC1 cleaning solution and SC2 cleaning solution for a second cleaning time; and drying the P-type substrate silicon wafer by spin drying.

[0080] Before performing secondary phosphorus diffusion, the P-type substrate silicon wafer needs to be cleaned to ensure the effectiveness of the secondary phosphorus diffusion.

[0081] Specifically, the P-type substrate silicon wafer is first cleaned using ultrasonic cleaning. Ultrasonic cleaning can remove silicon chips, particles and loose impurities from the surface of the P-type substrate silicon wafer, reducing the pressure of subsequent cleaning.

[0082] SC1 cleaning solution is prepared by mixing ammonia and hydrogen peroxide. It can be used to remove organic residues from the surface of P-type substrate silicon wafers and further remove particulate contaminants. SC2 cleaning solution is prepared by mixing hydrochloric acid and hydrogen peroxide. It can be used to remove metallic impurities such as iron and copper from the surface of P-type substrate silicon wafers, reducing the amount of metal residue.

[0083] For example, the first cleaning time can be 20 minutes, and the second cleaning time can be 10 minutes.

[0084] After cleaning the P-type substrate silicon wafer, it can be dried by high-speed centrifugation, which results in a high degree of cleanliness and good dryness.

[0085] This invention also provides a diode chip. The diode chip fabricated using the method provided in any embodiment of this invention has similar beneficial effects to other diode chip fabrication methods, and will not be described in detail here.

[0086] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0087] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for fabricating a diode chip, characterized in that, include: A single phosphorus diffusion process is performed on both sides of a P-type substrate silicon wafer to form a double-sided PN junction. - The junction and the first silicon dioxide layer; Photolithographic patterns are formed on both sides of the P-type substrate silicon wafer to create a hollow circular matrix; the circular matrix covers at least a portion of the P-type substrate silicon wafer. - The region of the junction, and penetrating the first silicon dioxide layer; Secondary phosphorus diffusion is performed to form PN junctions on both sides of the P-type substrate silicon wafer. - -N + The junction and the second silicon dioxide layer; the second silicon dioxide layer covers the first silicon dioxide layer; Trenches are formed at the four corners of both sides of the P-type substrate silicon wafer, and a glass passivation layer is formed in the trenches; Leadholes are etched on both sides of the P-type substrate silicon wafer and covered with metal electrodes.

2. The method for fabricating a diode chip according to claim 1, characterized in that, During the secondary phosphorus diffusion process, PN junctions are formed on both sides of the P-type substrate silicon wafer. - -N + Before the junction and the second silicon dioxide layer, it also includes: The doping concentration of phosphorus atoms in the secondary phosphorus diffusion is set; the doping concentration of phosphorus atoms in the primary phosphorus diffusion is less than the doping concentration of phosphorus atoms in the secondary phosphorus diffusion.

3. The method for fabricating a diode chip according to claim 1, characterized in that, The step of creating trenches at the four corners of both sides of the P-type substrate silicon wafer and forming a glass passivation layer at the trenches includes: Photoresist is coated on both sides of the P-type substrate silicon wafer, and double-sided trench lines are etched by exposure, development, and wet etching. Grooves are created at the locations of the groove lines using a wet etching method; Clean the P-type substrate silicon wafer and spin dry; Glass slurry is filled into the trench and crystallized at high temperature to form the glass passivation layer.

4. The method for fabricating a diode chip according to claim 3, characterized in that, The depth of the trench is PN - -N + A first preset multiple of the junction depth; the first preset multiple is greater than 1.

5. The method for fabricating a diode chip according to claim 3, characterized in that, After filling the trench with glass slurry and performing high-temperature crystallization to form the glass passivation layer, the process includes: The thickness of the glass passivation layer is measured; If the thickness of the glass passivation layer does not reach the preset thickness, continue to fill the trench with glass slurry and perform high-temperature crystallization.

6. The method for fabricating a diode chip according to claim 1, characterized in that, The step of etching lead holes on both sides of the P-type substrate silicon wafer and covering the metal electrodes includes: Photoresist is coated on both sides of the P-type substrate silicon wafer. Through exposure, development, and wet etching, lead holes are etched on both sides, penetrating both the second silicon dioxide layer and the first silicon dioxide layer. The lead holes cover at least a portion of the P-type substrate silicon wafer. - -N + The area of ​​the knot; Metal electrodes are respectively covered on both sides of the lead hole.

7. The method for fabricating a diode chip according to claim 1, characterized in that, A single phosphorus diffusion process is performed on both sides of a P-type substrate silicon wafer to form a double-sided PN junction. - Before the junction and the first silicon dioxide layer, it includes: The P-type substrate silicon wafer is polished and thinned by chemical etching; Clean the P-type substrate silicon wafer and spin dry.

8. The method for fabricating a diode chip according to claim 1, characterized in that, During the secondary phosphorus diffusion process, PN junctions are formed on both sides of the P-type substrate silicon wafer. - -N + Before the junction and the second silicon dioxide layer, it also includes: Clean the P-type substrate silicon wafer and spin dry.

9. The method for fabricating a diode chip according to claim 3, 7, or 8, characterized in that, The cleaning and drying of the P-type substrate silicon wafer includes: The P-type substrate silicon wafer is cleaned by ultrasonic cleaning for the first cleaning time. The P-type substrate silicon wafer was cleaned with SC1 cleaning solution and SC2 cleaning solution respectively for a second cleaning time; Spin dry the P-type substrate silicon wafer.

10. A diode chip, characterized in that, The diode chip is prepared using the method described in any one of claims 1-9.

Images